A high voltage starting circuit

Abstract

The present invention discloses a high-voltage startup circuit, comprising a startup and current bias circuit, a diode D1, a reference voltage circuit and an LDO circuit, wherein the input end of the startup and current bias circuit is connected to an enable signal EN, the first output end of the startup and current bias circuit is connected to the first input end of the LDO circuit, the second output end of the startup and current bias circuit is connected to the first input end of the reference voltage circuit and the fourth input end of the LDO circuit, the third output end of the startup and current bias circuit is connected to the second input end of the reference voltage circuit and the fifth input end of the LDO circuit, the first output end of the reference voltage circuit is connected to the second input end of the LDO circuit, and the second output end of the reference voltage circuit is connected to the third input end of the LDO circuit. The present invention does not require a process to support special devices, does not limit the minimum operating voltage of the system, can provide a flexible and optional bias voltage, and has a high output power supply accuracy.

Description

Technical Field

[0001] The invention relates to a starting circuit, in particular to a high-voltage starting circuit, and belongs to the technical field of semiconductor integrated circuits. Background Art

[0002] In an integrated circuit system, there is usually only one source power supply terminal Vsys, such as Figure 2 As shown. However, there are usually multiple functional sub-units A, B, C, etc. inside. And the more complex the system is, the more functional sub-units there are. The source power supply Vsys of the system is usually a variable with a wide input range (such as 4~60V). In order to achieve the best performance and cost, the internal functional sub-units usually require a stable and suitable power supply (such as 3.3V, 5V, etc.). Therefore, in an integrated circuit system, a functional sub-unit of a startup circuit is often required. The main purpose of this functional unit is to provide a suitable bias and power supply for other functional sub-units.

[0003] The traditional implementation scheme of the startup circuit functional subunit is as follows Figure 3 As shown. NM1 is a high-voltage depletion MOS. The main drawback of this solution is that it requires process support to provide a depletion MOS that can meet the Vsys withstand voltage requirements of the source power supply end, so its scope of application and cost will be limited. Secondly, the output voltage of vcc_int is greatly affected by process temperature, that is, the accuracy is limited. Based on this solution, another more common solution is as follows Figure 4 As shown. NM1 is an LDMOS or DEMOS that meets the Vsys withstand voltage requirement, and the clamp circuit can usually be implemented using a Zener diode or a MOS tube. The advantage of this solution over the traditional solution 1 is that it usually does not require special process support to provide special devices, so its cost and applicability are improved and improved compared to the traditional solution 1. However, the disadvantage of this solution is that its minimum operating voltage will be limited by the NM1 threshold voltage (before Vsys is lower than the clamp circuit clamping voltage, vcc_int will be lower than Vsys by an NM1 threshold voltage Va), as shown in Figure 5 At the same time, similar to the traditional solution 1, the accuracy of vcc_int of this solution is similar to that of solution 1, and is greatly affected by the process and temperature.

[0004] In summary, the startup circuit functional unit requires a more universal solution that meets at least two basic requirements: first, no special devices are required from the process; second, before vcc_int reaches the maximum voltage, its value can follow Vsys, that is, it will not affect the minimum operating voltage of the system. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a high-voltage starting circuit which does not require special devices and has high output accuracy.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A high-voltage startup circuit comprises a startup and current bias circuit, a diode D1, a reference voltage circuit and an LDO circuit, wherein an input end of the startup and current bias circuit is connected to an enable signal EN, a first output end of the startup and current bias circuit is connected to an anode of the diode D1 and a first input end of the LDO circuit, a cathode of the diode D1 is connected to a system source power supply Vsys, a second output end of the startup and current bias circuit is connected to a first input end of the reference voltage circuit and a fourth input end of the LDO circuit, a third output end of the startup and current bias circuit is connected to a second input end of the reference voltage circuit and a fifth input end of the LDO circuit, a first output end of the reference voltage circuit is connected to a second input end of the LDO circuit, a second output end of the reference voltage circuit is connected to a third input end of the LDO circuit, and an output end of the LDO circuit generates an output signal vcc_int.

[0008] Further, the startup and current bias circuit comprises a PMOS tube PM1, a PMOS tube PM2, an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3, a resistor R1, a resistor R2 and a resistor R3, the source of the PMOS tube PM1 and one end of the resistor R1 are connected to the system source power supply Vsys, the gate of the PMOS tube PM1 is connected to the other end of the resistor R1 and the source of the PMOS tube PM2, the drain of the PMOS tube PM1 is connected to one end of the resistor R2 and the gate of the PMOS tube PM2 and serves as the first output end of the startup and current bias circuit, and the resistor The other end of R2 is connected to the drain of the NMOS tube NM1, the gate of the NMOS tube NM1 is connected to the enable signal EN, the drain of the PMOS tube PM2 is connected to one end of the resistor R3 and the gate of the NMOS tube NM3 and serves as the second output end of the startup and current bias circuit, the other end of the resistor R3 is connected to the drain of the NMOS tube NM3 and the gate of the NMOS tube NM2 and serves as the third output end of the startup and current bias circuit, the source of the NMOS tube NM3 is connected to the drain of the NMOS tube NM2, and the source of the NMOS tube NM1 and the source of the NMOS tube NM2 are grounded.

[0009] Further, the reference voltage circuit includes PMOS tube PM3, PMOS tube PM4, PMOS tube PM5, PMOS tube PM6, PMOS tube PM7, PMOS tube PM8, PMOS tube PM11, PMOS tube PM12, PMOS tube PM13, NMOS tube NM4, NMOS tube NM5, NMOS tube NM8, NMOS tube NM9, NMOS tube NM12, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, transistor Q1, transistor Q2, transistor Q3 and capacitor C1, the source of PMOS tube PM3, the source of PMOS tube PM5, the source of PMOS tube PM7, resistor R One end of PMOS tube PM7 and one end of resistor R8 are connected to system source power supply Vsys, the gate of PMOS tube PM3 is connected to the gate of PMOS tube PM5, the gate of PMOS tube PM7, the drain of PMOS tube PM6 and one end of resistor R6, the drain of PMOS tube PM3 is connected to the source of PMOS tube PM4, the drain of PMOS tube PM5 is connected to the source of PMOS tube PM6, the drain of PMOS tube PM7 is connected to the source of PMOS tube PM8, the gate of PMOS tube PM4 is connected to the gate of PMOS tube PM6, the gate of PMOS tube PM8, the other end of resistor R6 and the drain of NMOS tube NM5 are connected, the drain of PMOS tube PM4 is connected to the source of PMOS tube PM11, The source of the PMOS tube PM12, the source of the PMOS tube PM13 and the upper stage of the NMOS tube NM12 are connected and serve as the first output end of the reference voltage circuit, the gate of the PMOS tube PM11 is connected to the gate of the PMOS tube PM12, the drain of the PMOS tube PM11 and the collector of the transistor Q1, the drain of the PMOS tube PM12 is connected to the collector of the transistor Q2, one end of the capacitor C1 and the gate of the PMOS tube PM13, the base of the transistor Q1 is connected to the base of the transistor Q2, the source of the NMOS tube NM9, one end of the resistor R9 and one end of the resistor R10 and serve as the second output end of the reference voltage circuit, the emitter of the transistor Q1 is connected to one end of the resistor R4, the emitter of the transistor Q2 is connected to the collector of the transistor Q2, and the drain of the transistor Q13 is connected to the collector of the transistor Q2. The emitter is connected to the other end of the resistor R4 and one end of the resistor R5, the drain of the PMOS tube PM13 is connected to the source of the NMOS tube NM5 and the drain of the NMOS tube NM4, the gate of the NMOS tube NM5 serves as the first input end of the reference voltage circuit, the gate of the NMOS tube NM4 serves as the second input end of the reference voltage circuit, the drain of the PMOS tube PM8 is connected to the drain of the NMOS tube NM8, the gate of the NMOS tube NM8 and the gate of the NMOS tube NM9, the source of the NMOS tube NM8 is connected to the collector of the transistor Q3 and the base of the transistor Q3, the other end of the resistor R7 is connected to the drain of the NMOS tube NM9, the other end of the resistor R8 is connected to the drain of the NMOS tube NM12,The source of the NMOS tube NM12 is connected to the other end of the resistor R9 and serves as the third output end of the reference voltage circuit to generate the reference voltage vref. The other end of the resistor R5, the other end of the capacitor C1, the source of the NMOS tube NM4, the emitter of the transistor Q3 and the other end of the resistor R10 are grounded.

[0010] Furthermore, the transistor Q1, the transistor Q2, the resistor R4, the resistor R5, the PMOS transistor PM11 and the PMOS transistor PM12 form a bandgap reference loop, and the base voltages of the transistor Q1 and the transistor Q2 are Vbg.

[0011] Furthermore, the PMOS transistor PM13, the NMOS transistor NM4, the NMOS transistor NM5, the resistor R6, the PMOS transistor PM5, the PMOS transistor PM6, the PMOS transistor PM3, the PMOS transistor PM4 and the bandgap reference loop form a large feedback loop, thereby ensuring the stability of Vbg.

[0012] Furthermore, the PMOS transistor PM7, the PMOS transistor PM8, the NMOS transistor NM8, the NMOS transistor NM9, the transistor Q3 and the resistor R7 form a fast start path.

[0013] Further, the LDO circuit includes a PMOS tube PM9, a PMOS tube PM10, an NMOS tube NM13, an NMOS tube NM14, an NMOS tube NM10, an NMOS tube NM1, an NMOS tube NM7, an NMOS tube NM6, a resistor R11, a resistor R12, a resistor R13, a capacitor C2 and a capacitor C3, one end of the resistor R11 and the source of the PMOS tube PM10 are connected to the system source power supply Vsys, the other end of the resistor R11 is connected to the source of the PMOS tube PM9, the gate of the PMOS tube PM9 serves as the first input end of the LDO circuit, the drain of the PMOS tube PM9 is connected to the gate of the PMOS tube PM10 and the drain of the NMOS tube NM13, the drain of the PMOS tube PM10 is connected to the drain of the NMOS tube NM14, one end of the capacitor C2, one end of the resistor R12, and one end of the capacitor C3 are connected and serve as the output end of the LDO circuit to generate an output signal vcc_int. , the gate of the NMOS tube NM13 is connected to the gate of the NMOS tube NM14 and serves as the second input terminal of the LDO circuit, the source of the NMOS tube NM13 is connected to the other end of the capacitor C2 and the drain of the NMOS tube NM10, the source of the NMOS tube NM14 is connected to the drain of the NMOS tube NM11, the gate of the NMOS tube NM10 serves as the third input terminal of the LDO circuit, the gate of the NMOS tube NM11 is connected to the other end of the resistor R12 and one end of the resistor R13, the source of the NMOS tube NM10 is connected to the source of the NMOS tube NM11 and the drain of the NMOS tube NM7, the gate of the NMOS tube NM7 serves as the fourth input terminal of the LDO circuit, the source of the NMOS tube NM7 is connected to the drain of the NMOS tube NM6, the gate of the NMOS tube NM6 serves as the fifth input terminal of the LDO circuit, and the source of the NMOS tube NM6, the other end of the resistor R13 and the other end of the capacitor C3 are grounded.

[0014] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides a high-voltage starting circuit, which does not require process support for special devices and does not limit the minimum operating voltage of the system. It can provide a flexible and optional bias voltage and has a high output power supply accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of a high voltage starting circuit of the present invention.

[0016] Figure 2 It is a typical block diagram of an integrated circuit system in the prior art.

[0017] Figure 3 It is a schematic diagram of a first implementation scheme of a startup circuit functional subunit in the prior art.

[0018] Figure 4It is a schematic diagram of the second implementation scheme of the functional subunit of the start-up circuit in the prior art.

[0019] Figure 5 It is a curve diagram showing the relationship between Vsys and vcc_int in the second implementation scheme of the startup circuit functional subunit in the prior art. DETAILED DESCRIPTION

[0020] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0021] like Figure 1 As shown, a high-voltage startup circuit of the present invention includes a startup and current bias circuit, a diode D1, a reference voltage circuit and an LDO circuit, the input end of the startup and current bias circuit is connected to an enable signal EN, the first output end of the startup and current bias circuit is connected to the anode of the diode D1 and the first input end of the LDO circuit, the cathode of the diode D1 is connected to the system source power supply Vsys, the second output end of the startup and current bias circuit is connected to the first input end of the reference voltage circuit and the fourth input end of the LDO circuit, the third output end of the startup and current bias circuit is connected to the second input end of the reference voltage circuit and the fifth input end of the LDO circuit, the first output end of the reference voltage circuit is connected to the second input end of the LDO circuit, the second output end of the reference voltage circuit is connected to the third input end of the LDO circuit, and the output end of the LDO circuit generates an output signal vcc_int.

[0022] The startup and current bias circuit includes a PMOS tube PM1, a PMOS tube PM2, an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3, a resistor R1, a resistor R2 and a resistor R3. The source of the PMOS tube PM1 and one end of the resistor R1 are connected to the system source power supply Vsys, the gate of the PMOS tube PM1 is connected to the other end of the resistor R1 and the source of the PMOS tube PM2, the drain of the PMOS tube PM1 is connected to one end of the resistor R2 and the gate of the PMOS tube PM2 and serves as the first output end of the startup and current bias circuit, and the resistor R2 is connected to the gate of the PMOS tube PM2. The other end is connected to the drain of the NMOS tube NM1, the gate of the NMOS tube NM1 is connected to the enable signal EN, the drain of the PMOS tube PM2 is connected to one end of the resistor R3 and the gate of the NMOS tube NM3 and serves as the second output end of the startup and current bias circuit, the other end of the resistor R3 is connected to the drain of the NMOS tube NM3 and the gate of the NMOS tube NM2 and serves as the third output end of the startup and current bias circuit, the source of the NMOS tube NM3 is connected to the drain of the NMOS tube NM2, and the source of the NMOS tube NM1 and the source of the NMOS tube NM2 are grounded.

[0023] The reference voltage circuit includes a PMOS tube PM3, a PMOS tube PM4, a PMOS tube PM5, a PMOS tube PM6, a PMOS tube PM7, a PMOS tube PM8, a PMOS tube PM11, a PMOS tube PM12, a PMOS tube PM13, an NMOS tube NM4, an NMOS tube NM5, an NMOS tube NM8, an NMOS tube NM9, an NMOS tube NM12, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a transistor Q1, a transistor Q2, a transistor Q3 and a capacitor C1, a source of the PMOS tube PM3, a source of the PMOS tube PM5, a source of the PMOS tube PM7, one end of the resistor R7 and One end of the resistor R8 is connected to the system source power supply Vsys, the gate of the PMOS tube PM3 is connected to the gate of the PMOS tube PM5, the gate of the PMOS tube PM7, the drain of the PMOS tube PM6 and one end of the resistor R6, the drain of the PMOS tube PM3 is connected to the source of the PMOS tube PM4, the drain of the PMOS tube PM5 is connected to the source of the PMOS tube PM6, the drain of the PMOS tube PM7 is connected to the source of the PMOS tube PM8, the gate of the PMOS tube PM4 is connected to the gate of the PMOS tube PM6, the gate of the PMOS tube PM8, the other end of the resistor R6 and the drain of the NMOS tube NM5, the drain of the PMOS tube PM4 is connected to the source of the PMOS tube PM11, the PMOS tube PM8 and the drain of the NMOS tube NM5. The source of the S transistor PM12, the source of the PMOS transistor PM13 and the upper stage of the NMOS transistor NM12 are connected and serve as the first output end of the reference voltage circuit, the gate of the PMOS transistor PM11 is connected to the gate of the PMOS transistor PM12, the drain of the PMOS transistor PM11 and the collector of the transistor Q1, the drain of the PMOS transistor PM12 is connected to the collector of the transistor Q2, one end of the capacitor C1 and the gate of the PMOS transistor PM13, the base of the transistor Q1 is connected to the base of the transistor Q2, the source of the NMOS transistor NM9, one end of the resistor R9 and one end of the resistor R10 and serve as the second output end of the reference voltage circuit, the emitter of the transistor Q1 is connected to one end of the resistor R4, the emitter of the transistor Q2 is connected to the collector of the transistor Q2, and the base of the transistor Q1 is connected to the base of the transistor Q2, the source of the NMOS transistor NM9, one end of the resistor R9 and one end of the resistor R10. The electrode of the PMOS tube PM13 is connected to the other end of the resistor R4 and one end of the resistor R5, the drain of the PMOS tube PM13 is connected to the source of the NMOS tube NM5 and the drain of the NMOS tube NM4, the gate of the NMOS tube NM5 serves as the first input end of the reference voltage circuit, the gate of the NMOS tube NM4 serves as the second input end of the reference voltage circuit, the drain of the PMOS tube PM8 is connected to the drain of the NMOS tube NM8, the gate of the NMOS tube NM8 and the gate of the NMOS tube NM9, the source of the NMOS tube NM8 is connected to the collector of the transistor Q3 and the base of the transistor Q3, the other end of the resistor R7 is connected to the drain of the NMOS tube NM9, the other end of the resistor R8 is connected to the drain of the NMOS tube NM12,The source of the NMOS tube NM12 is connected to the other end of the resistor R9 and serves as the third output end of the reference voltage circuit to generate the reference voltage vref. The other end of the resistor R5, the other end of the capacitor C1, the source of the NMOS tube NM4, the emitter of the transistor Q3 and the other end of the resistor R10 are grounded.

[0024] The LDO circuit includes a PMOS tube PM9, a PMOS tube PM10, an NMOS tube NM13, an NMOS tube NM14, an NMOS tube NM10, an NMOS tube NM1, an NMOS tube NM7, an NMOS tube NM6, a resistor R11, a resistor R12, a resistor R13, a capacitor C2 and a capacitor C3. One end of the resistor R11 and the source of the PMOS tube PM10 are connected to the system power supply Vsys, the other end of the resistor R11 is connected to the source of the PMOS tube PM9, the gate of the PMOS tube PM9 serves as the first input end of the LDO circuit, the drain of the PMOS tube PM9 is connected to the gate of the PMOS tube PM10 and the drain of the NMOS tube NM13, the drain of the PMOS tube PM10 is connected to the drain of the NMOS tube NM14, one end of the capacitor C2, one end of the resistor R12, and one end of the capacitor C3 are connected as the output end of the LDO circuit to generate an output signal vcc_int, and the NMOS The gate of the S transistor NM13 is connected to the gate of the NMOS transistor NM14 and serves as the second input terminal of the LDO circuit, the source of the NMOS transistor NM13 is connected to the other end of the capacitor C2 and the drain of the NMOS transistor NM10, the source of the NMOS transistor NM14 is connected to the drain of the NMOS transistor NM11, the gate of the NMOS transistor NM10 serves as the third input terminal of the LDO circuit, the gate of the NMOS transistor NM11 is connected to the other end of the resistor R12 and one end of the resistor R13, the source of the NMOS transistor NM10 is connected to the source of the NMOS transistor NM11 and the drain of the NMOS transistor NM7, the gate of the NMOS transistor NM7 serves as the fourth input terminal of the LDO circuit, the source of the NMOS transistor NM7 is connected to the drain of the NMOS transistor NM6, the gate of the NMOS transistor NM6 serves as the fifth input terminal of the LDO circuit, and the source of the NMOS transistor NM6, the other end of the resistor R13 and the other end of the capacitor C3 are grounded.

[0025] When the enable signal EN = 0, the high voltage startup circuit is in the off state, and when the enable signal EN = 1, the high voltage startup circuit starts to work. The voltage across the resistor R1 is equal to the gate-source voltage Vgs_pm1 of the PMOS tube PM1, so the bias current generated is a fixed value Vgs_pm1 / R1.

[0026] Transistor Q1, transistor Q2, resistor R4, resistor R5, PMOS transistor PM11 and PMOS transistor PM12 form a bandgap reference loop. The base voltage of transistor Q1 and transistor Q2 is Vbg, so the reference voltage vref=(1+R9 / R10)*Vbg.

[0027] The PMOS tube PM13, the NMOS tube NM4, the NMOS tube NM5, the resistor R6, the PMOS tube PM5, the PMOS tube PM6, the PMOS tube PM3, the PMOS tube PM4 and the bandgap reference loop form a large feedback loop to ensure the stability of Vbg.

[0028] PMOS tube PM7, PMOS tube PM8, NMOS tube NM8, NMOS tube NM9, transistor Q3 and resistor R7 form a fast startup path to ensure that the circuit can be established more quickly. When the circuit is stably established, the path will not have additional impact on the main circuit.

[0029] NMOS tube NM10 and NMOS tube NM11 are the input pair of tubes of the LDO circuit. The current mirror formed by PMOS tube PM9 and resistor R11 is not only the active load of the LDO circuit, but also provides a fast pull-up path for the adjustment tube PMOS tube PM10, thereby ensuring the smoothness of the voltage of the output signal vcc_int.

[0030] The output signal vcc_int=(1+R12 / R13)*Vbg.

[0031] The high-voltage startup circuit of the present invention utilizes the low voltage difference characteristic of PMOS to achieve the purpose of two voltage stabilizations. The pre-voltage stabilization point is located at the gate of the NMOS tube NM12, and the second voltage stabilization point is the output signal vcc_int of the LDO circuit. On the basis of the pre-voltage stabilization point, a reference voltage vref with flexible and adjustable output voltage is realized, and at the same time, the reference voltage vref provides an input reference voltage for the LDO circuit, thereby realizing a low voltage difference and a more accurate output signal vcc_int.

[0032] The present invention provides a high-voltage startup circuit, which does not require process support for special devices and does not limit the minimum operating voltage of the system. It can provide a flexible and optional bias voltage and has a high output power supply accuracy.

[0033] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A high voltage starting circuit, characterized in that: It comprises a startup and current bias circuit, a diode D1, a reference voltage circuit and an LDO circuit, wherein an input end of the startup and current bias circuit is connected to an enable signal EN, a first output end of the startup and current bias circuit is connected to an anode of the diode D1 and a first input end of the LDO circuit, a cathode of the diode D1 is connected to a system source power supply Vsys, a second output end of the startup and current bias circuit is connected to a first input end of the reference voltage circuit and a fourth input end of the LDO circuit, a third output end of the startup and current bias circuit is connected to a second input end of the reference voltage circuit and a fifth input end of the LDO circuit, a first output end of the reference voltage circuit is connected to a second input end of the LDO circuit, a second output end of the reference voltage circuit is connected to a third input end of the LDO circuit, and an output end of the LDO circuit generates an output signal vcc_int; The startup and current bias circuit comprises a PMOS tube PM1, a PMOS tube PM2, an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3, a resistor R1, a resistor R2 and a resistor R3, the source of the PMOS tube PM1 and one end of the resistor R1 are connected to the system source power supply Vsys, the gate of the PMOS tube PM1 is connected to the other end of the resistor R1 and the source of the PMOS tube PM2, the drain of the PMOS tube PM1 is connected to one end of the resistor R2 and the gate of the PMOS tube PM2 and serves as the first output end of the startup and current bias circuit, and the resistor R2 The other end of the PMOS transistor PM2 is connected to the drain of the NMOS transistor NM1, the gate of the NMOS transistor NM1 is connected to the enable signal EN, the drain of the PMOS transistor PM2 is connected to one end of the resistor R3 and the gate of the NMOS transistor NM3 and serves as the second output end of the startup and current bias circuit, the other end of the resistor R3 is connected to the drain of the NMOS transistor NM3 and the gate of the NMOS transistor NM2 and serves as the third output end of the startup and current bias circuit, the source of the NMOS transistor NM3 is connected to the drain of the NMOS transistor NM2, and the source of the NMOS transistor NM1 and the source of the NMOS transistor NM2 are grounded; The LDO circuit comprises a PMOS tube PM9, a PMOS tube PM10, an NMOS tube NM13, an NMOS tube NM14, an NMOS tube NM10, an NMOS tube NM1, an NMOS tube NM7, an NMOS tube NM6, a resistor R11, a resistor R12, a resistor R13, a capacitor C2 and a capacitor C3, one end of the resistor R11 and the source of the PMOS tube PM10 are connected to the system source power supply Vsys, the other end of the resistor R11 is connected to the source of the PMOS tube PM9, the gate of the PMOS tube PM9 serves as the first input end of the LDO circuit, the drain of the PMOS tube PM9 is connected to the gate of the PMOS tube PM10 and the drain of the NMOS tube NM13, the drain of the PMOS tube PM10 is connected to the drain of the NMOS tube NM14, one end of the capacitor C2, one end of the resistor R12, and one end of the capacitor C3 and serve as the output end of the LDO circuit to generate an output signal vcc_int, and the NMOS tube PM14 is connected to the gate of the PMOS tube PM10 and the drain of the NMOS tube NM13. The gate of the OS transistor NM13 is connected to the gate of the NMOS transistor NM14 and serves as the second input terminal of the LDO circuit, the source of the NMOS transistor NM13 is connected to the other end of the capacitor C2 and the drain of the NMOS transistor NM10, the source of the NMOS transistor NM14 is connected to the drain of the NMOS transistor NM11, the gate of the NMOS transistor NM10 serves as the third input terminal of the LDO circuit, the gate of the NMOS transistor NM11 is connected to the other end of the resistor R12 and one end of the resistor R13, the source of the NMOS transistor NM10 is connected to the source of the NMOS transistor NM11 and the drain of the NMOS transistor NM7, the gate of the NMOS transistor NM7 serves as the fourth input terminal of the LDO circuit, the source of the NMOS transistor NM7 is connected to the drain of the NMOS transistor NM6, the gate of the NMOS transistor NM6 serves as the fifth input terminal of the LDO circuit, the source of the NMOS transistor NM6, the other end of the resistor R13 and the other end of the capacitor C3 are grounded.

2. A high voltage starting circuit according to claim 1, characterized in that: The reference voltage circuit comprises PMOS tube PM3, PMOS tube PM4, PMOS tube PM5, PMOS tube PM6, PMOS tube PM7, PMOS tube PM8, PMOS tube PM11, PMOS tube PM12, PMOS tube PM13, NMOS tube NM4, NMOS tube NM5, NMOS tube NM8, NMOS tube NM9, NMOS tube NM12, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, transistor Q1, transistor Q2, transistor Q3 and capacitor C1, the source of PMOS tube PM3, the source of PMOS tube PM5, the source of PMOS tube PM7, one end of resistor R7 The gate of the PMOS tube PM3 is connected to the gate of the PMOS tube PM5, the gate of the PMOS tube PM7, the drain of the PMOS tube PM6 and one end of the resistor R6, the drain of the PMOS tube PM3 is connected to the source of the PMOS tube PM4, the drain of the PMOS tube PM5 is connected to the source of the PMOS tube PM6, the drain of the PMOS tube PM7 is connected to the source of the PMOS tube PM8, the gate of the PMOS tube PM4 is connected to the gate of the PMOS tube PM6, the gate of the PMOS tube PM8, the other end of the resistor R6 and the drain of the NMOS tube NM5, the drain of the PMOS tube PM4 is connected to the source of the PMOS tube PM11, the PMOS tube PM12 and the PMOS tube PM13. The source of the OS transistor PM12, the source of the PMOS transistor PM13 and the upper stage of the NMOS transistor NM12 are connected and serve as the first output end of the reference voltage circuit, the gate of the PMOS transistor PM11 is connected to the gate of the PMOS transistor PM12, the drain of the PMOS transistor PM11 and the collector of the transistor Q1, the drain of the PMOS transistor PM12 is connected to the collector of the transistor Q2, one end of the capacitor C1 and the gate of the PMOS transistor PM13, the base of the transistor Q1 is connected to the base of the transistor Q2, the source of the NMOS transistor NM9, one end of the resistor R9 and one end of the resistor R10 and serve as the second output end of the reference voltage circuit, the emitter of the transistor Q1 is connected to one end of the resistor R4, the emitter of the transistor Q2 is connected to the collector of the transistor Q2, and the emitter of the transistor Q1 is connected to the collector of the transistor Q2. The emitter is connected to the other end of the resistor R4 and one end of the resistor R5, the drain of the PMOS tube PM13 is connected to the source of the NMOS tube NM5 and the drain of the NMOS tube NM4, the gate of the NMOS tube NM5 serves as the first input end of the reference voltage circuit, the gate of the NMOS tube NM4 serves as the second input end of the reference voltage circuit, the drain of the PMOS tube PM8 is connected to the drain of the NMOS tube NM8, the gate of the NMOS tube NM8 and the gate of the NMOS tube NM9, the source of the NMOS tube NM8 is connected to the collector of the transistor Q3 and the base of the transistor Q3, the other end of the resistor R7 is connected to the drain of the NMOS tube NM9, the other end of the resistor R8 is connected to the drain of the NMOS tube NM12,The source of the NMOS tube NM12 is connected to the other end of the resistor R9 and serves as the third output end of the reference voltage circuit to generate the reference voltage vref. The other end of the resistor R5, the other end of the capacitor C1, the source of the NMOS tube NM4, the emitter of the transistor Q3 and the other end of the resistor R10 are grounded.

3. A high voltage starting circuit according to claim 2, characterized in that: The transistor Q1, the transistor Q2, the resistor R4, the resistor R5, the PMOS transistor PM11 and the PMOS transistor PM12 form a bandgap reference loop, and the base voltages of the transistor Q1 and the transistor Q2 are Vbg.

4. A high voltage starting circuit according to claim 3, characterized in that: The PMOS tube PM13, NMOS tube NM4, NMOS tube NM5, resistor R6, PMOS tube PM5, PMOS tube PM6, PMOS tube PM3, PMOS tube PM4 and the bandgap reference loop form a large feedback loop to ensure the stability of Vbg.

5. A high voltage starting circuit according to claim 2, characterized in that: The PMOS transistor PM7, the PMOS transistor PM8, the NMOS transistor NM8, the NMOS transistor NM9, the transistor Q3 and the resistor R7 form a fast start path.

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