Memory management method and device, computer system and related equipment

Abstract

The invention discloses a memory management method and device, a computer system and related equipment, and the memory management method comprises the steps: obtaining a first memory distribution request of a thread, the first memory distribution request being used for requesting to distribute a corresponding first memory block; when a first memory allocation request of a thread is obtained, obtaining information of a CPU running the thread; according to the information of the CPU of the running thread, obtaining a Per-CPU page frame cache of the CPU of the running thread; when the corresponding first memory block exists in the Per-CPU page frame cache, the corresponding first memory block is acquired from the Per-CPU page frame cache and allocated to the thread; when the corresponding first memory block does not exist in the Per-CPU page frame cache, performing first filling processing on the Per-CPU page frame cache; and after first filling processing is carried out on the Per-CPU page frame cache, obtaining a corresponding first memory block from the Per-CPU page frame cache and allocating the first memory block to the thread. According to the technical scheme, affinity of thread data can be achieved, and locality of memory access of the processor is kept.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and specifically to a memory management method, apparatus, computer system, and related equipment. Background Art

[0002] Computer systems including multiple processors are usually configured as non-uniform memory access (NUMA) architectures, where multiple processors can be configured to form multiple NUMA nodes, and the access speed between processors and memory located in the same NUMA node is significantly faster than the access speed across NUMA nodes.

[0003] Therefore, in a computer system adopting a NUMA architecture, how to achieve thread data affinity and maintain the locality of processor memory access has become a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0004] In view of this, embodiments of the present application provide a memory management method, apparatus, computer system and related equipment, which can achieve thread data affinity and maintain the locality of processor memory access.

[0005] To achieve the above objectives, the present application provides the following technical solutions:

[0006] The present invention provides a memory management method, comprising:

[0007] Obtaining a first memory allocation request of a thread, where the first memory allocation request is used to request allocation of a corresponding first memory block;

[0008] When the first memory allocation request of the thread is obtained, obtaining information of the CPU running the thread;

[0009] According to the information of the CPU running the thread, obtaining the Per-CPU page frame cache of the CPU running the thread;

[0010] When a corresponding first memory block exists in the Per-CPU page frame cache, obtaining a corresponding first memory block from the Per-CPU page frame cache and allocating it to the thread;

[0011] When the corresponding first memory block does not exist in the Per-CPU page frame cache, a first filling process is performed on the Per-CPU page frame cache; after the first filling process is performed on the Per-CPU page frame cache, a corresponding first memory block is obtained from the Per-CPU page frame cache and allocated to the thread.

[0012] Optionally, the obtaining the information of the CPU running the thread includes: using a restartable sequence mechanism to obtain the information of the CPU running the thread in real time.

[0013] Optionally, performing a first filling process on the Per-CPU page frame cache includes:

[0014] According to the information of the CPU running the thread, obtain the information of the target NUMA node to which the CPU running the thread belongs;

[0015] According to the information of the target NUMA node, a first memory block is obtained from the corresponding NUMA cache and filled into the Per-CPU page frame cache.

[0016] Optionally, when the corresponding NUMA cache cannot meet the filling requirement of the Per-CPU page frame cache, the first filling process is performed on the Per-CPU page frame cache, and the memory management method further includes:

[0017] According to the information of the target NUMA node, obtain a second memory block from a corresponding NUMA page heap, where the second memory block is larger than the first memory block;

[0018] Slice the second memory block obtained from the corresponding NUMA page heap to obtain a corresponding plurality of first memory blocks;

[0019] Filling the plurality of first memory blocks into corresponding NUMA caches;

[0020] After the plurality of first memory blocks are filled into the corresponding NUMA cache, the corresponding first memory blocks are obtained from the corresponding NUMA cache and filled into the Per-CPU page frame cache.

[0021] Optionally, when the corresponding NUMA page heap cannot meet the filling requirement of the corresponding NUMA cache, a first filling process is performed on the Per-CPU page frame cache, and the memory management method further includes:

[0022] According to the target NUMA node, obtaining a second memory block from a corresponding local virtual memory space and filling it into the corresponding NUMA page heap;

[0023] After obtaining a second memory block from the corresponding local virtual memory space and filling it into the corresponding NUMA page heap, obtaining a second memory block from the corresponding NUMA page heap;

[0024] Slice the second memory block obtained from the corresponding NUMA page heap to obtain a corresponding plurality of first memory blocks;

[0025] Filling the plurality of first memory blocks into corresponding NUMA caches;

[0026] After the plurality of first memory blocks are filled into the corresponding NUMA cache, the corresponding first memory blocks are obtained from the corresponding NUMA cache and filled into the Per-CPU page frame cache.

[0027] Optionally, after the first memory block corresponding to the thread is completely used, the memory management method further comprises: releasing the corresponding first memory block to the Per-CPU page frame cache.

[0028] Optionally, when the first memory allocation request is used to request allocation of a corresponding second memory block, and the second memory block is larger than the first memory block, after acquiring information of a CPU running the thread, the memory management method further includes:

[0029] According to the information of the CPU running the thread, obtain the information of the target NUMA node to which the CPU running the thread belongs;

[0030] According to the information of the target NUMA node, obtain the information of the corresponding NUMA page heap;

[0031] When the corresponding second memory block exists in the corresponding NUMA page heap, obtaining the corresponding second memory block from the corresponding NUMA page heap and allocating it to the thread;

[0032] When the corresponding second memory block does not exist in the corresponding NUMA page heap, a second filling process is performed on the corresponding NUMA page heap; after the second filling process is performed on the corresponding NUMA page heap, a corresponding second memory block is obtained from the corresponding NUMA page heap and allocated to the thread.

[0033] Optionally, performing a second filling process on the corresponding NUMA page heap further includes:

[0034] According to the target NUMA node, obtaining a second memory block from a corresponding local virtual memory space and filling it into the corresponding NUMA page heap;

[0035] After obtaining a second memory block from the corresponding local virtual memory space and filling it into the corresponding NUMA page heap, a second memory block is obtained from the corresponding NUMA page heap and allocated to the thread.

[0036] Optionally, after the second memory block corresponding to the thread is completely used, the memory management method further includes: releasing the corresponding second memory block to the corresponding NUMA page heap.

[0037] Accordingly, an embodiment of the present invention further provides a memory management device, comprising:

[0038] A request obtaining unit, adapted to obtain a first memory allocation request of a thread, wherein the first memory allocation request is used to request allocation of a corresponding first memory block;

[0039] A first information acquisition unit is adapted to acquire information of a CPU running the thread when a first memory allocation request of the thread is acquired; and acquire a Per-CPU page frame cache of the CPU running the thread according to the information of the CPU running the thread;

[0040] The first filling allocation unit is adapted to obtain the corresponding first memory block from the Per-CPU page frame cache and allocate it to the thread when the corresponding first memory block exists in the Per-CPU page frame cache; perform a first filling process on the Per-CPU page frame cache when the corresponding first memory block does not exist in the Per-CPU page frame cache; and obtain the corresponding first memory block from the Per-CPU page frame cache and allocate it to the thread after performing the first filling process on the Per-CPU page frame cache.

[0041] Optionally, the first information acquisition unit is adapted to adopt a restartable sequence mechanism to acquire information of the CPU running the thread in real time.

[0042] Optionally, the first filling allocation unit is suitable for obtaining information of a target NUMA node to which the CPU running the thread belongs based on information of the CPU running the thread; and obtaining a first memory block from a corresponding NUMA cache and filling it into a Per-CPU page frame cache based on information of the target NUMA node.

[0043] Optionally, the first filling allocation unit is also suitable for obtaining a second memory block from the corresponding NUMA page heap according to information of the target NUMA node when the corresponding NUMA cache cannot meet the filling demand of the Per-CPU page frame cache, and the second memory block is larger than the first memory block; slicing the second memory block obtained from the corresponding NUMA page heap to obtain a corresponding plurality of first memory blocks; filling the plurality of first memory blocks into the corresponding NUMA cache; after filling the plurality of first memory blocks into the corresponding NUMA cache, obtaining the corresponding first memory block from the corresponding NUMA cache and filling it into the Per-CPU page frame cache.

[0044] Optionally, the first filling allocation unit is also suitable for obtaining a second memory block from the corresponding local virtual memory space and filling it into the corresponding NUMA page heap according to the target NUMA node when the corresponding NUMA page heap cannot meet the filling requirements of the corresponding NUMA cache; after obtaining the second memory block from the corresponding local virtual memory space and filling it into the corresponding NUMA page heap, obtaining the second memory block from the corresponding NUMA page heap; slicing the second memory block obtained from the corresponding NUMA page heap to obtain a corresponding plurality of first memory blocks; filling the plurality of first memory blocks into the corresponding NUMA cache; after filling the plurality of first memory blocks into the corresponding NUMA cache, obtaining the corresponding first memory block from the corresponding NUMA cache and filling it into the Per-CPU page frame cache.

[0045] Optionally, the memory management device further includes: a first releasing unit, adapted to release the corresponding first memory block to the Per-CPU page frame cache after the first memory block corresponding to the thread has been used up.

[0046] Optionally, the memory management device further includes:

[0047] a second information acquisition unit adapted to, when the first memory allocation request is used to request allocation of a corresponding second memory block, and the second memory block is larger than the first memory block, after acquiring information about a CPU running the thread, acquire information about a target NUMA node to which the CPU running the thread belongs according to the information about the CPU running the thread; and acquire information about a corresponding NUMA page heap according to the information about the target NUMA node;

[0048] The second filling allocation unit is suitable for obtaining the corresponding second memory block from the corresponding NUMA page heap and allocating it to the thread when the corresponding second memory block exists in the corresponding NUMA page heap; performing a second filling process on the corresponding NUMA page heap when the corresponding second memory block does not exist in the corresponding NUMA page heap; and obtaining the corresponding second memory block from the corresponding NUMA page heap and allocating it to the thread after performing the second filling process on the corresponding NUMA page heap.

[0049] Optionally, the second filling allocation unit is also suitable for obtaining a second memory block from the corresponding local virtual memory space and filling it into the corresponding NUMA page heap according to the target NUMA node; after obtaining the second memory block from the corresponding local virtual memory space and filling it into the corresponding NUMA page heap, obtaining the second memory block from the corresponding NUMA page heap and allocating it to the thread.

[0050] Optionally, the memory management device further includes: a second releasing unit, adapted to release the corresponding second memory block to the corresponding NUMA page heap after the second memory block corresponding to the thread has been used up.

[0051] Correspondingly, an embodiment of the present invention further provides a computer system, comprising a memory management device, wherein the memory management device is configured to execute any one of the above-mentioned memory management methods.

[0052] Correspondingly, an embodiment of the present invention further provides a computer program product, including a computer program / instruction, wherein the computer program / instruction is used to implement any of the above-mentioned memory management methods when executed by a processor.

[0053] Correspondingly, an embodiment of the present invention further provides a storage medium, wherein the storage medium stores one or more computer executable instructions, and the one or more computer executable instructions are used to execute any of the memory management methods described above.

[0054] Compared with the prior art, the technical solution of the embodiment of the present application has the following advantages:

[0055] An embodiment of the present invention provides a memory management method, the method comprising: obtaining a first memory allocation request of a thread, the first memory allocation request being used to request allocation of a corresponding first memory block; when the first memory allocation request of the thread is obtained, obtaining information of a CPU running the thread; according to the information of the CPU running the thread, obtaining a Per-CPU page frame cache of the CPU running the thread; when a corresponding first memory block exists in the Per-CPU page frame cache, obtaining the corresponding first memory block from the Per-CPU page frame cache and allocating it to the thread; when the corresponding first memory block does not exist in the Per-CPU page frame cache, performing a first filling process on the Per-CPU page frame cache; after performing the first filling process on the Per-CPU page frame cache, obtaining the corresponding first memory block from the Per-CPU page frame cache and allocating it to the thread.

[0056] In the memory management method in the embodiment of the present invention, when there is a corresponding first memory block in the Per-CPU page frame cache of the CPU running the thread, the corresponding first memory block is obtained from the Per-CPU page frame cache and allocated to the thread; when there is no corresponding first memory block in the Per-CPU page frame cache, the Per-CPU page frame cache is first filled; after the Per-CPU page frame cache is first filled, the corresponding first memory block is obtained from the Per-CPU page frame cache and allocated to the thread. Therefore, the affinity of thread data can be achieved, the locality of CPU memory access is ensured, and the CPU's access to remote memory is avoided, which is conducive to improving the CPU's access speed to memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0058] Figure 1 A flowchart of an embodiment of a memory management method provided by the technical solution of the present invention;

[0059] Figure 2 Schematic diagram of the Per-CPU page frame cache of the CPU in an embodiment of the present invention;

[0060] Figure 3 A schematic diagram of a NUMA cache of a NUMA node in an embodiment of the present invention;

[0061] Figure 4 Schematic diagram of a NUMA page heap of a NUMA node in an embodiment of the present invention;

[0062] Figure 5 A schematic diagram of the correspondence between the local virtual memory space and the physical memory of a NUMA node in an embodiment of the present invention;

[0063] Figure 6 A flowchart of another embodiment of the memory management method provided by the technical solution of the present invention;

[0064] Figure 7 A schematic structural diagram of an embodiment of a memory management device provided by the technical solution of the present invention. DETAILED DESCRIPTION

[0065] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0066] Based on the background technology, in a computer system using NUMA architecture, the access speed of processors located in the same NUMA node to memory is significantly faster than the access speed to memory across NUMA nodes. Therefore, how to achieve thread data affinity, maintain the locality of CPU memory access, and avoid remote access has become a technical problem that technicians in this field need to solve urgently.

[0067] Based on this, an embodiment of the present invention provides a memory management method, the method comprising: obtaining a first memory allocation request of a thread, the first memory allocation request being used to request allocation of a corresponding first memory block; when the first memory allocation request of the thread is obtained, obtaining information of a CPU running the thread; according to the information of the CPU running the thread, obtaining a Per-CPU page frame cache of the CPU running the thread; when a corresponding first memory block exists in the Per-CPU page frame cache, obtaining a corresponding first memory block from the Per-CPU page frame cache and allocating it to the thread; when a corresponding first memory block does not exist in the Per-CPU page frame cache, performing a first filling process on the Per-CPU page frame cache; after performing the first filling process on the Per-CPU page frame cache, obtaining a corresponding first memory block from the Per-CPU page frame cache and allocating it to the thread.

[0068] In the memory management method in the embodiment of the present invention, when there is a corresponding first memory block in the Per-CPU page frame cache of the CPU running the thread, the corresponding first memory block is obtained from the Per-CPU page frame cache and allocated to the thread; when there is no corresponding first memory block in the Per-CPU page frame cache, the Per-CPU page frame cache is first filled; after the Per-CPU page frame cache is first filled, the corresponding first memory block is obtained from the Per-CPU page frame cache and allocated to the thread. Therefore, the affinity of thread data can be achieved, the locality of CPU memory access is ensured, and the CPU's access to remote memory is avoided, which is conducive to improving the CPU's access speed to memory.

[0069] Figure 1 The flowchart of an optional embodiment of the memory management method provided by the technical solution of the present invention is shown. Figure 1, a memory management method may specifically include the following steps:

[0070] Step S110: obtaining a first memory allocation request of a thread, where the first memory allocation request is used to request allocation of a corresponding first memory block;

[0071] Step S120: when the first memory allocation request of the thread is obtained, obtaining information of the CPU running the thread;

[0072] Step S130: acquiring the Per-CPU page frame cache of the CPU running the thread according to the information of the CPU running the thread;

[0073] Step S140: determine whether there is a corresponding first memory block in the Per-CPU page frame cache; when the determination result is yes, step S160 can be directly executed; when the determination result is no, steps S150 and S160 can be executed in sequence;

[0074] Step S150: performing a first filling process on the Per-CPU page frame buffer;

[0075] Step S160: Obtain a corresponding first memory block from the Per-CPU page frame cache and allocate it to the thread.

[0076] Please continue to refer to Figure 1 , execute step S110 to obtain a first memory allocation request of the thread, where the first memory allocation request is used to request allocation of a corresponding first memory block.

[0077] Obtaining the first memory allocation request of the thread provides a basis for subsequently obtaining information of the CPU running the thread when the first memory allocation request of the thread is obtained.

[0078] During execution, the thread may generate a first memory allocation request according to actual needs to request a memory space of a specified size. Specifically, the thread may send the first memory allocation request using a corresponding memory allocation function, wherein the memory allocation function includes a parameter for indicating the size of the memory space requested to be allocated.

[0079] As an example, the memory allocation function is a dynamic memory allocation (malloc) function, wherein the malloc function is used to request allocation of continuous memory with a specified size.

[0080] In other embodiments, other types of memory allocation functions other than the malloc function can be used to send the first memory allocation request. Those skilled in the art can set it according to actual needs and it is not limited here.

[0081] Generally speaking, the operation executed by the thread is relatively simple. Therefore, the memory space required by the thread during execution is relatively small. Accordingly, the first memory block requested to be allocated by the first memory allocation request can also be called a small memory block.

[0082] The size of the first memory block can be configured by those skilled in the art according to actual needs. As an example, the size of the first memory block is 128KB. It is understandable that the size of the first memory block can also be other values, which are not limited here.

[0083] According to actual needs of thread execution, the number of first memory blocks requested to be allocated by the first memory allocation request may be one or more.

[0084] Please continue to refer to Figure 1 , execute step S120, when the first memory allocation request of the thread is obtained, obtain information of the CPU running the thread.

[0085] When the first memory allocation request of the thread is obtained, information of the CPU running the thread is obtained, providing a basis for subsequently obtaining the Per-CPU page frame cache of the CPU running the thread according to the information of the CPU running the thread.

[0086] In an exemplary embodiment, the step of acquiring information about a CPU running the thread includes: acquiring information about the CPU running the thread in real time.

[0087] According to actual needs, in a computer system adopting a NUMA architecture, a thread can be run on a fixed CPU or migrated from one CPU to another CPU to ensure the high efficiency of thread execution. In the embodiment of the present invention, whether the thread is running on a fixed CPU or the thread is migrated from one CPU to another CPU, obtaining the information of the CPU running the thread refers to obtaining the information of the current CPU running the thread.

[0088] In an exemplary embodiment, a restartable sequences (rseq) mechanism is used to obtain information of the CPU running the thread in real time.

[0089] As a kernel mechanism, the restartable sequence mechanism enables the operation of obtaining the information of the CPU running the thread in real time to be atomically executed in the user state without being interrupted, or even if it is interrupted during execution, the operating system will automatically restart the sequence to execute the operation of obtaining the information of the CPU running the thread in real time, so that the operation of obtaining the information of the CPU running the thread in real time can be finally completed. Therefore, the use of the restartable sequence mechanism to obtain the information of the CPU running the thread in real time can improve the execution efficiency of the operation of obtaining the information of the CPU running the thread in real time.

[0090] In other embodiments, the information of the CPU running the thread can also be obtained in real time through the corresponding system call function. Those skilled in the art can select according to actual needs and are not limited here.

[0091] In an exemplary embodiment, the information of the CPU running the thread is an ID of the CPU running the thread. The ID of the CPU is used to uniquely identify the CPU. Accordingly, by obtaining the ID CPU-ID of the CPU running the thread, the CPU running the thread can be uniquely determined.

[0092] Please continue to refer to Figure 1 , execute step S130, and obtain the Per-CPU page frame cache of the CPU running the thread according to the information of the CPU running the thread.

[0093] According to the information of the CPU running the thread, a per-CPU (Per-CPU) page frame cache of the CPU running the thread is obtained, providing a basis for subsequent determination whether a corresponding first memory block exists in the Per-CPU page frame cache.

[0094] In a computer system using a NUMA architecture, each of the multiple CPUs is provided with a corresponding Per-CPU page frame cache. In other words, there is a one-to-one correspondence between the CPU and the Per-CPU page frame cache, and the Per-CPU page frame cache is a local cache or private cache of each CPU.

[0095] Accordingly, after obtaining the information of the CPU running the thread, the Per-CPU page frame cache of the CPU running the thread can be obtained according to the one-to-one correspondence between the CPU and the Per-CPU page frame cache.

[0096] Generally speaking, the CPU applies for and releases a single first memory block most frequently. By pre-storing multiple first memory blocks in the Per-CPU page frame cache, the CPU can be allowed to access the first memory block locally.

[0097] Please refer to Figure 2 , a first memory block in the Per-CPU page frame cache includes a plurality of first memory blocks region 0 to region Y allocated to a plurality of threads Thread 0 to Thread X. Wherein, X and Y are integers greater than or equal to 1 respectively.

[0098] Please continue to refer to Figure 1 , execute step S140 to determine whether there is a corresponding first memory block in the Per-CPU page frame cache; when the judgment result is yes, step S160 can be directly executed; when the judgment result is no, steps S150 and S160 can be executed in sequence.

[0099] In an exemplary embodiment, the first memory block cached in the Per-CPU page frame cache is stored in a linked list pointed to by a Per-CPU variable pointer _percpu*pageset, wherein the Per-CPU variable pointer _percpu*pageset is stored locally in the CPU running the thread.

[0100] Accordingly, by accessing the linked list pointed to by the Per-CPU variable pointer _percpu*pageset stored locally in the CPU, it can be determined whether the corresponding first memory block exists in the Per-CPU page frame cache.

[0101] Please continue to refer to Figure 1 , execute step S150 to perform a first filling process on the Per-CPU page frame cache.

[0102] When the corresponding first memory block does not exist in the Per-CPU page frame cache of the CPU running the thread, a first filling process is performed on the Per-CPU page frame cache to provide a basis for subsequently obtaining the corresponding first memory block from the Per-CPU page frame cache and allocating it to the thread.

[0103] It is understandable that the number of first memory blocks in the Per-CPU page frame cache is limited, and as time goes by, the first memory blocks in the Per-CPU page frame cache are also in a dynamic change process. Therefore, when receiving the first memory allocation request of the thread, the Per-CPU page frame cache of the CPU running the thread may contain one or more corresponding first memory blocks requested by the first memory allocation request, or may not contain one or more corresponding first memory blocks requested by the first memory allocation request.

[0104] Accordingly, when the corresponding one or more first memory blocks requested by the first memory allocation request do not exist in the Per-CPU page frame cache of the CPU running the thread, step S150 may be performed first.

[0105] In an exemplary embodiment, the step of performing a first filling process on the Per-CPU page frame cache includes: obtaining information of a target NUMA node to which the CPU running the thread belongs based on information of the CPU running the thread; and obtaining a first memory block from a corresponding NUMA cache and filling it into the Per-CPU page frame cache based on information of the target NUMA node.

[0106] In a computer system using the NUMA architecture, each NUMA node includes a corresponding NUMA cache. When each NUMA node includes multiple CPUs, the NUMA cache of the NUMA node, also known as the central cache, is located between the multiple CPUs and memory of the NUMA node. It is a local shared high-speed cache of multiple CPUs in the NUMA node, and its read and write speed is faster than that of the memory of the NUMA node, so that instructions and data can be provided to the CPU at high speed, thereby improving the execution speed of the application.

[0107] Please refer to Figure 3 A computer system using a NUMA architecture includes a plurality of NUMA nodes Node0 to Node N, and a NUMA cache of each NUMA node Node i includes first memory blocks stored in a plurality of free lists Free List 0 to Free List P, respectively. Where i is an integer greater than or equal to 0 and less than or equal to N, and P is an integer greater than or equal to 1.

[0108] Accordingly, when the corresponding first memory block does not exist in the Per-CPU page frame cache of the CPU running the thread, the first memory block in an idle state can be obtained from the corresponding NUMA cache and filled into the Per-CPU page frame cache, so that the Per-CPU page frame cache of the CPU running the thread has the first memory block that can be allocated to the thread.

[0109] Obtaining the first memory block from the corresponding NUMA cache and filling it into the Per-CPU page frame cache refers to adding the first memory block obtained from the corresponding NUMA cache to the linked list pointed to by the Per-CPU variable pointer _percpu*pageset of the CPU running the thread.

[0110] In an exemplary embodiment, the NUMA cache may adopt a multi-level hierarchical structure, wherein the NUMA cache at the first level has the smallest cache space and the shortest access delay time, and the cache space and access delay time of the NUMA cache at other levels gradually increase.

[0111] Accordingly, the first memory block may be obtained from the corresponding NUMA cache in descending order of hierarchy and filled into the Per-CPU page frame cache of the CPU running the thread.

[0112] As an example, the NUMA cache has a two-level hierarchical structure, that is, the NUMA cache includes a first-level NUMA cache and a second-level NUMA cache. Accordingly, the corresponding first memory block is first obtained from the first-level NUMA cache to be filled into the Per-CPU page frame cache of the CPU running the thread; when the first-level NUMA cache does not have an idle first memory block or the first memory block in the first-level NUMA cache is insufficient to meet the filling requirement of the Per-CPU page frame cache of the CPU running the thread, the corresponding first memory block is obtained from the second-level NUMA cache to be filled into the Per-CPU page frame cache of the CPU running the thread.

[0113] In other embodiments, the NUMA cache can also adopt a three-level hierarchical structure or more levels of NUMA cache, and those skilled in the art can set it according to actual needs, which is not limited here.

[0114] It is understandable that the cache space of the NUMA cache is limited. Therefore, when the first filling process is performed on the Per-CPU page frame cache, there may be a situation where there are no remaining first memory blocks in the corresponding NUMA cache or the remaining first memory blocks cannot meet the filling requirements of the Per-CPU page frame cache.

[0115] Accordingly, when the corresponding NUMA cache cannot meet the filling requirements of the Per-CPU page frame cache, the step of performing a first filling process on the Per-CPU page frame cache also includes: obtaining a second memory block from the corresponding NUMA page heap according to the information of the target NUMA node, the second memory block being larger than the first memory block; slicing the second memory block obtained from the corresponding NUMA page heap to obtain a corresponding plurality of first memory blocks; filling the plurality of first memory blocks into the corresponding NUMA cache; after filling the plurality of first memory blocks into the corresponding NUMA cache, obtaining the corresponding first memory block from the corresponding NUMA cache and filling it into the Per-CPU page frame cache.

[0116] Combined with reference Figure 4, taking a computer system using NUMA architecture including multiple NUMA nodes Node0~Node N as an example, each NUMA node Node i (i is an integer greater than or equal to 0 and less than or equal to N) includes a corresponding NUMA page heap. The NUMA page heap of each NUMA node is an independent virtual memory space in the local memory of each NUMA node, in which multiple idle memory blocks are stored in a step-by-step manner, and the size of each memory block is 2 order KB, where order is an integer greater than or equal to 2.

[0117] Accordingly, when the corresponding NUMA cache cannot meet the filling requirement of the Per-CPU page frame cache, a second memory block can be obtained from the corresponding NUMA page heap. The second memory block is larger than the first memory block. Specifically, the storage capacity of the second memory block is an integer multiple of the storage capacity of the first memory block.

[0118] Therefore, after obtaining the second memory block from the corresponding NUMA page heap, the obtained corresponding second memory block is divided into multiple first memory blocks, and the obtained multiple first memory blocks are filled into the corresponding NUMA cache, and then the corresponding first memory block is obtained from the corresponding NUMA cache and filled into the Per-CPU page frame cache.

[0119] In an exemplary embodiment, the second memory block is a memory page. Specifically, the second memory block is 256KB. It is understandable that the storage capacity of the second memory block can also be other values, which are not limited here.

[0120] It is understandable that the number of second memory blocks in the NUMA page heap is limited and is in dynamic change. Therefore, when the Per-CPU page frame cache is first filled, there may be a situation where there are no remaining second memory blocks in the corresponding NUMA page heap.

[0121] Accordingly, when the corresponding NUMA page heap cannot meet the filling requirements of the corresponding NUMA cache, the step of performing a first filling process on the Per-CPU page frame cache also includes: according to the target NUMA node, obtaining a second memory block from the corresponding local virtual memory space and filling it into the corresponding NUMA page heap; after obtaining the second memory block from the corresponding local virtual memory space and filling it into the corresponding NUMA page heap, obtaining the second memory block from the corresponding NUMA page heap and allocating it to the thread.

[0122] In an exemplary embodiment, according to the target NUMA node, the step of obtaining a second memory block from the corresponding local virtual memory space and filling it into the corresponding NUMA page heap includes: sending a second memory allocation request to the kernel, the second memory allocation request including information of the target NUMA node, so that the kernel allocates the corresponding second memory block from the corresponding local virtual memory space according to the target NUMA node; and filling the second memory block allocated by the kernel into the corresponding NUMA page heap.

[0123] In an exemplary embodiment, a memory mapping (mmp) function is used to send the second memory allocation request to the kernel, wherein the parameter of the mmp function includes the information of the target NUMA node.

[0124] A computer system using a NUMA architecture may include multiple NUMA nodes, and the physical memory of the computer system using the NUMA architecture is logically divided into multiple virtual memory areas according to the NUMA nodes, and a preset memory binding (mbind) function is used to establish a one-to-one mapping relationship between multiple NUMA nodes and multiple virtual memory areas. Accordingly, the virtual memory area bound to the NUMA node is the local virtual memory space of the NUMA node.

[0125] Please refer to Figure 5 , taking a computer system using NUMA architecture including 8 NUMA nodes as an example, a 4096G virtual memory area with a first address of 0x400-0000-0000 is allocated to NUMA node 0, a 4096G virtual memory area with a first address of 0x800-0000-0000 is allocated to NUMA node 1, ..., a 4096G virtual memory area with a first address of 0x2000-0000-0000 is allocated to NUMA node 7. Here, the first address refers to the first address of the virtual address.

[0126] Correspondingly, the 4096G virtual memory area with the first address 0x4000000-0000 is called the local virtual memory space of NUMA node 0, the 4096G virtual memory area with the first address 0x8000000-0000 is called the local virtual memory space of NUMA node 1, and so on. The 4096G virtual memory area with the first address 0x2000-0000-0000 is called the local virtual memory space of NUMA node 7.

[0127] When receiving the second memory allocation request, the kernel parses the second memory allocation request to obtain the information of the target NUMA node, and based on the information of the target NUMA node, searches for some free virtual memory space from the corresponding virtual memory area to allocate to the NUMA page heap of the target NUMA node.

[0128] Please continue to refer to Figure 5 , when the target NUMA node is NUMA node 0, the kernel will obtain the corresponding virtual memory space in an idle state from the 4096G virtual memory area with a first address of 0x400-0000-0000 and allocate it to NUMA node 0; when the target NUMA node is NUMA node 1, the kernel will obtain the corresponding virtual memory space in an idle state from the 4096G virtual memory area with a first address of 0x800-0000-0000 and allocate it to NUMA node 1; ...; when the target NUMA node is NUMA node 7, the kernel will obtain the corresponding virtual memory space in an idle state from the 4096G virtual memory area with a first address of 0x2000-0000-0000 and allocate it to NUMA node 7.

[0129] The virtual memory spaces corresponding to the above-mentioned NUMA nodes are equal only as an example. It is understandable that the sizes of the local virtual memory spaces of the NUMA nodes can also be at least partially different, and those skilled in the art can configure them as needed, which is not limited here.

[0130] After filling the corresponding NUMA page heap with the virtual memory space allocated by the kernel, the steps of obtaining the corresponding second memory block from the corresponding NUMA page heap are executed; the second memory block obtained from the corresponding NUMA page heap is cut into blocks to obtain corresponding multiple first memory blocks; the multiple first memory blocks are filled into the corresponding NUMA cache; after filling the multiple first memory blocks into the corresponding NUMA cache, the corresponding first memory block is obtained from the corresponding NUMA cache and filled into the Per-CPU page frame cache.

[0131] Among them, regarding obtaining the corresponding second memory block from the corresponding NUMA page heap; slicing the second memory block obtained from the corresponding NUMA page heap to obtain corresponding multiple first memory blocks; filling the multiple first memory blocks into the corresponding NUMA cache; after filling the multiple first memory blocks into the corresponding NUMA cache, obtaining the corresponding first memory block from the corresponding NUMA cache and filling it into the Per-CPU page frame cache, please refer to the description of the relevant parts in the aforementioned steps and will not be repeated here.

[0132] Please continue to refer to Figure 1 , execute step S160, obtain the corresponding first memory block from the Per-CPU page frame cache and allocate it to the thread.

[0133] When the corresponding first memory block exists in the Per-CPU page frame cache, the step of obtaining the corresponding first memory block from the Per-CPU page frame cache and allocating it to the thread can be directly executed. Alternatively, when the corresponding first memory block does not exist in the Per-CPU page frame cache, after performing a first filling process on the Per-CPU page frame cache, the step of obtaining the corresponding first memory block from the Per-CPU page frame cache and allocating it to the thread is executed.

[0134] The Per-CPU page frame cache of the CPU running the thread is a local private cache of the CPU running the thread, in which the first memory block in an idle state can be directly applied for use by the CPU running the thread without the need for synchronization between the various CPUs. This can reduce the overhead introduced by operations such as locking and unlocking of the application page, and is conducive to improving the efficiency of page allocation.

[0135] More importantly, obtaining the corresponding first memory block from the Per-CPU page frame cache of the CPU running the thread and allocating it to the thread can achieve thread data affinity, maintain the locality of CPU memory access, avoid remote memory access, reduce memory access latency, and help improve memory resource management efficiency.

[0136] In an exemplary embodiment, after the first memory block corresponding to the thread is used up, the memory management method further includes: releasing the corresponding first memory block to the Per-CPU page frame cache.

[0137] As an example, a memory release (free) function is used to release the corresponding first memory block to the Per-CPU page frame cache.

[0138] After the first memory block corresponding to the thread is used up, the corresponding first memory block is released to the corresponding Per-CPU page frame cache without releasing memory in the global partner system, thereby realizing local memory release and further improving the management efficiency of memory resources.

[0139] Figure 6 The flowchart of the memory management method is shown when the first memory allocation request is used to request allocation of the corresponding second memory block. Figure 6 , when the first memory allocation request is used to request allocation of a corresponding second memory block, the memory management method comprises:

[0140] Step S610: obtaining a first memory allocation request of a thread, where the first memory allocation request is used to request allocation of a corresponding second memory block, where the second memory block is larger than the first memory block;

[0141] Step S620: when the first memory allocation request of the thread is obtained, obtaining information of the CPU running the thread;

[0142] Step S630: acquiring information of a target NUMA node to which the CPU running the thread belongs according to information of the CPU running the thread;

[0143] Step S640: acquiring corresponding NUMA page heap information according to the information of the target NUMA node;

[0144] Step S650: determine whether the corresponding second memory block exists in the corresponding NUMA page heap; when the determination result is yes, step S670 may be directly executed; when the determination result is no, steps S660 and S670 may be executed in sequence;

[0145] Step S660: performing a second filling process on the corresponding NUMA page heap;

[0146] Step S670: Obtain a corresponding second memory block from the corresponding NUMA page heap and allocate it to the thread.

[0147] In an exemplary embodiment, the step of performing a second filling process on the corresponding NUMA page heap includes: according to the target NUMA node, obtaining a second memory block from the corresponding local virtual memory space and filling it into the corresponding NUMA page heap; after obtaining the second memory block from the corresponding local virtual memory space and filling it into the corresponding NUMA page heap, obtaining the second memory block from the corresponding NUMA page heap and allocating it to the thread.

[0148] In an exemplary embodiment, after the second memory block corresponding to the thread is completely used, the memory management method further includes: releasing the corresponding second memory block to the corresponding NUMA page heap.

[0149] Combined with reference Figure 1 and Figure 6 It can be seen that the memory management method provided in the embodiment of the present invention can allocate one or more first memory blocks or one or more second memory blocks to a thread according to the first memory allocation request of the thread, wherein the second memory block is a memory block larger than the first memory block.

[0150] In an exemplary embodiment, the second memory block is also referred to as a large memory block. For example, the second memory block is a memory block greater than or equal to 256 KB, or the second memory block is one or more memory pages.

[0151] Regarding the contents of each step of the memory management method when the first memory allocation request is used to request allocation of the corresponding second memory block, please refer to the description of the corresponding contents in the memory management method when the first memory allocation request is used to request allocation of the corresponding first memory block, and no further details will be given here.

[0152] Correspondingly, an embodiment of the present invention also provides a memory management device.

[0153] Figure 7 FIG. 1 is a schematic diagram showing a structure of an embodiment of a memory management device provided by the technical method of the present invention. Figure 7 A memory management device 70 may include: a request acquisition unit 701, adapted to acquire a first memory allocation request of a thread, the first memory allocation request being used to request allocation of a corresponding first memory block; a first information acquisition unit 702, adapted to acquire information of a CPU running the thread when the first memory allocation request of the thread is acquired; and acquire the Per-CPU page frame cache of the CPU running the thread according to the information of the CPU running the thread; a first filling allocation unit 703, adapted to acquire the corresponding first memory block from the Per-CPU page frame cache and allocate it to the thread when the corresponding first memory block exists in the Per-CPU page frame cache; and perform a first filling process on the Per-CPU page frame cache when the corresponding first memory block does not exist in the Per-CPU page frame cache; and after the first filling process is performed on the Per-CPU page frame cache, acquire the corresponding first memory block from the Per-CPU page frame cache and allocate it to the thread.

[0154] In an exemplary embodiment, the first information acquisition unit 702 is adapted to acquire the information of the CPU running the thread in real time by adopting a restartable sequence mechanism.

[0155] In an exemplary embodiment, the first filling allocation unit 703 is adapted to obtain information of a target NUMA node to which the CPU running the thread belongs based on information of the CPU running the thread; and obtain a first memory block from a corresponding NUMA cache and fill it into a Per-CPU page frame cache based on information of the target NUMA node.

[0156] In an exemplary embodiment, the first filling allocation unit 703 is also suitable for obtaining a second memory block from the corresponding NUMA page heap according to information of the target NUMA node when the corresponding NUMA cache cannot meet the filling demand of the Per-CPU page frame cache, and the second memory block is larger than the first memory block; slicing the second memory block obtained from the corresponding NUMA page heap to obtain a corresponding plurality of first memory blocks; filling the plurality of first memory blocks into the corresponding NUMA cache; after filling the plurality of first memory blocks into the corresponding NUMA cache, obtaining the corresponding first memory block from the corresponding NUMA cache and filling it into the Per-CPU page frame cache.

[0157] In an exemplary embodiment, the first filling allocation unit 703 is also suitable for obtaining a second memory block from the corresponding local virtual memory space and filling it into the corresponding NUMA page heap according to the target NUMA node when the corresponding NUMA page heap cannot meet the filling demand of the corresponding NUMA cache; after obtaining the second memory block from the corresponding local virtual memory space and filling it into the corresponding NUMA page heap, obtaining the second memory block from the corresponding NUMA page heap; slicing the second memory block obtained from the corresponding NUMA page heap to obtain a corresponding plurality of first memory blocks; filling the plurality of first memory blocks into the corresponding NUMA cache; after filling the plurality of first memory blocks into the corresponding NUMA cache, obtaining the corresponding first memory block from the corresponding NUMA cache and filling it into the Per-CPU page frame cache.

[0158] In an exemplary embodiment, the memory management device 70 further includes: a first releasing unit 704, adapted to release the corresponding first memory block to the Per-CPU page frame cache after the first memory block corresponding to the thread has been used up.

[0159] In an exemplary embodiment, the memory management device 70 further includes: a second information acquisition unit 705, which is suitable for, when the first memory allocation request is used to request allocation of a corresponding second memory block, and the second memory block is larger than the first memory block, after obtaining the information of the CPU running the thread, obtaining the information of the target NUMA node to which the CPU running the thread belongs according to the information of the CPU running the thread; obtaining the information of the corresponding NUMA page heap according to the information of the target NUMA node; a second filling allocation unit 706, which is suitable for, when the corresponding second memory block exists in the corresponding NUMA page heap, obtaining the corresponding second memory block from the corresponding NUMA page heap and allocating it to the thread; when the corresponding second memory block does not exist in the corresponding NUMA page heap, performing a second filling process on the corresponding NUMA page heap; after performing the second filling process on the corresponding NUMA page heap, obtaining the corresponding second memory block from the corresponding NUMA page heap and allocating it to the thread.

[0160] In an exemplary embodiment, the second filling allocation unit 706 is also suitable for obtaining a second memory block from the corresponding local virtual memory space and filling it into the corresponding NUMA page heap according to the target NUMA node; after obtaining the second memory block from the corresponding local virtual memory space and filling it into the corresponding NUMA page heap, obtaining the second memory block from the corresponding NUMA page heap and allocating it to the thread.

[0161] In an exemplary embodiment, the memory management device 70 further includes: a second releasing unit 707, adapted to release the corresponding second memory block to the corresponding NUMA page heap after the corresponding second memory block of the thread has been used up.

[0162] The memory management device in the embodiment of the present invention can be used to execute the aforementioned memory management method, or can also be used to use other functional modules to execute the memory management method in the embodiment of the present invention. For the memory management method provided by the embodiment of the present invention, please refer to the detailed description of the aforementioned part, which will not be repeated here.

[0163] The present application also provides a computer system. In some embodiments, the computer system may include a memory management device, which may be configured to execute the memory management method provided in the present application. The memory management method provided in the present application is described in the above section and will not be described in detail.

[0164] The present application also provides a computer program product, including a computer program / instruction, which is used to implement the memory management method provided in the present application when the computer program / instruction is executed by the processor. The memory management method provided in the present application is implemented by referring to the contents of the above section and will not be described in detail.

[0165] The present application embodiment provides a storage medium, wherein the storage medium stores one or more computer executable instructions, wherein the one or more computer executable instructions are used to execute the memory management method provided in the present application embodiment. The memory management method provided in the present application embodiment can be executed by referring to the contents of the aforementioned part, and will not be described in detail.

[0166] The above describes multiple implementation schemes provided by the embodiments of the present application. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present application.

[0167] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A memory management method, characterized in that: include: Obtaining a first memory allocation request of a thread, where the first memory allocation request is used to request allocation of a corresponding first memory block; When the first memory allocation request of the thread is obtained, obtaining information of the CPU running the thread; According to the information of the CPU running the thread, obtaining the Per-CPU (per CPU) page frame cache of the CPU running the thread; When a corresponding first memory block exists in the Per-CPU page frame cache, obtaining a corresponding first memory block from the Per-CPU page frame cache and allocating it to the thread; When the corresponding first memory block does not exist in the Per-CPU page frame cache, a first filling process is performed on the Per-CPU page frame cache; after the first filling process is performed on the Per-CPU page frame cache, a corresponding first memory block is obtained from the Per-CPU page frame cache and allocated to the thread.

2. The memory management method according to claim 1, characterized in that: The obtaining the information of the CPU running the thread includes: using a restartable sequence mechanism to obtain the information of the CPU running the thread in real time.

3. The memory management method according to claim 1, characterized in that: The first filling process of the Per-CPU page frame cache includes: According to the information of the CPU running the thread, obtain the information of the target NUMA (non-uniform memory access) node to which the CPU running the thread belongs; According to the information of the target NUMA node, a first memory block is obtained from the corresponding NUMA cache and filled into the Per-CPU page frame cache.

4. The memory management method according to claim 3, characterized in that: When the corresponding NUMA cache cannot meet the filling requirement of the Per-CPU page frame cache, performing a first filling process on the Per-CPU page frame cache further includes: According to the information of the target NUMA node, obtain a second memory block from a corresponding NUMA page heap, where the second memory block is larger than the first memory block; Slice the second memory block obtained from the corresponding NUMA page heap to obtain a corresponding plurality of first memory blocks; Filling the plurality of first memory blocks into corresponding NUMA caches; After the plurality of first memory blocks are filled into the corresponding NUMA cache, the corresponding first memory block is obtained from the corresponding NUMA cache and filled into the Per-CPU page frame cache.

5. The memory management method according to claim 4, characterized in that: When the corresponding NUMA page heap cannot meet the filling requirement of the corresponding NUMA cache, performing a first filling process on the Per-CPU page frame cache also includes: According to the target NUMA node, obtaining a second memory block from a corresponding local virtual memory space and filling it into the corresponding NUMA page heap; After obtaining a second memory block from the corresponding local virtual memory space and filling it into the corresponding NUMA page heap, obtaining a second memory block from the corresponding NUMA page heap; Slice the second memory block obtained from the corresponding NUMA page heap to obtain a corresponding plurality of first memory blocks; Filling the plurality of first memory blocks into corresponding NUMA caches; After the plurality of first memory blocks are filled into the corresponding NUMA cache, the corresponding first memory block is obtained from the corresponding NUMA cache and filled into the Per-CPU page frame cache.

6. The memory management method according to any one of claims 1 to 5, characterized in that: After the first memory block corresponding to the thread is used up, the method further includes: releasing the corresponding first memory block to the Per-CPU page frame cache.

7. The memory management method according to claim 1, characterized in that: When the first memory allocation request is used to request allocation of a corresponding second memory block, and the second memory block is larger than the first memory block, after acquiring information of the CPU running the thread, the method further includes: According to the information of the CPU running the thread, obtain the information of the target NUMA node to which the CPU running the thread belongs; According to the information of the target NUMA node, obtain the information of the corresponding NUMA page heap; When the corresponding second memory block exists in the corresponding NUMA page heap, obtaining the corresponding second memory block from the corresponding NUMA page heap and allocating it to the thread; When the corresponding second memory block does not exist in the corresponding NUMA page heap, a second filling process is performed on the corresponding NUMA page heap; after the second filling process is performed on the corresponding NUMA page heap, a corresponding second memory block is obtained from the corresponding NUMA page heap and allocated to the thread.

8. The memory management method according to claim 7, characterized in that: The performing a second filling process on the corresponding NUMA page heap further includes: According to the target NUMA node, obtaining a second memory block from a corresponding local virtual memory space and filling it into the corresponding NUMA page heap; After obtaining a second memory block from the corresponding local virtual memory space and filling it into the corresponding NUMA page heap, a second memory block is obtained from the corresponding NUMA page heap and allocated to the thread.

9. The memory management method according to claim 7 or 8, characterized in that: After the second memory block corresponding to the thread is used up, the method further includes: releasing the corresponding second memory block to the corresponding NUMA page heap.

10. A memory management device, characterized in that: include: A request obtaining unit, adapted to obtain a first memory allocation request of a thread, wherein the first memory allocation request is used to request allocation of a corresponding first memory block; A first information acquisition unit is adapted to acquire information of a CPU running the thread when a first memory allocation request of the thread is acquired; and acquire a Per-CPU page frame cache of the CPU running the thread according to the information of the CPU running the thread; The first filling allocation unit is adapted to obtain the corresponding first memory block from the Per-CPU page frame cache and allocate it to the thread when the corresponding first memory block exists in the Per-CPU page frame cache; perform a first filling process on the Per-CPU page frame cache when the corresponding first memory block does not exist in the Per-CPU page frame cache; and obtain the corresponding first memory block from the Per-CPU page frame cache and allocate it to the thread after performing the first filling process on the Per-CPU page frame cache.

11. The memory management device according to claim 10, characterized in that: The first information acquisition unit is adapted to acquire information of the CPU running the thread in real time by adopting a restartable sequence mechanism.

12. The memory management device according to claim 10, characterized in that: The first filling allocation unit is adapted to obtain information of a target NUMA node to which the CPU running the thread belongs according to information of the CPU running the thread; and obtain a first memory block from a corresponding NUMA cache and fill it into a Per-CPU page frame cache according to information of the target NUMA node.

13. The memory management device according to claim 12, characterized in that: The first filling allocation unit is further adapted to, when the corresponding NUMA cache cannot meet the filling requirement of the Per-CPU page frame cache, obtain a second memory block from the corresponding NUMA page heap according to the information of the target NUMA node, the second memory block being larger than the first memory block; perform block processing on the second memory block obtained from the corresponding NUMA page heap to obtain a corresponding plurality of first memory blocks; and fill the plurality of first memory blocks into the corresponding NUMA cache; After the plurality of first memory blocks are filled into the corresponding NUMA cache, the corresponding first memory block is obtained from the corresponding NUMA cache and filled into the Per-CPU page frame cache.

14. The memory management device according to claim 13, characterized in that: The first filling allocation unit is further adapted to, when the corresponding NUMA page heap cannot meet the filling demand of the corresponding NUMA cache, obtain a second memory block from the corresponding local virtual memory space according to the target NUMA node and fill it into the corresponding NUMA page heap; after obtaining the second memory block from the corresponding local virtual memory space and filling it into the corresponding NUMA page heap, obtain the second memory block from the corresponding NUMA page heap; cut the second memory block obtained from the corresponding NUMA page heap into blocks to obtain a corresponding plurality of first memory blocks; and fill the plurality of first memory blocks into the corresponding NUMA cache; After the plurality of first memory blocks are filled into the corresponding NUMA cache, the corresponding first memory block is obtained from the corresponding NUMA cache and filled into the Per-CPU page frame cache.

15. The memory management device according to any one of claims 10 to 14, characterized in that: Also includes: The first releasing unit is adapted to release the corresponding first memory block to the Per-CPU page frame cache after the first memory block corresponding to the thread has been used up.

16. The memory management device according to claim 10, characterized in that: Also includes: a second information acquisition unit adapted to, when the first memory allocation request is used to request allocation of a corresponding second memory block, and the second memory block is larger than the first memory block, after acquiring information about a CPU running the thread, acquire information about a target NUMA node to which the CPU running the thread belongs according to the information about the CPU running the thread; and acquire information about a corresponding NUMA page heap according to the information about the target NUMA node; The second filling allocation unit is suitable for obtaining the corresponding second memory block from the corresponding NUMA page heap and allocating it to the thread when the corresponding second memory block exists in the corresponding NUMA page heap; performing a second filling process on the corresponding NUMA page heap when the corresponding second memory block does not exist in the corresponding NUMA page heap; and obtaining the corresponding second memory block from the corresponding NUMA page heap and allocating it to the thread after performing the second filling process on the corresponding NUMA page heap.

17. The memory management device according to claim 16, characterized in that: The second filling allocation unit is also suitable for obtaining a second memory block from the corresponding local virtual memory space and filling it into the corresponding NUMA page heap according to the target NUMA node; after obtaining the second memory block from the corresponding local virtual memory space and filling it into the corresponding NUMA page heap, obtaining the second memory block from the corresponding NUMA page heap and allocating it to the thread.

18. The memory management device according to claim 16 or 17, characterized in that: Also includes: The second releasing unit is adapted to release the corresponding second memory block to the corresponding NUMA page heap after the second memory block corresponding to the thread has been used up.

19. A computer system, characterized in that: It comprises a memory management device, wherein the memory management device is configured to execute the memory management method according to any one of claims 1 to 9.

20. A computer program product comprising a computer program / instructions, characterized in that The computer program / instruction is used to implement the memory management method according to any one of claims 1 to 9 when executed by a processor.

21. A storage medium, characterized in that: The storage medium stores one or more computer executable instructions, and the one or more computer executable instructions are used to execute the memory management method according to any one of claims 1 to 9.

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