Method, device and system for heterogeneous inter-core communication

Abstract

The invention provides a method, device and system for heterogeneous inter-core communication, and the method comprises the steps: obtaining operation request information of a first core from a shared memory, the operation request information comprising operation mark information and to-be-operated variable information, and the to-be-operated variable information at least comprising a variable memory address; searching corresponding target variable information in Flash based on the variable memory address; mapping the searched target variable information into a mapping memory; and executing corresponding operation on the target variable information in the mapping memory based on the operation mark information. According to the method, interactive operations such as communication, reading and control among heterogeneous cores can be flexibly realized, and the method has flexibility and portability.

Description

Technical Field

[0001] The present application relates to the field of automotive electronic software technology, and in particular to a method, device and system for heterogeneous inter-core communication. Background Art

[0002] Communication between heterogeneous cores can usually be achieved using the Inter-Platform Communication Framework (IPCF), which connects different heterogeneous cores. IPCF can be a subsystem based on different parent operating systems, which can include: automatic sharing system, Linux system, open source real-time operating system (FreeRTOS) and Internet of Things operating system (Zephyr) system, etc.

[0003] IPCF allows applications to run on multiple homogeneous or heterogeneous processing cores, to be located on the same chip or different chips, to run on different parent operating systems, and to communicate through various transport interfaces. Typically, IPCF uses interrupts for inter-core communication.

[0004] However, the existing technology is easily affected by the standardization of the architecture during the development process based on IPCF, resulting in insufficient flexibility. In addition, due to the lack of compatibility of IPCF for cross-platform interaction, the software faces the problem of needing to be redeveloped after the hardware platform is replaced, so its portability is also poor. Summary of the invention

[0005] The present application provides a method, device and system for heterogeneous inter-core communication to solve the above-mentioned technical problems.

[0006] According to a first aspect of the present application, a method for heterogeneous inter-core communication is provided, which is applied to a second core end, where the second core and the first core are heterogeneous cores, and the first core and the second core are provided with a shared memory, and the method includes:

[0007] Acquire operation request information of the first core from the shared memory, wherein the operation request information includes: operation flag information and variable information to be operated, wherein the variable information to be operated includes at least a variable memory address;

[0008] Searching for corresponding target variable information in Flash based on the variable memory address;

[0009] Mapping the found target variable information into a mapping memory;

[0010] Based on the operation flag information, a corresponding operation is performed on the target variable information in the mapping memory.

[0011] In some implementations, before obtaining the operation request information of the first core from the shared memory, the method further includes:

[0012] Send variable basic information that can interact with the first core to the first core, the variable basic information including: variable memory address and variable size.

[0013] In some implementations, when the operation flag information is a first preset flag, performing a corresponding operation on the target variable information in the mapping memory based on the operation flag information includes:

[0014] Reading the target variable information in the mapping memory, the read target variable information includes: variable memory address, variable size and variable value;

[0015] The read target variable information is provided to the first core through the shared memory.

[0016] In some implementations, when the operation flag information is a second preset flag, the variable information to be operated further includes a variable control value; and performing a corresponding operation on the target variable information in the mapping memory based on the operation flag information includes:

[0017] Adjust the variable value in the target variable information in the mapping memory according to the variable control value;

[0018] Adjusting the operation mark information to a first preset mark;

[0019] Reading the target variable information in the adjusted mapping memory, the read target variable information includes: variable memory address, variable size and variable value;

[0020] The read target variable information is provided to the first core through the shared memory.

[0021] In some implementations, obtaining the operation request information of the first core from the shared memory includes:

[0022] The shared memory is viewed in a polling retrieval manner to obtain the operation request information.

[0023] According to a second aspect of the present application, a method for heterogeneous inter-core communication is provided, which is applied to a first core end, wherein the first core and the second core are heterogeneous cores, and the first core and the second core are provided with a shared memory, and the method includes:

[0024] Accessing the shared memory through the API and writing operation request information, wherein the operation request information includes: operation flag information and variable information to be operated, wherein the variable information to be operated includes at least a variable memory address, and the variable memory address is used by the second core to search for corresponding target variable information in the Flash, so as to map the searched target variable information to the mapping memory, thereby performing corresponding operations on the target variable information in the mapping memory based on the operation flag information;

[0025] The operation result of the second core on the variable information is obtained through the shared memory.

[0026] In some implementations, before writing the operation request information, the method further includes:

[0027] Receive variable basic information sent by the second core that can interact with the first core, where the variable basic information includes: variable memory address and variable size.

[0028] In some implementations, when the operation flag information is a second preset flag, the variable information to be operated further includes a variable control value, and the operation result of the variable information includes: a variable memory address and a variable value; after obtaining the operation result of the second core on the variable information through the shared memory, the method further includes:

[0029] By comparing the variable value with the variable control value to see if they are consistent, confirm whether the operation is successful.

[0030] According to a third aspect of the present application, a device for heterogeneous inter-core communication is provided, which is arranged at a second core end, and the device includes:

[0031] The inter-core communication module is used to obtain the operation request information of the first core from the shared memory, wherein the operation request information includes: operation flag information and variable information to be operated, wherein the variable information to be operated includes at least the variable memory address;

[0032] A memory core mapping module is used to search for corresponding target variable information in Flash based on the variable memory address, map the found target variable information to the mapping memory, and perform corresponding operations on the target variable information in the mapping memory based on the operation flag information.

[0033] According to a fourth aspect of the present application, a device for heterogeneous inter-core communication is provided, which is arranged at a first core end, and the device includes:

[0034] An operation request sending module, used to access the shared memory through the API and write operation request information, wherein the operation request information includes: operation flag information and variable information to be operated, wherein the variable information to be operated includes at least a variable memory address, and the variable memory address is used by the second core to search for corresponding target variable information in the Flash, so as to map the found target variable information to the mapping memory, thereby performing corresponding operations on the target variable information in the mapping memory based on the operation flag information;

[0035] An operation result acquisition module is used to obtain the operation result of the second core on the variable information through the shared memory.

[0036] According to a fifth aspect of the present application, a system for heterogeneous core communication is provided, the system comprising a first core and a second core, the first core and the second core being heterogeneous cores, the system being provided with a shared memory for the first core and the second core,

[0037] The first core is configured to: access the shared memory through an API, and write operation request information, wherein the operation request information includes: operation flag information and variable information to be operated, wherein the variable information to be operated includes at least a variable memory address;

[0038] The second core is configured to: obtain the operation request information from the shared memory, search for corresponding target variable information in the Flash based on the variable memory address, map the found target variable information to the mapped memory, perform a corresponding operation on the target variable information in the mapped memory based on the operation flag information, and provide the operation result to the first core through the shared memory;

[0039] The first core is further configured to: obtain the operation result through the shared memory.

[0040] In summary, the method, device and system for heterogeneous inter-core communication provided by the present application have at least the following beneficial effects:

[0041] The method for heterogeneous core communication of the present application, the second core and the first core are heterogeneous cores, the first core and the second core are provided with a shared memory, the second core first obtains the operation request information of the first core from the shared memory, wherein the operation request information includes: operation flag information and variable information to be operated, in addition, the variable information to be operated includes at least the variable memory address; then based on the variable memory address, the corresponding target variable information is found in the Flash; further, the corresponding target variable information found is mapped to the mapping memory; finally, based on the operation flag information, the corresponding target variable information in the mapping memory is performed corresponding operations. Furthermore, after the hardware platform is replaced, the present application does not need to re-develop the software, and the communication, reading and control and other interactive operations between heterogeneous cores can be flexibly realized through the shared memory and control logic of the present application. The present application overcomes the problem that the software needs to be redeveloped after the hardware platform is replaced due to the lack of compatibility of the IPCF cross-platform interaction pair. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0043] Figure 1 A flowchart of a method for heterogeneous inter-core communication provided in an embodiment of the present application;

[0044] Figure 2 A system architecture diagram of the A core and the R core provided in the embodiment of the present application;

[0045] Figure 3 A flowchart of another method for heterogeneous inter-core communication provided in an embodiment of the present application;

[0046] Figure 4 A flowchart of another method for heterogeneous inter-core communication provided in an embodiment of the present application;

[0047] Figure 5 A structural diagram of a device for heterogeneous inter-core communication provided in an embodiment of the present application;

[0048] Figure 6 A structural diagram of another device for heterogeneous inter-core communication provided in an embodiment of the present application;

[0049] Figure 7 A structural diagram of a system for heterogeneous inter-core communication provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] In order to make the above and other features and advantages of the present application more clear, the present application is further described below in conjunction with the accompanying drawings. It should be understood that the specific embodiments given herein are for the purpose of explaining to those skilled in the art and are only exemplary and not restrictive.

[0051] In the following description, many specific details are set forth to provide a thorough understanding of the present application. However, it is apparent to those skilled in the art that specific details need not be adopted to practice the present application. In other cases, well-known steps or operations are not described in detail to avoid blurring the present application.

[0052] The method for heterogeneous inter-core communication provided in the embodiment of the present application can be executed by the device for heterogeneous inter-core communication provided in the embodiment of the present application, and the device can be configured in a system for heterogeneous inter-core communication.

[0053] Reference Figure 1 As shown, the present application provides a method for heterogeneous core communication, which is applied to the second core end, the second core and the first core are heterogeneous cores, the first core and the second core are provided with a shared memory, and the method includes steps 110-140.

[0054] Step 110: Obtain operation request information of the first core from the shared memory.

[0055] In some implementations, the operation request information includes: operation flag information and variable information to be operated, wherein the variable information to be operated includes at least a variable memory address.

[0056] Heterogeneous cores may refer to a computing architecture composed of different processors or cores in a computer system. These processors or cores differ in performance, purpose, and structure, and by leveraging their respective computing advantages, they achieve optimal resource allocation, thereby improving overall performance and reducing power consumption. Among them, the first core and the second core of the present application may be any two heterogeneous cores, or two specific heterogeneous cores may be set as the first core and the second core according to demand, and the present application does not make any special restrictions here.

[0057] In some implementations, setting the shared memory may be implemented based on a random access memory (Ram).

[0058] In addition, the operation flag information of the present application can be used to identify the type of operation request information, and the variable information to be operated of the present application can be variable information used to perform operation control.

[0059] In some embodiments, Figure 2The figure shows the system architecture of two heterogeneous cores A core and R core. The MCU (R core) in the figure is the micro control unit of the second core end, where R core is the second core. The second core R core can obtain the operation request information of the first core (Acore) from the shared memory based on the Inter-Core Communication Module (ICCM).

[0060] Step 120: Search the Flash for corresponding target variable information based on the variable memory address.

[0061] Flash is also known as flash memory, which can be used to store variable information and software image files in the system. Flash memory is erasable memory, and the image files in the Flash can be replaced when the software in the system is upgraded / updated.

[0062] In some embodiments, Figure 2 As shown, Flash can be set in a memory core mapping module (Memory Core Mapping Module, MMCM for short) in the second core R core. That is, the second core R core can search for corresponding target variable information in the Flash of the MMCM based on the variable memory address.

[0063] The software image file stores the variable memory address, through which the corresponding variable can be found.

[0064] Step 130: Map the found target variable information into a mapping memory.

[0065] In some embodiments, the second core R core can map the target variable information found to the mapped memory based on MMCM. The mapped memory can be, for example, Ram. That is, in the embodiment of the present application, when the first core wants to perform a control operation on the variables in the second core, it will not directly operate on the variables in Flash, but will map the target variables to be operated to Ram, and perform operations on the variables in Ram. This not only has the advantage of fast operation speed, but also will not perform permanent control on the variables of the second core, and has the advantage of high flexibility.

[0066] Step 140: Perform corresponding operations on the target variable information in the mapping memory based on the operation flag information.

[0067] The type of the operation request information can be identified based on the operation flag information, and then a corresponding operation on the target variable information in the mapping memory is performed according to the type of the operation request information. For example, the corresponding operation may include: a read operation and a write operation.

[0068] The method for heterogeneous core communication of the present application is applied to the second core end, the second core and the first core are heterogeneous cores, the first core and the second core are provided with a shared memory, firstly, the operation request information of the first core is obtained from the shared memory, wherein the operation request information includes: operation flag information and variable information to be operated, in addition, the variable information to be operated includes at least the variable memory address; then, based on the variable memory address, the corresponding target variable information is found in the Flash; further, the corresponding target variable information found is mapped to the mapping memory; finally, based on the operation flag information, the corresponding target variable information in the mapping memory is performed correspondingly. Furthermore, after the hardware platform is replaced, the present application does not need to re-develop the software, and the ICCM and MMCM of the present application can flexibly realize the communication between heterogeneous cores. The present application overcomes the problem that the software needs to be redeveloped after the hardware platform is replaced due to the lack of compatibility of the IPCF cross-platform interaction pair.

[0069] Refer to the attached Figure 3 FIG. 1 is a flowchart of another method for heterogeneous core communication provided by an embodiment of the present application. The method is applied to a second core end, the second core and the first core are heterogeneous cores, and the first core and the second core are provided with a shared memory, and includes steps 310-390.

[0070] Step 310: Send variable basic information that can interact with the first core to the first core.

[0071] In some implementations, the basic variable information includes: variable memory address and variable size.

[0072] The second core described in the embodiment of the present application saves basic variable information that can be controlled and communicated by the first core in Flash, and sends the basic variable information to the first core.

[0073] In some implementations, the second core R core provides the variable basic information to the first core through the shared memory in the form of text or a .map file (a text file used to describe the mapping relationship between the source code and the target code of a program).

[0074] Step 320: Obtain operation request information of the first core from the shared memory.

[0075] In some implementations, the operation request information includes: operation flag information and variable information to be operated, wherein the variable information to be operated includes at least a variable memory address.

[0076] In some implementations, the operation request information is obtained by checking the shared memory in a polling retrieval manner. For example, the ICCM in the second core R core can use polling to retrieve the shared memory in a system scheduling task (i.e., an OS scheduling task, such as an acquisition task) with a duration of 1 ms (milliseconds) or 5 ms.

[0077] In some implementations, the first core may write operation request information in the shared memory based on the variable basic information. The existing IPCF uses an interrupt mode to apply for data transfer, which may result in insufficient resource allocation, so the vectors that can be transferred are limited. However, since the operation request written in the shared memory in the embodiment of the present application is operation flag information instead of data to be transferred, the limitation due to insufficient resources is lifted.

[0078] Step 330: Search the Flash for corresponding target variable information based on the variable memory address.

[0079] In some implementations, the Flash of the second core R core may store variable information and software image files in the system, and the software image files store variable memory addresses, through which corresponding variables may be found.

[0080] Step 340: Map the found target variable information into a mapping memory.

[0081] In some implementations, after the target variable is found in the Flash, the target variable information may be mapped to a mapped memory (ie, Ram) based on the MMCM.

[0082] The above mapping can be implemented through a memory copy function (Memcpy), which can be called when the system is initialized or when variables need to be controlled.

[0083] Based on this, the second core maps the found target variable information into the mapping memory, so that the first core can perform control operations on the target variable.

[0084] Step 350: When the operation flag information is a first preset flag, read the target variable information in the mapping memory.

[0085] The target variable information read includes: variable memory address, variable size and variable value. That is, when the second core sends the variable basic information that can interact with the first core to the first core in step 310, the sent variable basic information includes the variable memory address and variable size, but does not include the variable value. When the first core needs to obtain the variable value, the operation flag information can be set to the first preset flag in the sent operation request, and the variable information to be operated is set to the variable memory address corresponding to the variable whose value needs to be read.

[0086] For example, the first preset flag may be represented by the number 0, and the first preset flag may represent the execution of a read operation. Based on this, the second core may implement the read operation of the target variable when the operation flag information is the first preset flag.

[0087] Step 360: When the operation flag information is the second preset flag, adjust the variable value in the corresponding target variable information in the mapping memory according to the variable control value.

[0088] Wherein, if the operation flag information in the operation request is the second preset flag, the corresponding variable information to be operated also includes a variable control value, and the variable control value is the value after the value of the target variable needs to be set. Regardless of the current target variable value, the first control operation of checking the target variable is to adjust the variable value in the corresponding target variable information in the mapping memory according to the variable control value, that is, to modify the value of the variable to the current value (variable control value). The second preset flag can be a write flag, and the second preset flag can be represented by the number 1.

[0089] Step 370: Adjust the operation mark information to a first preset mark.

[0090] After completing the adjustment of the variable value in the corresponding target variable information in the mapped memory, in order to let the first core know whether the result of the adjustment operation is successful so as to determine whether to perform subsequent related operations, the implementation method of the present application adjusts the operation flag information in the operation request in the shared memory to a first preset flag, for example, adjusting the operation flag information from 1 to 0, that is, after completing the write operation, continuing the read operation by adjusting the flag bit value. At this time, the variable information to be operated in the operation request has not changed, so what is read is the same target variable with the adjusted value.

[0091] Step 380: read the target variable information in the mapping memory after adjustment.

[0092] It is understandable that the operation flag information is the first preset flag. For example, the first preset flag may be the number 0. When the operation flag information is the number 0, the corresponding operation is to read the target variable information in the mapping memory after adjustment.

[0093] Step 390: Provide the read target variable information to the first core through the shared memory.

[0094] In the embodiment of the present application, the second core can store the read target variable information into the shared memory so that the first core can obtain the target variable information through the shared memory, thereby confirming whether the operation on the target variable is successful by comparing the read variable value with the variable control value carried in the operation request.

[0095] The method for heterogeneous core communication of the present application first obtains the operation request information of the first core from the shared memory, wherein the operation request information includes: operation flag information and variable information to be operated, and in addition, the variable information to be operated includes at least the variable memory address; then the corresponding target variable information is found in the Flash based on the variable memory address; the corresponding target variable information found is further mapped to the mapped memory; finally, the corresponding operation is performed on the corresponding target variable information in the mapped memory based on the operation flag information. Furthermore, after the hardware platform is replaced, the present application does not need to redevelop the software, and the ICCM and MMCM of the present application can flexibly realize the communication between heterogeneous cores. The present application overcomes the problem that the software needs to be redeveloped after the hardware platform is replaced due to the lack of compatibility of the IPCF cross-platform interaction pair.

[0096] Refer to the attached Figure 4 As shown, it is a flow chart of a second embodiment of a method for heterogeneous core communication provided by an embodiment of the present application. The method is applied to a first core end (such as Figure 2 A core in the first core and the second core (such as Figure 2 The Rcore in the figure is a heterogeneous core, and the first core and the second core are provided with a shared memory, including steps 410-420.

[0097] Step 410: Access the shared memory through the API and write the operation request information.

[0098] In some implementations, the operation request information includes: operation flag information and variable information to be operated, wherein the variable information to be operated includes at least a variable memory address, and the variable memory address is used by the second core to search for corresponding variable information in Flash, so as to map the corresponding variable information found to the mapping memory, thereby performing corresponding operations on the corresponding variable information in the mapping memory based on the operation flag information. The specific operation method of the second core is described in the above embodiment and will not be repeated here.

[0099] In some implementations, before writing the operation request information, the method further includes: receiving basic variable information sent by the second core that can interact with the first core, wherein the basic variable information includes: a variable memory address and a variable size.

[0100] In some implementations, after the first core A core obtains the interactive variable basic information sent by the second core, it can copy it to the list that needs to be interacted with, that is, the first core can manage the variable basic information that can interact with the second core through a list.

[0101] In some embodiments, the first core needs to develop an application programming interface (API) as an application interface for the software control process. When software control is required, the shared memory can be accessed through the API to write the operation request information. For example, the first core develops an API, accesses the shared memory through the API, and writes the operation flag information and the variable memory address into the operation request information. Based on this, the present application can complete the writing process of the operation request information based on the first core end.

[0102] Step 420: Obtain, through the shared memory, an operation result of the second core on the variable information.

[0103] In some embodiments, the operation flag information may include a first preset flag and a second preset flag. When the operation flag information in the operation request is the first preset flag, if the second core executes the operation request, the second core stores the operation result of the target variable information into the shared memory, and the first core can obtain the read variable information from the shared memory. The operation result of the variable information includes: the variable memory address and the variable value, thereby obtaining the variable value of the target variable.

[0104] In some embodiments, when the operation flag information is a second preset flag, the variable information to be operated also includes a variable control value, and the operation result of the variable information includes: a variable memory address and a variable value; after obtaining the operation result of the second core for the variable information through the shared memory, the method also includes: confirming whether the operation is successful by comparing whether the variable value is consistent with the variable control value.

[0105] Refer to the attached Figure 5 As shown, a device for heterogeneous inter-core communication of the present application is arranged at the second core end, and the device includes: an inter-core communication module 510 and a memory core mapping module 520.

[0106] The inter-core communication module 510 is used to obtain the operation request information of the first core from the shared memory, and the operation request information includes: operation flag information and variable information to be operated, wherein the variable information to be operated includes at least the variable memory address; the inter-core communication module 510 can be the ICCM mentioned above.

[0107] The memory core mapping module 520 is used to search for corresponding target variable information in the Flash based on the variable memory address, map the found target variable information to the mapping memory, and perform corresponding operations on the target variable information in the mapping memory based on the operation flag information. The memory core mapping module 520 can be the MMCM described above.

[0108] The present application realizes that even in the scenario of replacing the hardware platform or redeveloping the software, the two modules can execute corresponding functions, thereby realizing heterogeneous inter-core communication, and has the characteristics of strong portability and flexibility.

[0109] Refer to the attached Figure 6 As shown, a device for heterogeneous inter-core communication of the present application is arranged at the first core end, and the device includes: an operation request sending module 510 and an operation result obtaining module 520.

[0110] The operation request sending module 610 is used to access the shared memory through the API and write the operation request information, wherein the operation request information includes: operation flag information and variable information to be operated, wherein the variable information to be operated includes at least a variable memory address, and the variable memory address is used by the second core to search for the corresponding target variable information in the Flash, so as to map the searched target variable information to the mapping memory, thereby performing a corresponding operation on the target variable information in the mapping memory based on the operation flag information;

[0111] The operation result acquisition module 620 is used to obtain the operation result of the second core on the variable information through the shared memory.

[0112] Refer to the attached Figure 7 As shown, the present application is a system for heterogeneous inter-core communication, the system includes a first core 710 and a second core 720, the first core 710 and the second core 720 are heterogeneous cores, and the system is provided with a shared memory 730 for the first core 710 and the second core 720.

[0113] The first core 710 is configured to: access the shared memory 730 through an API, and write operation request information, wherein the operation request information includes: operation flag information and variable information to be operated, wherein the variable information to be operated includes at least a variable memory address.

[0114] The second core 720 is configured to: obtain the operation request information from the shared memory 730, search for corresponding target variable information in the Flash based on the variable memory address, map the found target variable information to the mapped memory, and perform corresponding operations on the target variable information in the mapped memory based on the operation flag information, and provide the operation results to the first core 710 through the shared memory 730.

[0115] The first core 710 is further configured to obtain the operation result through the shared memory 730 .

[0116] It should be understood that each module / unit of the system of the present application can be implemented in whole or in part by software, hardware, firmware or a combination thereof. Each module / unit can be embedded in the processor of the electronic device or independent of the processor in the form of hardware or firmware, or can be stored in the memory of the electronic device in the form of software for the processor to call to perform the operation of each module / unit. Each module / unit can be implemented as an independent component or module, or two or more modules / units can be implemented as a single component or module.

[0117] The various technical features described above can be combined arbitrarily. Although all possible combinations of these technical features are not described, any combination of these technical features should be considered to be covered by this specification as long as there is no contradiction in such combination.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for heterogeneous core communication, applied to a second core end, the second core and the first core are heterogeneous cores, the first core and the second core are provided with a shared memory, characterized in that: The method comprises: Acquire operation request information of the first core from the shared memory, wherein the operation request information includes: operation flag information and variable information to be operated, wherein the variable information to be operated includes at least a variable memory address; Searching for corresponding target variable information in Flash based on the variable memory address; Mapping the found target variable information into a mapping memory; Based on the operation flag information, a corresponding operation is performed on the target variable information in the mapping memory.

2. The method according to claim 1, characterized in that: Before obtaining the operation request information of the first core from the shared memory, the method further includes: Send variable basic information that can interact with the first core to the first core, the variable basic information including: variable memory address and variable size.

3. The method according to claim 1, characterized in that When the operation flag information is a first preset flag, performing a corresponding operation on the target variable information in the mapping memory based on the operation flag information includes: Reading the target variable information in the mapping memory, the read target variable information includes: variable memory address, variable size and variable value; The read target variable information is provided to the first core through the shared memory.

4. The method according to claim 3, characterized in that When the operation flag information is a second preset flag, the variable information to be operated also includes a variable control value; and performing a corresponding operation on the target variable information in the mapping memory based on the operation flag information includes: Adjust the variable value in the target variable information in the mapping memory according to the variable control value; Adjusting the operation mark information to a first preset mark; Reading the target variable information in the adjusted mapping memory, the read target variable information includes: variable memory address, variable size and variable value; The read target variable information is provided to the first core through the shared memory.

5. The method according to any one of claims 1 to 4, characterized in that: The obtaining the operation request information of the first core from the shared memory includes: The shared memory is viewed in a polling retrieval manner to obtain the operation request information.

6. A method for heterogeneous core communication, applied to a first core end, wherein the first core and the second core are heterogeneous cores, and the first core and the second core are provided with a shared memory, characterized in that: The method comprises: Accessing the shared memory through the API and writing operation request information, wherein the operation request information includes: operation flag information and variable information to be operated, wherein the variable information to be operated includes at least a variable memory address, and the variable memory address is used by the second core to search for corresponding target variable information in the Flash, so as to map the searched target variable information to the mapping memory, thereby performing corresponding operations on the target variable information in the mapping memory based on the operation flag information; The operation result of the second core on the variable information is obtained through the shared memory.

7. The method according to claim 6, characterized in that Before writing the operation request information, the method further includes: Receive variable basic information sent by the second core that can interact with the first core, where the variable basic information includes: variable memory address and variable size.

8. The method according to claim 6, characterized in that When the operation flag information is a second preset flag, the variable information to be operated also includes a variable control value, and the operation result of the variable information includes: a variable memory address and a variable value; after obtaining the operation result of the second core on the variable information through the shared memory, the method further includes: By comparing the variable value with the variable control value to see if they are consistent, confirm whether the operation is successful.

9. A device for heterogeneous inter-core communication, arranged at a second core end, characterized in that: The device comprises: The inter-core communication module is used to obtain the operation request information of the first core from the shared memory, wherein the operation request information includes: operation flag information and variable information to be operated, wherein the variable information to be operated includes at least the variable memory address; A memory core mapping module is used to search for corresponding target variable information in Flash based on the variable memory address, map the found target variable information to the mapping memory, and perform corresponding operations on the target variable information in the mapping memory based on the operation flag information.

10. A device for heterogeneous inter-core communication, arranged at a first core end, characterized in that: The device comprises: An operation request sending module, used to access the shared memory through the API and write operation request information, wherein the operation request information includes: operation flag information and variable information to be operated, wherein the variable information to be operated includes at least a variable memory address, and the variable memory address is used by the second core to search for corresponding target variable information in the Flash, so as to map the found target variable information to the mapping memory, thereby performing corresponding operations on the target variable information in the mapping memory based on the operation flag information; An operation result acquisition module is used to obtain the operation result of the second core on the variable information through the shared memory.

11. A system for heterogeneous core communication, the system comprising a first core and a second core, the first core and the second core being heterogeneous cores, the system being provided with a shared memory for the first core and the second core, characterized in that: The first core is configured to: access the shared memory through an API, and write operation request information, wherein the operation request information includes: operation flag information and variable information to be operated, wherein the variable information to be operated includes at least a variable memory address; The second core is configured to: obtain the operation request information from the shared memory, search for corresponding target variable information in the Flash based on the variable memory address, map the found target variable information to the mapped memory, perform a corresponding operation on the target variable information in the mapped memory based on the operation flag information, and provide the operation result to the first core through the shared memory; The first core is further configured to: obtain the operation result through the shared memory.

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