Portable general digital processing test system and test method

Abstract

The invention belongs to the technical field of digital signal processing, and particularly relates to a portable general digital processing test system and method, and the system comprises an upper computer, a lower computer which communicates with the upper computer, and a cable assembly which is connected with the lower computer. Wherein the cable assembly is used for being connected with a tested piece; the upper computer sends a test instruction to the lower computer according to a test requirement of a user, the lower computer comprises a ZYNQ chip and a plurality of test interfaces connected with the ZYNQ chip, a PS end of the ZYNQ chip receives, stores and analyzes the test instruction of the upper computer, a PL end sends test data based on the analyzed test instruction, and the ZYNQ chip sends the test data to the lower computer. Test data are transmitted to the tested machine through the test interface and the cable assembly. And the PL end processes the returned feedback data and then generates a test result, and the test result is packaged through the PS end and uploaded to the upper computer.

Description

Technical Field

[0001] The invention belongs to the technical field of digital signal processing, and in particular relates to a portable universal digital processing test system and a test method. Background Art

[0002] Automatic test equipment (ATE) can effectively shorten the test verification time of the product under test. The rapid and full verification of the product can not only improve the reliability of the product, but also save product development and maintenance costs, while making it easier for users to use and repair the product.

[0003] ATE has gone through about three generations of technology accumulation and iteration, namely product-specific test equipment, desktop instrument stacking system and modular instrument stacking system, and has been widely adapted and applied in the field of automated testing. At present, this distributed stacking architecture is more effective for "large and comprehensive" interface testing needs, but it also has the characteristics of large system size and insufficient mobility. For radar digital processing modules, the types and numbers of interfaces of this product are relatively fixed, and the module testing mobility requirements are relatively high. Especially for products with strict environmental test requirements, they often require highly targeted, compact, portable and flexible ATE products, that is, "small and fine", to meet the test and verification needs of designers.

[0004] Centralized ATE products, in response to relatively fixed interface requirements, centrally distribute various test resources in the test system, and flexibly communicate and control with the host computer through embedded operating system adaptation to meet automated test indicators, while meeting the designer's needs for compact and portable use. Summary of the invention

[0005] In order to solve the above problems, the present application provides a portable universal digital processing test system, a host computer, a slave computer communicating with the host computer, and a cable assembly connected to the slave computer;

[0006] Wherein, the cable assembly is used to connect with the device under test;

[0007] The host computer sends test instructions to the lower computer according to the user's test requirements.

[0008] The lower computer includes a ZYNQ chip and multiple test interfaces connected to the ZYNQ chip. The PS end of the ZYNQ chip receives, stores and parses the test instructions of the upper computer. The PL end sends test data based on the parsed test instructions. The test data is transmitted to the machine under test through the test interface and the cable assembly.

[0009] The PL side processes the feedback data and generates a test result, which is packaged by the PS side and uploaded to the host computer.

[0010] Preferably, the test interface includes a low-speed interface and a high-speed interface, the low-speed interface includes ARINC429, UART, GPIO, and 1553B interfaces; the high-speed interface communicates with the machine under test through photoelectric conversion, and the communication protocols include: SRIO, AURORA, JESD204B, FC, and SGMII.

[0011] Preferably, ARINC429 and UART implement constant receiving and sending test, increasing number receiving and sending test, decreasing number receiving and sending test, and host computer receiving and sending data test; GPIO implements level test and waveform parameter test; high-speed interface communication adopts a test mode with padded header and tail, specified data length and format.

[0012] Preferably, the communication between the PL end and the test interface uses a configurable custom IP.

[0013] Preferably, the PL end communicates with the UART using a 16-channel configurable UART IP to achieve automatic testing of communication protocols such as RS485, RS422 and RS232; the PL end communicates with the GPIO using a 16-channel configurable discrete quantity IP to achieve 3.3V single-ended discrete quantity testing, 5V single-ended discrete quantity testing, 28V single-ended discrete quantity testing, 3.3V differential discrete quantity testing, and 5V differential discrete quantity testing; the PL end communicates with the ARINC429 using a configurable IP to achieve automatic testing; the PL end communicates with the high-speed interface using a configurable IP to achieve configuration of high-speed link ports whose communication protocols are SRIO, AURORA, JESD204B, FC, and SGMII, and achieves connection with the machine under test and automatic testing through an optical cable assembly.

[0014] Preferably, the communication between the PS end and the host computer adopts a link-unified ICD, and the unified ICD includes a test instruction packet and a test response packet in the same format.

[0015] Preferably, the instruction classes of the test instruction package of the unified ICD are divided into initialization, sending data, receiving data, starting test, and stopping test; the test categories are divided into SRIO test, SGMII test, AURORA test, memory test, UART test, and discrete quantity test.

[0016] Preferably, the cable assembly connecting the low-speed port and the device under test uniformly adopts a connector of model DB15, and the DB15 connector has 15 pins, and the 15 pins are divided into three groups, each group including input, output and ground.

[0017] Preferably, the communication protocol between the PS end and the PL end adopts the AXI protocol.

[0018] A portable universal digital processing test method, using the portable universal digital processing test system, comprises:

[0019] Step 1: Digital processing test system connection;

[0020] Step 2: Determine whether the system is connected successfully. If it fails, go to step 3, otherwise go to step 4;

[0021] Step 3: Check the system wiring, and then proceed to step 1;

[0022] Step 4: Enter the basic information of the device under test;

[0023] Step 5: Check the test type, automatic test or manual interface test;

[0024] Step 6: Start testing;

[0025] Step 7: Wait for the test results;

[0026] Step 8: Output test report;

[0027] Step 9: Determine whether to continue the test, if yes, go to step 5, otherwise go to step 10;

[0028] Step 10: End of testing.

[0029] The advantages of the present application include: a portable general digital processing test system design method and control protocol designed by the present invention, which concentrates test resources on a test board, avoids instrument stacking, and can meet the requirements of small, portable and automated embedded test systems. The software program realizes modular secondary development, which greatly facilitates product development, experimental testing, field testing and other usage scenarios, and saves product development and maintenance costs.

[0030] The present invention can be applied to the field of embedded system testing and verification, especially to the full testing and experimental verification of digital signal processing modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a detailed resource configuration diagram of the automatic test system of the present invention;

[0032] Figure 2 It is a flow chart of the automatic testing system of the system of the present invention;

[0033] Figure 3 It is a mode diagram of the automatic test system of the present invention;

[0034] Figure 4 It is a block diagram of automatic test program development of the lower computer of the system of the present invention. DETAILED DESCRIPTION

[0035] In order to make the technical solution and advantages of the present application clearer, the technical solution of the present application will be further described in detail in detail and in detail in conjunction with the accompanying drawings. It can be understood that the specific embodiments described here are only partial embodiments of the present application, which are only used to explain the present application, not to limit the present application. It should be noted that, for the convenience of description, only the parts related to the present application are shown in the accompanying drawings, and other related parts can refer to the general design. In the absence of conflict, the embodiments in the present application and the technical features in the embodiments can be combined with each other to obtain new embodiments.

[0036] In order to describe the present invention more specifically, the technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0037] refer to Figure 1 ,Detailed resource configuration of the automatic test system of the present invention: a host computer, a slave computer communicating with the host computer, and a cable assembly connected to the slave computer;

[0038] Wherein, the cable assembly is used to connect with the device under test;

[0039] The host computer sends test instructions to the lower computer according to the user's test requirements.

[0040] The lower computer includes a ZYNQ chip and multiple test interfaces connected to the ZYNQ chip. The PS end of the ZYNQ chip receives, stores and parses the test instructions of the upper computer. The PL end sends test data based on the parsed test instructions. The test data is transmitted to the machine under test through the test interface and the cable assembly.

[0041] The PL side processes the feedback data and generates a test result, which is packaged by the PS side and uploaded to the host computer.

[0042] In this example, the ZYNQ processor PS runs an embedded operating system to schedule test tasks and control test interfaces. It is connected to the host PC via a Gigabit network and is responsible for receiving, storing and parsing host control instructions and communication data. It distributes and controls corresponding test interface actions according to test requirements. At the same time, the PL side processes the test interface link test receiving and sending data and is responsible for storing and uploading interface data to the host PC.

[0043] In this example, the ZYNQ processor is interconnected through interface driver chips and cable assemblies to complete the access and control of low-speed interface data, mainly including ARINC429, UART, GPIO and other interfaces;

[0044] In this example, the low-speed interfaces such as ARINC429 and UART are controlled by the host computer to implement several modes such as constant receiving and sending test, increasing number receiving and sending test, decreasing number receiving and sending test, and host computer receiving and sending data test, and the test results are sent back;

[0045] In this example, GPIO implements level test and waveform parameter (pulse width, period, etc.) test, and returns the test results;

[0046] In this example, the SERDES part of ZYNQ is connected to the cable assembly through high-speed links such as SRIO, AURORA, JESD204B, FC, SGMII, etc., and receives the PS-side instructions of ZYNQ at the same time, and communicates the corresponding high-speed interface protocol data through the logical protocol IP. Implement the test mode that the header and tail can be filled, specify the data length and format, and return the test results;

[0047] In this example, the cable assembly is connected to the lower computer and the digital processing module under test, and the cable assembly signal includes an electrical signal cable and an optical signal cable;

[0048] refer to Figure 2 , the automatic system design method test flow chart is executed according to the following steps:

[0049] Step 1: System connection;

[0050] Step 2: Determine whether the system is connected successfully. If it fails, go to step 3, otherwise go to step 4;

[0051] Step 3: Check the system wiring, and then proceed to step 1;

[0052] Step 4: Enter the basic information of the device under test;

[0053] Step 5: Check the test type, automatic test or manual interface test;

[0054] Step 6: Start testing;

[0055] Step 7: Wait for the test results;

[0056] Step 8: Output test report;

[0057] Step 9: Determine whether to continue the test, if yes, go to step 5, otherwise go to step 10;

[0058] Step 10: End of testing.

[0059] refer to Figure 4 The automatic test program development process of the lower computer of the system of the present invention is as follows:

[0060] The main functions of the lower computer PS part are three parts: one is to communicate with the upper computer through the Gigabit network; the second is to parse the upper computer instructions; the third is to start the corresponding automatic test according to the upper computer instructions. Except for the official IP used for communication with the upper computer, the other parts of the PL part are developed in a custom and configurable logic IP mode, mainly the following four types: one is 16-channel configurable UARTIP, connecting the driver can realize the automatic test of RS485, RS422 and RS232; the second is 16-channel configurable discrete quantity IP, connecting the driver can realize 3.3V single-ended discrete quantity input and output test, 5V single-ended discrete quantity input and output test, 28V single-ended discrete quantity input and output test, 3.3V differential discrete quantity input and output test, 5V differential discrete quantity input and output test; ARINC429 configurable IP, connecting the driver to realize automatic test; SERDES port configurable IP, can realize the configuration of SRIO, AURORA, JESD204B, FC, SGMII and other high-speed link ports, and realize the connection with the device under test through the optical cable assembly to realize automatic test.

[0061] Reference Table 1 lists a communication link unified ICD of the present invention, which is used for the unified format of the communication link in the system, and is convenient for system development and expansion. ICD is divided into a test instruction packet and a test response packet, and adopts the same format. ICD contains a 4-byte header, a 2-byte packet length, a 1-byte type of the device under test, a 1-byte test result, a 20-byte status bit, and an 8-byte reserved bit. ICD can be filled with different test instructions and test results, such as instruction categories are divided into initialization, sending data, receiving data, starting test, stopping test, etc., test categories are divided into SRIO test, SGMII test, AURORA test, memory test, UART test, discrete quantity test, etc., URAT test can be specifically refined into RS485, RS422, RS232, etc.

[0062] Table 1 An automatic test system communication link type ICD of the present invention

[0063]

[0064] Reference Table 2 lists a definition of a unified low-speed port adapter cable of the present invention. The test end of the cable in this definition uniformly adopts DB15 docking, and the compatibility between different interfaces is guaranteed during design. The same DB15 is divided into three groups of areas, each of which contains a group of input, output and GND. Through the unified definition of the adapter cable, the efficiency of testing and system development can be improved.

[0065] Table 2 Definition of a low-speed port adapter cable of the present invention

[0066]

[0067] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited by the embodiments. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principles of the present invention shall be considered as equivalent replacement modes and shall be included in the protection scope of the present invention.

[0068] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A portable universal digital processing test system, characterized in that: A host computer, a slave computer communicating with the host computer, and a cable assembly connected to the slave computer; Wherein, the cable assembly is used to connect with the device under test; The host computer sends test instructions to the lower computer according to the user's test requirements. The lower computer includes a ZYNQ chip and multiple test interfaces connected to the ZYNQ chip. The PS end of the ZYNQ chip receives, stores and parses the test instructions of the upper computer. The PL end sends test data based on the parsed test instructions. The test data is transmitted to the machine under test through the test interface and the cable assembly. The PL side processes the feedback data and generates a test result, which is packaged by the PS side and uploaded to the host computer.

2. The portable universal digital processing test system as claimed in claim 1, characterized in that: The test interface includes low-speed interface and high-speed interface. The low-speed interface includes ARINC429, UART, GPIO, and 1553B interfaces. The high-speed interface communicates with the device under test through photoelectric conversion. The communication protocols include: SRIO, AURORA, JESD204B, FC, and SGMII.

3. The portable universal digital processing test system as claimed in claim 2, characterized in that: ARINC429 and UART implement constant receiving and sending test, increasing number receiving and sending test, decreasing number receiving and sending test, and host computer receiving and sending data test; GPIO implements level test and waveform parameter test; high-speed interface communication adopts a test mode with packet header and packet tail padding and specified data length and format.

4. The portable universal digital processing test system as claimed in claim 1, characterized in that: The communication between the PL side and the test interface uses a configurable custom IP.

5. The portable universal digital processing test system as claimed in claim 4, characterized in that: The PL end communicates with UART using 16-channel configurable UART IP to realize automatic testing of communication protocols such as RS485, RS422 and RS232; the PL end communicates with GPIO using 16-channel configurable discrete quantity IP to realize 3.3V single-ended discrete quantity test, 5V single-ended discrete quantity test, 28V single-ended discrete quantity test, 3.3V differential discrete quantity test, and 5V differential discrete quantity test; the PL end communicates with ARINC429 using configurable IP to realize automatic testing; the PL end communicates with the high-speed interface using configurable IP to realize the configuration of high-speed link ports with communication protocols such as SRIO, AURORA, JESD204B, FC, and SGMII, and realizes connection with the machine under test and automatic testing through optical cable assemblies.

6. The portable universal digital processing test system as claimed in claim 1, characterized in that: The communication between the PS end and the host computer adopts a link-unified ICD, and the unified ICD includes a test instruction packet and a test response packet in the same format.

7. The portable universal digital processing test system as claimed in claim 6, characterized in that: The instruction categories of the test instruction package of the unified ICD are divided into initialization, sending data, receiving data, starting test, and stopping test; the test categories are divided into SRIO test, SGMII test, AURORA test, memory test, UART test, and discrete quantity test.

8. The portable universal digital processing test system as claimed in claim 1, characterized in that: The cable assembly connecting the low-speed port and the device under test uniformly adopts a DB15 connector. The DB15 connector has 15 pins, and the 15 pins are divided into three groups, each group including input, output and ground.

9. The portable universal digital processing test system as claimed in claim 1, characterized in that: The communication protocol between the PS and PL ends adopts the AXI protocol.

10. A portable universal digital processing test method, using the portable universal digital processing test system according to any one of claims 1 to 9, characterized in that: include: Step 1: Digital processing test system connection; Step 2: Determine whether the system is connected successfully. If it fails, go to step 3, otherwise go to step 4; Step 3: Check the system wiring, and then proceed to step 1; Step 4: Enter the basic information of the device under test; Step 5: Check the test type, automatic test or manual interface test; Step 6: Start testing; Step 7: Wait for the test results; Step 8: Output test report; Step 9: Determine whether to continue the test, if yes, go to step 5, otherwise go to step 10; Step 10: End of testing.

Images