Low-delay high-speed interface serialization circuit and method and data sending equipment

Abstract

The invention provides a low-delay high-speed interface serialization circuit and method and data sending equipment, and the circuit comprises a clock generation module which generates a first clock which is opposite to a local high-frequency clock based on the input local high-frequency clock and a plurality of frequency division clocks with different frequency division multiplying powers; the loading signal generation module is used for generating a loading signal based on the logical operation result of each frequency division clock; and the data serial module receives multiple groups of parallel data to be sent, performs shift storage on the multiple groups of data to be sent under the control of the loading signal, and shifts out the multiple groups of data to be sent one by one under the control of the first clock to form serial data. Data sampling is carried out when the negative edge of the local high-frequency clock arrives, data shifting is carried out through the low-frequency frequency division clock, parallel data to be sent are converted into serial data, introduced delay can be reduced, meanwhile, the circuit structure is simplified, and chip miniaturization is better facilitated.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to a low-latency high-speed interface serialization circuit, method and data transmission device. Background Art

[0002] With the rise of artificial intelligence and the explosive growth of data volume, people have higher and higher requirements for data transmission bandwidth and energy efficiency, which has greatly stimulated the development of high-speed serial interface circuits. At the same time, the design of high-speed interface circuits is constantly challenging the process limits to meet higher speed and performance requirements.

[0003] During data transmission, parallel data usually needs to be converted into serial data for transmission. Traditional technology is to transmit data two bits at a time in series and multiplex the 2-to-1 module to achieve multi-bit data serial transmission. However, each multiplexing of the data selector will introduce a large delay, affecting the stability and reliability of data transmission. Summary of the invention

[0004] In view of the above problems existing in the prior art, the present invention proposes a low-latency high-speed interface serialization circuit, method and data sending device, which mainly solves the problem that the prior art has high serial conversion delay during high-speed data transmission, affecting the stability and reliability of data transmission.

[0005] In order to achieve the above purpose and other purposes, the technical solution adopted by the present invention is as follows.

[0006] The present application provides a low-latency high-speed interface serialization circuit, comprising: a clock generation module, which generates a first clock that is inversely phased with the local high-frequency clock and a plurality of divided clocks with different frequency division ratios based on an input local high-frequency clock; a load signal generation module, which generates a load signal based on the logic operation results of each of the divided clocks; a data serialization module, which receives multiple groups of parallel data to be sent, shifts and stores the multiple groups of data to be sent under the control of the load signal, and shifts out the multiple groups of data to be sent one by one under the control of the first clock to form serial data.

[0007] In an embodiment of the present application, the local high-frequency clock is generated by a data interface physical layer based on a local system clock.

[0008] In an embodiment of the present application, the duty cycle of the loading signal includes 1:3.

[0009] In an embodiment of the present application, the load signal generating module includes a logic operator, and the logic operator performs logical combination on a plurality of the divided clocks to obtain the load signal.

[0010] In one embodiment of the present application, the data serial module includes a plurality of data transmission units connected in series in sequence, each of the data transmission units includes a data selector and a D flip-flop; the output end of the data selector is connected to the input end of the D flip-flop, the output end of the D flip-flop serves as the output end of the corresponding data transmission unit, and is connected to one of the data input ends of the data selector of another data transmission unit through the output end of the D flip-flop to form a series structure, the output end of the D flip-flop located at the end of the series structure serves as the output end of the data serial module; one of the data input ends of the data selector located at the head end of the series structure is connected to a common ground; each of the data selectors is respectively connected to a group of the data to be sent, and the loading signal is connected to the selection control end of each of the data selectors; the first clock is connected to the clock input end of each of the D flip-flops.

[0011] In an embodiment of the present application, the data serial module performs data sampling at the rising edge of the first clock to shift out the corresponding data to be sent.

[0012] In an embodiment of the present application, the rising edge phase of the load signal is determined by the rising edge phase of the local high-frequency clock.

[0013] In an embodiment of the present application, the divided clock includes: a divided-by-two clock and a divided-by-four clock.

[0014] The present application also provides a low-latency high-speed interface serialization method, comprising:

[0015] Based on the input local high-frequency clock, a first clock that is inverted with the local high-frequency clock and multiple divided clocks with different division ratios are generated; a loading signal is generated based on the logical operation results of each of the divided clocks; multiple groups of parallel data to be sent are received, and the multiple groups of data to be sent are shifted and stored under the control of the loading signal, and the multiple groups of data to be sent are shifted out one by one under the control of the first clock to form serial data.

[0016] The present application also provides a data sending device, comprising the low-latency high-speed interface serialization circuit.

[0017] As described above, the low-latency, high-speed interface serialization circuit, method, and data transmission device proposed in the present application have the following beneficial effects.

[0018] The present application performs data sampling when the negative edge of the local high-frequency clock arrives, and uses a low-frequency divided clock to shift data, converting the parallel data to be sent into serial data. It does not need to go through the multiplexing 2-to-1 module, thereby reducing the introduced delay, simplifying the circuit structure, and being more conducive to chip miniaturization. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the traditional serial circuit structure.

[0020] Figure 2 This is the timing diagram of the traditional serial circuit.

[0021] Figure 3 Schematic diagram of the architecture of a low-latency high-speed interface serialization circuit in one embodiment of the present application.

[0022] Figure 4 Schematic diagram of a low-latency high-speed interface serialization circuit in one embodiment of the present application.

[0023] Figure 5 FIG. 4 is a timing diagram of a serialization circuit in an embodiment of the present application.

[0024] Figure 6 Schematic diagram of the process of a low-latency high-speed interface serialization method in one embodiment of the present application.

[0025] Figure 7 Schematic diagram of the architecture of a data sending device in one embodiment of the present application. DETAILED DESCRIPTION

[0026] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0027] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0028] The inventor has found that the prior art realizes multi-bit data serial transmission by serializing data every 2 bits and multiplexing the 2-to-1 module. Figure 1 , Figure 1 This is a schematic diagram of the traditional serial circuit structure. Let's take a 4-to-1 circuit as an example. Figure 1 This is the implementation of a serial 4-to-1 circuit. The circuit is mainly composed of a D flip-flop and a 2-to-1 data selector. The D flip-flop is used to implement data shift sampling, and the 2-to-1 data selector is used to convert 2 parallel data into 1 serial data. Figure 2 , Figure 2This is the timing diagram of the traditional serial circuit. Figure 2 The timing diagram shows that the initial data is aligned with the rising edge of the clock, and each multiplexing of the 2-to-1 module will introduce a delay of one entire cycle of the current sampling clock. For high-speed interface circuits, serial transmission of multi-bit width data will introduce too much delay, and for every additional 2 bits, more 2-to-1 modules must be multiplexed, resulting in more circuit components, which is not conducive to the miniaturization of the chip.

[0029] Based on the above problems existing in the prior art, the present application proposes a low-latency, high-speed interface serialization circuit, method and data sending device. The technical solution of the present application is elaborated in detail below in conjunction with specific embodiments.

[0030] See also Figure 3 , Figure 3 The schematic diagram of the architecture of the low-latency high-speed interface serialization circuit in one embodiment of the present application. The serialization circuit includes: a clock generation module 01, a load signal generation module 02 and a data serialization module 03. The clock generation module 01 can be used to generate a first clock that is inverted with the local high-frequency clock and a plurality of divided clocks with different frequency division ratios based on the input local high-frequency clock; the load signal generation module 02 can be used to generate a load signal load based on the logical operation results of each of the divided clocks; the data serialization module 03 can be used to receive multiple groups of parallel data to be sent, shift and store the multiple groups of data to be sent under the control of the load signal load, and shift out the multiple groups of data to be sent one by one under the control of the first clock to form serial data.

[0031] In one embodiment, the local high-frequency clock is a high-frequency clock whose frequency is an integer multiple of the local system clock frequency. Exemplarily, the frequency of the local high-frequency clock may be 4 times the frequency of the local system clock. Of course, the frequency may also be adjusted according to actual serial control requirements without limitation. Specifically, since the high-speed data interface physical layer usually operates at a frequency that is several times the frequency of the local system clock, the local high-frequency clock may be provided by the high-speed data interface physical layer.

[0032] In one embodiment, the clock generation module 01 may include an inverter and multiple frequency dividers, the inverter and the frequency divider are in parallel, and the local high-frequency clock is input into the inverter to obtain a first clock. When the rising edge of the first clock arrives, the data serial module 03 samples the parallel data to be sent. The frequency divider converts the local high-frequency clock into a low-frequency clock to obtain a divided clock with different frequency division ratios. For example, the divided clock may include a two-divided clock, a four-divided clock, etc. The load signal generation module 02 obtains the load signal load by logically combining multiple divided clocks. Of course, the structure and composition of the specific clock generation module 01 can also be configured and adjusted according to actual application requirements without limitation here.

[0033] In one embodiment, the load signal generating module 02 may include one or more logic operators. In the embodiment of the present application, the load signal generating module 02 receives a two-frequency-divided clock and a four-frequency-divided clock and performs a logical combination to obtain a load signal load as an example. The load signal generating module 02 may use a logic AND operator to obtain the load signal load by performing an AND operation on the two-frequency-divided clock and the four-frequency-divided clock. When there are more than two divided frequency clocks, a plurality of divided frequency clocks may be subjected to a logic AND operation to obtain the load signal load. Of course, the logical combination of divided frequency clocks is not limited to an AND operation, and the internal composition of the load signal generating module 02 and the operation logic for obtaining the load signal load may also be set and adjusted according to actual application requirements, which are not limited here.

[0034] In one embodiment, the data serial module 03 includes a plurality of data transmission units connected in series in sequence, each of the data transmission units includes a data selector and a D flip-flop; the output end of the data selector is connected to the input end of the D flip-flop, the output end of the D flip-flop serves as the output end of the corresponding data transmission unit, and is connected to one of the data input ends of the data selector of another data transmission unit through the output end of the D flip-flop to form a series structure, the output end of the D flip-flop located at the end of the series structure serves as the output end of the data serial module 03; one of the data input ends of the data selector located at the head end of the series structure is connected to a common ground; each of the data selectors is respectively connected to a group of the data to be sent, and the load signal load is connected to the selection control end of each of the data selectors; the first clock is connected to the clock input end of each of the D flip-flops.

[0035] See also Figure 4 , Figure 4This is a schematic diagram of a low-latency, high-speed interface serialization circuit in an embodiment of the present application. Taking the data serial module 03 composed of four data transmission units as an example, each data transmission unit includes a data selector and a D flip-flop, each data selector includes a selection control terminal, two data input terminals and an output terminal, and the D flip-flop includes an input terminal, an output terminal and a clock input terminal. The output terminal of the data selector is connected to the input terminal of the D flip-flop, and the output terminal of the D flip-flop is connected to one of the data input terminals of the data selector of the next data transmission unit, thereby forming a series structure of multiple data transmission units. The clock input terminal of each D flip-flop is connected to the first clock, and the D flip-flop is controlled by the first clock to shift data. One of the data input terminals of each data selector is connected to a group of data to be sent. Assume that the data to be sent includes four groups, respectively represented as dp <0> 、dp <1> 、dp <2> and dp <3> , one of the data input terminals int0 of the data selector at the head end of the series structure is connected to the common ground VSS, and the other data input terminal int1 is connected to dp <3> ; int0 of the second data selector is connected to the output terminal Q of the D flip-flop at the head of the series structure, and int1 is connected to dp <2> ; int0 of the third data selector is connected to the output terminal Q of the D flip-flop of the previous data transmission unit, and int1 is connected to dp <1> ; int0 of the fourth data selector is connected to the output terminal Q of the D flip-flop of the previous data transmission unit, and int1 is connected to dp <0> , the D flip-flop connected to the output end of the fourth data selector is the D flip-flop at the end of the series structure, and the output end of the D flip-flop serves as the output end of the entire data series module. The selection control end of each data selector is connected to the loading signal load, and the data selector is controlled by the low-frequency loading signal load to shift and store the data to be sent, and then the high-frequency first clock is used to control the D flip-flop to shift the data out to form serial data. Only using the high-frequency first clock for data sampling can reduce the data sampling error problem that may be caused by multiple samplings of clocks with different frequencies, reduce the timing requirements on the sampling path, and at the same time realize data loading through the low-frequency loading signal load, and only using the high-frequency first clock for sampling can greatly reduce the delay caused by multiple data conversions. Of course, the number of data transmission units in the series structure can also be set and adjusted according to actual application requirements, and there is no restriction here.

[0036] See also Figure 5 , Figure 5 FIG. 1 is a timing diagram of a serialization circuit in an embodiment of the present application. Figure 5It can be seen that the rising edge phase of the load signal load is determined by the local high-frequency clock (i.e., it is consistent with the local input data), and only the falling edge of the local high-frequency clock needs to be used for sampling during the data serial sampling process, which can not only ensure the correctness of data sampling, but also greatly reduce the delay, and the delay is only one unit time interval (Unit Interval, UI). Exemplarily, the duty cycle of the load signal load can be set to 1:3, and of course, the duty cycle can also be set according to the actual shift sampling requirements, which is not limited here.

[0037] Based on the technical solution of the above embodiment of the present application, the clock generation module 01 generates clocks of multiple frequencies and phases based on the local high-frequency clock, and the loading signal load is generated by logically combining the multiple clocks generated by the clock generation module 01. The loading signal load is used to load the parallel data to be sent, and then the inverted clock of the local high-frequency clock is used to control the D flip-flop to shift the data. The data serialization is realized through the shifting function of the D flip-flop, which simplifies the circuit structure, uses fewer hardware modules, reduces the chip area, reduces the cost, and is more conducive to chip miniaturization. At the same time, data loading is realized by loading the signal load, and only the falling edge of the local high-frequency clock is used for sampling, which can reduce the problem of data sampling errors that may be caused by multiple samplings of clocks with different frequencies, and reduce the timing requirements on the path.

[0038] See also Figure 6 , Figure 6 The following is a flow chart of a low-latency high-speed interface serialization method in an embodiment of the present application. The serialization method comprises the following steps:

[0039] Step S600, generating a first clock having a phase opposite to the local high-frequency clock and a plurality of divided clocks having different frequency division ratios based on the input local high-frequency clock;

[0040] Step S610, generating a load signal based on the logic operation results of each of the divided clocks;

[0041] Step S620, receiving multiple groups of parallel data to be sent, shifting and storing the multiple groups of data to be sent under the control of the load signal, and shifting out the multiple groups of data to be sent one by one under the control of the first clock to form serial data.

[0042] The serialization method of the embodiment of the present application relies on the aforementioned low-latency and high-speed serialization circuit, and the specific circuit structure will not be repeated here. Based on the local high-frequency clock, a first clock and multiple divided clocks are generated, and a loading signal is obtained by logically combining the divided clocks. The loading signal is also a low-frequency signal. Parallel data is loaded based on the loading signal, and the loaded data is shifted out to form serial data using the inverted clock of the local high-frequency clock. The first clock is also a high-frequency clock, and serialized data sampling is performed only through the high-frequency clock, which can reduce the problem of sampling data errors caused by traditional sampling of multiple clocks with different frequencies, and also greatly reduce the delay, which can be controlled within one UI.

[0043] See also Figure 7 , Figure 7 Schematic diagram of the architecture of a data transmission device 70 in an embodiment of the present application. The data transmission device 70 may include one or more of the aforementioned low-latency high-speed interface serialization circuits 71, which are used to convert parallel data into serial data for transmission. The structure and composition of the specific data transmission device 70 can be set and adjusted according to actual production application requirements, and are not limited here.

[0044] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A low-latency high-speed interface serialization circuit, characterized in that: include: A clock generating module, which generates a first clock which is inverted with respect to the local high-frequency clock and a plurality of divided clocks with different frequency division ratios based on an input local high-frequency clock; A load signal generating module, which generates a load signal based on the logic operation result of each of the divided frequency clocks; A data serial module receives multiple groups of parallel data to be sent, shifts and stores the multiple groups of data to be sent under the control of the loading signal, and shifts out the multiple groups of data to be sent one by one under the control of the first clock to form serial data.

2. The low-latency high-speed interface serialization circuit according to claim 1, characterized in that: The local high-frequency clock is generated by the data interface physical layer based on the local system clock.

3. The low-latency high-speed interface serialization circuit according to claim 1, characterized in that: The duty cycle of the loading signal includes 1:

3.

4. The low-latency high-speed interface serialization circuit according to claim 1, characterized in that: The load signal generating module includes a logic operator, and the logic operator is used to logically combine a plurality of the divided clocks to obtain the load signal.

5. The low-latency high-speed interface serialization circuit according to claim 1, characterized in that: The data serial module includes a plurality of data transmission units connected in series in sequence, each of the data transmission units includes a data selector and a D flip-flop; the output end of the data selector is connected to the input end of the D flip-flop, the output end of the D flip-flop serves as the output end of the corresponding data transmission unit, and is connected to one of the data input ends of the data selector of another data transmission unit through the output end of the D flip-flop to form a series structure, the output end of the D flip-flop located at the end of the series structure serves as the output end of the data serial module; one of the data input ends of the data selector located at the head end of the series structure is connected to a common ground; each of the data selectors is respectively connected to a group of the data to be sent, and the loading signal is connected to the selection control end of each of the data selectors; the first clock is connected to the clock input end of each of the D flip-flops.

6. The low-latency high-speed interface serialization circuit according to claim 1, characterized in that: The data serial module performs data sampling at the rising edge of the first clock to shift out the corresponding data to be sent.

7. The low-latency high-speed interface serialization circuit according to claim 1, characterized in that: The rising edge phase of the load signal is determined by the rising edge phase of the local high-frequency clock.

8. The low-latency high-speed interface serialization circuit according to claim 1, characterized in that: The frequency-divided clock includes: a divided-by-two clock and a divided-by-four clock.

9. A low-latency high-speed interface serialization method, characterized in that: include: Generate a first clock which is inverted with respect to the local high-frequency clock and a plurality of divided clocks with different frequency division ratios based on an input local high-frequency clock; generating a load signal based on a logic operation result of each of the divided frequency clocks; A plurality of groups of parallel data to be sent are received, the plurality of groups of data to be sent are shifted and stored under the control of the loading signal, and the plurality of groups of data to be sent are shifted out one by one under the control of the first clock to form serial data.

10. A data transmission device, characterized in that: It comprises the low-latency high-speed interface serialization circuit described in any one of claims 1-8.

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