Low-delay high-speed interface deserialization circuit and method and data receiving equipment
By using a high -frequency clock and the solution -stringing circuit based on high -frequency clocks and frequency split clocks in high -speed interface circuits, the problems of high -delay and complicated circuits in the existing technology have been solved, and low -delayed and efficient data solving serial lines are achieved. It promotes miniaturization of chip.
Patent Information
- Application Number
- CN202411315540.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-20
- Publication Date
- 2025-01-24
AI Technical Summary
The prior art has high delays during the deserialization process and many circuit devices, which is not conducive to the miniaturization of chips.
A low -delay high -speed interface unlocking lines, including clock generating modules, shifting multi -way data generation modules, and data solving serial modules. Based on the first clock and frequency split clock based on the local high -frequency clock, the data shift and sampling are performed, and the multi -way data to be converted into multi -road parallel data output.
It effectively reduces the delay of the data transmission link, simplifies the circuit structure, reduces the number of hardware modules, facilitates chip miniaturization, and reduces timing requirements and the possibility of data sampling errors.
Smart Images
Figure CN119357105A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of data transmission, and in particular to a low-latency high-speed interface deserialization circuit, method and data receiving device. Background Art
[0002] With the rise of artificial intelligence and the explosive growth of data volume, people have higher and higher requirements for data transmission bandwidth and energy efficiency, which has greatly stimulated the development of high-speed serial interface circuits. At the same time, the design of high-speed interface circuits is constantly challenging the process limits to meet higher speed and performance requirements.
[0003] The prior art realizes multi-bit data deserialization transmission by multiplexing 1-to-2 deserialization modules. However, this method introduces too much delay and has too many circuit components, which is not conducive to the miniaturization of the chip. Summary of the invention
[0004] In view of the above problems existing in the prior art, the present invention proposes a low-latency high-speed interface deserialization circuit, method and data receiving device, which mainly solve the problem of high delay in the deserialization process in the prior art.
[0005] In order to achieve the above purpose and other purposes, the technical solution adopted by the present invention is as follows.
[0006] The present application provides a low-latency high-speed interface deserialization circuit, comprising:
[0007] A clock generating module, which generates a first clock which is inversely phased with the local high-frequency clock and a frequency-divided clock of the local high-frequency clock based on an input local high-frequency clock;
[0008] a shifted multi-channel data generating module, which performs data shifting based on the first clock to convert the input serial data into multiple channels of data to be deserialized, wherein the delay interval between two adjacent channels of data to be deserialized is equal to one cycle of the local high-frequency clock;
[0009] The data deserialization module performs data sampling based on the divided clock to convert the multiple channels of deserialized data into multiple channels of parallel data output.
[0010] In one embodiment of the present application, the shifted multi-channel data generating module includes a plurality of first D flip-flops connected in series in sequence, the clock input end of each of the first D flip-flops is connected to the first clock, and the output end of each of the first D flip-flops respectively outputs one path of the data to be deserialized to the data deserialization module.
[0011] In an embodiment of the present application, a buffer is provided between two adjacent first D flip-flops.
[0012] In one embodiment of the present application, the data deserialization module includes a plurality of parallel second D flip-flops; the clock input terminal of each of the second D flip-flops is connected to the divided clock, the data input terminal is connected to one of the data to be deserialized, and the data output terminal outputs one of the parallel data.
[0013] In an embodiment of the present application, the divided clock includes a divided-by-four clock.
[0014] In an embodiment of the present application, the duty cycle of the divided clock includes 1:1.
[0015] The present application also provides a low-latency high-speed interface deserialization method, comprising: generating a first clock that is inverted to the local high-frequency clock and a divided clock of the local high-frequency clock based on an input local high-frequency clock; performing data shifting based on the first clock to convert the input serial data into multiple channels of data to be deserialized, wherein the delay interval between two adjacent channels of data to be deserialized is equal to one cycle of the local high-frequency clock; performing data sampling based on the divided clock to convert the multiple channels of data to be deserialized into multiple channels of parallel data output.
[0016] The present application also provides a data receiving device, comprising the low-latency high-speed interface deserialization circuit.
[0017] As described above, the present invention provides a low-latency, high-speed interface deserialization circuit, method and data receiving device, which have the following beneficial effects.
[0018] The present application utilizes a first clock and a divided clock for deserialization, performs data shifting based on the first clock control, obtains multi-path delayed data to be deserialized with a difference of one local high-frequency clock cycle, and then utilizes a low-frequency divided clock for data sampling to achieve data deserialization. The circuit structure is simple, the hardware modules are fewer, and it is conducive to chip miniaturization. At the same time, it reduces the data sampling error problem that may be caused by multiple samplings of clocks with different frequencies, and reduces the timing requirements on the path. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 The schematic diagram of the existing deserialization 1 to 4 circuit.
[0020] Figure 2 It is a timing diagram of the existing deserialization 1 to 4 circuit.
[0021] Figure 3 Schematic diagram of the architecture of a low-latency high-speed interface deserialization circuit in one embodiment of the present application.
[0022] Figure 4 Schematic diagram of a low-latency high-speed interface deserialization circuit in one embodiment of the present application.
[0023] Figure 5This is a timing diagram of a low-latency high-speed interface deserialization circuit in one embodiment of the present application.
[0024] Figure 6 Schematic diagram of the process of low-latency high-speed interface deserialization method in one embodiment of the present application.
[0025] Figure 7 Schematic diagram of the architecture of a data receiving device in one embodiment of the present application. DETAILED DESCRIPTION
[0026] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.
[0027] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0028] The inventor has found that the prior art realizes multi-bit data deserialization transmission by multiplexing 1 to 2 modules. Taking the 1 to 4 circuit as an example, Figure 1 The schematic diagram of the existing deserialization 1 to 4 circuit is shown in FIG. The circuit is mainly composed of a D flip-flop, which is used to realize the shift sampling of data. Figure 2 The timing diagram of the existing deserialization 1 to 4 circuit is shown in FIG. Figure 2 The timing diagram shows that the initial data is aligned with the rising edge of the clock. To ensure the correctness of data sampling, the clock negative edge is used for sampling first, and then the 1-to-2 data deserialization operation is performed. Each time the 1-to-2 module is multiplexed, a delay of 3 / 4 cycles of the current sampling clock is introduced. For high-speed interface circuits, deserialization of multi-bit width data will introduce too much delay, and there are many circuit components, which is not conducive to the miniaturization of chips.
[0029] Based on the above problems existing in the prior art, the present application proposes a low-latency, high-speed interface deserialization circuit, method and data receiving device. The technical solution of the present application is elaborated in detail below in conjunction with specific embodiments.
[0030] See also Figure 3 , Figure 3The schematic diagram of the architecture of the low-latency high-speed interface deserialization circuit in one embodiment of the present application. The low-latency high-speed interface deserialization circuit in the embodiment of the present application includes: a clock generation module 01, which generates a first clock that is inverted with the local high-frequency clock and a frequency-divided clock of the local high-frequency clock based on the input local high-frequency clock; a shifted multi-channel data generation module 02, which performs data shifting based on the first clock to convert the input serial data into multiple channels of data to be deserialized, wherein the delay interval between two adjacent channels of data to be deserialized is equal to one cycle of the local high-frequency clock; a data deserialization module 03, which performs data sampling based on the frequency-divided clock to convert the multiple channels of data to be deserialized into multiple channels of parallel data output.
[0031] In one embodiment, the local high-frequency clock is a high-frequency clock whose frequency is an integer multiple of the local system clock frequency. Exemplarily, the frequency of the local high-frequency clock may be 4 times the frequency of the local system clock. Of course, the frequency may also be adjusted according to actual deserialization control requirements without limitation. Specifically, since the high-speed data interface physical layer usually operates at a frequency that is several times the frequency of the local system clock, the local high-frequency clock may be provided by the high-speed data interface physical layer.
[0032] In one embodiment, the clock generation module 01 may include an inverter and a frequency divider, the inverter and the frequency divider are in parallel, and the local high-frequency clock is input into the inverter to obtain a first clock. When the rising edge of the first clock arrives, the shifted multi-channel data generation module 02 samples the serial data. The frequency divider converts the local high-frequency clock into a low-frequency clock to obtain a divided clock. For example, the divided clock may include a two-divided clock or a four-divided clock. Of course, the structure and composition of the specific clock generation module 01 can also be configured and adjusted according to actual application requirements without limitation. The divided clock is input into the data deserialization module 03, so that the data deserialization module 03 performs data sampling based on the divided clock, and converts the multi-channel delayed interval of the deserialization data to be deserialized in a local high-frequency clock cycle into parallel data of the corresponding number of channels.
[0033] See also Figure 4 , Figure 4The schematic diagram of the low-latency high-speed interface deserialization circuit in one embodiment of the present application. In one embodiment, the shift multiple data generation module 02 has multiple first D flip-flops connected in series in sequence, and the clock input end of each of the first D flip-flops is connected to the first clock, and the output end of each of the first D flip-flops outputs one path of the data to be deserialized to the data deserialization module 03. Taking the shift multiple data generation module 02 composed of four D flip-flops connected in series as an example, the clock input end of each first D flip-flop in the series structure is connected to the first clock, and when the rising edge of the first clock arrives, the data is shifted by using the shift function of the first D flip-flop. The input and output ends of the four first D flip-flops are connected in series in sequence, and the input end of the first D flip-flop at the head end of the series structure is connected to the serial data. After the first first D flip-flop is shifted, the first path of the data to be deserialized ds_d3 is obtained, after the second first D flip-flop is shifted, the second path of the data to be deserialized ds_d2 is obtained, after the third first D flip-flop is shifted, the second path of the data to be deserialized ds_d1 is obtained, and after the fourth first D flip-flop is shifted, the fourth path of the data to be deserialized ds_d0 is obtained. Two adjacent channels of deserialized data are separated by a local high-frequency clock cycle. For example, ds_d3 and ds_d2 differ by a local high-frequency clock cycle, ds_d2 and ds_d1 differ by a local high-frequency clock cycle, and ds_d1 and ds_d0 differ by a local high-frequency clock cycle. The number of the first D flip-flops can be set and adjusted according to actual application requirements, and is not limited here.
[0034] In one embodiment, a buffer is provided between each first D flip-flop in the shifted multi-channel data generating module 02, and the node between the buffer and the connected first D flip-flop serves as the output node of the data to be deserialized. Specifically, a buffer can be connected in series between two adjacent first D flip-flops, and a buffer can be connected to the input end of the D flip-flop, thereby increasing the holding time of the sampling and ensuring the correct sampling and shifting of the data.
[0035] In one embodiment, the data deserialization module 03 may include a plurality of parallel second D flip-flops; the clock input of each of the second flip-flops is connected to the divided clock, the data input is connected to one of the data to be deserialized, and the data output outputs one of the parallel data. Specifically, taking the data deserialization module 03 composed of four parallel second D flip-flops as an example, the clock input of each second D flip-flop is connected to the divided signal, and the data is sampled using the low-frequency clock obtained by dividing the local high-frequency clock, and the data input of each second D flip-flop is connected to one of the data to be deserialized output by the shift multi-channel data generation module 02. The data output from the output ends of the four second D flip-flops constitute four parallel data. Exemplarily, the data input of the first second D flip-flop is connected to the ds_d3 obtained above, and the output dp <3> ; The data input terminal of the second D flip-flop is connected to the ds_d2 obtained above, and the output dp <2> ; The data input terminal of the third second D flip-flop is connected to the ds_d1 obtained above, and the output dp <1> ; The data input terminal of the fourth second D flip-flop is connected to the ds_d0 obtained above, and the output dp <0> , dp <3> 、dp <2> 、dp <1> 、dp <0> Of course, the number of the second D flip-flops in the data deserialization module 03 can be set and adjusted according to actual application requirements, and is not limited here.
[0036] See also Figure 5 , Figure 5 This is a timing diagram of a low-latency high-speed interface deserialization circuit in an embodiment of the present application. Here, the four-divided clock of the local high-frequency clock clk4x is used as the sampling clock of the data deserialization module 03. The duty cycle of the divided clock can be set to 1:1. The specific duty cycle of the divided clock can be set and adjusted according to the actual sampling requirements, and there is no restriction here. The local high-frequency clock clk4x generates a first clock clk4xb and a divided clock clk1x through the clock generation module 01. The received local serial data ds is connected in series with the first clock clk4xb through four D flip-flops to obtain four groups of data with a delay of one high-frequency clock cycle, and a buffer is connected to the input end of the D flip-flop to increase the sampling time and ensure the correct sampling and shifting of the data. The four groups of data ds_d3~ds_d0 are sampled with the divided clock clk1x respectively, that is, 4 output parallel data dp are obtained. <3> ~dp <0> .based on Figure 2 and Figure 5 By comparing the timing diagrams, it can be seen that the traditional deserialization circuit has a delay of 10 unit intervals (UI), while the deserialization circuit using the embodiment of the present application has a delay of only 8 UI. The deserialization circuit of the present application can effectively reduce the delay of the data transmission link.
[0037] Based on the technical solution of the embodiment of the present application, the shift function of the D flip-flop is used to first obtain multi-channel serial data with a delay difference of one high-frequency clock cycle, and then the multi-channel serial data is sampled using a local low-frequency clock to achieve data deserialization, simplifying the circuit structure, using fewer hardware modules, reducing the chip area, reducing costs, and being more conducive to chip miniaturization. At the same time, the data sampling error problem that may be caused by multiple samplings of clocks with different frequencies is reduced, the timing requirements on the path are reduced, and a buffer is added before the D flip-flop, which increases the hold time, and the delay of the entire data transmission link is reduced.
[0038] See also Figure 6 , Figure 6 The following is a flow chart of a low-latency high-speed interface deserialization method in an embodiment of the present application. The deserialization method comprises the following steps:
[0039] Step S600, generating a first clock that is inversely phased with the local high-frequency clock and a frequency-divided clock of the local high-frequency clock based on the input local high-frequency clock;
[0040] Step S610, performing data shifting based on the first clock to convert the input serial data into multiple channels of data to be deserialized, wherein the delay interval between two adjacent channels of data to be deserialized is equal to one cycle of the local high-frequency clock;
[0041] Step S620: performing data sampling based on the divided clock to convert the multiple channels of deserialized data into multiple channels of parallel data output.
[0042] The deserialization method of the embodiment of the present application relies on the aforementioned low-latency high-speed interface deserialization circuit, and the specific circuit structure is not repeated here. The deserialization method of the embodiment of the present application first generates a negative edge sampling clock of a local high-frequency clock and a local low-frequency clock through the clock generation module 01, and the received serial data is passed through the shift multi-channel data generation module 02 to obtain multiple groups of data with a delay difference of one local high-frequency clock cycle, and then the multiple groups of data are sampled respectively with the divided clock to obtain output parallel data.
[0043] See also Figure 7 , Figure 7 Schematic diagram of the architecture of a data receiving device 70 in an embodiment of the present application. The present application embodiment also provides a data receiving device 70, which includes one or more of the aforementioned low-latency high-speed interface deserialization circuits 71, receives serial data, and converts the serial data into parallel data using the low-latency high-speed interface deserialization circuits 71. The specific deserialization process has been described in detail in the aforementioned embodiment and will not be repeated here.
[0044] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A low-latency high-speed interface deserialization circuit, characterized in that: include: A clock generating module, which generates a first clock which is inversely phased with the local high-frequency clock and a frequency-divided clock of the local high-frequency clock based on an input local high-frequency clock; a shifted multi-channel data generating module, which performs data shifting based on the first clock to convert the input serial data into multiple channels of data to be deserialized, wherein the delay interval between two adjacent channels of data to be deserialized is equal to one cycle of the local high-frequency clock; The data deserialization module performs data sampling based on the divided clock to convert the multiple channels of deserialized data into multiple channels of parallel data output.
2. The low-latency high-speed interface deserialization circuit according to claim 1, characterized in that: The shift multi-channel data generating module includes a plurality of first D flip-flops connected in series in sequence, the clock input end of each first D flip-flop is connected to the first clock, and the output end of each first D flip-flop respectively outputs one channel of the to-be-deserialized data to the data deserialization module.
3. The low-latency high-speed interface deserialization circuit according to claim 2, characterized in that: A buffer is arranged between two adjacent first D flip-flops.
4. The low-latency high-speed interface deserialization circuit according to claim 1, characterized in that: The data deserialization module comprises a plurality of parallel second D flip-flops; the clock input terminal of each of the second D flip-flops is connected to the divided clock, the data input terminal is connected to one of the data to be deserialized, and the data output terminal outputs one of the parallel data.
5. The low-latency high-speed interface deserialization circuit according to claim 1, characterized in that: The divided-frequency clock includes a divided-frequency clock by four.
6. The low-latency high-speed interface deserialization circuit according to claim 1, characterized in that: The duty cycle of the divided clock includes 1:
1.
7. A low-latency high-speed interface deserialization method, characterized in that: include: Generate a first clock which is inversely phased with the local high-frequency clock and a divided clock of the local high-frequency clock based on an input local high-frequency clock; Performing data shifting based on the first clock to convert the input serial data into multiple channels of data to be deserialized, wherein the delay interval between two adjacent channels of data to be deserialized is equal to one cycle of the local high-frequency clock; Data sampling is performed based on the divided clock to convert the multiple channels of to-be-deserialized data into multiple channels of parallel data output.
8. A data receiving device, characterized in that: It comprises the low-latency high-speed interface deserialization circuit described in any one of claims 1-6.