IP core hardware time side channel detection method based on path

Abstract

The invention discloses a path-based IP core hardware time side channel detection method, and aims to reduce verification time overhead of information flow tracking logic and facilitate rapid detection of a time side channel. According to the method, RTL hardware design codes or gate-level netlists are verified in the design or test stage, chip vulnerabilities of manufactured tape-out sheets are not considered, and the purpose is to identify and eliminate security vulnerabilities before hardware manufacturing. According to the method, the shortest path from the specified input to the target output of the integrated backdoor-level netlist is extracted, the information flow tracking logic is constructed for the shortest path, and finally, the time side channel vulnerability of the hardware IP core is verified. By extracting the shortest path, the complexity of information flow tracking logic is reduced, and the safety verification efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of time side channel detection, and in particular to a path-based IP core hardware time side channel detection method. Background Art

[0002] Timing side-channel attacks infer sensitive information by analyzing the response, processing, or execution time of hardware designs, thereby undermining system security. Timing side-channel attacks are highly concealed and difficult to detect and defend against. Therefore, it is crucial to identify and detect timing side-channel vulnerabilities in hardware architectures (IP cores) in the pre-silicon design stage. Zhang et al. introduced the hardware design language SecVerilog in the paper "A hardware design language for timing-sensitive information-flow security" to perform static analysis of information flow at the hardware level, and can use a secure type system to accurately reason about and securely enhance the timing information flow. The paper "Information flow isolation in i2c and usb" proposed gate-level information flow tracing (GLIFT) that can track information flow at the Boolean logic gate level and can be used to identify timing side-channel vulnerabilities. Qin et al. proposed a method for modeling hardware design timing changes in the paper "A formal model for proving hardware timing properties and identifying timing channels". By proving the timing invariance of the hardware design, the timing side channel can be detected. Khitam et al. proposed a method for verifying and monitoring the security properties of timing-based information flow in the paper “Efficient method for timing-based information flow verification in hardware designs”. Hu et al. proposed a method for creating an information flow model suitable for verification properties for specific information flow security properties in the paper “Property specific information flow analysis for hardware security verification” to quickly detect time side channel vulnerabilities. Existing security verification methods require designers to write hardware models in new languages ​​or create new information flow tracking logic to track each flow of the hardware design. The model is highly complex and the verification and detection overhead is large. It is worth noting that when verifying the security properties of time information flow, only the paths related to the security properties to be verified need to be focused on. For example, it is possible to identify whether the information of a subset of confidential signal bits (one or several confidential signal bits) is leaked to the target output signal, and only the propagation path from a specific confidential signal bit to the output signal in the hardware IP design is focused on. This will simplify the generated information flow tracking logic and improve the verification efficiency. Summary of the invention

[0003] The present invention proposes a path-based IP core hardware time side channel detection method. Starting from the path related to the time information flow, the information flow tracking logic of the shortest path from the specified input to the target output is generated, and formal verification and simulation analysis are performed to detect the time side channel of the hardware design in the design stage. The invention reduces the complexity and scale of the information flow tracking logic and improves the efficiency of security verification.

[0004] The path-based IP core hardware time side channel detection framework proposed in the present invention is as follows Figure 2 As shown, the invention analyzes the confidentiality security requirements of the hardware design, extracts the specified input signal and the target output signal, finds the shortest path from the specified input signal to the target output signal, then maps the tracing logic to the extracted shortest path, generates the tracing logic about the shortest path, and then converts the security attributes and security rules into security constraints and assertions. Finally, formal verification tools and simulation tools are used to analyze whether the hardware design meets the security rule requirements, and the time side channel vulnerability is further confirmed by simulation verification through the counterexample given by the formal verification tool.

[0005] The analysis framework includes three processing modules: the shortest path generation module, the information flow tracing logic generation module, and the security detection module. The shortest path generation module extracts the shortest path from the specified input to the target output based on the gate-level netlist. The information flow tracing logic generation module mainly generates the corresponding tracing logic for the shortest path of the gate-level netlist. The security detection module uses formal verification tools to verify the analysis and simulates the extracted counterexamples to confirm the time side channel. The following introduces these three components respectively:

[0006] 1) The shortest path generation module is the most important module in the analysis framework. This module first generates a gate-level netlist file for the hardware design, selects the specified input and target output according to the security threat model and security attribute requirements of the security verification module, and then extracts the shortest path from the specified input to the target output. The present invention proposes a shortest path extraction method such as Figure 3 This method finds the shortest path from a specified input signal to a target output signal. The input is a gate-level netlist file, a specified input signal, and a target output signal. The output is the shortest path.

[0007] Step 1: First, traverse the gate-level netlist to see if the specified input signal exists in the fan-in cone. If so, add this node to the path array and store the path array in queue Q.

[0008] Step 2: When the queue Q is not empty, take the path array from the queue and take out the fan-out of the last element of the path array.

[0009] Step 3: If the target output signal is the fan-out of the last element of the path array, then the path array is output. The output path array is the shortest path we are looking for.

[0010] Step 4: If the target output signal is not the fan-out of the last element of the path array, continue to traverse the gate-level netlist file to check whether the fan-out of the last element of the path array exists in the fan-in cone. If so, add the node to the path array, and then add the added path array to the queue Q.

[0011] Step 5: When the algorithm finds the target output, it outputs the stored path array, which contains all the nodes from the specified input signal to the target output signal.

[0012] 2) Information flow tracing logic generation module, firstly selects appropriate information flow propagation rules according to the accuracy requirements to establish an information flow tracing logic library containing basic logic gates, mainly including AND gates, OR gates, NOT gates and D flip-flops. Then, the logic gates contained in the shortest path are mapped one by one according to the information flow tracing logic library, and the information flow tracing logic of the shortest path is generated.

[0013] 3) The security detection module includes the construction of security attributes and security rule assertions, formal verification detection and simulation confirmation of counterexamples. Based on the confidentiality security requirements and security threat models, the security attributes and security rules that the hardware design needs to meet are constructed, and security attribute and security rule assertion statements are constructed accordingly as constraints of the formal verification tool. Then the assertion statements and information flow tracing logic are integrated into the formal verification tool for verification. If the assertion fails, the formal verification tool will provide a counterexample that violates the time side channel security rule. Finally, the information flow tracing logic of the entire hardware design is used to simulate and analyze the counterexample to confirm that the hardware design has time side channel information leakage. It is worth noting that since the extracted shortest path is only a part of the entire IP core hardware design circuit, the shortest path tracing logic input includes not only the security attribute labels of the IP core hardware design input port but also the security attribute labels from the internal circuit of the IP core hardware design. For these security attribute labels from the internal design, the formal verification tool automatically assigns values ​​to them without constraints. In order to confirm that the situation provided by the counterexample exists in the state space of the time side channel security rule violation, simulation verification is required based on the situation provided by the counterexample. According to the definition of information flow tracing, if the counterexample provided by the formal verification tool causes the security attribute label of the shortest path tracing logic input to be contaminated, that is, the situation provided by the counterexample does exist in the state space where the time side channel security rule is violated, it means that the existence of a time side channel in the hardware design is confirmed, causing the confidential information of the specified input to flow out to the output signal port through the shortest path channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A step diagram of a path-based IP core hardware time side channel detection method proposed by the present invention;

[0015] Figure 2 A framework flow chart of a path-based IP core hardware time side channel detection method proposed by the present invention;

[0016] Figure 3 A shortest path extraction method for a path-based IP core hardware time side channel detection method proposed by the present invention; DETAILED DESCRIPTION

[0017] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when the detailed description of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0018] Figure 1 It is a flow chart of an experimental scheme of a path-based IP core hardware time side channel detection method of the present invention.

[0019] In this embodiment, if Figure 1 As shown, the path-based IP core hardware time side channel detection method of the present invention comprises the following steps:

[0020] Step 1: This experiment uses the RSA-T100 hardware IP design from Trust-HUB.org.

[0021] Step 2: First, use the logic synthesis tool Synopsys Design Compiler to perform logic synthesis on the RSA-T100 hardware IP core to generate a gate-level netlist. Then analyze the generated logic netlist and select the specified input signal (i.e., the confidential signal bit key signal) and the target output signal (i.e., the ready signal) according to the time side channel security threat model and confidentiality security requirements faced by RSA-T100.

[0022] Step 3: Find the shortest path from the specified input signal to the output signal through the proposed shortest path extraction algorithm.

[0023] Step 4: Generate information flow tracking logic based on the extracted shortest path. Instantiate the information flow tracking logic for each gate-level circuit logic unit in the path to generate the information flow tracking logic of the shortest path of the RSA-T100 hardware IP core.

[0024] Step 5: Use the formal verification tool Questa Formal to perform formal verification. First, perform information flow security analysis on the RSA-T100 hardware IP core, divide the security levels of related signals, set security labels, build information flow security rules, generate security attribute assertion statements, and define and implement the prohibition or permission of information flow through security attributes and security rule assertion statements.

[0025] In this embodiment, for the RSA-T100 hardware IP core, to verify that there is no time side channel, it is necessary to ensure that there is no information flow between the confidential signal bit and the completion signal. If there is information flow, it proves that there is a time side channel. The input signal inExp[1] and the output signal ready signal are used as the specified input signal and the target output signal, and the shortest path between the target signals is extracted, so that the label of the confidential signal bit inExp[1] is HIGH, indicating that the confidential signal bit is confidential, and the label of the output signal ready is LOW, indicating that the confidential signal bit inExp[1] should not flow to the ready signal. The information flow tracking logic generated by the extracted shortest path involves only the pollution labels of the specified input signal and output signal and the pollution labels of the internal circuit signals. Therefore, only the specified input signal inExp[1] and the target output signal ready need to be constrained. The pollution labels of the internal circuit signals are not constrained, and the formal verification tool automatically assigns values. The specific description is as follows:

[0026] 1:set inExp[1]_t=high

[0027] 2: assert ready_t = low

[0028] The assertion properties were verified using a formal verification tool, and the result showed that the assertion failed. This result shows that in the verification state space of the formal verification tool, there is a situation that makes the label of the ready signal HIGH, so the verification failed and there is a time information flow that violates the safety rules.

[0029] Step 8: Perform simulation verification of the counterexample. Since the extracted path is only a part of the entire gate-level netlist, part of the value of the security attribute label of the information flow tracing logic input of the shortest path is automatically assigned by the formal verification tool. In this embodiment, the situation provided by the counterexample is simulated and verified using the complete information flow tracing logic designed by the IP core. It is only necessary to confirm through simulation verification that the situation provided by the counterexample effectively shows that the information flow eventually flows to the observed output signal via the shortest path, and then it can be confirmed that the hardware IP core has a time side channel vulnerability. Checking the counterexample given by the verification tool, the results show that when the label of the confidential signal bit inExp[1] is HIGH, after encryption is completed, the label of the ready signal changes from LOW to HIGH, and the information of the confidential signal bit is propagated to the ready signal through the path, indicating that the counterexample violates the set security attribute assertion. The counter-example provided the situation using the complete information flow tracing logic of the IP core design to simulate and verify. For those security attribute labels automatically assigned by the formal verification tool, the counter-example provided the situation where the security attribute label value of the information flow tracing logic of the shortest path is HIGH, which is consistent with the simulation result of the complete information flow tracing logic of the IP core design, ensuring that there is at least one input situation that makes the HIGH level information of the specified input inExp[1] flow through the extracted shortest path and finally flow to the LOW level output signal ready. The simulation experiment effectively confirmed the existence of the time side channel vulnerability of the RSA-T100 hardware IP core.

[0030] The present invention provides a path-based IP core time side channel detection method. By analyzing the security attributes, the shortest path from the specified input signal to the target output signal in the gate-level netlist is extracted, and then the information flow tracking logic is added to the logic gates on the path, and the formal verification tool Questa formal is used to detect whether there is a time information flow from the specified input signal to the output signal, and the counterexample given by the formal verification tool is used for simulation verification, so as to detect the existence of the time side channel vulnerability. Based on the information flow tracking logic of the shortest path, the present invention can effectively reduce the complexity of the formal verification of the information flow tracking logic, improve the efficiency of security verification, and effectively detect the time side channel vulnerability in the IP core.

Claims

1. A path-based IP core hardware time side channel detection method, characterized in that: The following steps are involved: a) Determine the logic netlist of the hardware design to be tested, and select the specified input signals and output signals to be verified according to the security threat model; b) finding the shortest path from the specified input signal to the target output signal through the shortest path extraction algorithm; c) Instantiate the information flow tracking logic for each logic unit in the path to generate the information flow tracking logic for the shortest path of the hardware IP core; d) Divide the generated path information flow tracing logic into security levels of relevant signals, set security labels, build information flow security rules, generate security attribute assertion statements, and use formal verification tools to perform security verification. If the verification fails, extract counterexamples that violate the information flow security rules. e) Perform simulation verification based on the counterexample provided by the formal verification tool to confirm that the IP core design has a time side channel vulnerability.

2. A path-based IP core hardware time side channel detection method according to claim 1, characterized in that: In step a, for a gate-level netlist generated by a logic synthesis tool or obtained from a third party, the designated input signals and output signals to be verified are determined according to confidentiality security rule requirements and a hardware design security threat model.

3. A path-based IP core hardware time side channel detection method according to claim 1, characterized in that: In step b, the shortest path extraction is implemented based on the breadth-first search algorithm. The goal is to find a shortest path from a specified input signal to a target output signal. The input is a gate-level netlist, a specified input signal, and a target output signal. First, traverse the gate-level netlist to see if the specified input signal exists in the fan-in cone. If so, add this node to the path array and store the path array in the queue Q. When the queue Q is not empty, take out the path array from the queue and take out the fan-out of the last element of the path array. If the target output signal is the fan-out of the last element of the path array, output the path array, and the output path array is the shortest path we are looking for. If the target output signal is not the fan-out of the last element of the path array, continue to traverse the gate-level netlist file to see if the fan-out of the last element of the path array exists in the fan-in cone. If so, add the node to the path array, and then add the added path array to the queue Q. When the algorithm finds the target output, it outputs the stored path array, which contains all the nodes from the specified input signal to the target output signal.

4. A path-based IP core hardware time side channel detection method according to claim 1, characterized in that In step c, an information flow tracing logic library with minimum complete functions is constructed, and each logic unit in the shortest path extracted from the hardware design is traced and mapped to generate the information flow tracing logic of the shortest path.

5. As claimed in claim 1, a path-based IP core hardware time side channel detection method, characterized in that: In step d, use formal verification tools to verify security attribute assertions. Divide the signals in the IP core into security levels, mark confidential signals as HIGH, and mark publicly observable data as LOW. For the information flow tracing logic of the shortest path, mark the security attribute label of the specified input signal as HIGH, and the security attribute labels of other signals are not constrained, and the formal verification tool automatically assigns values. Finally, convert the security attributes and security rules into scripts (including assertions) that can be recognized by the formal verification tool, and call the verification tool for security verification. If the verification fails, extract counterexamples that violate the information flow security rules.

6. As claimed in claim 1, a path-based IP core hardware time side channel detection method, characterized in that: In step e, the situation provided by the counterexample is simulated and verified using the complete information flow tracing logic of the IP core design. The value of the input signal of the IP core hardware design and the value of the security attribute label of the shortest path information flow tracing logic are obtained through the counterexample. According to the results obtained by the counterexample, the EDA simulation tool is used for simulation verification. The situation where the value of the security attribute label of the information flow tracing logic of the shortest path provided by the counterexample is HIGH is consistent with the result of the simulation using the complete information flow tracing logic of the IP core design. This means that there is at least one input situation that satisfies the following: the HIGH-level information of the specified input flows through the extracted shortest path and finally flows to the LOW-level output signal. The simulation experiment confirms the existence of the IP core hardware time side channel.

Images