Subthreshold circuit time sequence optimization method and related device

Abstract

The invention discloses a time sequence optimization method of a sub-threshold circuit and a related device. The time sequence convergence problem of the sub-threshold circuit is optimized. The method comprises the following steps: carrying out time sequence analysis on data input and output paths of each trigger in a sub-threshold circuit, and identifying paths which do not meet a setting time requirement or a holding time requirement; for the paths which do not meet the establishment time requirement, timing optimization is carried out between the output end of the combinational circuit and the data input end of the trigger by adopting a feedback equalization mode, or timing optimization is carried out at the clock input end of the trigger by adopting a clock delay mode; for the path which does not meet the retention time requirement, time sequence optimization is carried out between the output end of the combinational circuit and the data input end of the trigger by adopting a mode of increasing input data delay; and for the paths which do not meet the retention time requirement and the establishment time requirement, dividing the paths into four types of sub-paths, and then performing time sequence optimization on each type of sub-paths.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a subthreshold circuit timing optimization method and related devices. Background Art

[0002] Subthreshold circuits are circuits that use transistors to operate in the subthreshold region (i.e., the region where the gate voltage of the transistor is lower than the threshold voltage). Subthreshold circuits have the characteristics of low power consumption, however, their low power consumption characteristics are at the expense of circuit speed, which may cause timing convergence problems in the circuit (timing convergence refers to ensuring that all signals reach their destinations within a predetermined time when designing a circuit to meet the functional and performance requirements of the circuit). Therefore, more effective timing optimization techniques are needed to ensure the normal operation of subthreshold circuits. Summary of the invention

[0003] In view of the above problems, the present application provides a subthreshold circuit timing optimization method and related devices to optimize the timing convergence problem of the subthreshold circuit. The specific scheme is as follows:

[0004] The first aspect of the present application provides a subthreshold circuit timing optimization method, comprising:

[0005] Perform timing analysis on the data input and output paths of each trigger in the subthreshold circuit to identify the paths that do not meet the setup time requirement or the hold time requirement;

[0006] For a path that does not meet the setup time requirement but meets the hold time requirement: between the output of the combinational circuit and the data input of the trigger, the path is optimized by feedback equalization; or, at the clock input of the trigger, the path is optimized by clock delay; the combinational circuit is a digital circuit connected to the data input of the trigger and formed by multiple logic units connected according to specific logic functions;

[0007] For a path that does not meet the hold time requirement but meets the setup time requirement: between the output terminal of the combinational circuit and the data input terminal of the trigger, the path is optimized in timing by increasing the input data delay;

[0008] For paths that do not meet the hold time requirement and do not meet the setup time requirement: the paths are divided into four categories of sub-paths, the first category of sub-paths are sub-paths that do not meet the setup time requirement but meet the hold time requirement, the second category of sub-paths are sub-paths that do not meet the hold time requirement but meet the setup time requirement, the third category of sub-paths are sub-paths that do not meet the hold time requirement and do not meet the setup time requirement, and the fourth category of sub-paths are sub-paths that meet both the hold time requirement and the setup time requirement; between all logic units that belong only to the first category of sub-paths, the first category of sub-paths are optimized for timing by means of feedback equalization; between all logic units that belong only to the second category of sub-paths, the second category of sub-paths are optimized for timing by means of increasing input data delay; between all logic units that belong only to the third category of sub-paths, the third category of sub-paths are optimized for timing by means of feedback equalization and increasing input data delay.

[0009] In a possible implementation, the timing optimization of the path between the output terminal of the combinational circuit and the data input terminal of the trigger by feedback equalization includes:

[0010] disconnecting the output terminal of the combinational circuit from the data input terminal of the flip-flop;

[0011] A feedback equalizer is inserted between the output of the combinational circuit and the data input of the trigger, so that the output of the combinational circuit is connected to the data input of the feedback equalizer, the data output of the feedback equalizer is connected to the data input of the trigger, and the data output of the trigger is connected to the feedback input of the feedback equalizer.

[0012] In a possible implementation, the step of optimizing the timing of a path between an output terminal of the combinational circuit and a data input terminal of a trigger by means of feedback equalization further includes:

[0013] A Schmitt trigger is inserted between the data output of the feedback equalizer and the data input of the trigger, so that the input of the Schmitt trigger is connected to the data output of the feedback equalizer, and the output of the Schmitt trigger is connected to the data input of the trigger.

[0014] In a possible implementation, the timing optimization of the path is performed by using a clock delay method at the clock input end of the trigger, including: adding a delay circuit at the clock input end of the trigger;

[0015] The delay circuit comprises: a PMOS capacitor or an NMOS capacitor; when the MOS capacitor is an NMOS capacitor, the gate of the NMOS capacitor is connected to the clock input terminal of the trigger, and the semiconductor substrate of the NMOS capacitor is grounded; when the MOS capacitor is a PMOS capacitor, the gate of the PMOS capacitor is connected to the clock input terminal of the trigger, and the semiconductor substrate of the PMOS capacitor is connected to the power supply;

[0016] Alternatively, the delay circuit comprises: a logic unit whose input signal is the same as the output signal, the input terminal of the logic unit is connected to the clock input terminal of the trigger, and the output terminal of the logic unit is suspended;

[0017] Alternatively, the output end of the delay circuit is connected to the clock input end of the trigger, and the input end of the delay circuit is used to receive a clock signal.

[0018] In a possible implementation, the timing optimization of the path between the output terminal of the combinational circuit and the data input terminal of the trigger is performed by increasing the input data delay, including: disconnecting the connection between the output terminal of the combinational circuit and the data input terminal of the trigger; inserting a delay circuit between the output terminal of the combinational circuit and the data input terminal of the trigger;

[0019] Alternatively, between the output end of the combinational circuit and the data input end of the trigger, the path is optimized in a manner of increasing the input data delay, including: adding a delay circuit at the data input end of the trigger; the delay circuit includes a PMOS capacitor or an NMOS capacitor; when the MOS capacitor is an NMOS capacitor, the gate of the NMOS capacitor is connected to the data input end of the trigger, and the semiconductor substrate of the NMOS capacitor is grounded; when the MOS capacitor is a PMOS capacitor, the gate of the PMOS capacitor is connected to the data input end of the trigger, and the semiconductor substrate of the PMOS capacitor is connected to the power supply;

[0020] Alternatively, the path is optimized for timing by increasing the input data delay between the output terminal of the combinational circuit and the data input terminal of the trigger, including: adding a delay circuit at the data input terminal of the trigger; the delay circuit includes a logic unit whose input signal is the same as the output signal, the input terminal of the logic unit is connected to the data input terminal of the trigger, and the output terminal of the logic unit is left floating.

[0021] In a possible implementation, before performing timing analysis on the data input and output paths of each trigger in the subthreshold circuit, it also includes: performing isomorphic analysis on each path of the subthreshold circuit, performing timing analysis and timing optimization on only one of all isomorphic paths, and then reusing the timing optimization result of the current path in other isomorphic paths.

[0022] A second aspect of the present application provides a subthreshold circuit timing optimization device, comprising:

[0023] A timing analysis unit, used to perform timing analysis on the data input and output paths of each trigger in the sub-threshold circuit, and identify the paths that do not meet the setup time requirement or the hold time requirement;

[0024] A first timing optimization unit is used for, for a path that does not meet the setup time requirement but meets the hold time requirement: between the output end of the combinational circuit and the data input end of the trigger, to optimize the timing of the path by means of feedback equalization; or, at the clock input end of the trigger, to optimize the timing of the path by means of clock delay; the combinational circuit is a digital circuit connected to the data input end of the trigger and formed by connecting a plurality of logic units according to specific logic functions;

[0025] A second timing optimization unit is used to optimize the timing of a path that does not meet the hold time requirement but meets the setup time requirement by increasing the input data delay between the output terminal of the combinational circuit and the data input terminal of the trigger;

[0026] The third timing optimization unit is used for the paths that do not meet the hold time requirement and the setup time requirement: dividing the paths into four categories of sub-paths, the first category of sub-paths being sub-paths that do not meet the setup time requirement but meet the hold time requirement, the second category of sub-paths being sub-paths that do not meet the hold time requirement but meet the setup time requirement, the third category of sub-paths being sub-paths that do not meet the hold time requirement and do not meet the setup time requirement, and the fourth category of sub-paths being sub-paths that meet both the hold time requirement and the setup time requirement; among all logic units that belong only to the first category of sub-paths, the first category of sub-paths are timing optimized by means of feedback equalization; among all logic units that belong only to the second category of sub-paths, the second category of sub-paths are timing optimized by means of increasing input data delay; among all logic units that belong only to the third category of sub-paths, the third category of sub-paths are timing optimized by means of feedback equalization and increasing input data delay.

[0027] A third aspect of the present application provides a computer program product, comprising computer-readable instructions. When the computer-readable instructions are executed on an electronic device, the electronic device implements the subthreshold circuit timing optimization method of the first aspect or any implementation of the first aspect.

[0028] A fourth aspect of the present application provides an electronic device, comprising at least one processor and a memory connected to the processor, wherein:

[0029] The memory is used to store computer programs;

[0030] The processor is used to execute the computer program so that the electronic device can implement the subthreshold circuit timing optimization method of the above-mentioned first aspect or any implementation manner of the first aspect.

[0031] A fifth aspect of the present application provides a computer storage medium, which carries one or more computer programs. When the one or more computer programs are executed by an electronic device, the electronic device can implement the subthreshold circuit timing optimization method of the above-mentioned first aspect or any implementation of the first aspect.

[0032] By means of the above technical scheme, the subthreshold circuit timing optimization method provided by the present application first classifies the situations that do not meet the timing requirements, and then selects a more suitable timing optimization method for each specific situation where the timing is not met, and implements corresponding timing optimization measures accordingly, thereby generating a more matching unit circuit layout and accelerating the timing convergence speed of the subthreshold circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0034] Figure 1 A flow chart of a subthreshold circuit timing optimization method provided in this application;

[0035] Figure 2 A schematic diagram of a subthreshold circuit structure before timing optimization provided by the present application;

[0036] Figure 3 A schematic diagram of a subthreshold circuit structure provided by the present application that has been optimized in timing to meet the setup time requirement;

[0037] Figure 4 A schematic diagram of a subthreshold circuit structure provided by the present application that has been optimized for timing to meet the setup time requirement;

[0038] Figure 5 A schematic diagram of a subthreshold circuit structure provided by the present application that has been optimized for timing to meet the setup time requirement;

[0039] Figure 6 A schematic diagram of a subthreshold circuit structure provided by the present application that has been optimized for timing to meet the setup time requirement;

[0040] Figure 7 A schematic diagram of a subthreshold circuit structure provided by the present application that has been optimized for timing to meet the setup time requirement;

[0041] Figure 8 A schematic diagram of a subthreshold circuit structure provided by the present application that has been optimized for timing to meet the setup time requirement;

[0042] Fig. 9 A schematic diagram of a subthreshold circuit structure provided by the present application that has been optimized in timing to meet the hold time requirement;

[0043] Fig.10 A schematic diagram of another subthreshold circuit structure provided by the present application that has been optimized for timing to meet the hold time requirement;

[0044] Fig.11 A schematic diagram of another subthreshold circuit structure provided by the present application that has been optimized for timing to meet the hold time requirement;

[0045] Fig.12 A schematic diagram of another subthreshold circuit structure provided by the present application that has been optimized for timing to meet the hold time requirement;

[0046] Fig.13 This is another schematic diagram of a subthreshold circuit structure before timing optimization provided by the present application. DETAILED DESCRIPTION

[0047] The threshold voltage is the minimum gate voltage required for a transistor to enter the saturation region or linear region from the cutoff region. According to the size of the transistor's gate voltage relative to its threshold voltage, the working region of the transistor can be divided into the superthreshold region, the near-threshold region, and the subthreshold region. The following is a detailed description of these three regions:

[0048] 1. Superthreshold region

[0049] The superthreshold region refers to the region where the gate voltage of a transistor is significantly higher than its threshold voltage. A circuit that uses a transistor to operate in the superthreshold region is called a superthreshold circuit.

[0050] 2. Near-threshold area

[0051] The near-threshold region is located between the subthreshold region and the superthreshold region, and specifically refers to the region where the gate voltage of the transistor is slightly higher than or close to its threshold voltage. A circuit that uses a transistor to operate in the near-threshold region is called a near-threshold circuit.

[0052] 3. Subthreshold region

[0053] The subthreshold region refers to the region where the gate voltage of a transistor is lower than its threshold voltage. A circuit that uses a transistor to operate in the subthreshold region is called a subthreshold circuit.

[0054] In the subthreshold region, the conductive channel (channel) between the source and drain of the transistor is not fully formed, so the transistor is not fully turned on, so the operating voltage of the transistor is relatively low. Due to the low operating voltage, the leakage current of the transistor (i.e., the weak current flowing from the source to the drain; the leakage current in the subthreshold region is also called the subthreshold current, which decays exponentially with the gate voltage) will also be significantly reduced, so the static power consumption of the subthreshold circuit is much lower than that of the superthreshold circuit and the near-threshold circuit. The low power consumption characteristics of the subthreshold circuit make it have great potential in trigger design and other digital circuit designs.

[0055] However, the low power consumption characteristics of subthreshold circuits come at the expense of circuit speed. In subthreshold circuits, due to the reduction in operating voltage, the operating speed of transistors slows down (i.e., the switching time increases), resulting in an increase in the propagation delay of signals in the circuit. The cumulative effect of this delay is particularly evident in complex circuits, which may cause timing convergence problems in the circuit (timing convergence refers to ensuring that all signals reach their destination within a predetermined time when designing a circuit to meet the functional and performance requirements of the circuit). Therefore, more effective timing optimization techniques are needed to ensure the normal operation of subthreshold circuits.

[0056] In this regard, an embodiment of the present application provides a subthreshold circuit timing optimization method. The method first classifies situations that do not meet the timing requirements, then selects a more suitable timing optimization method for each specific situation where the timing is not met, and implements corresponding timing optimization measures accordingly, thereby generating a more matching unit circuit layout and accelerating the timing convergence speed of the subthreshold circuit.

[0057] A subthreshold circuit timing optimization method provided by an embodiment of the present application is described in detail below in conjunction with the accompanying drawings. A person skilled in the art will appreciate that, with the development of technology and the emergence of new scenarios, the technical solution provided by the embodiment of the present application is also applicable to similar technical problems.

[0058] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, which is only to describe the distinction mode adopted by the objects of the same attributes when describing in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0059] See also Figure 1, a subthreshold circuit timing optimization method provided by an embodiment of the present application includes:

[0060] Step S01: Performing timing analysis on the data input and output paths of each trigger in the sub-threshold circuit to identify the paths that do not meet the setup time requirement or the hold time requirement.

[0061] Specifically, in digital circuit design, a trigger is a bistable circuit element with memory function. It can store one bit of binary information (i.e. 0 and 1) and update its state under the control of a specific clock signal. In subthreshold circuit design, it is crucial to ensure that the trigger works correctly, which involves precise control of timing parameters, especially setup time and hold time.

[0062] The trigger edge refers to the edge of the clock signal (rising or falling) at which the state of the flip-flop changes. For example, the D flip-flop is a flip-flop triggered by the rising edge of the clock, and its trigger edge is the rising edge of the clock signal.

[0063] Setup time refers to the minimum time that the data input signal must remain stable before the trigger edge of the trigger clock signal arrives. In other words, the data input signal must arrive in advance and remain stable before the trigger edge of the clock signal to ensure that the trigger has enough time to identify and stably capture the data input signal. If the data input signal changes too quickly before the trigger edge of the clock signal, the trigger may not be able to correctly capture the data input signal, resulting in data errors or instability.

[0064] Hold time refers to the minimum time that the data input signal must remain stable after the trigger edge of the clock signal of the flip-flop arrives. This is because even if the trigger edge of the clock signal has occurred, the circuit inside the flip-flop needs a certain amount of time to process and stabilize the new state. If the data input signal changes immediately after the trigger edge of the clock signal, then this change may be misread by the internal circuit of the flip-flop, resulting in data errors or instability.

[0065] In subthreshold circuit design, static timing analysis software or Monte Carlo circuit simulation software can be used to perform timing analysis on the data input and output paths of each trigger in the subthreshold circuit to identify all paths in the subthreshold circuit that do not meet the timing requirements, including: paths that do not meet the setup time requirements but meet the hold time requirements, paths that do not meet the hold time requirements but meet the setup time requirements, and paths that do not meet the setup time requirements and do not meet the hold time requirements. For different types of timing problems, the embodiments of the present application adopt different optimization strategies.

[0066] Step S02: For the path that does not meet the setup time requirement but meets the hold time requirement: between the output of the combinational circuit and the data input of the trigger, the path is optimized in timing by means of feedback equalization; or, at the clock input of the trigger, the path is optimized in timing by means of clock delay, so that the path meets both the setup time and hold time requirements, and the control ends here.

[0067] Specifically, for paths that do not meet the setup time requirements but meet the hold time requirements, the embodiments of the present application propose two optimization strategies: using feedback equalization to perform timing optimization, or using clock delay to perform timing optimization, so that the path also meets the setup time requirements (that is, ensuring that the data stably arrives at the trigger data input terminal before the clock edge arrives, meeting the setup time requirements).

[0068] Feedback equalization, one of the timing optimization strategies, specifically refers to inserting a feedback equalizer at an appropriate position of the path, and adjusting the phase and amplitude of the feedback signal to compensate for the path delay so that the data is stable before the clock edge. Feedback equalization is used between the output of the combinational circuit and the data input of the trigger to optimize the path timing. The specific implementation method includes the following steps Sa1 to Sa2:

[0069] Step Sa1: Disconnect the connection between the output terminal of the combinational circuit and the data input terminal of the trigger, such as Figure 2 As shown, then enter step Sa2; Figure 2 As shown ( Figure 2 DFF in the figure represents a trigger, and the pins D, Clk, Q, and Q_bar of the trigger represent a data input terminal, a clock input terminal, a data output terminal, and an inverted output terminal, respectively. The output state of the pin Q_bar is opposite to that of the pin Q). The combinational circuit is a digital circuit connected to the data input terminal of the trigger and composed of multiple logic units connected according to specific logic functions.

[0070] Specifically, a combinational circuit, also known as a combinational logic circuit, is a digital circuit composed of multiple logic units connected according to specific logic functions. These logic units usually refer to various logic gates, such as AND gates, OR gates, NOT gates, NAND gates, NOR gates, XOR gates, etc. The output of a combinational circuit depends only on the current input signal, and has nothing to do with the previous state or historical input of the circuit. In other words, the output of a combinational circuit is a function of the input signal, and this function does not involve time delay (except for propagation delay, which is the time required for the signal to pass through the circuit).

[0071] Step Sa2: insert a feedback equalizer between the output of the combinational circuit and the data input of the trigger, that is, connect the output of the combinational circuit to the data input of the feedback equalizer, connect the data output of the feedback equalizer to the data input of the trigger, and feed back the data output of the trigger to the feedback input of the feedback equalizer, such as Figure 3 See also Figure 3 The feedback equalizer includes, for example, an inverter INV1 and four MOS transistors M1 to M4 , and the data output end of the trigger is connected to the gates of the MOS transistors M2 to M3 in the feedback equalizer.

[0072] Specifically, the output signal of the combinational circuit is first processed by the feedback equalizer before being used as the input of the trigger. The feedback equalizer adjusts the switching threshold of the logic gate before the trigger according to the pre-sampled output, so that the load capacitance of the critical path is quickly charged / discharged, which can reduce the propagation delay of the critical path in the combinational circuit, which creates an opportunity to increase the operating frequency and / or voltage expansion of the combinational circuit, making the subthreshold circuit more robust to timing errors, and it can significantly reduce the main leakage power consumption of the entire design. The design parameters of the feedback equalizer depend on the specific timing problem and the required adjustment amount.

[0073] It should be noted that the changes in the connection relationship of the circuit in the embodiment of the present application (disconnection, insertion, etc.) can be adjusted using EDA (Electronic Design Automation) software. In traditional circuit design, the disconnection and insertion of circuits usually require engineers to do it manually, which is time-consuming and error-prone. However, using EDA software, the disconnection and insertion of circuits can be automatically realized. EDA software will automatically adjust the connection relationship of the circuit according to the design rules and user needs to ensure the correctness and stability of the circuit.

[0074] In one possible implementation, see Figure 4 A Schmitt trigger can also be inserted between the data output of the feedback equalizer and the data input of the trigger, that is, the input of the Schmitt trigger is connected to the data output of the feedback equalizer, and the output of the Schmitt trigger is connected to the data input of the trigger.

[0075] As a buffer with dual thresholds, the Schmitt trigger is cleverly designed to connect the output of the feedback circuit (i.e., feedback equalizer) to its own input. This connection method brings two major benefits: on the one hand, the feedback circuit stage can effectively reduce the inter-symbol interference caused by voltage scaling, thereby improving the stability of the circuit; on the other hand, the Schmitt trigger can smoothly process any abnormal signals that may be generated by the feedback circuit, thereby preventing timing errors from occurring when the circuit is running at high speed, ensuring high-speed and reliable operation of the circuit.

[0076] In addition, as another timing optimization strategy, the timing optimization of the path is performed by using clock delay at the clock input of the trigger (i.e., adding a delay circuit at the clock input of the trigger) in order to delay the arrival time of the clock signal, thereby giving the data signal more time to meet the setup time requirements. The design of the delay circuit can adopt the following three schemes:

[0077] Solution 1: The delay circuit added to the clock input end of the trigger may include a MOS capacitor. Specifically, in the MOS tube, the gate is isolated from the source and the drain by an insulating layer (usually silicon dioxide). This insulating layer, the gate, and the semiconductor substrate constitute a MOS capacitor. When the MOS tube is used as a capacitor, a capacitor can be formed between its gate and the source (or drain). Since the capacitor has the characteristics of charging and discharging, when the input signal changes, the capacitor needs a certain amount of time to charge or discharge to reach a stable state. This process generates a delay. By adjusting the size or structure of the MOS tube, the size of the capacitor can be changed, thereby controlling the delay time. The MOS capacitor used in the embodiment of the present application can be an NMOS capacitor or a PMOS capacitor, such as Figure 5 or Figure 6 shown. Figure 5 It shows that when the MOS capacitor is an NMOS capacitor, the gate of the NMOS capacitor is connected to the clock input terminal of the trigger, and the semiconductor substrate of the NMOS capacitor is grounded; Figure 6 It shows that when the MOS capacitor is a PMOS capacitor, the gate of the PMOS capacitor is connected to the clock input terminal of the trigger, and the semiconductor substrate of the PMOS capacitor is connected to the power supply).

[0078] Solution 2: The delay circuit added to the clock input terminal of the trigger can also include a logic unit whose input signal and output signal are the same, the input terminal of the logic unit is connected to the clock input terminal of the trigger, and the output terminal of the logic unit is left floating, such as Figure 7 shown.

[0079] A logic unit whose input signal is the same as its output signal, that is, a logic unit that does not play a logical role. Such logic units may include buffer circuits, drivers, and even-numbered inverters in series. Although they do not change the logic state themselves, they will introduce a certain delay due to the existence of internal circuits. The magnitude of the delay depends on the internal circuit structure and component parameters of the logic unit. The floating output of the logic unit means that it is not connected to the subsequent load circuit. In this case, the signal propagation inside the logic unit will not be disturbed by the subsequent load, and the resulting delay effect is more stable.

[0080] In one possible implementation, Figure 7 The logic units in the chip can adopt low-power design to reduce energy waste.

[0081] In one possible implementation, Figure 7 The logic unit in can be a logic unit using a wide gate length MOS device. The specific analysis is as follows: The wide gate length MOS device has a longer gate length than the MOS device used in the conventional logic unit. The increase in gate length will cause the switching speed of the MOS device to slow down because the carriers need longer time to cross the channel under the gate. When the output signal of the combinational circuit reaches the input of the delay logic unit, due to the slower switching speed of the wide gate length MOS device, the signal will experience an additional delay when passing through the delay logic unit. The time of this delay depends on the specific parameters of the wide gate length MOS device (such as gate length, channel width, etc.) and the characteristics of the input signal (such as amplitude, frequency, etc.). Finally, the delayed signal will reach the data input of the trigger, thereby realizing the delay processing of the signal.

[0082] Solution 3: The specific structure of the delay circuit added to the clock input end of the trigger is not limited, but the output end of the delay circuit is connected to the clock input end of the trigger, and the input end of the delay circuit is used to receive the clock signal, such as Figure 8 shown.

[0083] Of course, the embodiment of the present application may also combine and apply the two timing optimization strategies given in step S02, and may combine and apply any two or three delay circuit design solutions under the second timing optimization strategy.

[0084] Step S03: For the path that does not meet the hold time requirement but meets the setup time requirement: between the output end of the combinational circuit and the data input end of the trigger, the path is optimized in timing by increasing the input data delay (i.e., increasing the unit delay time) so that the path meets both the hold time requirement and the setup time requirement, and the control ends here.

[0085] Specifically, an input data delay is added between the output end of the combinational circuit and the data input end of the trigger, that is, the input data of the trigger is delayed, thereby extending the holding time of the data signal and ensuring that the data is held long enough after the clock edge to meet the holding time requirement of the trigger. The specific implementation method may include the following steps Sb1 to Sb2:

[0086] Step Sb1: disconnect the output terminal of the combinational circuit and the data input terminal of the trigger, and then proceed to step Sb2;

[0087] Step Sb2: Insert a delay circuit (such as Fig. 9As shown in FIG. 1 ), specifically comprising: connecting the input end of the delay circuit to the input end of the combinational circuit, and connecting the output end of the delay circuit to the data input end of the trigger. The delay circuit can be composed of a plurality of small delay circuit units connected in series.

[0088] Alternatively, the specific implementation method of delaying the input data of the trigger may also include: adding a delay circuit at the data input end of the trigger; the delay circuit includes a MOS capacitor. The MOS capacitor may be an NMOS capacitor or a PMOS capacitor, such as Fig.10 or Fig.11 shown. Fig.10 It shows that when the MOS capacitor is an NMOS capacitor, the gate of the NMOS capacitor is connected to the data input terminal of the trigger, and the semiconductor substrate of the NMOS capacitor is grounded; Fig.11 It shows that when the MOS capacitor is a PMOS capacitor, the gate of the PMOS capacitor is connected to the data input terminal of the trigger, and the semiconductor substrate of the PMOS capacitor is connected to the power supply.

[0089] Alternatively, the specific implementation method of delaying the input data of the trigger may also include: adding a delay circuit to the data input end of the trigger; the delay circuit includes a logic unit whose input signal is the same as the output signal, the input end of the logic unit is connected to the data input end of the trigger, and the output end of the logic unit is left floating, such as Fig.12 In addition, the logic unit can adopt a low power design to reduce energy waste. Fig.12 The logic unit device in the embodiment may be a logic unit using a wide gate length MOS device.

[0090] Of course, the above three design schemes for delaying the input data of the trigger can also be applied in combination.

[0091] Step S04: For the path that does not meet the hold time requirement and does not meet the setup time requirement: divide the path into four categories of sub-paths, the first category of sub-paths are sub-paths that do not meet the setup time requirement but meet the hold time requirement, the second category of sub-paths are sub-paths that do not meet the hold time requirement but meet the setup time requirement, the third category of sub-paths are sub-paths that do not meet the hold time requirement and do not meet the setup time requirement, and the fourth category of sub-paths are sub-paths that meet both the hold time requirement and the setup time requirement; then enter step S05.

[0092] Specifically, path partitioning refers to dividing the paths in the circuit into different groups or categories according to certain rules or algorithms in the circuit netlist (which can be regarded as a graph structure).

[0093] Step S05: Among all the logic units that belong only to the first type of sub-path, the first type of sub-path is optimized in timing by means of feedback equalization; among all the logic units that belong only to the second type of sub-path, the second type of sub-path is optimized in timing by means of increasing input data delay; among all the logic units that belong only to the third type of sub-path, the third type of sub-path is optimized in timing by means of feedback equalization and increasing input data delay, so that the third type of sub-path satisfies both the setup time requirement and the hold time requirement, and the control is terminated here.

[0094] Specifically, in order to simplify the optimization process, avoid optimization conflicts, and improve optimization efficiency and effect, this embodiment chooses to exclude corresponding common logic units for timing optimization, as detailed below:

[0095] Find the common logic unit between the first type of sub-path and the second type of sub-path, then in the first type of sub-path, after excluding the logic unit shared with the second type of sub-path, between all remaining non-common logic units (i.e., logic units belonging only to the first type of sub-path), optimize the timing of the first type of sub-path by using feedback equalization, so that the first type of sub-path can simultaneously meet the setup time requirement and the hold time requirement; and, in the second type of sub-path, after excluding the logic unit shared with the first type of sub-path, between the remaining non-common logic units (i.e., logic units belonging only to the second type of sub-path), optimize the timing of the second type of sub-path by increasing the input data delay, so that the second type of sub-path can simultaneously meet the hold time requirement and the setup time requirement;

[0096] In the third type of sub-path, after excluding the logic units shared with the first type of sub-path and the second type of sub-path, the timing of the third type of sub-path is optimized by feedback equalization and increasing the input data delay between all remaining non-common logic units (i.e., logic units belonging only to the third type of sub-path), so that the third type of sub-path can meet both the setup time requirement and the hold time requirement.

[0097] For example, Fig.13As shown, the first type of sub-path P1 is: U1-U4-U7-U9, the second type of sub-path P2 is: U2-U5-U7-U9, and the third type of sub-path P3 is: U3-U6-U8-U9. Find the common logic units (U7, U9) that do not meet the requirements of sub-path P1 and sub-path P2, and then perform timing optimization between all logic units (U1, U4) before U7 on sub-path P1, so that sub-path P1 meets the setup time requirement; perform timing optimization between all logic units (U2, U5) before U7 on sub-path P2, so that sub-path P2 meets the hold time requirement. Find the common logic unit (U9) between the first type of sub-path P1, the second type of sub-path P2, and the third type of sub-path P3, and perform timing optimization between all logic units (U3, U6, U8) before U9 on sub-path P3, so that sub-path P3 meets the setup time requirement and the hold time requirement.

[0098] In summary, the embodiments of the present application select and implement a matching timing optimization method (including accurately determining the device parameter values ​​of circuits such as feedback equalizers and delay circuits) for each path that does not meet the specific timing requirements, so that the path meets both the time requirements and the hold time requirements, thereby generating a more matching unit circuit layout and accelerating the timing convergence speed of the subthreshold circuit.

[0099] It should be noted that all the above timing optimization processes include the optimization of the device size in the path to determine the transistor size parameter value that is more suitable for the timing requirements of the path. Based on these new device size parameter values, the system will automatically fine-tune the layout of the unit circuit to generate the unit circuit layout under the corresponding new parameter values. Compared with the existing practice of only selecting suitable units from a predefined unit library, this method can generate unit circuits that are more in line with specific needs, thereby more effectively achieving timing optimization and significantly accelerating the convergence process.

[0100] In a possible implementation, before performing timing analysis on the data input and output paths of each trigger in the subthreshold circuit, the paths of the subthreshold circuit can be first subjected to isomorphic analysis. For all isomorphic paths, only one path is subjected to timing analysis and timing optimization, and then the timing optimization result of this path is reused in other isomorphic paths. This strategy not only significantly reduces redundant calculations during the optimization process, but also greatly improves the optimization efficiency.

[0101] Corresponding to the above method embodiment, the embodiment of the present application further provides a subthreshold circuit timing optimization device, including:

[0102] A timing analysis unit, used to perform timing analysis on the data input and output paths of each trigger in the sub-threshold circuit, and identify the paths that do not meet the setup time requirement or the hold time requirement;

[0103] A first timing optimization unit is used for, for a path that does not meet the setup time requirement but meets the hold time requirement: between the output end of the combinational circuit and the data input end of the trigger, to optimize the timing of the path by means of feedback equalization; or, at the clock input end of the trigger, to optimize the timing of the path by means of clock delay; the combinational circuit is a digital circuit connected to the data input end of the trigger and formed by connecting a plurality of logic units according to specific logic functions;

[0104] A second timing optimization unit is used to optimize the timing of a path that does not meet the hold time requirement but meets the setup time requirement by increasing the input data delay between the output terminal of the combinational circuit and the data input terminal of the trigger;

[0105] The third timing optimization unit is used for the paths that do not meet the hold time requirement and the setup time requirement: dividing the paths into four categories of sub-paths, the first category of sub-paths being sub-paths that do not meet the setup time requirement but meet the hold time requirement, the second category of sub-paths being sub-paths that do not meet the hold time requirement but meet the setup time requirement, the third category of sub-paths being sub-paths that do not meet the hold time requirement and do not meet the setup time requirement, and the fourth category of sub-paths being sub-paths that meet both the hold time requirement and the setup time requirement; among all logic units that belong only to the first category of sub-paths, the first category of sub-paths are timing optimized by means of feedback equalization; among all logic units that belong only to the second category of sub-paths, the second category of sub-paths are timing optimized by means of increasing input data delay; among all logic units that belong only to the third category of sub-paths, the third category of sub-paths are timing optimized by means of feedback equalization and increasing input data delay.

[0106] In addition, an embodiment of the present application also provides a computer program product, including computer-readable instructions. When the computer-readable instructions are executed on an electronic device, the electronic device implements any of the above-mentioned subthreshold circuit timing optimization methods.

[0107] An embodiment of the present application further provides an electronic device, comprising at least one processor and a memory connected to the processor, wherein:

[0108] The memory is used to store computer programs;

[0109] The processor is used to execute the computer program so that the electronic device can implement any of the above-mentioned sub-threshold circuit timing optimization methods.

[0110] An embodiment of the present application also provides a computer storage medium, which carries one or more computer programs. When the one or more computer programs are executed by an electronic device, the electronic device can implement any of the above-mentioned subthreshold circuit timing optimization methods.

[0111] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the embodiments of the present application. Therefore, the embodiments of the present application will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features disclosed herein.

Claims

1. A subthreshold circuit timing optimization method, characterized in that: include: Perform timing analysis on the data input and output paths of each trigger in the subthreshold circuit to identify the paths that do not meet the setup time requirement or the hold time requirement; For a path that does not meet the setup time requirement but meets the hold time requirement: between the output of the combinational circuit and the data input of the trigger, the path is optimized by feedback equalization; or, at the clock input of the trigger, the path is optimized by clock delay; the combinational circuit is a digital circuit connected to the data input of the trigger and formed by multiple logic units connected according to specific logic functions; For a path that does not meet the hold time requirement but meets the setup time requirement: between the output terminal of the combinational circuit and the data input terminal of the trigger, the path is optimized in timing by increasing the input data delay; For paths that do not meet the hold time requirement and do not meet the setup time requirement: the paths are divided into four categories of sub-paths, the first category of sub-paths are sub-paths that do not meet the setup time requirement but meet the hold time requirement, the second category of sub-paths are sub-paths that do not meet the hold time requirement but meet the setup time requirement, the third category of sub-paths are sub-paths that do not meet the hold time requirement and do not meet the setup time requirement, and the fourth category of sub-paths are sub-paths that meet both the hold time requirement and the setup time requirement; between all logic units that belong only to the first category of sub-paths, the first category of sub-paths are optimized for timing by means of feedback equalization; between all logic units that belong only to the second category of sub-paths, the second category of sub-paths are optimized for timing by means of increasing input data delay; between all logic units that belong only to the third category of sub-paths, the third category of sub-paths are optimized for timing by means of feedback equalization and increasing input data delay.

2. The subthreshold circuit timing optimization method according to claim 1, characterized in that: The timing optimization of the path between the output terminal of the combinational circuit and the data input terminal of the trigger is performed by using feedback equalization, including: disconnecting the output terminal of the combinational circuit from the data input terminal of the flip-flop; A feedback equalizer is inserted between the output of the combinational circuit and the data input of the trigger, so that the output of the combinational circuit is connected to the data input of the feedback equalizer, the data output of the feedback equalizer is connected to the data input of the trigger, and the data output of the trigger is connected to the feedback input of the feedback equalizer.

3. The subthreshold circuit timing optimization method according to claim 2, characterized in that: The timing optimization of the path between the output terminal of the combinational circuit and the data input terminal of the trigger is performed by using feedback equalization, and further includes: A Schmitt trigger is inserted between the data output of the feedback equalizer and the data input of the trigger, so that the input of the Schmitt trigger is connected to the data output of the feedback equalizer, and the output of the Schmitt trigger is connected to the data input of the trigger.

4. The subthreshold circuit timing optimization method according to claim 1, characterized in that: The method of optimizing the timing of the path by clock delay at the clock input end of the trigger comprises: adding a delay circuit at the clock input end of the trigger; The delay circuit comprises: a PMOS capacitor or an NMOS capacitor; when the MOS capacitor is an NMOS capacitor, the gate of the NMOS capacitor is connected to the clock input terminal of the trigger, and the semiconductor substrate of the NMOS capacitor is grounded; when the MOS capacitor is a PMOS capacitor, the gate of the PMOS capacitor is connected to the clock input terminal of the trigger, and the semiconductor substrate of the PMOS capacitor is connected to the power supply; Alternatively, the delay circuit comprises: a logic unit whose input signal is the same as the output signal, the input terminal of the logic unit is connected to the clock input terminal of the trigger, and the output terminal of the logic unit is suspended; Alternatively, the output end of the delay circuit is connected to the clock input end of the trigger, and the input end of the delay circuit is used to receive a clock signal.

5. The subthreshold circuit timing optimization method according to claim 1, characterized in that: The timing optimization of the path is performed by increasing the input data delay between the output terminal of the combinational circuit and the data input terminal of the trigger, including: disconnecting the connection between the output terminal of the combinational circuit and the data input terminal of the trigger; inserting a delay circuit between the output terminal of the combinational circuit and the data input terminal of the trigger; Alternatively, between the output end of the combinational circuit and the data input end of the trigger, the path is optimized in a manner of increasing the input data delay, including: adding a delay circuit at the data input end of the trigger; the delay circuit includes a PMOS capacitor or an NMOS capacitor; when the MOS capacitor is an NMOS capacitor, the gate of the NMOS capacitor is connected to the data input end of the trigger, and the semiconductor substrate of the NMOS capacitor is grounded; when the MOS capacitor is a PMOS capacitor, the gate of the PMOS capacitor is connected to the data input end of the trigger, and the semiconductor substrate of the PMOS capacitor is connected to the power supply; Alternatively, the path is optimized for timing by increasing the input data delay between the output terminal of the combinational circuit and the data input terminal of the trigger, including: adding a delay circuit at the data input terminal of the trigger; the delay circuit includes a logic unit whose input signal is the same as the output signal, the input terminal of the logic unit is connected to the data input terminal of the trigger, and the output terminal of the logic unit is left floating.

6. The subthreshold circuit timing optimization method according to any one of claims 1 to 5, characterized in that: Before performing timing analysis on the data input and output paths of each trigger in the subthreshold circuit, the method also includes: performing isomorphic analysis on each path of the subthreshold circuit, performing timing analysis and timing optimization on only one path among all isomorphic paths, and then reusing the timing optimization result of the current path in other isomorphic paths.

7. A subthreshold circuit timing optimization device, characterized in that: include: A timing analysis unit, used to perform timing analysis on the data input and output paths of each trigger in the sub-threshold circuit, and identify the paths that do not meet the setup time requirement or the hold time requirement; A first timing optimization unit is used for, for a path that does not meet the setup time requirement but meets the hold time requirement: between the output end of the combinational circuit and the data input end of the trigger, to optimize the timing of the path by means of feedback equalization; or, at the clock input end of the trigger, to optimize the timing of the path by means of clock delay; the combinational circuit is a digital circuit connected to the data input end of the trigger and formed by connecting a plurality of logic units according to specific logic functions; A second timing optimization unit is used to optimize the timing of a path that does not meet the hold time requirement but meets the setup time requirement by increasing the input data delay between the output terminal of the combinational circuit and the data input terminal of the trigger; The third timing optimization unit is used for the paths that do not meet the hold time requirement and the setup time requirement: dividing the paths into four categories of sub-paths, the first category of sub-paths being sub-paths that do not meet the setup time requirement but meet the hold time requirement, the second category of sub-paths being sub-paths that do not meet the hold time requirement but meet the setup time requirement, the third category of sub-paths being sub-paths that do not meet the hold time requirement and do not meet the setup time requirement, and the fourth category of sub-paths being sub-paths that meet both the hold time requirement and the setup time requirement; among all logic units that belong only to the first category of sub-paths, the first category of sub-paths are timing optimized by means of feedback equalization; among all logic units that belong only to the second category of sub-paths, the second category of sub-paths are timing optimized by means of increasing input data delay; among all logic units that belong only to the third category of sub-paths, the third category of sub-paths are timing optimized by means of feedback equalization and increasing input data delay.

8. A computer program product, characterized in that The method comprises computer-readable instructions, and when the computer-readable instructions are executed on an electronic device, the electronic device implements the subthreshold circuit timing optimization method as claimed in any one of claims 1 to 6.

9. An electronic device, characterized in that: The method comprises at least one processor and a memory connected to the processor, wherein: The memory is used to store computer programs; The processor is used to execute the computer program so that the electronic device can implement the subthreshold circuit timing optimization method according to any one of claims 1 to 6.

10. A computer storage medium, characterized in that: The storage medium carries one or more computer programs, and when the one or more computer programs are executed by an electronic device, the electronic device can implement the subthreshold circuit timing optimization method as described in any one of claims 1 to 6.

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