Clock tree adaptive optimization method using useful skew based on risc-v architecture

Abstract

The application discloses a new clock tree adaptive optimization method based on RISC-V architecture and utilizing useful skew, after S1, layout; S2, layout; S3, clock tree synthesis, S10, register-to-register timing path optimization is carried out; after S4, wiring, S20, register-to-memory timing path optimization is carried out. Through adaptive iteration, the application does not need complicated algorithms, solves the shortage of auto useful skew of the EDA tool itself, maximally repairs the timing problem, and simultaneously adopts the method of combining delay units, so that the win-win effect of high performance and low power consumption of chip design is realized.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of IC design, and relates to a new clock tree adaptive optimization method based on a RISC-V architecture and utilizing useful skew. BACKGROUND

[0002] With the advancement of semiconductor process design, the scale and integration of chips have been significantly improved, and the market has increasingly high requirements for chip performance. Therefore, the clock structure inside the chip has become more complex, and the timing convergence of the design has become a great challenge for engineers. Clock networks account for a significant proportion of power consumption increments, usually accounting for 15%-40% of the total chip power consumption. The quality of the clock tree has a significant impact on the power efficiency and performance of the processor. Traditional optimization strategies may not be able to meet the timing requirements of the design, which makes it an important step to optimize the clock tree through new optimization methods during the chip design process. At the same time, with the improvement of integration, the cost and cost of chip tape-out increase rapidly, and cost has become an increasingly important factor in the chip design process.

[0003] In digital IC design, ideally, the clock reaches all timing units at the same time to obtain a "zero skew" clock tree. However, in reality, due to the different distances, the clock reaches different timing units with different clock delays. In order to obtain a reasonable clock tree structure, it is necessary to make the delay difference of the clock signal reaching each unit as small as possible while reaching. In today's very large scale integrated circuits, how to design a reasonable clock network is a problem worth considering.

[0004] A synchronous timing circuit model contains two timing units, where A is the launch register, B is the capture register, P is the combinational logic delay of the timing path, and L and C represent the delays of the clock signal reaching registers A and B, respectively. Assuming that the clock period is T, the delay of the combinational logic is Tc, the internal delay of the timing unit is Tclk-q, and the clock skew of the two clock paths is Tskew=|L-C|. Before and after the signal jumps,

[0005] To meet the setup time constraint, Tsetup must satisfy the following formula, Tclk-q+Tc<T+Tskew-Tsetup

[0006] To meet the hold time constraint, Thold must satisfy the following formula, Tclk-q+Tc>Tskew+Thold

[0007] When there is setup time and hold time violation in the timing path, it can be repaired by adjusting the clock skew. The useful skew refers to the different through clock delay, so that some registers meet the timing requirements. If the front and back level paths of the register meet the timing requirements and there is timing margin, the timing margin can be used to repair the violation path by adjusting the position of some registers on the clock path (forward or backward), thereby improving the overall timing convergence. For example, when there is a setup time violation in a certain path, and the post-path of the path has timing margin on the setup time constraint, the clock skew can be created by adjusting the network delay of the clock source to the register between adjacent paths without affecting the function of the clock tree to repair the timing violation.

[0008] With the development of Moore's law, the process of integrated circuits is more and more advanced, but the cost of tape-out is higher and higher for integrated circuit design engineers. Therefore, in order to enable the chip to normally flow and save cost, it is particularly important to reduce power consumption while meeting performance requirements. Repairing timing violations by useful skew method will greatly increase the number of buffer usage, and most buffers use low voltage transistors (LVT), which will cause a sharp increase in power consumption and cost. Therefore, in order to meet the dual demands of high performance and low power consumption of the market, it is extremely critical to consider the rationality of the timing convergence scheme and the subsequent joint optimization measures for power consumption and performance.

[0009] The prior art proposes a bidirectional timing continuous borrowing useful skew execution method, which considers the timing margin of the front and back paths of the key path with timing violation at the same time, borrows timing margin from the front and back paths when correcting the timing violation of the key path, thereby speeding up the timing convergence. In addition, when the timing margin of the front and back level paths is insufficient, the scheme can also continuously borrow the timing margin of the front and back multi-level paths, thereby fully utilizing the timing margin in integrated circuit design, reducing the iteration time and the strong dependence of back-end staff on EDA tools, and greatly improving the timing convergence efficiency.

[0010] The prior art at least includes the following disadvantages:

[0011] 1. The existing method does not maximize the repair of timing violation problems;

[0012] 2. Existing methods that are relatively close to this approach use traditional methods to repair timing using useful deviations. In order to solve the problem that the current useful deviation function does not make sufficient use of timing margins, resulting in the inability to correct the timing of the critical path, a method of borrowing timing sequentially forward is adopted. However, as can be seen from the formulas for setup time and hold time constraints, while borrowing timing sequentially forward and backward to repair setup time violations, the adjustment of clock deviations to make setup time constraints meet the requirements often leads to hold time violations. After EDA tools detect hold time violations, they usually take measures such as replacing delay units on the path, which will cause the clock path length to deviate from the expected target.

[0013] 3. Existing solutions borrow timing parameters step-by-step from front to back. However, in practice, the effect of applying early useful skew is not always ideal. While early useful skew is expected to reduce clock network latency, it often results in an increase. This is because while an early useful skew is specified to achieve the target, it's difficult to advance the clock path to ensure proper chip functionality. Therefore, EDA tools may introduce additional delays into the clock path, extending the total length of the clock tree to meet the early useful skew requirement. For example, if the total clock tree length is 500ps, and optimizing the target path requires a 100ps early useful skew, but the clock path length is already close to its limit and cannot be reduced further, the tool will increase the total clock tree length to 600ps to meet the requirement. This actually increases the network latency of the clock tree, raising the timing penalty caused by on-chip variation (OCV).

[0014] 4. Existing designs only address violations that exist directly between registers. However, in a design, there may also be hold-time violations in the timing path before the register to memory. Moreover, fixing these violations introduces a large amount of buffering into the timing path.

[0015] 5. In existing technologies, timing violation issues are only fixed within a single process;

[0016] 6. By borrowing timing step by step forward and backward, a large amount of buffer is introduced into the clock path, which will greatly increase the power consumption and cost of the chip design, but there are no subsequent optimization measures. Summary of the Invention

[0017] To solve the above problems, the technical solution of the present invention is a clock tree adaptive optimization method based on RISC-V architecture using useful bias. After S1, layout; S2, placement; and S3, clock tree synthesis, S10, timing path optimization between registers is performed; and after S4, routing, S20, timing path optimization between registers and memory is performed.

[0018] Preferably, the S10 comprises the following steps:

[0019] S11, screening target critical path between registers to registers;

[0020] S12, judging whether there is a deviation optimization condition;

[0021] Yes, then S13, generating a feedback early intervention clock tree synthesis guidance file;

[0022] No, then exiting the loop, proceeding to S4, routing;

[0023] Preferably, the S10 comprises the following steps:

[0024] S101, establishing a critical path matrix, newly creating an optimization path list, initializing a delay variable delayA=0;

[0025] S102, judging whether there is a deviation optimization condition;

[0026] No, then exiting the loop, proceeding to S4, routing;

[0027] Yes, then S103, determining an optimization parameter value delay;

[0028] S104, reading the optimization path list;

[0029] S105, judging whether the list has a critical path;

[0030] Yes, then S106, updating delay=delay+delayA;

[0031] No, then S107, delayA=delay;

[0032] S108, netlist writing into a critical path;

[0033] S109, adding a critical path parameter delayA;

[0034] S110, generating a clock tree synthesis guidance file.

[0035] Preferably, the S20 comprises the following steps:

[0036] S21, screening an optimization target path from registers to memory;

[0037] S22, synthesizing a clock model adding a driving layout;

[0038] S23, executing a timing engineering change command;

[0039] S24, judging whether there is a deviation optimization condition;

[0040] If yes, return to S21;

[0041] If no, complete S20, execute S5, joint optimization of power consumption timing.

[0042] Preferably, the S5 includes adding a buffer to increase the path delay, and when the clock signal is transmitted to two physically adjacent registers, the adjacent two registers use the same path buffer.

[0043] The present application has at least the following beneficial effects: in different processes of digital IC design, through a new ADFF (Adaptive Full Flow) optimization method, different violation problems between registers and memories are screened, the critical path is iterated, not only through feedback to guide the early intervention of the clock tree synthesis stage, but also to add driving in the wiring stage, to adaptively repair the violation, so that the timing is more convergent. And at the same time of optimization, through the joint optimization method of power consumption and performance, the number of buffers used by the method is reduced, and the cost and power consumption of the whole chip design are reduced.

[0044] Through adaptive iteration, without complicated algorithms, the shortcomings of the EDA tool itself auto useful skew are solved, and the timing problem is maximally repaired, and the use of the combined delay unit method realizes the win-win effect of high performance and low power consumption of chip design. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 A step flow chart of the clock tree adaptive optimization method based on the RISC-V architecture using useful skew of an embodiment of the present application;

[0046] Figure 2 A specific step flow chart of S10 of the clock tree adaptive optimization method based on the RISC-V architecture using useful skew of an embodiment of the present application;

[0047] Figure 3 A repair hold time violation model diagram of the prior art;

[0048] Figure 4 An EDA tool repair hold time violation model diagram of the prior art;

[0049] Figure 5 A hold time violation repair model diagram using useful skew of the present application;

[0050] Figure 6 A combined delay unit schematic diagram of the clock tree adaptive optimization method based on the RISC-V architecture using useful skew of an embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application.

[0052] On the contrary, the present application covers any substitution, modification, equivalent method and solution defined by the claims within the essence and scope of the present application. Further, in order to make the public have a better understanding of the present application, some specific details are described in detail in the following detailed description of the present application. The present application can also be completely understood without the description of these details by those skilled in the art.

[0053] Referring to Figure 1 For the flowchart of the method embodiment of the present application, when S1, placement; S2, layout; S3, clock tree synthesis, S10, register-to-register timing path optimization is performed; when S4, routing, S20, register-to-memory timing path optimization is performed.

[0054] S10 includes the following steps:

[0055] S11, screening target critical path between registers;

[0056] S12, determining whether there is a deviation optimization condition;

[0057] Yes, S13, generating a feedback early intervention clock tree synthesis guide file;

[0058] No, exit the loop and perform S4, routing.

[0059] S20 includes the following steps:

[0060] S21, screening the target path of the register-to-memory that can be optimized;

[0061] S22, adding a driving layout to the clock model during synthesis;

[0062] S23, executing a timing engineering change command;

[0063] S24, determining whether there is a deviation optimization condition;

[0064] Yes, return to S21;

[0065] No, complete S20 and perform S5, joint optimization of power timing.

[0066] Referring to Figure 2 S10 includes the following steps:

[0067] S101, a key path matrix is established, a new optimization path list is created, and a delay variable delayA=0 is initialized;

[0068] S102, it is judged whether there is a deviation optimization condition;

[0069] No, the loop is exited, S4 is executed, and wiring is performed;

[0070] Yes, S103 is performed to determine an optimization parameter value delay;

[0071] S104, the optimization path list is read;

[0072] S105, it is judged whether the list has a key path;

[0073] Yes, S106 is performed to update delay=delay+delayA;

[0074] No, S107 is performed, delayA=delay;

[0075] S108, a netlist is written into a key path;

[0076] S109, a key path parameter delayA is added;

[0077] S110, a guide file for clock tree synthesis is generated.

[0078] The application proposes a new ADFF (Adaptive Full Flow) clock tree optimization method. Chip physical design usually includes Floorplan (layout), Place (layout), CTS (clock tree synthesis), Route (wiring) and timing ECO (Engineering Change Order). In the conventional process, the designer usually uses the tool to optimize the timing with the bias after the layout and wiring. This paper proposes a method of joint feedback optimization in the CTS and Route stages. In the CTS stage, the timing path is traversed and feedback is obtained, and these feedback information is returned to the pre-CTS stage for early intervention, and adaptive iteration is realized to accurately identify all key paths and solve the setup time violation problem. In the Route stage, the synthesis strategy is applied based on the hold time violation, and finally the joint optimization of power consumption and timing is realized to achieve full-process repair and power consumption improvement of the clock tree timing violation.

[0079] For reg2reg path, after a round of normal CTS, an optimization method based on iterative algorithm is proposed to update the CTS guidance file by dynamically adjusting the path delay, so as to iteratively optimize the timing of the critical path. Firstly, initialize the delay variable delayA = Δ = 0, and create a new optimization path list file DelayList to store the paths that can be optimized. The timing path that can be optimized must meet the following two conditions: there is sufficient timing margin for the establishment time constraint of the subsequent path, and the hold time constraint of the target path is still met. In each cycle after the second round, if the target optimization path does not exist in the list, the path and the delay value to be adjusted are updated to the list; if the path already exists in the list, the delay value to be adjusted is added to the existing delay value in the list. Then, the updated path and delay value are used to generate the CTS guidance file, which is fed back to the pre-CTS stage for re-synthesis to continue the iterative timing repair. After the critical path matrix is established, the loop formula is as follows:

[0080] For i = 1 to n

[0081] If (Si > Sth and Hi > Hth) Then

[0082] If Then

[0083] Δ = D0

[0084] Else

[0085] Di = D0 + Δ

[0086] Δ = Di

[0087] DelayList ← DelayList ∪ {(Pi, Di)}

[0088] WriteToGuidanceFile (Pi, Di)

[0089] Run CTS

[0090] Where D0 represents the determined optimization parameter value, Pi is the i-th path in the table, Si > Sth and Hi > Hth represent the two timing margin prerequisites that the optimization path must meet, and through the above loop, adaptive iterative optimization of the path is realized.

[0091] The core of the clock tree synthesis guide file of the method is to add a virtual delay value by using the set_clock_balance_points-delay command. The tool usually takes the principle of balancing the clock tree, and the virtual delay does not actually exist, so the introduction of the virtual delay increases the network delay of the clock path, thereby helping to solve the setup time violation of the target path.

[0092] S5 includes adding a buffer to increase the path delay, and when the clock signal is transmitted to two physically adjacent registers, the two adjacent registers use the same buffer.

[0093] For the reg2mem (register-memory) path, the skew is repaired by reducing the clock delay to the memory. See Figure 3 To basically repair the setup time violation model, there are several registers connected to the memory. It is assumed that the delay of the clock arriving at the register is 300ps, the delay of the clock arriving at the memory is 350ps, and the path delay of the register to the memory is 40ps. Clock jitter, clock uncertainty, and memory hold time requirements are ignored. According to the hold time constraint formula, the several register-to-memory timing paths all produce hold time violations.

[0094] See Figure 4 To repair such hold time violations for EDA tools is to insert a large number of buffers at the violation to increase the path delay. See Figure 5 The clock delay to the memory is reduced, and the hold time violation is repaired by using the useful skew. According to the setup time constraint formula, if the clock path network delay from the clock source to the start of the timing path is reduced, the setup time violation of the path will also be repaired. Therefore, the setup time constraint of the subsequent mem2reg path will also be improved. Reducing the clock delay of the memory by 10ps not only repairs the 10ps hold time violation of the reg2mem path, but also increases the setup time constraint margin of the subsequent mem2reg path by 10ps.

[0095] In optimizing timing, due to the demand for high performance, the buffers inserted by adding drivers are all low voltage transistors (LVT), which will significantly increase power consumption and increase the cost of the chip. Therefore, we use the method of merging and optimizing delay cells to strictly control the number of cells and achieve joint optimization of power consumption and timing. See Figure 6When the clock signal is transmitted to two registers with close physical locations, if the buffer added on the last stage clock path is added to repair the timing violation, the buffers of multiple registers will be merged into one delay cell. Under the premise of keeping the function unchanged and meeting the design rules, the net on the broken path (such as the net at the point of x in the figure) is connected to the buffer behind the net on another path, so as to realize the sharing of the delay cells of the two paths, thereby greatly reducing the power consumption. Figure 6

[0096] In order to distinguish the adaptive full flow and the buffer automatically inserted by the tool, the "indelaybuffer" suffix is added when naming the delay cell. All nets are traversed, and all nets connected with two or more inserted buffers are screened out. The net connects two registers, and ensures that all subsequent connected delay cells are inserted by the method. The screening method is as follows:

[0097] get_net-of[get_cells*indelaybuffer*-hier]

[0098] For i=1to n get_pins-of nets

[0099] sizeof_collection pins number=2.

[0100] The application realizes a new Adaptive Full Flow (ADFF) clock tree adaptive optimization method based on RISC-V architecture, which efficiently utilizes useful skew. In the conventional flow, the designer usually uses the useful skew to perform timing optimization after layout and routing. Through iterative cycle optimization by timing feedback at different stages, the application finally adopts a joint strategy of power consumption and timing to improve the quality of the clock tree and reduce the burden of the chip.

[0101] ​Although modern EDA (Electronic Design Automation) tools generally have the "auto useful skew" function, these tools still have significant limitations in practical applications. When using the auto function, the clock tree is optimized by setting prepone and postpone. Increasing the prepone and postpone parameter values set in the tool can improve the timing situation, but will introduce additional buffers on the small violation paths that can be repaired through the normal layout and routing process, resulting in a significant increase in the number of Clock Cells. Too many buffers not only cause longer routing time and higher routing resource consumption, but also increase clock jitter and reduce clock tree quality, which is particularly significant in high-frequency designs. Conversely, parameter settings that are too small may not effectively repair timing violations on critical paths.

[0102] In the design of the present application, in the clock tree synthesis (CTS) stage of the IC design process, the timing paths are traversed and feedback is obtained, and these feedback information is returned to the pre-CTS stage for early intervention, and adaptive iteration is realized to accurately identify all critical paths and solve the problem of setup time violations; In the routing stage, based on the hold time violations, comprehensive strategies are applied specifically, and finally through the joint optimization of power consumption and timing, the full-process repair and power consumption improvement of the clock tree timing violations are realized.

[0103] The present application not only makes the timing of chip design more convergent, but also greatly reduces the cost and power consumption required for useful skew, and can repair more timing violations that cannot be optimized by normal layout and routing processes.

[0104] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A clock tree adaptive optimization method with useful bias based on RISC-V architecture, characterized in that, In S1, routing; in S2, layout; After S3, clock tree synthesis, S10, register to register timing path optimization is performed; after S4, routing, S20, register to memory timing path optimization is performed; The S10 includes the following steps: S11, screening target critical path between registers; S12, judging whether there is a deviation optimization condition; Yes, S13, generating a feedback early intervention clock tree synthesis guide file; No, exiting the loop and performing S4, routing; The S10 includes the following steps: S101, establishing a critical path matrix, creating a new optimization path list file, and initializing a delay variable delayA=0; S102, judging whether there is a deviation optimization condition; No, exiting the loop and performing S4, routing; Yes, S103, determining an optimization parameter value delay; S104, reading a path list to be optimized; S105, judging whether the list exists the critical path; Yes, S106, updating delay=delay+delayA; No, S107, delayA=delay; S108, netlist writing into a critical path; S109, adding a critical path parameter delayA; S110, generating a clock tree synthesis guide file; The S20 includes the following steps: S21, screening an optimized register to memory target path; S22, synthesizing a clock model and adding a driving layout; S23, executing a timing engineering change command; S24, judging whether there is a deviation optimization condition; Yes, returning to S21; No, completing S20 and performing S5, joint optimization of power consumption and timing; The S5 includes adding a buffer to increase path delay, and when a clock signal is transmitted to two physically adjacent registers, the two adjacent registers use the same buffer through a merging operation.

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