Switchable floating memristor simulator based on bidirectional symmetry characteristic

Abstract

The invention provides a switchable floating memristor simulator based on a bidirectional symmetry characteristic. The switchable floating memristor simulator comprises three multipliers U1, U2 and U3, a node z, a capacitor C1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first voltage V1, a second voltage V2, and two current feedback operational amplifiers U4 and U5. According to the floating memristor simulator, theoretical constraints needing to be met by the floating memristor with the bidirectional conduction characteristic are deduced based on the memristor theory, and the floating memristor circuit conforming to the structure is provided, so that the memristor simulator has non-directivity, a hysteresis loop is not affected by the connection direction, and the performance of the floating memristor simulator is improved. In addition, several switches are added, so that the circuit realizes free switching between the grounding memristor and the floating memristor, and the diversity of the circuit is increased.

Description

Technical Field

[0001] The invention belongs to the field of electronic communication and information engineering, and in particular relates to a switchable floating memristor emulator based on bidirectional symmetric characteristics. Background Art

[0002] Memristor was originally conceived by Professor Shaotang Cai as a two-terminal electronic component used to correspond to the missing constituent flux connection between charge and magnetic flux. Because memristors cannot be directly commercialized at present, various memristor simulation circuits have been proposed and used to discover various dynamic characteristics of memristor systems. In the field of chaos, the nonlinear structure of memristors greatly enriches the dynamic characteristics of the system, making chaotic systems more prone to hyperchaos, multi-stability and other phenomena. Therefore, the complexity of chaotic systems is improved, and the security performance in chaotic encryption is further improved. However, these actual simulation circuits have a restrictive feature, that is, one terminal is connected to the ground and the other terminal is connected to the ground, which limits their widespread use in circuit design and applications. Therefore, memristors with floating ground characteristics have received widespread attention. Summary of the invention

[0003] Purpose of the invention: The technical problem to be solved by the present invention is to provide a switchable floating memristor emulator based on bidirectional symmetric characteristics in view of the deficiencies in the prior art, including three multipliers U1, U2 and U3, a node z, a capacitor C1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first voltage V1, a second voltage V2, and two current feedback operational amplifiers U4 and U5;

[0004] Among them, the three multipliers U1, U2 and U3 have the same structure, and all include an X non-inverting input terminal X1, an X inverting input terminal X2, a Y non-inverting input terminal Y1, a Y inverting input terminal Y2, a negative power supply terminal VS-, a positive power supply terminal VS+, a summing input terminal Z, and a voltage output terminal W;

[0005] The two current feedback operational amplifiers U4 and U5 have the same structure, and both include a non-inverting terminal 3, an inverting terminal 1, a negative power supply terminal 4, a positive power supply terminal 7, and a current output terminal 5;

[0006] The X non-inverting input terminal X1 and the Y non-inverting input terminal Y1 of the multiplier U1 are connected to the input signal A, the X inverting input terminal X2 and the Y inverting input terminal Y2 are connected to the input signal B, the voltage output terminal W of the multiplier U1 is connected in series with the first resistor R1 to the summing input port Z to realize the current transmission function, the positive power supply terminal VS+ is connected to the positive power supply Vp, and the negative power supply terminal VS- is connected to the negative power supply Vn;

[0007] The first resistor R1 is connected to the capacitor C1 to realize an integration circuit, and the first voltage V1 is connected in series with the second resistor R2 to the node z;

[0008] The X non-inverting input terminal X1 and the Y non-inverting input terminal Y1 of the multiplier U2 are connected to the node z, the X inverting input terminal X2 and the Y inverting input terminal Y2 are grounded, the voltage output terminal W of the multiplier U2 is connected to the third resistor R3, the summing input port Z of the multiplier U2 is connected to 90% of the resistance value of the third resistor R3, the positive power supply terminal VS+ is connected to the positive power supply Vp, and the negative power supply terminal VS- is connected to the negative power supply Vn;

[0009] The X non-inverting input terminal X1 of the multiplier U3 is connected to the second voltage V2, the Y non-inverting input terminal Y1 is connected to the voltage output terminal W of the multiplier U2, the Y non-inverting input terminal Y1 is also connected to the input signal A, the Y inverting input terminal Y2 is connected to the input signal B, and the summing input port Z of the multiplier U3 is connected to the second switch S2; the voltage output terminal W of the multiplier U3 is connected to the first switch S1, the positive power supply terminal VS+ is connected to the positive power supply Vp, and the negative power supply terminal VS- is connected to the negative power supply Vn.

[0010] The first switch S1 has its terminal 1 connected to the non-inverting terminal 3 of the operational amplifier U5; the first switch S1 has its terminal 2 connected in series to the fifth resistor R5, and further connected in series to the third switch S3.

[0011] The first terminal of the second switch S2 is grounded, and the second terminal is connected to the input signal B.

[0012] Terminal 1 of the third switch S3 is connected to the Y non-inverting input terminal Y1 of the multiplier U3, and terminal 2 of the third switch S3 is connected to the Y inverting input terminal Y2 of the multiplier U3.

[0013] The inverting terminal 2 of the operational amplifier U5 is connected to the inverting terminal 2 of the operational amplifier U4 through a fourth resistor R4 in series, the non-inverting terminal 3 of U5 is grounded, the current output terminal 5 of U5 is first connected to the fourth switch S4 and then to the input signal B, the positive power supply terminals of the operational amplifiers U4 and U5 are both connected to the positive power supply Vp, and the negative power supply terminals are both connected to the negative power supply Vn.

[0014] When the first switch S1 and the second switch S2 are placed at the 1 end and the fourth switch S4 is closed, the memristor emulator is in a floating memristor state;

[0015] When the first switch S1 is placed at the 2 end, the second switch S2 is placed at the 1 end, the third switch S3 is placed at the 1 end and the fourth switch S4 is disconnected, the memristor emulator is in the in-phase grounded memristor state. At this time, the B end is in a high impedance state, and the A end can normally input the excitation signal. When observing the hysteresis loop, the B end needs to be grounded.

[0016] When the first switch S1, the second switch S2 and the third switch S3 are all placed at terminal 2 and the fourth switch S4 is disconnected, the memristor emulator is in an inverting grounded memristor state. At this time, terminal A is in a high impedance state, and terminal B can normally input an excitation signal. Terminal A needs to be grounded when observing the hysteresis loop.

[0017] According to the following constraints (1) and (2), the structural representation equation (3) of the switchable floating memristor emulator is obtained:

[0018] (1)

[0019] (2)

[0020] (3)

[0021] in and represent the voltage and current passing through the memristor at time t, respectively. is the memristor scalar; represents a set variable consisting of n state variables, Represents a collection variable The first-order derivative with respect to time, f, is a function of and A continuous function of .

[0022] The memristor structure of the actual circuit of the switchable floating memristor emulator is obtained by the superposition theorem, which is expressed as equation (4):

[0023] (4)

[0024] Among them, R1, R2, R4, C1, and V1 respectively represent the resistance value of the first resistor, the resistance value of the second resistor, the resistance value of the fourth resistor, the capacitance of the capacitor, and the voltage value of the first voltage.

[0025] Based on the theoretical definition of memristor, the present invention proposes a memristor emulator with bidirectional symmetry and the ability to switch freely between two modes: general grounded memristor and floating memristor. Further optimization is made to the directionality of the existing floating memristor, so that the memristor becomes a non-directional device, and the memristor structure does not change with the conduction direction. Not only are relevant specifications made in theory, but also the feasibility is verified through actual circuits.

[0026] Beneficial effects: The present invention is rooted in the theory of memristors, and derives the theoretical constraints that a floating memristor with bidirectional conduction characteristics needs to meet, and provides a floating memristor circuit that conforms to the structure, so that the memristor emulator has no directionality, and the hysteresis loop is not affected by the connection direction. In addition, several switches are added to enable the circuit to freely switch between grounded memristors and floating memristors, increasing the diversity of the circuit. The floating memristor circuit uses the multiplier AD633 as the main voltage acquisition module, so the two ends of the memristor have the characteristic of high input impedance. At the same time, the second-generation current transmitter AD844 is used as the current output module to realize a pair of current outputs of opposite phase and equal amplitude, so that the input current of the floating memristor is the same as the output current. The input and output ends of the floating memristor circuit in this article are highly symmetrical, which is beneficial to matching the bidirectional symmetrical structure proposed by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is the connection method of the grounded memristor emulator of the present invention.

[0028] Figure 2 This is the connection method of the floating memristor emulator of the present invention.

[0029] Figure 3 The invention relates to a switchable bidirectional symmetrical floating memristor circuit.

[0030] Figure 4 It is a bidirectional symmetrical floating memristor hysteresis loop diagram of the present invention.

[0031] Figure 5 It is the in-phase grounded memristor hysteresis loop diagram of the present invention.

[0032] Figure 6 It is the reverse-phase grounded memristor hysteresis loop diagram of the present invention. DETAILED DESCRIPTION

[0033] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more clear.

[0034] The embodiment of the present invention provides a switchable floating memristor emulator based on bidirectional symmetry characteristics. The n-dimensional voltage-controlled memristor system is expressed as equation (1):

[0035] (1)

[0036] in and represent the voltage and current through the memristor, respectively. is the memristor scalar; represents a set variable consisting of n state variables, Represents a collection variable The first-order derivative with respect to time, f, is a function of and A continuous function of .

[0037] The present invention analyzes the feasibility of realizing bidirectional conduction in theory based on the definition of memristor. Figure 1 The figure shows two states of a grounded memristor, forward connection and reverse connection. In the figure, M1 represents a memristor. The difference between the A terminal and the B terminal is set to When , it indicates positive connection, and the difference is When it indicates reverse connection, according to formula (1), the current in (2) and (3) is obtained and The memristor model, represents the first current, which is the current flowing into terminal A when the grounded memristor is in the positive connection state. represents the third current, which is the current flowing into terminal A when the grounded memristor is in reverse connection. Because the memristor is a resistor whose resistance changes with the magnetic control, Kirchhoff's current law gives , and get formula (4), where represents the second current, which is the current flowing into terminal B when the grounded memristor is in reverse connection:

[0038] (2)

[0039] (3)

[0040] (4)

[0041] If the n-dimensional voltage-controlled memristor system has bidirectional conduction characteristics, then:

[0042] (5)

[0043] From equations (2) and (4), we can see that , It’s all about variables When is an even function, equation (5) is satisfied. Therefore, it can be obtained that the original definition of memristor satisfies the bidirectional conduction characteristic only under limited conditions. Figure 2 is the circuit model of floating memristor based on formula (1), where M1 still represents a memristor. From formula (1), we get and Memristor models (6), (7), represents the fourth current, which is the current flowing out of the floating memristor from terminal A. represents the fifth current, which is the current flowing out of the floating memristor from terminal B:

[0044] (6)

[0045] (7)

[0046] because , ,in represents the potential difference between the A and B terminals of the memristor, Represents the potential difference between the B terminal and the A terminal of the memristor. If the floating memristor has a bidirectional conduction characteristic, then Figure 2 The memristors connected to system 1 and system 2 should be the same, that is, (6) and (7) have the same memristor structure, then , It’s all about variables An even function of .

[0047] In summary, a memristor with bidirectional conduction characteristics needs to satisfy not only formula (1) but also formula (8):

[0048] (8) Based on the constraints of formula (1) and formula (8), the present invention designs a floating memristor structure with bidirectional symmetry characteristics, as shown in equation (9):

[0049] (9)

[0050] The embodiment of the present invention provides a switchable floating memristor simulator based on bidirectional symmetry characteristics, the circuit model is as follows Figure 3 As shown, Vp and Vn represent positive power supply and negative power supply respectively for powering the multiplier and operational amplifier, the X in-phase input terminal X1 and the Y in-phase input terminal Y1 of the multiplier U1 are connected to the input signal A, the X inverting input terminal X2 and the Y inverting input terminal Y2 are connected to the input signal B, the voltage output terminal W is connected in series with the first resistor R1 to the input terminal Z to realize the current transmission function, the positive power supply terminal VS+ is connected to the positive power supply Vp, and the negative power supply terminal VS- is connected to the negative power supply Vn. The first resistor R1 is connected to the capacitor C1 to realize the integration circuit, and the first voltage V1 is connected in series with the second resistor R2 to the node The X non-inverting input terminal X1 and the Y non-inverting input terminal Y1 of the multiplier U2 are connected to the node , the X inverting input terminal X2 and the Y inverting input terminal Y2 are grounded, the voltage output terminal W is connected to the potentiometer R3, the input terminal Z is connected to 90% of the resistance of the third resistor R3, the positive power supply terminal VS+ is connected to the positive power supply Vp, and the negative power supply terminal VS- is connected to the negative power supply Vn.

[0051] The X non-inverting input terminal X1 of the multiplier U3 is connected to the second voltage V2, the Y non-inverting input terminal Y1 is connected to the W terminal of the multiplier U2, Y1 is connected to the input signal A terminal, the Y inverting input terminal Y2 is connected to the input signal B, the Z terminal is connected to the second switch S2, the positive power supply terminal VS+ is connected to the positive power supply Vp, and the negative power supply terminal VS- is connected to the negative power supply Vn; the 1 terminal of the second switch S2 is grounded, the 2 terminal is connected to the input signal B, the W terminal is connected to the first switch S1, the 2 terminal of the first switch S1 is connected in series with the fifth resistor R5, and then connected in series with the third switch S3, the 1 terminal of the third switch S3 is connected to the Y non-inverting input terminal Y1 of the multiplier U3, and the 2 terminal of the third switch S3 is connected to the Y inverting input terminal Y2 of the multiplier U3; the 1 terminal of the first switch S1 is connected to the non-inverting terminal 3 of the operational amplifier U5, and the current output terminal 5 is first connected to the fourth switch S4 and then connected back to the B port;

[0052] The inverting terminal 2 of U5 is connected to the inverting terminal 2 of the operational amplifier U4 through a fourth resistor R4 in series, the non-inverting terminal is grounded, the current output terminal 5 of U5 is connected to the A port, the positive power supply terminals of both are connected to the positive power supply Vp, and the negative power supply terminals are connected to the negative power supply Vn;

[0053] When the first switch S1 and the second switch S2 are placed at the 1 end and the fourth switch S4 is closed, the memristor emulator is in a floating memristor state;

[0054] When the first switch S1 is placed at terminal 2, the second switch S2 is placed at terminal 1, the third switch S3 is placed at terminal 1 and the fourth switch S4 is disconnected, the memristor emulator is in the in-phase grounded memristor state. At this time, terminal B is in a high impedance state and terminal A can normally input an excitation signal. Therefore, terminal B needs to be grounded when observing the hysteresis loop.

[0055] When the first switch S1, the second switch S2 and the third switch S3 are all placed at the 2 end and the fourth switch S4 is disconnected, the memristor emulator is in the reverse grounded memristor state. At this time, the A end is in a high impedance state and the B end can normally input the excitation signal. Therefore, the A end needs to be grounded when observing the hysteresis loop. The memristor structure of the actual circuit is obtained by the superposition theorem as equation (10):

[0056] (10)

[0057] The resistors R1=R3=R4=1kΩ, R2=5kΩ, R5=500Ω, C1=100nF, V1=-3V, V2=1V, Vp=15V, Vn=-15V. The resistor R5 is used to convert the voltage output of the multiplier into current output. It does not participate in the internal structure calculation of the memristor, and a reasonable value can be selected. Figure 4 For this parameter, when V M This is the hysteresis loop when the frequency is 3kHz and the amplitude is 3Vpp. Figure 5 For this parameter, when V MThis is the in-phase memristor hysteresis loop at a frequency of 500Hz and an amplitude of 3Vpp. Figure 6 For this parameter, when V M is the anti-phase memristor hysteresis loop at a frequency of 500Hz and an amplitude of 3Vpp. Figure 4 It can be seen (the left side is AB= V M , on the right side is BA = V M ), the hysteresis loop does not change shape with the change of the conduction direction of the memristor, verifying its bidirectional conduction characteristics. Figure 5 and Figure 6 It can be seen that the hysteresis loops of the in-phase and anti-phase grounded memristor emulators are completely different under the stimulation of the same signal. This shows that even if the internal equations of the grounded memristor emulator meet the requirements of memristor non-directionality, it cannot achieve non-directionality in structure. This further proves the necessity of realizing bidirectional conduction of the memristor emulator in the floating state, and at the same time makes the memristor emulator multi-modal.

[0058] The input terminals A and B of the bidirectional symmetrical convertible floating memristor emulator provided in this embodiment are highly symmetrical inside the circuit, so the hysteresis loop of the floating memristor does not change with the change of the conduction direction of A and B. This circuit uses AD633 as the voltage input terminal and AD844 as the current output terminal to completely separate the voltage operation and circuit output, making the circuit structure more streamlined and user-friendly and practical, with certain scalability. At the same time, the emulator allows the user to select the structure inside the memristor emulator through a switch to achieve free switching between grounded memristor and floating memristor.

[0059] The floating memristor emulator circuit inherits the floating characteristics of the original floating memristor, is not restricted by grounding, and ensures that the input and output currents at both ends of the memristor emulator are equal in magnitude and opposite in direction. In addition, the present invention also has a bidirectional symmetric characteristic under floating conditions. In a single system, the memristor structure of the memristor itself can be selected by changing the connection direction of the memristor; when multiple systems are reused, three systems can also share the same memristor structure. The floating memristor circuit based on the bidirectional conduction characteristic proposed by the present invention structurally meets the original memristor definition formula, proving that the bidirectional conduction characteristic is a potential achievable characteristic of the memristor. By meeting the relevant theoretical conditions, the memristor circuit can be freed from the constraints of directionality and can be non-directional like a resistor, and the memristor emulator can be connected to the circuit in series or in parallel under floating conditions. In addition, the present invention introduces several switches to realize the free switching between grounded memristors and bidirectional symmetrical floating memristors. The present invention theoretically derives the establishment conditions and verifies the relevant results through actual circuits.

[0060] The present invention provides a switchable floating memristor emulator based on bidirectional symmetric characteristics. There are many methods and ways to implement the technical solution. The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention. All components not specified in this embodiment can be implemented by existing technologies.

Claims

1. A switchable floating memristor emulator based on bidirectional symmetry characteristics, characterized in that: It includes three multipliers U1, U2 and U3, a node z, a capacitor C1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first voltage V1, a second voltage V2, and two current feedback operational amplifiers U4 and U5; Among them, the three multipliers U1, U2 and U3 have the same structure, and all include an X non-inverting input terminal X1, an X inverting input terminal X2, a Y non-inverting input terminal Y1, a Y inverting input terminal Y2, a negative power supply terminal VS-, a positive power supply terminal VS+, a summing input terminal Z, and a voltage output terminal W; The two current feedback operational amplifiers U4 and U5 have the same structure, and both include a non-inverting terminal 3, an inverting terminal 1, a negative power supply terminal 4, a positive power supply terminal 7, and a current output terminal 5; The X non-inverting input terminal X1 and the Y non-inverting input terminal Y1 of the multiplier U1 are connected to the input signal A, the X inverting input terminal X2 and the Y inverting input terminal Y2 are connected to the input signal B, the voltage output terminal W of the multiplier U1 is connected in series with the first resistor R1 to the summing input port Z to realize the current transmission function, the positive power supply terminal VS+ is connected to the positive power supply Vp, and the negative power supply terminal VS- is connected to the negative power supply Vn; The first resistor R1 is connected to the capacitor C1 to realize an integration circuit, and the first voltage V1 is connected in series with the second resistor R2 to the node z; The X non-inverting input terminal X1 and the Y non-inverting input terminal Y1 of the multiplier U2 are connected to the node z, the X inverting input terminal X2 and the Y inverting input terminal Y2 are grounded, the voltage output terminal W of the multiplier U2 is connected to the third resistor R3, the summing input port Z of the multiplier U2 is connected to 90% of the resistance value of the third resistor R3, the positive power supply terminal VS+ is connected to the positive power supply Vp, and the negative power supply terminal VS- is connected to the negative power supply Vn; The X non-inverting input terminal X1 of the multiplier U3 is connected to the second voltage V2, the Y non-inverting input terminal Y1 is connected to the voltage output terminal W of the multiplier U2, the Y non-inverting input terminal Y1 is also connected to the input signal A, the Y inverting input terminal Y2 is connected to the input signal B, and the summing input port Z of the multiplier U3 is connected to the second switch S2; the voltage output terminal W of the multiplier U3 is connected to the first switch S1, the positive power supply terminal VS+ is connected to the positive power supply Vp, and the negative power supply terminal VS- is connected to the negative power supply Vn.

2. A switchable floating memristor emulator based on bidirectional symmetric characteristics according to claim 1, characterized in that: The first switch S1 has its terminal 1 connected to the non-inverting terminal 3 of the operational amplifier U5; the first switch S1 has its terminal 2 connected in series to the fifth resistor R5, and further connected in series to the third switch S3.

3. A switchable floating memristor emulator based on bidirectional symmetric characteristics according to claim 2, characterized in that: The first terminal of the second switch S2 is grounded, and the second terminal is connected to the input signal B.

4. A switchable floating memristor emulator based on bidirectional symmetry characteristics according to claim 3, characterized in that: Terminal 1 of the third switch S3 is connected to the Y non-inverting input terminal Y1 of the multiplier U3, and terminal 2 of the third switch S3 is connected to the Y inverting input terminal Y2 of the multiplier U3.

5. A switchable floating memristor emulator based on bidirectional symmetric characteristics according to claim 4, characterized in that: The inverting terminal 2 of the operational amplifier U5 is connected to the inverting terminal 2 of the operational amplifier U4 through a fourth resistor R4 in series, the non-inverting terminal 3 of U5 is grounded, the current output terminal 5 of U5 is first connected to the fourth switch S4 and then to the input signal B, the positive power supply terminals of the operational amplifiers U4 and U5 are both connected to the positive power supply Vp, and the negative power supply terminals are both connected to the negative power supply Vn.

6. A switchable floating memristor emulator based on bidirectional symmetry characteristics according to claim 5, characterized in that: When the first switch S1 and the second switch S2 are placed at the 1 end and the fourth switch S4 is closed, the memristor emulator is in a floating memristor state; When the first switch S1 is placed at the 2 end, the second switch S2 is placed at the 1 end, the third switch S3 is placed at the 1 end and the fourth switch S4 is disconnected, the memristor emulator is in the in-phase grounded memristor state. At this time, the B end is in a high impedance state, and the A end can normally input the excitation signal. When observing the hysteresis loop, the B end needs to be grounded. When the first switch S1, the second switch S2 and the third switch S3 are all placed at terminal 2 and the fourth switch S4 is disconnected, the memristor emulator is in an inverting grounded memristor state. At this time, terminal A is in a high impedance state, and terminal B can normally input an excitation signal. Terminal A needs to be grounded when observing the hysteresis loop.

7. A switchable floating memristor emulator based on bidirectional symmetric characteristics according to claim 6, characterized in that: According to the following constraints (1) and (2), the structural representation equation (3) of the switchable floating memristor emulator is obtained: （1） ， （2）， （3）， in and represent the voltage and current passing through the memristor at time t, respectively. is the memristor scalar; represents a set variable consisting of n state variables, Represents a collection variable The first-order derivative with respect to time, f, is a function of and A continuous function of .

8. A switchable floating memristor emulator based on bidirectional symmetric characteristics according to claim 7, characterized in that: The memristor structure of the actual circuit of the switchable floating memristor emulator is obtained by the superposition theorem, which is expressed as equation (4): （4）， Among them, R1, R2, R4, C1, and V1 respectively represent the resistance value of the first resistor, the resistance value of the second resistor, the resistance value of the fourth resistor, the capacitance of the capacitor, and the voltage value of the first voltage.

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