A working method for simulating a computer chip

Abstract

The present invention relates to the field of artificial intelligence technology, and discloses a working method for simulating a computer chip. The method includes: receiving training data and initial values of model parameters; the initial values of the model parameters are used to initialize the parameters of the storage arithmetic unit; according to the training data, the regulator iteratively updates the parameters of the storage arithmetic unit, and when the iteration completion condition is satisfied, a first arithmetic model corresponding to the storage arithmetic unit is generated; inputting the model input value corresponding to the first target scenario into the analog computer chip, and outputting the model output value corresponding to the first target scenario through the first arithmetic model in the analog computer chip. The above solution can autonomously generate an arithmetic model inside the analog computer chip and can perform self-learning updates, thereby increasing the application scope of the working method and improving the accuracy of the artificial intelligence chip applying the working method.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence technology, and particularly to a working method for simulating a computer chip. Background Art

[0002] In the prior art, the working method of an artificial intelligence chip is usually as follows: First, according to the design requirements and application scenarios of the chip, an operation model is generated outside the chip, and then the operation model generated outside is input into the artificial intelligence chip. Since the operation model is trained based on the data of a specific working scenario outside the chip, when the operation model is input into the artificial intelligence chip, the artificial intelligence chip can only be applied to a specific working scenario.

[0003] It can be seen from this that the working method of the artificial intelligence chip in the prior art can only be applied to a fixed working scenario, and the operation model inside the artificial intelligence chip using this working method cannot perform self-learning and updating, resulting in a narrow application range of this working method and low accuracy of the artificial intelligence chip using this working method. Summary of the Invention

[0004] In view of this, the present invention provides a working method for simulating a computer chip to increase the application range of the working method of the artificial intelligence chip.

[0005] In a first aspect, the present invention provides a working method for simulating a computer chip, which is executed by a simulated computer chip. A storage arithmetic unit and a regulator are provided in the simulated computer chip; the topological structure of the storage arithmetic unit is the same as the topological structure of the target neural network model. The method includes:

[0006] Receiving training data and an initial value of model parameters; the initial value of the model parameters is used to initialize the parameters of the storage arithmetic unit;

[0007] According to the training data, the regulator iteratively updates the parameters of the storage arithmetic unit, and when the iteration completion condition is satisfied, a first operation model corresponding to the storage arithmetic unit is generated;

[0008] Inputting the model input value corresponding to the first target scenario into the simulated computer chip, and outputting the model output value corresponding to the first target scenario through the first operation model in the simulated computer chip.

[0009] In a possible implementation manner, the iteratively updating the parameters of the storage arithmetic unit by the regulator according to the training data includes:

[0010] Processing the sample input value in the training data through the storage arithmetic unit to obtain an actual output value;

[0011] If the first error value between the actual output value and the expected output value in the training data does not meet the iteration completion condition, the parameters of the storage arithmetic unit are iteratively updated by a regulator according to the actual output value and the expected output value in the training data.

[0012] In a possible implementation, the iteration completion condition is that the first error value is less than an error threshold.

[0013] In a possible implementation, when the number of actual output values is greater than 1;

[0014] The method further includes:

[0015] Obtain the errors between each actual output value and the corresponding expected output value;

[0016] Determine the mean value of the errors between each actual output value and the corresponding expected output value as the first error value.

[0017] In a possible implementation, in the storage arithmetic unit, the input end is connected to the output end through n layers of memories and n layers of arithmetic units; adjacent two layers of arithmetic units are connected through one layer of memory; the transfer function of the memory corresponds to the parameters of the memory;

[0018] The iteratively updating the parameters of the storage arithmetic unit by a regulator according to the actual output value and the expected output value in the training data includes:

[0019] According to the actual output value and the expected output value in the training data, adjust the parameters of each memory in the nth layer of the storage arithmetic unit by a regulator;

[0020] According to each memory in the nth layer with updated parameters and the expected output value in the training data, obtain the operation update values of each arithmetic unit in the corresponding (n - 1)th layer by a regulator, and use the operation update values as the expected output values of the (n - 1)th layer of arithmetic units;

[0021] According to the actual output values and the expected output values of each arithmetic unit in the (q - 1)th layer, adjust the parameters of each memory in the (q - 1)th layer of the storage arithmetic unit by a regulator;

[0022] According to each memory in the (q - 1)th layer with updated parameters and the expected output values of each arithmetic unit in the (q - 1)th layer, obtain the operation update values of each arithmetic unit in the corresponding (q - 2)th layer by a regulator, and use the operation update values as the expected output values of the (q - 2)th layer of arithmetic units, where n ≥ q ≥ 3.

[0023] In a possible implementation, the method further includes:

[0024] According to the actual output value and the expected output value of the first - layer arithmetic unit, the parameters of each memory in the first layer of the storage arithmetic unit are adjusted by a regulator.

[0025] In a possible implementation, the parameters of the memory are related to the floating - gate charges of the MOS transistors in the non - volatile storage cells in the memory.

[0026] In a possible implementation, the method further includes:

[0027] When an expected output value corresponding to a model input value and a model adjustment level signal are received through the expected output value input pin, the first arithmetic model is adjusted according to the actual output value corresponding to the model input value, the expected output value corresponding to the model input value, and the received model adjustment level signal, to obtain a second arithmetic model.

[0028] In a possible implementation, the adjusting the first arithmetic model according to the actual output value corresponding to the model input value, the expected output value corresponding to the model input value, and the received model adjustment level signal to obtain a second arithmetic model includes:

[0029] When the model adjustment level signal is received and the target memory is updated, obtain the memory parameter value of the target memory, and obtain the parameter update value of the target memory according to the actual output value corresponding to the model input value and the expected output value corresponding to the model input value;

[0030] If the difference between the memory parameter value and the parameter update value is greater than an update threshold, update the parameters of the target memory through the regulator.

[0031] In a possible implementation, the method further includes:

[0032] When the analog computer chip is applied to a second target scenario, the analog computer chip obtains the first training set and the first parameter initial value; the first training set is the training data corresponding to the second target scenario; the first parameter initial value is the initial model parameter value corresponding to the second target scenario;

[0033] Initialize the parameters of the storage arithmetic unit according to the first parameter initial value;

[0034] Iteratively update the parameters of the storage arithmetic unit according to the first training set, and when the iteration completion condition is met, generate a third arithmetic model corresponding to the storage arithmetic unit;

[0035] Input the model input value corresponding to the second target scenario into the analog computer chip, and output the model output value corresponding to the second target scenario through the third operation model in the analog computer chip.

[0036] In a possible implementation, the method further includes:

[0037] When the analog computer chip is applied to a third target scenario, the analog computer chip obtains the second training set; the second training set is the training data corresponding to the third target scenario;

[0038] According to the second training set, iteratively update the parameters of the storage arithmetic unit in the first operation model, and when the iteration completion condition is satisfied, generate a fourth operation model;

[0039] Input the model input value corresponding to the third target scenario into the analog computer chip, and output the model output value corresponding to the third target scenario through the fourth operation model in the analog computer chip.

[0040] On the other hand, a working method of an analog computer chip is provided. A storage arithmetic unit and a regulator are provided in the analog computer chip; the topological structure of the storage arithmetic unit is the same as the topological structure of the target neural network model; the target neural network model is generated in a computer device; the method includes:

[0041] Obtain training data and initial model parameter values; the initial model parameter values are used to initialize the target neural network model;

[0042] Train the target neural network model with the training data;

[0043] Set the parameters of each memory in the storage arithmetic unit according to the trained target neural network model to obtain the first operation model in the analog computer chip;

[0044] Input the model input value corresponding to the first target scenario into the analog computer chip, and obtain the model output value corresponding to the first target scenario output by the analog computer chip through the first operation model.

[0045] In a possible implementation, the setting the parameters of each memory in the storage arithmetic unit according to the trained target neural network model to obtain the first operation model in the analog computer chip includes:

[0046] Input the model parameters of the target neural network model into the regulator of the analog computer chip through the model parameter initial value input pins of the analog computer chip, so that the regulator adjusts the parameters of the corresponding memories according to the model parameters of the target neural network model.

[0047] In a possible implementation manner, the parameters of the memory are related to the floating gate charges of the MOS transistors in the non-volatile storage units in the memory.

[0048] In a possible implementation manner, the method further includes:

[0049] When receiving the expected output value corresponding to the model input value and the model adjustment level signal through the expected output value input pin, adjust the first arithmetic model according to the actual output value corresponding to the model input value, the expected output value corresponding to the model input value, and the received model adjustment level signal to obtain a second arithmetic model.

[0050] In a possible implementation manner, the adjusting the first arithmetic model according to the actual output value corresponding to the model input value, the expected output value corresponding to the model input value, and the received model adjustment level signal to obtain a second arithmetic model includes:

[0051] When receiving the model adjustment level signal and updating the target memory, obtain the memory parameter value of the target memory, and obtain the parameter update value of the target memory according to the actual output value corresponding to the model input value and the expected output value corresponding to the model input value;

[0052] If the difference between the memory parameter value and the parameter update value is greater than the update threshold, update the parameters of the target memory through the regulator in the analog computer chip.

[0053] In a possible implementation manner, the method further includes:

[0054] When the analog computer chip is applied to a second target scenario, the analog computer chip obtains the first training set and the first parameter initial value; the first training set is the training data corresponding to the second target scenario; the first parameter initial value is the model parameter initial value corresponding to the second target scenario;

[0055] Initialize the parameters of the storage arithmetic unit according to the first parameter initial value;

[0056] Iteratively update the parameters of the storage arithmetic unit according to the first training set, and when the iteration completion condition is satisfied, generate a third arithmetic model corresponding to the storage arithmetic unit;

[0057] Input the model input value corresponding to the second target scenario into the analog computer chip, and output the model output value corresponding to the second target scenario through the third operation model in the analog computer chip.

[0058] In a possible implementation, the method further includes:

[0059] When the analog computer chip is applied to a third target scenario, the analog computer chip obtains the second training set; the second training set is the training data corresponding to the third target scenario;

[0060] According to the second training set, iteratively update the parameters of the storage arithmetic unit in the first operation model, and generate a fourth operation model when the iteration completion condition is met;

[0061] Input the model input value corresponding to the third target scenario into the analog computer chip, and output the model output value corresponding to the third target scenario through the fourth operation model in the analog computer chip.

[0062] On the other hand, an analog computer chip is provided. A storage arithmetic unit and a regulator are provided in the analog computer chip; the analog computer chip is used to execute the working method of the above-mentioned analog computer chip.

[0063] On the other hand, a computer device is provided. A processing unit and a storage unit are provided on the computer device. Computer instructions are stored in the storage unit, and the processing unit is used to execute the computer instructions to execute the working method of the above-mentioned analog computer chip.

[0064] In summary, the present application provides two working methods for an analog computer chip. Both of these two working methods can autonomously generate an operation model inside the analog computer chip and can perform self-learning updates, thereby increasing the application scope of these two working methods and improving the accuracy of the artificial intelligence chip applying these two working methods;

[0065] In the first working method of the analog computer chip provided by the present application, it uses the chip to autonomously train and generate the first operation model. Since the internal circuits (regulator and storage arithmetic unit) of the analog computer chip in the present application are all composed of analog devices, therefore, the training using analog devices inside the chip in the present application is faster and consumes less energy compared to the training using digital arithmetic units such as graphics cards in the host computer. Therefore, this method is applicable to small-batch personalized customized analog computer chips;

[0066] In the second working method of the analog computer chip provided by this application, according to the application scenario of the analog computer chip, the expected output value and the initial model parameter values suitable for this application scenario are input into the host computer, the target neural network model is trained, and then the parameters of each memory in the storage arithmetic unit are set according to the trained target neural network model, so as to generate the first arithmetic model. At this time, this analog computer chip can be directly used in actual normal work without prior training. This method is applicable to analog computer chips for mass production and with known initial application scenarios;

[0067] In the two working methods of the analog computer chip provided by this application, when the analog computer chip has an arithmetic error or changes the application scenario (target scenario) and the first arithmetic model needs to be adjusted, the second arithmetic model, the third arithmetic model, and the fourth arithmetic model are all obtained by training with analog devices inside the chip, so as to accelerate the speed of model adjustment and reduce the energy consumption of model adjustment. Brief Description of the Drawings

[0068] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0069] Figure 1 Shows a working method of an analog computer chip according to an embodiment of this application;

[0070] Figure 2 Shows a network architecture diagram of an analog computer chip according to an embodiment of this application;

[0071] Figure 3 Shows a specific structural schematic diagram of a storage arithmetic unit according to an embodiment of this application;

[0072] Figure 4 Shows a specific structural diagram of the memory in the storage arithmetic unit according to an embodiment of this application;

[0073] Figure 5 Shows a structural schematic diagram of the first error comparison circuit according to an embodiment of this application;

[0074] Figure 6 Shows a specific structural schematic diagram of a comparison sub-circuit according to an embodiment of this application;

[0075] Figure 7 Shows a parameter initial value extraction circuit according to an embodiment of this application;

[0076] Figure 8 shows the operation update value generation circuit in the embodiment of the present application;

[0077] Figure 9 shows the model adjustment circuit in the embodiment of the present application;

[0078] Figure 10 shows another working method of the analog computer chip related to the embodiment of the present application;

[0079] Figure 11 is a schematic diagram of the hardware structure of the computer device according to the embodiment of the present invention. Detailed implementation manners

[0080] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0081] The present application provides a working method for an analog computer chip. This working method can autonomously generate an operation model inside the analog computer chip and can perform self-learning and updating, thereby expanding the application scope of this working method and improving the accuracy of the artificial intelligence chip applying this working method;

[0082] It should be noted that the steps executed by a computer shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0083] Figure 1 shows a working method of an analog computer chip related to the embodiment of the present application. The method is executed by the analog computer chip, as Figure 2 shown, which shows a network architecture diagram of an analog computer chip related to the embodiment of the present application. As Figure 2 shown, a storage arithmetic unit and a regulator are provided in the analog computer chip. The analog computer chip can adjust the parameters of the storage arithmetic unit, so that the storage arithmetic unit represents the mapping relationship between specific input data and specific output data. Figure 1 The corresponding working method of the analog computer chip includes:

[0084] Step 101, receiving training data and initial model parameters.

[0085] Among them, the initial values of the model parameters are used to initialize the parameters of the storage arithmetic unit.

[0086] Specifically, the analog computer chip includes an input pin for the initial values of the model parameters. The input pin for the initial values of the model parameters is connected to the host computer. The host computer inputs the initial values of the model parameters into the analog computer chip. The initial values of the model parameters enter the regulator in the chip, and the initial values of the model parameters initialize the parameters of the storage arithmetic unit through the regulator, so that each transfer function in the storage arithmetic unit is set according to each initial value of the model parameters.

[0087] Optionally, the initial values of the model parameters can be random values; or, the initial values of the model parameters can be manually set by R & D personnel according to the application scenario of the analog computer chip.

[0088] When the analog computer chip is in normal use, the input pin for the initial values of the model parameters is left floating or connected to a specific voltage value, so that the initial values of the model parameters do not participate in the normal operation of the analog computer chip.

[0089] Please refer to Figure 3 , which shows a schematic structural diagram of a storage arithmetic unit involved in an embodiment of the present application. As Figure 3 shown, in this storage arithmetic unit, the input end is connected to the output end through n layers of memories and n layers of arithmetic units; adjacent two layers of arithmetic units are connected through one layer of memory; the transfer function of the memory corresponds to the parameters of the memory.

[0090] Specifically, the first layer in this storage arithmetic unit is an input node (for example, including each input node such as input 1, input 2, input 3, etc.), and the last layer is an output node (for example, including each output node such as output 1, output 2, output 3, etc.). Taking the normal working process of the analog computer chip as an example, the input node is used to receive the model input value. At this time, after the model input value passes through several memories in the first layer, it reaches several arithmetic units in the first layer (for example, including arithmetic unit 11, arithmetic unit 12, arithmetic unit 13), and then after passing through several memories in the second layer, it reaches several arithmetic units in the second layer, and so on. After passing through n layers of memories and arithmetic units, the model output value is output through each output node.

[0091] In the embodiment of the present application, Figure 3 each memory in is used to fit different transfer functions, so that the storage arithmetic unit composed of multiple layers of memories and multiple layers of arithmetic units can represent the mapping relationship between specific input data and specific output data. Figure 3 Each arithmetic unit in is used to accumulate and then output the output voltages of each memory connected to it. Optionally, the arithmetic unit can be an adder composed of analog devices.

[0092] Figure 4 The specific structural diagram of the memory in the storage arithmetic unit involved in the embodiments of the present application is shown. As Figure 4 shown, VIN is the input voltage of the memory, the input voltage VIN is the independent variable x of the transfer function corresponding to the memory, VOUT is the output voltage of the memory, and this output voltage VOUT is input into the corresponding arithmetic unit of the same layer. The output voltage VOUT is used as the dependent variable y of the transfer function, VR is the first fixed voltage input to the memory, and the first fixed voltage VR is the constant c of the function. The memory is composed of an operational amplifier with a non-infinite gain, and the gain of the operational amplifier can be obtained through calculation or measurement. Thus, it can be known that when the resistance value of the first resistor R1 is equal to the resistance value of the fourth resistor R4, the resistance value of the second resistor R2 is equal to the resistance value of the third resistor R3, and when the gain of the first operational amplifier A1 is represented by A11, Figure 3 in the structure of the memory shown , that is, at this time, when is represented by W, the transfer function corresponding to this memory is ;

[0093] Furthermore, non-volatile memory cells are used as resistors, that is, the first resistor R1 and the fourth resistor R4, or the second resistor R2 and the third resistor R3 are both composed of non-volatile memory cells. At this time, the parameters of the memory are related to the floating gate charges of the MOS transistors in the non-volatile memory cells in the memory. By adjusting the stored data in the non-volatile memory cells (such as the floating gate charges of the MOS transistors in the non-volatile memory cells), the resistance value can be changed, thereby adjusting the parameters of the memory to obtain the transfer function required for this memory.

[0094] Therefore, when the initial values of the model parameters are input into the regulator, the regulator adjusts the floating gate charges of the MOS transistors in the non-volatile memory cells, thereby changing the corresponding resistance values, so that each memory can be respectively characterized by the transfer function corresponding to the initial values of the model parameters.

[0095] Step 102: According to the training data, iteratively update the parameters of the storage arithmetic unit through the regulator, and when the iteration completion condition is satisfied, generate the first arithmetic model corresponding to the storage arithmetic unit.

[0096] In the embodiments of the present application, the training data includes sample input values and expected output values.

[0097] Furthermore, the analog computer chip includes a model input value input pin and an expected output value input pin. The model input value input pin and the expected output value input pin are both connected to the host computer; during the parameter update process of the analog computer chip, the host computer inputs the sample input values through the model input value input pin, and the host computer inputs the expected output values through the expected output value input pin;

[0098] When the analog computer chip is in normal use, the input pin of the expected output value is left floating or connected to a specific voltage value, so that the expected output value does not participate in the normal operation of the analog computer chip; while the input pin of the model input value is used to access the input value during normal operation to process the input value during normal operation.

[0099] The following specifically describes the parameter update process of the analog computer chip:

[0100] The parameter update process of the analog computer chip mainly involves the iterative update of the parameters of the storage arithmetic unit. Specifically, the analog computer chip processes the sample input values in the training data through the storage arithmetic unit to obtain the actual output values; if the first error value between the actual output values and the expected output values in the training data does not meet the iteration completion condition (optionally, the iteration completion condition is that the first error value is less than the error threshold), then the parameters of the storage arithmetic unit are iteratively updated through the regulator according to the actual output values and the expected output values in the training data.

[0101] That is, during the iterative update process of the storage arithmetic unit, the analog computer chip will judge whether the current iteration meets the iteration completion condition. If the first error value is less than the preset error threshold, it means that the iteration completion condition is met. At this time, the storage arithmetic unit with updated parameters can be implemented as the first arithmetic model. If the first error value is greater than or equal to the error threshold, the parameters of the storage arithmetic unit still need to be iteratively updated.

[0102] Specifically, a first error comparison circuit is provided in the regulator, and the first error comparison circuit calculates the first error value between the actual output value and the expected output value.

[0103] When the number of the actual output values is greater than 1; the mean value of the errors between each actual output value and the corresponding expected output value is determined as the first error value.

[0104] Please refer to Figure 5 , which shows a schematic structural diagram of the first error comparison circuit involved in the embodiments of the present application. As Figure 5 shown, the first error comparison circuit includes a plurality of comparison sub-circuits, and a comparison resistor corresponding to each comparison sub-circuit (for example, including a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7). The output end of each comparison sub-circuit is connected to the non-inverting input end of the second operational amplifier A2 through the corresponding comparison resistor; the second operational amplifier A2 constitutes a follower structure; the output end of the second operational amplifier A2 is connected to the non-inverting input end of the third operational amplifier A3; and the inverting input end of the third operational amplifier is connected to the error threshold voltage VPD.

[0105] Further, the number of comparison sub - circuits is the same as the number of output nodes of the storage arithmetic unit; the first input ends of the respective comparison sub - circuits are respectively connected to the actual output values of the output nodes of the storage arithmetic unit;

[0106] The expected output value input ends of the analog computer chip respectively transmit expected output values to the second input ends of the respective comparison sub - circuits of the first error comparator, and each expected output value corresponds one - to - one with the actual output value.

[0107] Please refer to Figure 6 , which shows a specific structural schematic diagram of a comparison sub - circuit involved in an embodiment of the present application. As Figure 6 shown, for a comparison sub - circuit, the non - inverting input end of the fourth operational amplifier is the second input end of the comparison sub - circuit, which is used to connect the expected output value; the inverting input end of the fourth operational amplifier is the first input end of the comparison sub - circuit, which is used to connect the actual output value; the output end of the fourth operational amplifier is connected to the first end of the first switch S1; the output end of the fourth operational amplifier is also connected to the second end of the second switch S2 through the first inverter F1; and the output end of the fourth operational amplifier is also connected to the non - inverting input end of the fifth operational amplifier; the inverting input end of the fifth operational amplifier is grounded; the output end of the fifth operational amplifier is used to control the working state of the first switch S1.

[0108] Specifically, the output value of the fourth operational amplifier A4 is the difference between the expected output value and the actual output value. When the difference is greater than or equal to 0, the fifth operational amplifier A5 outputs a high level, the first switch S1 is directly connected to the output end of the fourth operational amplifier A4, and the comparison sub - circuit outputs the difference. When the difference is less than 0, the fifth operational amplifier A5 outputs a low level, the first switch S1 is connected to the output end of the fourth operational amplifier A4 through the first inverter F1, and the comparison sub - circuit outputs the opposite value of the difference. Therefore, the output value of the comparison sub - circuit is the error between the expected output value and the actual output value. At the same time, the error output by the comparison sub - circuit is always a positive voltage value, thus ensuring the correctness of the subsequent logic.

[0109] At this time, the output values (such as VP1, VP2... VPi) of the respective comparison sub - circuits obtain the error average value VPS (i.e., the voltage value corresponding to the first error value) between each expected output value and its corresponding actual output value through the first error comparison circuit, and the error average value VPS is a positive voltage value. At this time, the error average value VPS is compared with the error threshold voltage VPD (i.e., the voltage value corresponding to the error threshold). When the error average value VPS is less than the error threshold voltage VPD, the third operational amplifier A3 outputs a low level, and the regulator stops working. When the error average value VPS is greater than or equal to the error threshold voltage VPD, the third operational amplifier A3 outputs a high level, and the regulator continues to work.

[0110] When the regulator continues to work, that is, when iteratively updating the parameters of the storage arithmetic unit according to the actual output value and the expected output value in the training data, for each memory in the nth layer, the regulator can adjust the parameters of each memory in the nth layer of the storage arithmetic unit according to the actual output value and the expected output value in the training data;

[0111] Specifically, assuming that the expected output values in the training data are respectively , , …… , and the actual output values of the arithmetic unit in the nth layer (that is, the actual output values of each output node) are respectively , …… , then the error EL between the expected output value and the actual output value can be expressed as: ; At this time, from the specific structure of the memory of the present application, the actual output value of the a-th arithmetic unit in the nth layer can be obtained. Thus, the error can be obtained. At this time, taking the parameter of the first memory in the nth layer as an example to illustrate the following calculation method. Specifically, substitute the initial values of other parameters except into the error EL, and take the derivative of in the obtained error EL formula. Then, substitute the parameter initial value of into the formula after taking the derivative, and finally obtain the derivative value corresponding to . Similarly, the derivative values corresponding to other W parameters are obtained in turn. At the same time, in order to balance the training speed and training accuracy, a correction coefficient also needs to be set. This correction coefficient is a constant. Therefore, at this time, the correction value corresponding to the parameter of the first memory in the nth layer can be obtained;

[0112] From the above analysis, substitute the initial values of other parameters except into the error EL, and after taking the derivative of in the obtained error EL formula, can be obtained, where i is a known fixed value when designing the circuit, is the input of the first memory in the nth layer corresponding to the parameter, is the value of the first fixed voltage VR, is the expected output value of the arithmetic unit corresponding to the first memory in the nth layer in the nth layer, is the sum of the outputs of other memories connected to the corresponding arithmetic units in the n-th layer except for the first memory in the n-th layer. is the parameter initial value of the first memory in the n-th layer; thus, the correction value can be obtained. ;

[0113] As Figure 7 shown, it shows a parameter initial value extraction circuit involved in an embodiment of the present application. In an analog computer chip, each memory corresponds to a parameter initial value extraction circuit. Among them, the sixth operational amplifier A6 in the parameter initial value extraction circuit has the same parameters as the first operational amplifier A1 in the memory, and the gains are both A11. The non-inverting input terminal of the sixth operational amplifier A6 is connected to the second fixed voltage VR1 through the second resistor R2; the non-inverting input terminal of the sixth operational amplifier A6 is grounded through the first resistor R1; the inverting input terminal of the sixth operational amplifier A6 is connected to the first fixed voltage VR through the third resistor R3; the inverting input terminal of the sixth operational amplifier A6 is connected to the output terminal of the sixth operational amplifier A6 through the fourth resistor R4. The resistor parameters, resistor settings in the parameter initial value extraction circuit and the memory, and the parameters of the first fixed voltage VR are also the same. And the second fixed voltage VR1 of the parameter initial value extraction circuit is VR + 1. Therefore, at this time, the voltage value output at the output terminal of the parameter initial value extraction circuit can be obtained. It can be seen that the voltage value VW output at the output terminal of the parameter initial value extraction circuit is the voltage value corresponding to the parameter initial value W of the memory.

[0114] Therefore, a correction value generation circuit (the correction value generation circuit can be specifically set according to the formula of the correction value ) and a parameter initial value extraction circuit are set in the regulator. The correction value generation circuit obtains the correction value of the transfer function according to the actual output value and the expected output value. The parameter initial value extraction circuit extracts the parameter initial value of the transfer function. At this time, the regulator subtracts the correction value from the parameter initial value through a subtraction circuit to obtain a parameter update value, and the regulator adjusts the floating gate charge of the MOS transistor of the corresponding non-volatile storage unit according to the parameter update value, so as to adjust the parameters of the first memory in the n-th layer of the storage arithmetic unit.

[0115] After that, using the same circuit and method, the parameters of each memory in the n-th layer of the storage arithmetic unit can be adjusted by the regulator.

[0116] Moreover, the regulator will also obtain the operation update values of each arithmetic unit in the (n - 1)-th layer corresponding to the updated parameters of each memory in the n-th layer and the expected output value in the training data, and use the operation update value as the expected output value of the arithmetic unit in the (n - 1)-th layer.

[0117] Specifically, each arithmetic unit in the (n - 1)-th layer corresponds to m memories (where the number of m is the same as the number of arithmetic units in the n-th layer). All the operation update values calculated by the m memories need to be added up and then divided by m, and the obtained average value is the operation update value of each arithmetic unit in the corresponding (n - 1)-th layer;

[0118] For example, as Figure 3 shown, assuming that the number of arithmetic units in each layer is 3 and there are 2 layers of arithmetic units. After the memory update parameters in the second layer, the expected output value of arithmetic unit 21 is . At this time, the and values that have not been updated by the operation are substituted into the above formula to obtain the first operation update value of arithmetic unit 11 in the first layer. Similarly, according to the expected output values of arithmetic units 22 and 23, the second operation update value and the third operation update value of arithmetic unit 11 in the first layer are obtained. Finally, it can be obtained that the operation update value of arithmetic unit 11 in the first layer; then, the operation update value of arithmetic unit 12 in the first layer and the operation update value of arithmetic unit 13 in the first layer are obtained by the same method. And, and are respectively used as the expected output values of arithmetic units 11, 12, and 13 in the first layer;

[0119] It can be seen from this that the calculation method of the expected input voltage of the memory between arithmetic unit 11 and arithmetic unit 21 (that is, the voltage value corresponding to the first operation update value of arithmetic unit 11 in the first layer) is as follows: First, subtract the output value of the memory after the update parameters between arithmetic unit 12 and arithmetic unit 21 from the expected output value of arithmetic unit 21, and then subtract the output value of the memory after the update parameters between arithmetic unit 13 and arithmetic unit 21, so as to obtain the output value of the memory after the update parameters between arithmetic unit 11 and arithmetic unit 21. Then, according to the formula , the first operation update value of arithmetic unit 11 in the first layer is , where is the parameter after the update of the memory between arithmetic unit 11 and arithmetic unit 21, and y is the output value of the memory after the update parameters between arithmetic unit 11 and arithmetic unit 21; Therefore, according to this method, the operation update value generation circuit in the present application can be obtained. As Figure 8 shown, it includes a divider A9;

[0120] As Figure 8 shown, and etc. are the output voltages after updating the parameters of other memories connected to the nth-layer target arithmetic unit in the nth-layer memory, excluding the nth-layer target memory. At this time, as Figure 8 shown, the operation update value generation circuit is used to obtain the operation update value corresponding to the nth-layer target arithmetic unit.

[0121] Similarly, taking Figure 3 as an example, assume that the target arithmetic unit is the arithmetic unit 21 in Figure 3 , and the target memory is the memory between the arithmetic unit 11 and the arithmetic unit 21. is the parameter after updating the target memory corresponding voltage value. Among them, the parameter after updating the target memory corresponding voltage value The acquisition circuit of refers to the circuit structure of the parameter initial value extraction circuit. The output voltage VY1 of the tenth operational amplifier A10 is the first operation update value of the first-layer arithmetic unit 11 corresponding voltage value;

[0122] Similarly, by using the same operation update value generation circuit, the second operation update value of the first-layer arithmetic unit 11 can be obtained corresponding voltage value and the third operation update value of the first-layer arithmetic unit 11 corresponding voltage value;

[0123] Therefore, at this time, m operation update value generation circuits and an addition averaging circuit together constitute an expected output value generation circuit for the (n - 1)th layer. Among them, the voltage values obtained by the m operation update value generation circuits are input into the addition averaging circuit, and the addition averaging circuit can obtain the operation update value of an arithmetic unit in the (n - 1)th layer. For example, the voltage value corresponding to the first operation update value of the arithmetic unit 11 , the voltage value corresponding to the second operation update value of the arithmetic unit 11 , and the voltage value corresponding to the third operation update value of the arithmetic unit 11 are input into the addition averaging circuit, and the operation update value of the arithmetic unit 11 ; this operation update value can be used as the expected output value of the arithmetic unit 11;

[0124] It can be seen from this that after setting the same number of expected output value generation circuits as the (n - 1)th layer arithmetic units, the expected output values of each arithmetic unit in the (n - 1)th layer can be obtained; among them, the number of operation update value generation circuits included in each expected output value generation circuit is the same as the number of (n)th layer arithmetic units;

[0125] Similarly, according to the actual output values and expected output values of each arithmetic unit in the (q - 1)-th layer, the parameters of each memory in the (q - 1)-th layer of the storage arithmetic unit are adjusted by a regulator;

[0126] According to each memory in the (q - 1)-th layer with updated parameters and the expected output values of each arithmetic unit in the (q - 1)-th layer, the arithmetic update values of each arithmetic unit in the (q - 2)-th layer are obtained through the regulator, and the arithmetic update values are used as the expected output values of the arithmetic units in the (q - 2)-th layer, where n ≥ q ≥ 3.

[0127] Similarly, for the parameter update process of the first-layer memory, the analog computer chip can still adjust the parameters of each memory in the first layer of the storage arithmetic unit according to the actual output values and expected output values of the first-layer arithmetic units through the regulator.

[0128] The logic of the above adjustment process of the memory parameters and the process of obtaining the expected output values of each arithmetic unit is similar, and will not be elaborated here.

[0129] When the regulator adjusts the parameters of each memory in the first layer of the storage arithmetic unit according to the actual output values and expected output values of the first-layer arithmetic units, it can be considered that the storage arithmetic unit has completed a self-learning update process of the arithmetic model, that is, completed an iteration process.

[0130] At this time, after the analog computer chip completes an iteration process, it will continue to use the sample input values and expected output values that have not been used in the training data for model training until the first error value between the actual output value and the expected output value of the n-th layer arithmetic unit is less than the preset error threshold, and a first arithmetic model is generated.

[0131] Step 103: Input the model input value corresponding to the first target scenario into the analog computer chip, and output the model output value corresponding to the first target scenario through the first arithmetic model in the analog computer chip.

[0132] After the first arithmetic model is generated, it can be considered that the analog computer chip has met the conditions for entering the normal working state at this time. At this time, if the model input value that conforms to the application scenario (that is, the model input value corresponding to the first target scenario) is directly input into the analog computer chip, the first arithmetic model in the analog computer chip can perform arithmetic operations on the model input value corresponding to the first target scenario, so as to output the model output value corresponding to the first target scenario.

[0133] Furthermore, when the actual output value has a large deviation in the current application scenario, the host computer can input the expected output value corresponding to the model input value into the analog computer chip through the expected output value input pin, and at the same time input a model adjustment level signal;

[0134] Correspondingly, when the analog computer chip receives the expected output value corresponding to the model input value and the model adjustment level signal through the expected output value input pin, the first arithmetic model is adjusted by the regulator according to the actual output value corresponding to the model input value, the expected output value corresponding to the model input value, and the received model adjustment level signal, to obtain a second arithmetic model.

[0135] When the actual output value has a large deviation in the current application scenario, the regulator adjusts the parameters of each memory in each layer of the storage arithmetic unit according to the actual output value and the expected output value input by the host computer, so as to self-learn and update to obtain a second arithmetic model.

[0136] Specifically, when receiving the model adjustment level signal and updating the target memory, obtain the memory parameter value of the target memory, and according to the actual output value corresponding to the model input value and the expected output value corresponding to the model input value, obtain the parameter update value of the target memory;

[0137] If the difference between the memory parameter value and the parameter update value is greater than the update threshold, the parameters of the target memory are updated by the regulator.

[0138] Specifically, the regulator further includes Figure 9 The model adjustment circuit shown. The steps to obtain the second arithmetic model are basically the same as the steps to obtain the first arithmetic model. However, the difference between the two is that when obtaining the second arithmetic model, the host computer also inputs a model adjustment level signal into the analog computer chip through the expected output value input pin. The model adjustment level signal is input to the control end of the second switch S2 of the model adjustment circuit, and the second switch S2 is turned on, and Figure 9 VW in is the memory parameter value of the target memory, and is the parameter update value of the target memory. When the difference between the memory parameter value and the parameter update value is greater than the update threshold VT, the output voltage VL of the model adjustment circuit is at a high level. At this time, the regulator updates the parameters of the target memory. If the difference between the memory parameter value and the parameter update value is less than the update threshold VT, the regulator does not update the parameters of the target memory, and the target memory still retains the initial parameters.

[0139] As can be seen from the above analysis, when the model adjustment circuit is set in the regulator, when generating the first operation model, the second switch S2 is in the off state, and the model adjustment circuit does not affect the generation of the first operation model; when generating the second operation model, the second switch S2 is in the on state, and the model adjustment circuit starts to work. At this time, if the difference between the parameter update value and its corresponding memory parameter value is small, it indicates that the memory parameter value of the target memory is within the acceptable error range. When the difference between the parameter update value and its corresponding memory parameter value is large, it indicates that the memory parameter value of the target memory is outside the error range and needs to be adjusted. Thus, when generating the second operation model, the first operation model is modified as little as possible because the first operation model is trained by several data, and the entire first operation model cannot be adjusted extensively due to only one current model input value, thereby improving the stability and reliability of the operation model.

[0140] When applying this analog computer chip to other application scenarios, according to the new application scenario of the analog computer chip, the expected output value and the initial model parameter value suitable for this application scenario are input through the expected output value input pin and the initial model parameter value input pin, and according to the above training steps, a third operation model is re-trained or further trained.

[0141] Specifically, when the analog computer chip is applied to the second target scenario and the similarity between the second target scenario and the first target scenario is small (for example, less than the similarity threshold), then the first training set and the first initial parameter value are obtained; the first training set is the training data corresponding to the second target scenario; the first initial parameter value is the initial model parameter value corresponding to the second target scenario;

[0142] Initialize the parameters of the storage arithmetic unit according to the first initial parameter value;

[0143] According to the first training set, iterate and update the parameters of the storage arithmetic unit, and when the iteration completion condition is met, generate the third operation model corresponding to the storage arithmetic unit;

[0144] Then, the model input value corresponding to the second target scenario can be input into the analog computer chip, and the model output value corresponding to the second target scenario is output through the third operation model in the analog computer chip.

[0145] Among them, the initialization process and the iterative update process of the storage arithmetic unit are similar to the generation process of the first operation model, which will not be elaborated here.

[0146] Through the above solution, when the analog computer chip needs to be applied to a second target scenario with a large difference from the first target scenario, a third operation model can be re-trained.

[0147] Specifically, when the analog computer chip is applied to the third target scenario and the similarity between the third target scenario and the first target scenario is relatively large (for example, greater than or equal to the similarity threshold), the second training set is obtained; the second training set is the training data corresponding to the third target scenario.

[0148] According to the second training set, the parameters of the storage arithmetic unit in the first arithmetic model are iteratively updated, and when the iteration completion condition is satisfied, the fourth arithmetic model corresponding to the storage arithmetic unit is generated.

[0149] At this time, the model input value corresponding to the third target scenario is input into the analog computer chip, and the model output value corresponding to the third target scenario can be output through the fourth arithmetic model in the analog computer chip.

[0150] Among them, the iterative update process of the storage arithmetic unit is similar to that of the second arithmetic model, which will not be elaborated here.

[0151] Through the above solution, when the analog computer chip needs to be applied to a scenario that is similar to the first target scenario but different (such as the third target scenario), on the basis of the first arithmetic model, the fourth arithmetic model can be directly obtained through the second training set of the third target scenario, and the fourth arithmetic model can be directly applied to the data processing of the third target scenario.

[0152] In summary, in the working method of the analog computer chip provided in this application, the first arithmetic model is generated by the chip's independent training. Since the internal circuits (regulator and storage arithmetic unit) of the analog computer chip in this application are all composed of analog devices, the training using analog devices inside the chip in this application is faster and consumes less energy compared to the training using digital arithmetic units such as graphics cards in the host computer. Therefore, this method is applicable to small-batch personalized customized analog computer chips; when the analog computer chip has an arithmetic error or changes the application scenario and needs to adjust the first arithmetic model, the second arithmetic model, the third arithmetic model, and the fourth arithmetic model are all obtained by training with analog devices inside the chip, thereby accelerating the speed of model adjustment and reducing the energy consumption of model adjustment.

[0153] Figure 10 Another working method of the analog computer chip according to an embodiment of the present application is shown. A storage arithmetic unit and a regulator are provided in the analog computer chip; the topological structure of the storage arithmetic unit is the same as that of the target neural network model. Some steps in this method are executed by a computer device. For example, the target neural network model can be generated in this computer device, and the analog computer chip can also have a network architecture as Figure 2 shown. Figure 10 The corresponding working method of the analog computer chip includes:

[0154] Step 1001: Obtain training data and initial model parameters; the initial model parameters are used to initialize the target neural network model.

[0155] Specifically, in the embodiments of the present application, the computer device first obtains the training data and initial model parameters required by the target neural network model. The initial model parameters are used to initialize the target neural network model, and the training data is used to train the initialized target neural network model.

[0156] Step 1002: Train the target neural network model with the training data.

[0157] In the embodiments of the present application, the computer device can directly input the sample input value in the training data into the target neural network model, and then compare the actual output value of the target neural network model with the expected output value in the training data to obtain a first error value between the actual output value and the expected output value in the training data. When the first error value is less than the error threshold, the training is completed; if the first error value is greater than or equal to the error threshold, the target neural network model is updated according to the first error value.

[0158] Step 1003: Set the parameters of each memory in the storage arithmetic unit according to the trained target neural network model to obtain a first arithmetic model in the analog computer chip.

[0159] Optionally, after the target neural network model is trained, the model parameters of the target neural network model can be input into the regulator of the analog computer chip through the initial value input pin of the model parameters of the analog computer chip, so that the regulator adjusts the parameters of the corresponding memories according to the model parameters of the target neural network model, thereby obtaining a first arithmetic model in the analog computer chip.

[0160] Optionally, in the embodiments of the present application, the parameters of the memory are related to the floating gate charges of the MOS transistors in the non-volatile memory cells in the memory. Therefore, the regulator can adjust the floating gate charges of the MOS transistors in the corresponding non-volatile memory cells according to each parameter, thereby adjusting the parameters of each memory in each layer of the storage arithmetic unit.

[0161] Step 1004: Input the model input value corresponding to the first target scenario into the analog computer chip, and obtain the model output value corresponding to the first target scenario output by the analog computer chip through the first arithmetic model.

[0162] Furthermore, when an expected output value corresponding to the model input value and a model adjustment level signal are received through the expected output value input pin, the first operation model is adjusted according to the actual output value corresponding to the model input value, the expected output value corresponding to the model input value and the received model adjustment level signal to obtain a second operation model.

[0163] Optionally, when the model adjustment level signal is received and the target memory is updated, the memory parameter value of the target memory is obtained, and the parameter update value of the target memory is obtained based on the actual output value corresponding to the model input value and the expected output value corresponding to the model input value.

[0164] and Figure 1 The corresponding embodiments are similar. When the actual output value deviates greatly in the current application scenario, the upper computer can input the expected output value corresponding to the model input value into the analog computer chip through the expected output value input pin, and input the model adjustment level signal at the same time, so as to adjust the parameters of each memory in each layer of the storage operator, so that the first operation model can be self-learned and updated to the second operation model.

[0165] Likewise with Figure 1 The corresponding embodiment is similar. During the self-learning update process of the first operation model, when the difference between the memory parameter value and the parameter update value is less than or equal to the update threshold, the parameter of the target memory is within an acceptable error range and is not updated as much as possible. If the difference between the memory parameter value and the parameter update value is greater than the update threshold, the parameter of the target memory is outside the error range and needs to be adjusted.

[0166] When the analog computer chip is applied to other application scenarios, the expected output value and the model parameter initial value suitable for the application scenario are input through the expected output value input pin and the model parameter initial value input pin according to the new application scenario of the analog computer chip. Figure 1 The training step of the corresponding embodiment retrains or further trains to obtain the third operation model or the fourth operation model.

[0167] and Figure 1 The corresponding embodiments are similar. Specifically, when the simulated computer chip is applied to the second target scene, and the similarity between the second target scene and the first target scene is small (for example, less than a similarity threshold), a first training set and a first parameter initial value are obtained; the first training set is training data corresponding to the second target scene; the first parameter initial value is a model parameter initial value corresponding to the second target scene;

[0168] Initialize the parameters of the storage operator in the first operation model according to the initial values ​​of the model parameters;

[0169] Based on this first training set, the parameters of the storage arithmetic unit are iteratively updated, and when the iteration completion condition is met, a third arithmetic model is generated;

[0170] At this time, the model input values corresponding to the second target scenario are input into the analog computer chip, and the model output values corresponding to the second target scenario can be output through the third arithmetic model in the analog computer chip.

[0171] Through the above solution, when the analog computer chip needs to be applied to a second target scenario with a large difference from the first target scenario, the third arithmetic model can be directly obtained through retraining by the analog devices inside the analog computer chip.

[0172] Specifically, when the analog computer chip is applied to a third target scenario and the similarity between the third target scenario and the first target scenario is large (for example, greater than or equal to the similarity threshold), the second training set is obtained; the second training set is the training data corresponding to the third target scenario;

[0173] Based on this second training set, the parameters of the storage arithmetic unit in the first arithmetic model are iteratively updated, and when the iteration completion condition is met, a fourth arithmetic model is generated;

[0174] At this time, the model input values corresponding to the third target scenario are input into the analog computer chip, and the model output values corresponding to the third target scenario are output through the fourth arithmetic model in the analog computer chip.

[0175] Among them, the iterative update process of the storage arithmetic unit is similar to that of the first arithmetic model and will not be elaborated here. Through the above solution, when the analog computer chip needs to be applied to a scenario that is similar to the first target scenario but different, on the basis of the first arithmetic model, through the second training set of the third target scenario, direct training can be carried out in the analog devices inside the analog computer chip to obtain the fourth arithmetic model, and the fourth arithmetic model can be directly applied to the data processing of the third target scenario.

[0176] In summary, the working method of the analog computer chip provided in this application inputs the expected output value and the initial value of the model parameters suitable for the application scenario of the analog computer chip into the host computer according to the application scenario of the analog computer chip, trains the target neural network model, and then sets the parameters of each memory in the storage arithmetic unit according to the trained target neural network model, so as to generate the first arithmetic model in the analog computer chip. At this time, the analog computer chip can be directly used in actual normal work without prior training. This method is applicable to analog computer chips for mass production and with known initial application scenarios. When the analog computer chip has an arithmetic error or changes the application scenario and needs to adjust the first arithmetic model, the second arithmetic model, the third arithmetic model, and the fourth arithmetic model are all trained using analog devices inside the chip, so as to speed up the model adjustment speed and reduce the energy consumption of model adjustment.

[0177] Please refer to Figure 11 , Figure 11 which is a schematic structural diagram of a computer device provided by an optional embodiment of the present invention. This computer device can be used to execute the training steps of the artificial intelligence model involved in the above embodiments. As Figure 11 shown, the computer device includes: one or more processing units 10, a storage unit 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Each component communicates with each other using different buses and can be installed on a common motherboard or installed in other ways as needed. The processing unit can process instructions executed within the computer device, including instructions stored in the storage unit or on the storage unit to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processing units and / or multiple buses can be used together with multiple storage units and multiple storage units. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a set of blade servers, or a multi-processing unit system). Figure 9 In

[0178] Figure

[0179] The storage unit 20 stores instructions executable by at least one processing unit 10, so that the at least one processing unit 10 executes the method shown in the above embodiments.

[0180] The storage unit 20 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the computer device and the like. In addition, the storage unit 20 may include a high-speed random access storage unit, and may also include a non-transitory storage unit, such as at least one disk storage unit component, a flash memory device, or other non-transitory solid-state storage unit components. In some alternative embodiments, the storage unit 20 optionally includes a storage unit remotely provided relative to the processing unit 10, and these remote storage units can be connected to the computer device through a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0181] The storage unit 20 may include a volatile storage unit, for example, a random access storage unit; the storage unit may also include a non-volatile storage unit, for example, a flash storage unit, a hard disk, or a solid-state drive; the storage unit 20 may further include a combination of the above types of storage units.

[0182] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or be implemented as computer code that can be recorded on a storage medium, or be implemented as computer code originally stored in a remote storage medium or a non-transitory machine-readable storage medium and to be downloaded through a network and stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processing unit, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash storage unit, a hard disk, or a solid-state drive, etc.; further, the storage medium can also include a combination of the above types of storage units. It can be understood that a computer, a processing unit, a microprocessing unit controller, or programmable hardware includes a storage component that can store or receive software or computer code, and when the software or computer code is accessed and executed by the computer, the processing unit, or the hardware, the method shown in the above embodiment is implemented.

[0183] A part of the present invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the present invention through the operations of the computer. Those skilled in the art should understand that the forms of existence of computer program instructions in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways for computer program instructions to be executed by a computer include, but are not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Herein, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to the computer.

[0184] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for simulating the operation of a computer chip, characterized in that: The method is performed by an analog computer chip, wherein a storage operator and a regulator are provided in the analog computer chip; the storage operator and the regulator are both composed of analog devices; the topological structure of the storage operator is the same as the topological structure of the target neural network model, and the method comprises: Receiving training data and initial values ​​of model parameters; the initial values ​​of model parameters are used to initialize parameters of the storage operator; Iteratively updating the parameters of the storage operator through the regulator according to the training data, and generating a first operation model corresponding to the storage operator when an iteration completion condition is met; Inputting a model input value corresponding to a first target scenario into the simulation computer chip, and outputting a model output value corresponding to the first target scenario through a first computing model in the simulation computer chip; In the storage operator, the input end is connected to the output end through n layers of memory and n layers of operators; two adjacent layers of operators are connected through a layer of memory; the transfer function of the memory corresponds to the parameters of the memory; the storage operator is used to characterize the mapping relationship between specific input data and specific output data.

2. The method according to claim 1, characterized in that The iterative updating of the parameters of the storage operator by the regulator according to the training data comprises: Processing the sample input values ​​in the training data by the storage operator to obtain actual output values; If the first error value between the actual output value and the expected output value in the training data does not satisfy the iteration completion condition, the parameters of the storage operator are iteratively updated through the regulator according to the actual output value and the expected output value in the training data.

3. The method according to claim 2, characterized in that The iteration completion condition is that the first error value is less than an error threshold.

4. The method according to claim 3, characterized in that When the number of the actual output values ​​is greater than 1; The method further comprises: Obtain the error between each actual output value and the corresponding expected output value; The average of the errors between the actual output values ​​and the corresponding expected output values ​​is determined as the first error value.

5. The method according to claim 3, characterized in that: The iterative updating of the parameters of the storage operator by a regulator according to the actual output value and the expected output value in the training data comprises: According to the actual output value and the expected output value in the training data, the parameters of each memory in the nth layer of the storage operator are adjusted by the regulator; According to the expected output values ​​in the memories and training data of the nth layer after the parameters are updated, the corresponding operation update values ​​of the operators in the n-1th layer are obtained through the regulator, and the operation update values ​​are used as the expected output values ​​of the operators in the n-1th layer; According to the actual output value and expected output value of each operator in the q-1th layer, the parameters of each memory in the q-1th layer of the storage operator are adjusted by the regulator; According to the various memories of the q-1th layer and the various expected output values ​​of the q-1th layer after the updated parameters, the corresponding operation update values ​​of the operators in the q-2th layer are obtained through the regulator, and the operation update values ​​are used as the expected output values ​​of the operators in the q-2th layer, where n≥q≥3.

6. The method according to claim 5, characterized in that The method further comprises: According to the actual output value and expected output value of the first layer operator, the parameters of each memory of the first layer in the storage operator are adjusted by the regulator.

7. The method according to claim 5, characterized in that The parameters of the memory are related to the floating gate charge of the MOS tube of the non-volatile memory unit in the memory.

8. The method according to any one of claims 1 to 7, characterized in that: The method further comprises: When an expected output value corresponding to the model input value and a model adjustment level signal are received through the expected output value input pin, the first operation model is adjusted according to the actual output value corresponding to the model input value, the expected output value corresponding to the model input value and the received model adjustment level signal to obtain a second operation model.

9. The method according to claim 8, characterized in that The step of adjusting the first operation model according to the actual output value corresponding to the model input value, the expected output value corresponding to the model input value, and the received model adjustment level signal to obtain the second operation model includes: When the model adjustment level signal is received and the target memory is updated, a memory parameter value of the target memory is obtained, and a parameter update value of the target memory is obtained according to an actual output value corresponding to the model input value and an expected output value corresponding to the model input value; If the difference between the memory parameter value and the parameter update value is greater than an update threshold, the parameter of the target memory is updated by the regulator.

10. The method according to claim 1, characterized in that The method further comprises: When the simulation computer chip is applied to a second target scene, the simulation computer chip obtains a first training set and a first parameter initial value; the first training set is training data corresponding to the second target scene; the first parameter initial value is a model parameter initial value corresponding to the second target scene; Initialize the parameters of the storage operator according to the first parameter initial value; Iteratively updating the parameters of the storage operator according to the first training set, and generating a third operation model corresponding to the storage operator when an iteration completion condition is met; The model input value corresponding to the second target scene is input into the simulation computer chip, and the model output value corresponding to the second target scene is output through the third computing model in the simulation computer chip.

11. The method according to claim 1, characterized in that: The method further comprises: When the simulation computer chip is applied to a third target scene, the simulation computer chip obtains a second training set; the second training set is training data corresponding to the third target scene; Iteratively updating the parameters of the storage operator in the first operation model according to the second training set, and generating a fourth operation model when an iteration completion condition is met; The model input value corresponding to the third target scene is input into the simulation computer chip, and the model output value corresponding to the third target scene is output through the fourth computing model in the simulation computer chip.

12. A method for simulating the operation of a computer chip, characterized in that: The analog computer chip is provided with a storage operator and a regulator; the storage operator and the regulator are both composed of analog devices; the topological structure of the storage operator is the same as the topological structure of the target neural network model; The target neural network model is generated in a computer device; the method comprises: Acquire training data and initial values ​​of model parameters; the initial values ​​of model parameters are used to initialize the target neural network model; Training the target neural network model using the training data; The parameters of each memory in the storage operator are set according to the trained target neural network model to obtain a first operation model in the simulated computer chip; in the storage operator, the input end is connected to the output end through n layers of memory and n layers of operators; two adjacent layers of operators are connected through a layer of memory; the transfer function of the memory corresponds to the parameter of the memory; the storage operator is used to characterize the mapping relationship between specific input data and specific output data; Inputting a model input value corresponding to a first target scenario into the simulation computer chip, and obtaining a model output value corresponding to the first target scenario output by the simulation computer chip through the first computing model; When the simulated computer chip is applied to the third target scene, the simulated computer chip obtains a second training set; the second training set is training data corresponding to the third target scene; Iteratively updating the parameters of the storage operator in the first operation model according to the second training set, and generating a fourth operation model when an iteration completion condition is met; The model input value corresponding to the third target scene is input into the simulation computer chip, and the model output value corresponding to the third target scene is output through the fourth computing model in the simulation computer chip.

13. The method according to claim 12, characterized in that The method of setting the parameters of each memory in the storage operator according to the trained target neural network model to obtain a first operation model in the simulated computer chip includes: The model parameters of the target neural network model are input into the regulator of the analog computer chip through the model parameter initial value input pin of the analog computer chip, so that the regulator adjusts the parameters of the corresponding memories according to the model parameters of the target neural network model.

14. The method according to claim 13, characterized in that The parameters of the memory are related to the floating gate charge of the MOS tube of the non-volatile memory unit in the memory.

15. The method according to any one of claims 12 to 14, characterized in that: The method further comprises: When an expected output value corresponding to the model input value and a model adjustment level signal are received through the expected output value input pin, the first operation model is adjusted according to the actual output value corresponding to the model input value, the expected output value corresponding to the model input value and the received model adjustment level signal to obtain a second operation model.

16. The method according to claim 15, characterized in that The step of adjusting the first operation model according to the actual output value corresponding to the model input value, the expected output value corresponding to the model input value, and the received model adjustment level signal to obtain the second operation model includes: When the model adjustment level signal is received and the target memory is updated, a memory parameter value of the target memory is obtained, and a parameter update value of the target memory is obtained according to an actual output value corresponding to the model input value and an expected output value corresponding to the model input value; If the difference between the memory parameter value and the parameter update value is greater than an update threshold, the parameter of the target memory is updated by the regulator in the analog computer chip.

17. The method according to any one of claims 12 to 14, characterized in that: The method further comprises: When the simulation computer chip is applied to a second target scene, the simulation computer chip obtains a first training set and a first parameter initial value; the first training set is training data corresponding to the second target scene; the first parameter initial value is a model parameter initial value corresponding to the second target scene; Initialize the parameters of the storage operator according to the first parameter initial value; Iteratively updating the parameters of the storage operator according to the first training set, and generating a third operation model corresponding to the storage operator when an iteration completion condition is met; The model input value corresponding to the second target scene is input into the simulation computer chip, and the model output value corresponding to the second target scene is output through the third computing model in the simulation computer chip.

18. An analog computer chip, characterized in that: The analog computer chip is provided with a storage operator and a regulator; the analog computer chip is used to execute the working method of the analog computer chip as described in any one of claims 1 to 11.

19. A computer device, characterized in that: The computer device is provided with a processing unit and a storage unit, the storage unit stores computer instructions, and the processing unit is used to execute the computer instructions to perform the working method of simulating a computer chip as claimed in any one of claims 12 to 17.

Images