Model generation method for simulating computer chip

Abstract

The invention relates to the technical field of artificial intelligence, and discloses a model generation method for simulating a computer chip. The method comprises the following steps: acquiring a training data set; iteratively updating the neural network model according to the training data set until an iteration condition is met, so as to obtain a target parameter value of each transfer function in the neural network model; wherein the neural network model comprises n layers of operation nodes, and any operation node in each layer of operation nodes is connected with each node in the upper layer of nodes through different transfer functions; the target parameter values of the transfer functions among the operation nodes are used for correspondingly setting parameters of operation units among the adders in the model for simulating the computer chip, so that the model for simulating the computer chip is generated; the topological structure of the model for simulating the computer chip is the same as that of the neural network model. According to the scheme, the analog computer chip has higher computing power and higher computing speed when the size is the same.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence technology, and in particular to a model generation method for simulating computer chips. Background Art

[0002] With the rise of artificial intelligence technology, artificial intelligence chips that can realize certain specific functions have received widespread attention and application.

[0003] However, artificial intelligence chips in the prior art are generally digital computer chips, which are generally composed of a graphics processor, a field programmable gate array and other module circuits. Therefore, the computing units of artificial intelligence chips in the prior art are digital computing units. A single computing unit in an artificial intelligence chip requires a large number of transistors. For example, each computing unit may have tens of thousands of transistors, and there are usually only a few thousand computing units in the model of artificial intelligence chips in the prior art. At this time, in order to realize the simultaneous calculation of tens of thousands or even hundreds of millions of data, a large number of artificial intelligence chips must be used to calculate the data in parallel.

[0004] Therefore, in the above scheme, when using digital computer chips as artificial intelligence chips, there are disadvantages such as large size, slow speed and high power consumption. Summary of the invention

[0005] In view of this, the present invention provides a model generation method for simulating computer chips, which overcomes the shortcomings of artificial intelligence chips such as large size, slow speed and high power consumption.

[0006] In a first aspect, the present invention provides a method for generating a model for simulating a computer chip, the method comprising: Get the training dataset; Iteratively updating the neural network model according to the training data set until an iteration condition is satisfied, so as to obtain target parameter values ​​of each transfer function in the neural network model; The neural network model includes n layers of operation nodes, and any operation node in each layer of operation nodes is connected to each node in the upper layer through different transfer functions; the target parameter value of the transfer function between each operation node is used to set the parameters of the operation unit between each adder in the model of the simulated computer chip, thereby generating a model of the simulated computer chip; The model of the simulated computer chip includes n adding layers, and any adder in each adding layer is connected to each adder in the upper adding layer through different operation units; the topological structure of the model of the simulated computer chip is the same as the topological structure of the neural network model.

[0007] In an optional implementation, the training data set includes input data and label values; the label value is the expected output value of the output node of the neural network model after the input data is input into the neural network model; Iteratively updating the neural network model according to the training data set includes: Inputting the input data into a neural network model to obtain an actual operation value of the neural network model; According to the error between the actual operation value and the label value, the parameters of each transfer function in the neural network model are updated.

[0008] In an optional implementation, before iteratively updating the neural network model according to the training data set, the method further includes: Acquire the topological structure of the model of the simulated computer chip and the circuit structure of the computing unit; Determining the connection relationship between the various computing nodes in the neural network model according to the topological structure of the model simulating the computer chip; According to the circuit structure of the operation unit, the formula of the transfer function in the neural network model is determined.

[0009] In an optional embodiment, the neural network model also includes an output layer; the output nodes in the output layer are connected one-to-one with the operation nodes of the last layer; the output nodes are used to output the actual output values ​​of the operation nodes of the last layer as the actual operation values ​​of the neural network model.

[0010] In an optional implementation, updating the parameters of each transfer function in the neural network model according to the error between the actual operation value and the label value includes: Get the node error between the actual output value and the expected output value of each operation node in the jth layer; 2≥j≥n; Taking the node error between the actual output value and the expected output value of each operation node of the j-th layer as the dependent variable, taking the parameters of each transfer function between the operation node of the j-1-th layer and the operation node of the j-th layer as the independent variables for derivation, and obtaining the derivative value corresponding to each transfer function between the operation node of the j-1-th layer and the operation node of the j-th layer; Based on the update coefficient and the derivative value corresponding to each transfer function between the j-1th layer operation node and the jth layer operation node, respectively update the parameters of each transfer function between the j-1th layer operation node and the jth layer operation node; The expected output value of the j-1th layer operation node is calculated according to each updated transfer function between the j-1th layer operation node and the j-th layer operation node, and the expected output value of the j-th layer operation node.

[0011] In an optional implementation, there are k computing nodes in the j-th layer; where k≥1; The calculating the expected output value of the j-1th layer operation node according to each updated transfer function between the j-1th layer operation node and the j-th layer operation node, and the expected output value of the j-th layer operation node, comprises: For any target node in the j-1th layer of computing nodes, obtain k updated values ​​of the target node according to the transfer function between the target node and the k computing nodes in the jth layer, and the expected output values ​​of the k computing nodes in the jth layer; The average of the k updated values ​​of the target node is used as the expected output value of the target node.

[0012] In an optional implementation, the upper layer nodes of the first layer operation nodes include various input nodes; The method further comprises: Obtain the node error between the actual output value and the expected output value of each operation node in the first layer; Taking the node error between the actual output value and the expected output value of each operation node of the first layer as the dependent variable, taking the parameters of the transfer function between each input node and each operation node of the first layer as the independent variables to derive, to obtain the derivative value corresponding to the transfer function between each input node and each operation node of the first layer; Based on the update coefficient and the derivative value corresponding to each transfer function between each input node and each operation node of the first layer, the parameters of each transfer function between each input node and each operation node of the first layer are updated respectively.

[0013] In an optional embodiment, the method further includes: The output values ​​of the transfer functions that are greater than or equal to a first threshold are set as the first threshold, and the output values ​​of the transfer functions that are less than or equal to a second threshold are set as the second threshold; the first threshold is greater than the second threshold.

[0014] In an optional implementation, the transfer function is:

[0015] Wherein, x is the input value of the transfer function; y is the output value of the transfer function; W is the first adjustable parameter of the transfer function; c is a constant; VV is the first threshold value of the transfer function; and 0 is the second threshold value of the transfer function.

[0016] In an optional implementation, the transfer function is:

[0017] Wherein, x is the input value of the transfer function; y is the output value of the transfer function; B is the second adjustable parameter of the transfer function; A22 is the gain constant; VV is the first threshold value of the transfer function; and 0 is the second threshold value of the transfer function.

[0018] In an optional implementation, the iteration condition includes at least one of the following: The number of iterations is greater than the preset number; The error between the actual output value of the neural network model and the label value is less than the preset error threshold.

[0019] In a possible implementation manner, the iterative updating of the neural network model according to the training data set until an iteration condition is satisfied further includes: Acquire an initial parameter set; the initial parameter set includes initial parameter values ​​of each transfer function; The parameters of each transfer function are set to corresponding initial parameter values.

[0020] In a possible implementation manner, the initial parameter values ​​of the respective transfer functions are preset; Alternatively, the initial parameter values ​​of each transfer function are randomly selected within a specified range.

[0021] In a possible implementation, the method further includes: Obtain a verification data set; the verification data set includes verification data and corresponding label values; The verification data is processed by the iteratively updated neural network model to obtain a verification prediction value; The prediction accuracy of the neural network model is obtained according to the verification prediction value and the label value corresponding to the verification data.

[0022] In a possible implementation, the method further includes: Determine the address of the operation unit corresponding to the transfer function between each operation node; According to the target parameter value of the transfer function between the various operation nodes and the address of the operation unit corresponding to the transfer function, the parameters of the operation unit between the various adders in the model of the simulated computer chip are set to generate the model of the simulated computer chip.

[0023] In a possible implementation, a non-volatile storage unit is provided in the computing unit; The step of setting the parameters of the operation units between the adders in the model of the simulated computer chip according to the target parameter values ​​of the transfer functions between the operation nodes and the addresses of the operation units corresponding to the transfer functions to generate the model of the simulated computer chip comprises: According to the target parameter value of the transfer function between the various operation nodes and the address of the operation unit corresponding to the transfer function, the storage data of the non-volatile storage unit in the operation unit between the various adders in the model of the simulated computer chip is set to generate a model of the simulated computer chip.

[0024] In a second aspect, the present invention provides a model generation device for simulating a computer chip, the device comprising: A data set acquisition module is used to acquire a training data set; A training module, used for iteratively updating the neural network model according to the training data set until an iteration condition is met, so as to obtain target parameter values ​​of each transfer function in the neural network model; The neural network model includes n layers of operation nodes, and any operation node in each layer of operation nodes is connected to each node in the upper layer through different transfer functions; the target parameter value of the transfer function between each operation node is used to set the parameters of the operation unit between each adder in the model of the simulated computer chip, thereby generating a model of the simulated computer chip; The model of the simulated computer chip includes n adding layers, and any adder in each adding layer is connected to each adder in the upper adding layer through different operation units; the topological structure of the model of the simulated computer chip is the same as the topological structure of the neural network model.

[0025] In a possible implementation manner, the device further includes: An address determination module, used to determine the address of the operation unit corresponding to the transfer function between each operation node; A parameter setting module is used to set the parameters of the operation units between the adders in the model of the simulated computer chip according to the target parameter value of the transfer function between the various operation nodes and the address of the operation unit corresponding to the transfer function, so as to generate a model of the simulated computer chip.

[0026] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the model generation method for simulating a computer chip according to the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0027] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the method for generating a model of a simulated computer chip according to the first aspect or any corresponding embodiment thereof.

[0028] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute the method for generating a model of a simulated computer chip according to the first aspect or any corresponding embodiment thereof.

[0029] In summary, the present application provides a method for generating a model of an analog computer chip, which utilizes an external computer in combination with an analog computer chip to train an artificial intelligence model in the external computer, and then sets and adjusts the storage data of the non-volatile storage units of each operation unit in the model of the analog computer chip according to the parameters of the artificial intelligence model, thereby realizing the setting and adjustment of the parameters of the operation unit, thereby generating a model of the analog computer chip, and the model of the analog computer chip can realize the same or similar functions as the artificial intelligence model after training; at the same time, since the operation units in the present application are all composed of analog circuits, the generated model of the analog computer chip has tens of thousands or even hundreds of millions of operation units under the same chip volume, which greatly improves the computing power of the artificial intelligence chip, and can realize the calculation of tens of thousands or even hundreds of millions of data at the same time, so that the analog computer chip has stronger computing power and faster computing speed at the same volume. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 is a flow chart of a method for generating a model of a simulated computer chip according to an embodiment of the present invention; Figure 2 A schematic diagram of an application of a neural network model involved in an embodiment of the present application is shown; Figure 3A schematic diagram showing a flow chart of a method for generating a model of a simulated computer chip according to an embodiment of the present application; Figure 4 A topological structure diagram of a model simulating a computer chip involved in an embodiment of the present application is shown; Figure 5 A schematic diagram of the circuit structure of a first type of operation unit involved in an embodiment of the present application is shown; Figure 6 A schematic diagram of the circuit structure of a second computing unit involved in an embodiment of the present application is shown; Figure 7 is a schematic diagram of a regulating circuit corresponding to the circuit structure of the first operation unit; Figure 8 It is a schematic diagram of the structure of a model generation device for simulating a computer chip; Fig. 9 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0033] The present application provides a method for generating a model of a simulated computer chip. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0034] In this embodiment, a method for generating a model of an analog computer chip is provided. In the method, a neural network model (i.e., an artificial intelligence model) is first trained according to the application scenario corresponding to the analog computer chip, and then the parameters of the operation units between the adders in the model of the analog computer chip are adjusted according to the parameters of the trained neural network model, thereby generating a model of the analog computer chip. At this time, the model of the analog computer chip can characterize the connection relationship between the modules such as the adder and the operation unit of the finally generated analog computer chip, as well as the specific parameters of each module in the analog computer chip.

[0035] The training process of the above-mentioned neural network model can be executed by computer devices with high computing performance, such as servers and personal computers; and the adjustment of the parameters of the operation units between the various adders in the model of the simulated computer chip can be achieved by a specially designed adjustment circuit.

[0036] Figure 1 is a flow chart of a method for generating a model of a simulated computer chip according to an embodiment of the present invention, such as Figure 1 As shown, the process includes the following steps: Step 101, obtaining a training data set.

[0037] The training data set includes input data and label values; optionally, the input data may be data in one of the fields of machine translation, speech recognition, image recognition, and text-to-image generation, and the label value is the expected output value of the output node of the neural network model after the input data is input into the neural network model. Optionally, the label value may be obtained by manual annotation after relevant technicians identify and process the input data.

[0038] At this time, according to the application scenario of the simulated computer chip, input data that meets the processing conditions of the neural network model is selected. For example, when the computer chip needs to recognize and process image data, the image data can be converted according to specified rules (for example, by normalization, etc.) to obtain input data that meets the processing conditions of the neural network model. At this time, the input data can be input into the computer device deployed with the neural network model as the training data required for the computer device to train the neural network model.

[0039] Step 102, iteratively updating the neural network model according to the training data set until an iteration condition is met, so as to obtain target parameter values ​​of each transfer function in the neural network model.

[0040] Analog computer chips have a wide range of application scenarios, and can be used in fields such as machine translation, speech recognition, image recognition, or text generation and image generation. However, no matter what scenario the analog computer chip is used in, as long as the corresponding input data is input into the analog computer chip, the corresponding output data must be obtained. Therefore, the neural network model corresponding to the analog computer chip should also have the same function. Figure 2 As shown, it shows an application schematic diagram of the neural network model involved in the embodiment of the present application. After the input data in the training data set is input into the neural network model as training data, the ideal output data obtained should be equal to the label value, but the actual output data of the neural network model often differs from the label value. Therefore, according to the error between the label value and the actual output data, the neural network model can be trained, so that the actual output result of the trained neural network model is closer to the label value.

[0041] In the embodiment of the present application, the neural network model includes n layers of operation nodes, and any operation node in each layer of operation nodes is connected to each node in the upper layer through different transfer functions.

[0042] At this time, in the operation process of the neural network model, after receiving the input data, each layer of operation nodes can process the input data through different transfer functions, and then transfer it to the operation nodes of the next layer until the output value of the neural network model is obtained. In this neural network model, since the target parameters of the transfer function between the two layers of nodes can vary within a certain range, the target parameters of each transfer function in the neural network model are adjusted during the training process, so that the neural network model can fit the mapping relationship between various input data and output data, so that the neural network model can process the input data and obtain an output result that is close to the label value.

[0043] Correspondingly, the model of the simulated computer chip includes n adding layers, and any adder in each adding layer is connected to each adder in the upper adding layer through different operation units.

[0044] Step 103: determine the addresses of the operation units corresponding to the transfer functions between the various operation nodes.

[0045] Step 104, according to the target parameter value of the transfer function between the various operation nodes and the address of the operation unit corresponding to the transfer function, the parameters of the operation unit between the various adders in the model of the simulated computer chip are set to generate the model of the simulated computer chip.

[0046] In the embodiment of the present application, the target parameter values ​​of the transfer functions between the various operation nodes are used to set the parameters of the operation units between the various adders in the model of the simulated computer chip, thereby generating the model of the simulated computer chip.

[0047] That is to say, the topological structure of the model of the simulated computer chip is the same as the topological structure of the neural network model. Since the trained neural network model can process the input data to obtain an output result that is similar to the label value, and since the topological structure of the model of the simulated computer chip is the same as the topological structure of the neural network model, at this time, it is only necessary to set the parameters of the operation unit in the model of the simulated computer chip and the parameters of the transfer function in the neural network model accordingly to obtain the model of the simulated computer chip. At this time, the model in the simulated computer chip can achieve the same or similar data processing effect as the neural network model.

[0048] In summary, the present application provides a method for generating a model of an analog computer chip, which utilizes an external computer in combination with an analog computer chip to train an artificial intelligence model (i.e., a neural network model) in the external computer, and then sets and adjusts the parameters of each computing unit in the model of the analog computer chip according to the parameters of the artificial intelligence model, thereby generating a model of the analog computer chip. At this time, the model of the analog computer chip can achieve the same or similar functions as the artificial intelligence model after training. At the same time, since the computing units in the present application are all composed of analog circuits, the generated model of the analog computer chip has tens of thousands or even hundreds of millions of computing units under the same chip volume, which greatly improves the computing power of the artificial intelligence chip and can achieve simultaneous calculation of tens of thousands or even hundreds of millions of data, thereby making the analog computer chip have stronger computing power and faster computing speed at the same volume.

[0049] Please refer to Figure 3 , which shows a schematic flow chart of a method for generating a model of a simulated computer chip involved in an embodiment of the present application, such as Figure 3 As shown, the model generation method of the simulated computer chip includes the following steps: Step 301, obtaining the topological structure of the model of the simulated computer chip and the circuit structure of the computing unit.

[0050] In the embodiment of the present application, since the topological structure of the model of the simulated computer chip is the same as the topological structure of the neural network model, it is necessary to obtain the topological structure of the model of the simulated computer chip actually used, and then construct the neural network model according to the topological structure of the model of the simulated computer chip.

[0051] And because the operation unit in the model of the analog computer chip is used to transfer data between the adders of two adjacent layers, which is similar to the role of the transfer function in the neural network model, the computer device also needs to determine the circuit structure of the operation unit of the model of the analog computer chip, so as to determine what transfer function the neural network model adopts.

[0052] Step 302, determining the connection relationship between each computing node in the neural network model according to the topological structure of the model simulating the computer chip.

[0053] Please refer to Figure 4 , which shows a topological structure diagram of a model of a simulated computer chip involved in an embodiment of the present application. Figure 4As shown, the model of the analog computer chip includes n adding layers, and any adder in each adding layer is connected to each adder in the upper adding layer through different operation units. The model of the analog computer chip also includes an output layer; the output nodes in the output layer are connected one-to-one with the adders in the last layer; the output nodes are used to output the actual output value of the adder in the last layer as the actual operation value of the model of the analog computer chip.

[0054] Furthermore, after obtaining the topological structure of the model of the simulated computer chip, the operation unit in the simulated computer chip can be replaced with a transfer function, and the adder in the model of the simulated computer chip can be replaced with an operation node, thereby constructing a topological structure similar to the above. Figure 4 The topology of the model of the simulated computer chip shown is identical to the neural network model.

[0055] Step 303, determining the formula of the transfer function in the neural network model according to the circuit structure of the operation unit.

[0056] Please refer to Figure 5 , which shows a schematic diagram of the circuit structure of the first type of operation unit involved in the embodiment of the present application. Figure 5 As shown, VIN is the input voltage, the input voltage VIN is the x of the transfer function, VOUT is the output voltage, the output voltage VOUT is the y of the transfer function, VR is the fixed voltage, and the fixed voltage VR is the constant c of the transfer function. It can be seen that when the resistance value of the first resistor R1 is equal to the resistance value of the fourth resistor R4, the resistance value of the second resistor R2 is equal to the resistance value of the third resistor R3, and the gain of the first operational amplifier A1 is represented by A11, Figure 3 In the first arithmetic unit circuit structure shown in FIG. , that is, at this time, After being expressed by the first adjustable parameter W, the transfer function corresponding to the circuit of the first type of operation unit is: .

[0057] Please refer to Figure 6 , which shows a schematic diagram of the circuit structure of the second operation unit involved in the embodiment of the present application. Wherein, VIN is the input voltage, the input voltage VIN is the x of the transfer function, VOUT is the output voltage, the output voltage VOUT is the y of the transfer function, VR is the fixed voltage of the circuit, and the fixed voltage VR is the constant c of the transfer function. It can be seen that when the gain of the second operational amplifier A2 is represented by A22, Figure 6 The circuit structure of the second operation unit shown in FIG. , that is, at this time, After being expressed by the second adjustable parameter B, the transfer function corresponding to the circuit of the second type of operation unit is: .

[0058] At this time, when the first type of operation unit is used, the corresponding transfer function is When the value of the first adjustable parameter W is changed, the first type of operation unit can be set and adjusted. Similarly, when the second type of operation unit is used, the corresponding transfer function is When the value of the second adjustable parameter B is changed, the second operation unit can be set and adjusted; at the same time, since the first operation unit circuit and the second operation unit circuit are both composed of operational amplifiers, the output voltage VOUT of the first operation unit circuit and the second operation unit circuit should be between the positive input power supply and the negative input power supply of the operational amplifier. Generally speaking, the positive input power supply of the operational amplifier The power supply value is 5V or 3.3V, and the negative input power supply is GND, which is 0V. Therefore, the accurate transfer function corresponding to the first operation unit circuit is: , the exact transfer function corresponding to the second operation unit circuit is ; Wherein, VV is the first threshold value of the transfer function; 0 is the second threshold value of the transfer function; Therefore, at this time, the external computer in the present application can input the training data, when the transfer function is Based on the training, the value of the first adjustable parameter W corresponding to each transfer function is obtained, or when the transfer function is On this basis, the value of the second adjustable parameter B corresponding to each transfer function is obtained through training.

[0059] Preferably, in the above transfer function, the first threshold VV of the transfer function is actually the voltage of the positive input power supply of the operational amplifier (the first operational amplifier or the second operational amplifier), for example, it may be 5V; optionally, the first threshold VV of the transfer function may also be 3.3V or other values.

[0060] Step 304: Acquire an initial parameter set; the initial parameter set includes initial parameter values ​​of each transfer function.

[0061] After determining in step 303 that the neural network model selects the transfer function corresponding to the first type of operation unit or the transfer function corresponding to the second type of operation unit, the computer device also needs to set the initial parameter values ​​of each transfer function in the neural network model to initialize the neural network model.

[0062] Optionally, the initial parameter value may be preset or manually set; Optionally, the initial parameter value may also be randomly selected within a preset range.

[0063] Step 305: setting the parameters of each transfer function to corresponding initial parameter values.

[0064] Step 306: Obtain a training data set.

[0065] Step 307, iteratively updating the neural network model according to the training data set until an iteration condition is met, so as to obtain target parameter values ​​of each transfer function in the neural network model.

[0066] In one possible implementation, a computer device inputs the input data into a neural network model to obtain an actual operation value of the neural network model; and updates the parameters of each transfer function in the neural network model based on an error between the actual operation value and the label value.

[0067] Specifically, with Figure 4 The neural network model with the same topological structure as the model of the simulated computer chip shown in the figure is taken as an example. The neural network model has an input layer, and the input layer includes various input nodes. The input data in the training data set ( ) is input into each transfer function from each input node, and reaches each operation node of the first layer after calculation. In the embodiment of the present application, each operation node acts as an adder to add the calculation results of each transfer function.

[0068] At this time, each operation node of the first layer adds up the i input data obtained by the transfer function calculation, and inputs them into each transfer function of the second layer as the input data of the second layer, and reaches each operation node of the second layer after calculation, and so on, reaches each operation node of the nth layer, and each operation node of the nth layer adds up the i input data obtained by the transfer function calculation of the nth layer and inputs them into each output node as the actual output value obtained by the calculation; Taking the transfer function corresponding to the circuit of the first type of operation unit as an example, when the number of input nodes and operation nodes in each layer is 3 and the number of operation nodes is 2, the calculation result of operation node 11 is: ,in is the value of the transfer function between the operation node op and the qth node in the previous layer, where o, p, and q are all positive integers greater than or equal to 1 and less than or equal to 3, for example is the value of W of the transfer function between in1 and operation node 11, is the value of W of the transfer function between in2 and operation node 11, is the value of W of the transfer function between in3 and operation node 11. Similarly, the calculation result of operation node 12 is: , the calculation result of operation node 13 is: , then we can get the calculation result of operation node 21: , the calculation result of operation node 22 is: , the calculation result of operation node 23 , then we can get that the actual output value obtained by the neural network model operation includes , and ; Assumptions and input data ( ) and their corresponding label values ​​are , , … , and the actual output values ​​obtained by the neural network model are , … When , the error between the actual output value and the label value is obtained; Specifically, the error is: ; At this time, if the error EL is less than the preset error threshold, the training is completed, and the first adjustable parameter W in each transfer function is stored in an external computer as a target parameter value in a certain order.

[0069] If the error EL is greater than a preset error threshold, it is necessary to update the first adjustable parameter W in each transfer function between the nth layer operation node and the n-1th layer operation node according to the error between the operation value and the expected output value.

[0070] Specifically, in the embodiment of the present application, the computer device obtains the node error between the actual output value and the expected output value of each operation node in the jth layer; 2≥i≥n; The node error between the actual output value and the expected output value of each operation node of the j-th layer is taken as the dependent variable, and the parameters of each transfer function between the operation node of the j-1-th layer and the operation node of the j-th layer are taken as the independent variables to be differentiated, so as to obtain the derivative value corresponding to each transfer function between the operation node of the j-1-th layer and the operation node of the j-th layer; Based on the update coefficient and the derivative value corresponding to each transfer function between the j-1th layer operation node and the jth layer operation node, respectively update the parameters of each transfer function between the j-1th layer operation node and the jth layer operation node; The expected output value of the j-1th layer operation node is calculated according to each updated transfer function between the j-1th layer operation node and the j-th layer operation node, and the expected output value of the j-th layer operation node.

[0071] Taking the nth layer operation node and the n-1th layer operation node, that is, j=n, as an example, the parsing process of the execution steps of the above steps is as follows: Since the actual output value of the neural network model Therefore, the corresponding label value is used as the expected output value of the output node of the neural network model. At this time, the error between the actual output value of the output node of the neural network model and the expected output value is At this time, the first adjustable parameter W of each transfer function is derived to obtain the state at this moment. When the value is greater, the derivative value DEL of the function is greater. If the derivative value DEL is greater, it means that the state at this moment is The larger the error corresponding to the value, the smaller the derivative value DEL is, indicating that the state at this moment is The smaller the error corresponding to the value; For example, when the number of input nodes and operation nodes at each layer is 3 and the number of operation nodes is 2, the calculation result of operation node 21 is: , the calculation result of operation node 22 is: , the calculation result of operation node 23 , the error between the actual output value and the expected output value , at this time, except After the values ​​of other parameters except After that, Substitute the parameter value into the derived formula and we get The corresponding derivative value , similarly, the derivative values ​​corresponding to other W are obtained in turn; It should be noted that in the embodiment of the present application, it is necessary to add restrictive conditions in the calculation process of the transfer function, for example, the actual output value of each transfer function that is greater than or equal to the first threshold is set as the first threshold, and the actual output value of each transfer function that is less than or equal to the second threshold is set as the second threshold; the first threshold is greater than the second threshold, wherein the first threshold is the voltage value of the positive input power supply of the operational amplifier in the operational unit corresponding to the transfer function; the second threshold is the voltage value of the negative input power supply of the operational amplifier in the operational unit corresponding to the transfer function.

[0072] Since the transfer function corresponds to the first type of operation unit circuit, and the output value of the first operation unit circuit should be greater than 0V and less than the voltage of the positive input power supply of the operational amplifier, such as 5V, in this embodiment of the present application, when When it is greater than 5, The value of is 5. When the value of is less than 0, The value of is 0.

[0073] At this time, according to the calculated derivative values ​​DEL corresponding to the first adjustable parameters W, the first adjustable parameters W are updated to ,in is the update coefficient, which can be set according to the training accuracy and training speed Specific values ​​of, where The larger it is, the faster the training speed is but the lower the accuracy is. The smaller it is, the slower the training speed but the higher the accuracy.

[0074] Substitute each updated value of W into each transfer function between the n-th layer operation node and the n-1-th layer operation node, and then obtain the corresponding operation update value of each operation node in the n-1-th layer operation node according to each expected output value, and use the operation update value as the expected output value of the n-1-th layer operation node; Specifically, each operation node in the n-1th layer corresponds to i transfer functions. All operation update values ​​calculated by the i transfer functions need to be added together and divided by i. The average value obtained is the operation update value of each operation node in the corresponding n-1th layer operation node. The operation update value is used as the expected output value of the n-1th layer operation node.

[0075] After the expected output value of the n-1th layer operation node is obtained, the first adjustable parameter W of the transfer function between the n-2th layer operation node and the n-1th layer operation node can be updated by the updating method of the first adjustable parameter W as shown above, and this step is iterated until the expected output value of the 1st layer operation node is obtained.

[0076] For example, when the number of input nodes and operation nodes at each layer is 3 and the number of operation nodes is 2, after the updated value of W is introduced, the calculation result of operation node 21 is , at this time, and Substitute the initial value of into the above formula to obtain the first operation update value of the first layer operation node 11 Similarly, the second calculation update value of the first layer calculation node 11 is obtained according to the calculation results of the calculation nodes 22 and 23. and the third operation update value of the first layer operation node 11 Finally, we can get the updated value of the operation node 11 in the first layer. ; Then, the same method is used to obtain the calculation update value of the first layer calculation node 12 and the calculation update value of the first layer calculation node 13 , and, and They are respectively used as the expected output values ​​of the first-layer operation node 11, the operation node 12 and the operation node 13.

[0077] After the expected output value of the operation node of the first layer is obtained, the computer device can obtain the node error between the actual output value and the expected output value of each operation node of the first layer; The node error between the actual output value and the expected output value of each operation node of the first layer is taken as the dependent variable, and the parameters of the transfer function between each input node and each operation node of the first layer are respectively taken as the independent variables to be differentiated, so as to obtain the derivative value corresponding to the transfer function between each input node and each operation node of the first layer; Based on the update coefficient and the derivative value corresponding to each transfer function between each input node and each operation node of the first layer, the parameters of each transfer function between each input node and each operation node of the first layer are updated respectively.

[0078] Since the parameter updating process of each transfer function between each input node and each operation node of the first layer is similar to the parameter updating process of each transfer function between each operation node of the nth layer and each operation node of the n-1th layer, it will not be repeated here.

[0079] If the parameter update process of each transfer function between each input node and each operation node of the first layer is completed, then an iterative training process for the neural network model is completed, and the number of iterations is increased by 1.

[0080] During the iteration process, if the number of iterations is greater than the preset number, or during the iteration process, the error between the actual output value of the output node and the label value is less than the error threshold, the training ends, and the first adjustable parameter W in each updated transfer function is stored in an external computer as a target parameter value in a certain order; If the number of iterations is less than the preset number, the updated first adjustable parameter W is brought into all transfer functions to obtain updated transfer functions, thereby continuing the iterative process.

[0081] Optionally, in the embodiment of the present application, after completing the iteration process, the computer device may also obtain a verification data set; the verification data set includes verification data and corresponding label values; The computer device processes the verification data through the iteratively updated neural network model to obtain a verification prediction value; According to the verification prediction value and the label value corresponding to the verification data, the prediction accuracy of the neural network model is obtained to determine whether the neural network model can be used to set the model of the simulated computer chip; if the prediction accuracy is greater than or equal to the accuracy threshold, the parameters of the operation units between the adders in the model of the simulated computer chip can be set accordingly according to the target parameter value of the transfer function between the operation nodes of the neural network model; if the prediction accuracy is less than the accuracy threshold, continue to iterate the training through the training data set.

[0082] Step 308, determining that the transfer function between each operation node in the neural network model corresponds to the address of the operation unit of the model simulating the computer chip.

[0083] Step 309, according to the target parameter value of the transfer function between the various operation nodes and the address of the operation unit, the parameters of the operation unit between the various adders in the model of the simulated computer chip are set to generate the model of the simulated computer chip.

[0084] After the training of the neural network model is completed, the computer device can determine the address of the operation unit corresponding to the transfer function between each operation node of the neural network model in the model of the simulated computer chip, and then set the parameters of the operation unit between each adder in the model of the simulated computer chip according to the address of the operation unit based on the target parameter value of the transfer function between each operation node to generate a model of the simulated computer chip.

[0085] Specifically, the computer device inputs the target parameter values ​​and their sequential relationship in each transfer function (that is, the sequential relationship stored in an external computer in a certain order as mentioned above, and the sequential relationship is the address information of the operation unit of the model of the analog computer chip corresponding to each transfer function) into the adjustment circuit of the analog computer chip; wherein, the adjustment circuit can be located in the analog computer chip, or can be an independent circuit externally connected to the analog computer chip.

[0086] The adjustment circuit can set and adjust the parameters of each computing unit in the model of the simulated computer chip according to the input target parameter value and its sequential relationship, so that the generated model of the simulated computer chip has the same or similar functions as the trained neural network model shown in the embodiment of the present application.

[0087] For details, please refer to Figure 5 and Figure 6 .like Figure 5As shown, when the first operation unit circuit is used, the value of the first adjustable parameter W can be changed by changing the resistance values ​​of the first resistor R1 and the fourth resistor R4 or changing the resistance values ​​of the second resistor R2 and the third resistor R3, thereby achieving setting adjustment of the operation unit. In a possible implementation, a non-volatile storage unit is provided in the operation unit of the model of the simulated computer chip. For example, the non-volatile storage unit can be used as a resistor, that is, the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 are all composed of non-volatile storage units, or the first resistor R1 and the fourth resistor R4 are composed of non-volatile storage units, or the second resistor R2 and the third resistor R3 are composed of non-volatile storage units. At this time, by adjusting the storage data of the non-volatile storage unit (such as the floating gate charge of the MOS tube of the non-volatile storage unit), its resistance value can be changed. Therefore, according to the target parameter value of the transfer function between each operation node and the address of the operation unit corresponding to the transfer function, the storage data of the non-volatile storage unit in the operation unit between each adder in the model of the simulated computer chip is set, thereby generating a model of the simulated computer chip.

[0088] Specifically, the two non-volatile storage units constituting the first resistor R1 and the fourth resistor R4 or the two non-volatile storage units constituting the second resistor R2 and the third resistor R3 are used as an adjustment point and connected to the adjustment circuit. When it is necessary to set the parameters of a certain operation unit, the adjustment circuit finds the non-volatile storage unit corresponding to the adjustment point of the operation unit, and sets the storage data of the adjustment non-volatile storage unit according to the value of the first adjustable parameter W (such as charging and discharging the floating gate of the MOS tube of the non-volatile storage unit to change its resistance value), thereby obtaining the required parameters of the operation unit.

[0089] like Figure 6As shown, when the second operation unit circuit is adopted, the value of the second adjustable parameter B can be changed by changing the resistance value of the fifth resistor R5 or the resistance value of the sixth resistor R6, thereby realizing the setting and adjustment of the operation unit. Therefore, at this time, the non-volatile storage unit can be used as a resistor, that is, the fifth resistor R5 and the sixth resistor R6 are both composed of non-volatile storage units, or the fifth resistor R5 is composed of non-volatile storage units, or the sixth resistor R6 is composed of non-volatile storage units. At this time, by adjusting the storage data of the non-volatile storage unit (such as the floating gate charge of the MOS tube of the non-volatile storage unit), its resistance value can be changed. Therefore, the non-volatile storage unit constituting the fifth resistor R5 or the sixth resistor R6 is used as an adjustment point and connected to the adjustment circuit. When it is necessary to set and adjust the parameters of a certain operation unit, the adjustment circuit finds the non-volatile storage unit corresponding to the adjustment point of the operation unit, and sets and adjusts the storage data of the non-volatile storage unit according to the value of the second adjustable parameter B (such as charging and discharging the floating gate of the MOS tube of the non-volatile storage unit to change its resistance value), thereby obtaining the required parameters of the operation unit.

[0090] The regulation circuit is designed as Figure 7 The structure shown.

[0091] Among them, the target parameter values ​​and their sequential relationship are input into the adjustment circuit. The adjustment circuit charges and discharges the gate capacitance of the MOS tube in the corresponding node in turn according to the target parameter values ​​and their sequential relationship to set and adjust its resistance value, thereby setting and adjusting the parameters of each operation unit. After all the operation units in the model of the simulated computer chip are set and adjusted, the model of the simulated computer chip can have the same or similar functions as the above-mentioned trained neural network model.

[0092] In summary, the present application provides a method for generating a model of an analog computer chip, which utilizes an external computer in combination with an analog computer chip to train an artificial intelligence model in the external computer, and then sets and adjusts the storage data of the non-volatile storage units of each operation unit in the model of the analog computer chip according to the parameters of the artificial intelligence model, thereby realizing the setting and adjustment of the parameters of the operation unit, thereby generating a model of the analog computer chip, and the model of the analog computer chip can realize the same or similar functions as the artificial intelligence model after training; at the same time, since the operation units in the present application are all composed of analog circuits, the generated model of the analog computer chip has tens of thousands or even hundreds of millions of operation units under the same chip volume, which greatly improves the computing power of the artificial intelligence chip, and can realize the calculation of tens of thousands or even hundreds of millions of data at the same time, so that the analog computer chip has stronger computing power and faster computing speed at the same volume.

[0093] In the present embodiment, a model generation device for simulating a computer chip is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware is also possible and conceived.

[0094] This embodiment provides a model generation device for simulating a computer chip, such as Figure 8 As shown, including: The data set acquisition module 801 is used to acquire a training data set; A training module 802 is used to iteratively update the neural network model according to the training data set until an iteration condition is met to obtain target parameter values ​​of each transfer function in the neural network model; The neural network model includes n layers of operation nodes, and any operation node in each layer of operation nodes is connected to each node in the upper layer through different transfer functions; the target parameter value of the transfer function between each operation node is used to set the parameters of the operation unit between each adder in the model of the simulated computer chip, so as to generate the model of the simulated computer chip; The model of the simulated computer chip includes n adding layers, and any adder in each adding layer is connected to each adder in the upper adding layer through different operation units; the topological structure of the model of the simulated computer chip is the same as the topological structure of the neural network model.

[0095] In a possible implementation manner, the device further includes: An address determination module 803, used to determine the address of the operation unit corresponding to the transfer function between each operation node; The parameter setting module 804 is used to set the parameters of the operation units between the adders in the model of the simulated computer chip according to the target parameter value of the transfer function between the various operation nodes and the address of the operation unit corresponding to the transfer function, so as to generate a model of the simulated computer chip.

[0096] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0097] The model generation device for simulating a computer chip in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0098] The embodiment of the present invention also provides a computer device having the above Figure 8 The model generation device of the simulated computer chip is shown.

[0099] See also Fig. 9 , Fig. 9 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Fig. 9 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig. 9 A processor 10 is taken as an example.

[0100] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0101] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0102] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0103] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0104] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0105] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of computer program instructions in computer-readable media includes, but is not limited to, source files, executable files, installation package files, etc., and accordingly, the way in which computer program instructions are executed by a computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0106] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for generating a model for simulating a computer chip, characterized in that: The method comprises: Get the training dataset; Iteratively updating the neural network model according to the training data set until an iteration condition is satisfied, so as to obtain target parameter values ​​of each transfer function in the neural network model; the neural network model includes n layers of operation nodes, and any operation node in each layer of operation nodes is connected to each node in the upper layer through a different transfer function; the target parameter values ​​of the transfer functions between the operation nodes are used to set the parameters of the operation units between the adders in the model of the simulated computer chip, so as to generate a model of the simulated computer chip; The model of the simulated computer chip includes n adding layers, and any adder in each adding layer is connected to each adder in the upper adding layer through different operation units; the topological structure of the model of the simulated computer chip is the same as the topological structure of the neural network model.

2. The model generation method according to claim 1, characterized in that: The training data set includes input data and label values; the label value is the expected output value of the output node of the neural network model after the input data is input into the neural network model; Iteratively updating the neural network model according to the training data set includes: Inputting the input data into a neural network model to obtain an actual operation value of the neural network model; According to the error between the actual operation value and the label value, the parameters of each transfer function in the neural network model are updated.

3. The model generation method according to claim 2, characterized in that: Before iteratively updating the neural network model according to the training data set, the method further includes: Acquire the topological structure of the model of the simulated computer chip and the circuit structure of the computing unit; Determining the connection relationship between the various computing nodes in the neural network model according to the topological structure of the model simulating the computer chip; According to the circuit structure of the operation unit, the formula of the transfer function in the neural network model is determined.

4. The model generation method according to claim 2, characterized in that: The neural network model also includes an output layer; the output nodes in the output layer are connected one-to-one with the operation nodes of the last layer; the output nodes are used to output the actual output values ​​of the operation nodes of the last layer as the actual operation values ​​of the neural network model.

5. The model generation method according to claim 4, characterized in that: The updating of the parameters of each transfer function in the neural network model according to the error between the actual operation value and the label value comprises: Get the node error between the actual output value and the expected output value of each operation node in the jth layer; 2≥j≥n; Taking the node error between the actual output value and the expected output value of each operation node of the j-th layer as the dependent variable, taking the parameters of each transfer function between the operation node of the j-1-th layer and the operation node of the j-th layer as the independent variables for derivation, and obtaining the derivative value corresponding to each transfer function between the operation node of the j-1-th layer and the operation node of the j-th layer; Based on the update coefficient and the derivative value corresponding to each transfer function between the j-1th layer operation node and the jth layer operation node, respectively update the parameters of each transfer function between the j-1th layer operation node and the jth layer operation node; The expected output value of the j-1th layer operation node is calculated according to each updated transfer function between the j-1th layer operation node and the j-th layer operation node, and the expected output value of the j-th layer operation node.

6. The model generation method according to claim 5, characterized in that: There are k computing nodes in the jth layer; where k≥1; The calculating the expected output value of the j-1th layer operation node according to each updated transfer function between the j-1th layer operation node and the j-th layer operation node, and the expected output value of the j-th layer operation node, comprises: For any target node in the j-1th layer of computing nodes, obtain k updated values ​​of the target node according to the transfer function between the target node and the k computing nodes in the jth layer, and the expected output values ​​of the k computing nodes in the jth layer; The average of the k updated values ​​of the target node is used as the expected output value of the target node.

7. The model generation method according to claim 6, characterized in that: The upper nodes of the first layer of operation nodes include various input nodes; The method further comprises: Obtain the node error between the actual output value and the expected output value of each operation node in the first layer; Taking the node error between the actual output value and the expected output value of each operation node of the first layer as the dependent variable, taking the parameters of the transfer function between each input node and each operation node of the first layer as the independent variables to derive, to obtain the derivative value corresponding to the transfer function between each input node and each operation node of the first layer; Based on the update coefficient and the derivative value corresponding to each transfer function between each input node and each operation node of the first layer, the parameters of each transfer function between each input node and each operation node of the first layer are updated respectively.

8. The model generation method according to claim 7, characterized in that: The method further comprises: The output values ​​of the transfer functions that are greater than or equal to a first threshold are set as the first threshold, and the output values ​​of the transfer functions that are less than or equal to a second threshold are set as the second threshold; the first threshold is greater than the second threshold.

9. The model generation method according to claim 8, characterized in that: The transfer function is: Wherein, x is the input value of the transfer function; y is the output value of the transfer function; W is the first adjustable parameter of the transfer function; c is a constant; VV is the first threshold value of the transfer function; and 0 is the second threshold value of the transfer function.

10. The model generation method according to claim 8, characterized in that: The transfer function is: Wherein, x is the input value of the transfer function; y is the output value of the transfer function; B is the second adjustable parameter of the transfer function; A22 is the gain constant; VV is the first threshold value of the transfer function; and 0 is the second threshold value of the transfer function.

11. The model generation method according to any one of claims 1 to 10, characterized in that: The iteration condition includes at least one of the following: The number of iterations is greater than the preset number; The error between the actual output value of the neural network model and the label value is less than the preset error threshold.

12. The model generation method according to any one of claims 1 to 10, characterized in that: The iterative updating of the neural network model according to the training data set until an iteration condition is met also includes: Acquire an initial parameter set; the initial parameter set includes initial parameter values ​​of each transfer function; The parameters of each transfer function are set to corresponding initial parameter values.

13. The model generation method according to claim 12, characterized in that: The initial parameter values ​​of each transfer function are preset; Alternatively, the initial parameter values ​​of each transfer function are randomly selected within a specified range.

14. The model generation method according to any one of claims 1 to 10, characterized in that: The method further comprises: Obtain a verification data set; the verification data set includes verification data and corresponding label values; The verification data is processed by the iteratively updated neural network model to obtain a verification prediction value; The prediction accuracy of the neural network model is obtained according to the verification prediction value and the label value corresponding to the verification data.

15. The model generation method according to claim 12, characterized in that: The method further comprises, Determine the address of the operation unit corresponding to the transfer function between each operation node; According to the target parameter value of the transfer function between the various operation nodes and the address of the operation unit corresponding to the transfer function, the parameters of the operation unit between the various adders in the model of the simulated computer chip are set to generate the model of the simulated computer chip.

16. The model generation method according to claim 15, characterized in that: The computing unit is provided with a non-volatile storage unit; The step of setting the parameters of the operation units between the adders in the model of the simulated computer chip according to the target parameter values ​​of the transfer functions between the operation nodes and the addresses of the operation units corresponding to the transfer functions to generate the model of the simulated computer chip comprises: According to the target parameter value of the transfer function between the various operation nodes and the address of the operation unit corresponding to the transfer function, the storage data of the non-volatile storage unit in the operation unit between the various adders in the model of the simulated computer chip is set to generate a model of the simulated computer chip.

17. A model generation device for simulating a computer chip, characterized in that: The device comprises: A data set acquisition module is used to acquire a training data set; A training module, used for iteratively updating the neural network model according to the training data set until an iteration condition is met, so as to obtain target parameter values ​​of each transfer function in the neural network model; The neural network model includes n layers of operation nodes, and any operation node in each layer of operation nodes is connected to each node in the upper layer through different transfer functions; the target parameter value of the transfer function between each operation node is used to set the parameters of the operation unit between each adder in the model of the simulated computer chip, thereby generating a model of the simulated computer chip; The model of the simulated computer chip includes n adding layers, and any adder in each adding layer is connected to each adder in the upper adding layer through different operation units; the topological structure of the model of the simulated computer chip is the same as the topological structure of the neural network model.

18. The model generation device according to claim 17, characterized in that: The device also includes: An address determination module, used to determine the address of the operation unit corresponding to the transfer function between each operation node; A parameter setting module is used to set the parameters of the operation units between the adders in the model of the simulated computer chip according to the target parameter value of the transfer function between the various operation nodes and the address of the operation unit corresponding to the transfer function, so as to generate a model of the simulated computer chip.

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