Register allocation method and device, computer equipment, readable storage medium and program product
By creating a target virtual register and dynamically allocated universal physical registers, the problem that the classic algorithm cannot handle the array variables cannot be solved, and the efficiency of the GPU is improved.
Patent Information
- Application Number
- CN202411505379.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-25
- Publication Date
- 2025-01-24
AI Technical Summary
Classic register allocation algorithms cannot effectively process array-type variables, resulting in reduced GPU efficiency.
By creating the target virtual register and converting the read and write instructions of the array variable into pseudo-instructions, the sub-register index is set according to the size of the array variable, and the general-purpose physical register is dynamically allocated based on the sub-register index.
Effective register allocation of array variables is achieved, improving GPU efficiency and reducing the number of memory accesses.
Smart Images
Figure CN119359523A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of image processing technology, and in particular to a register allocation method, apparatus, computer equipment, computer-readable storage medium, and computer program product. Background Art
[0002] The program executed on the GPU (Graphics Processing Unit) is generally called a shader. The GPU compiler is responsible for converting the shader into a series of machine instructions that can be executed on the target GPU hardware platform. The intermediate calculation results of the executable program will be written into the register or memory and can be read from the register or memory the next time it is used.
[0003] Memory is usually located outside the computing unit. Due to the limitations of access speed and bandwidth, GPUs often need to spend a long time accessing memory when executing instructions, which seriously restricts program performance. Therefore, the compiler will try to put variables into registers, but the number of registers in the GPU is always a scarce resource compared to the variables in the shader. The compiler will use a register allocation algorithm to prioritize registers for variables with high weights. The weight is based on the frequency of the variable in the shader. The higher the frequency, the higher the weight of the variable, which can reduce the total number of memory accesses.
[0004] However, the classic register allocation algorithm cannot handle array variables, so for array variables, the traditional GPU compiler will reserve a portion of consecutively numbered registers for array variables in advance. In this way, because array variables occupy a fixed portion of physical registers, the physical registers available for allocation to other non-array variables are reduced accordingly, which may cause some variables with higher weights to not be allocated physical registers and overflow into the memory, which in turn reduces GPU efficiency. Summary of the invention
[0005] Based on this, it is necessary to provide a register allocation method, apparatus, computer device, computer-readable storage medium and computer program product that can improve GPU efficiency in response to the above technical problems.
[0006] In a first aspect, the present application provides a register allocation method, the method comprising:
[0007] Obtaining instructions to be processed, and determining array variables in the instructions to be processed;
[0008] Creating corresponding target virtual registers for each of the array variables;
[0009] Converting the read and write instructions of each array variable into pseudo instructions of each target virtual register, wherein the pseudo instructions are used to read and write the target virtual register of the array variable;
[0010] According to the size of each array variable, setting the sub-register index of the operand of each target virtual register;
[0011] Based on the sub-register index, a corresponding general physical register is allocated to each of the target virtual registers.
[0012] In one embodiment, each of the target virtual registers includes N consecutive general physical registers, the N general physical registers are sub-registers of the target virtual register, and N is a positive integer;
[0013] The allocating a corresponding general physical register to each of the target virtual registers based on the sub-register index includes:
[0014] A unique general physical register is determined based on the target virtual register index and the sub-register index, and the target virtual register is allocated to the corresponding general physical register.
[0015] In one embodiment, allocating a corresponding general physical register to each of the target virtual registers based on the sub-register index includes:
[0016] detecting whether there is a conflict when allocating the target virtual register to the current general physical register based on the sub-register index;
[0017] In the absence of a conflict, allocating the target virtual register to the current general physical register;
[0018] If there is a conflict and all the general physical registers have not been traversed, the next general physical register is obtained as the current general physical register, until there is no conflict, the target virtual register is allocated to the current general physical register.
[0019] In one embodiment, the method further comprises:
[0020] In the case where there is a conflict and all the general physical registers have been traversed, obtaining a first weight corresponding to the virtual register to which the general physical register has been allocated, wherein the first weight is determined based on a usage frequency of an array variable corresponding to the virtual register to which the general physical register has been allocated;
[0021] When the first weight is less than the second weight corresponding to the target virtual register, the general physical register corresponding to the virtual register to which the general physical register has been allocated is released, and the target virtual register is allocated to the released general physical register.
[0022] In one embodiment, allocating a corresponding general physical register to each of the target virtual registers based on the sub-register index includes:
[0023] Obtaining an active interval of each of the target virtual registers;
[0024] Based on the subregister index, setting a mask for each active subregister in the active interval;
[0025] In case the masks of the sub-registers overlap, detecting whether there is a conflict between active intervals of the sub-registers;
[0026] A corresponding general physical register is allocated to each of the target virtual registers based on the conflict detection result.
[0027] In one embodiment, obtaining the active interval of each of the target virtual registers includes:
[0028] Starting from each read pseudo instruction corresponding to the target virtual register, searching for a write pseudo instruction of the target virtual register in reverse order along the control flow graph of the instruction to be processed;
[0029] In the case where a write pseudo instruction of the target virtual register is searched, an active range of the target virtual register is obtained based on each of the read pseudo instructions and the searched write pseudo instruction.
[0030] In one embodiment, before the step of reversely searching for the write pseudo instruction of the target virtual register along the control flow chart of the instruction to be processed starting from each read pseudo instruction corresponding to the target virtual register, the step further includes:
[0031] Inserting an implicit fixed value instruction in the control flow graph, wherein the implicit fixed value instruction is used to remove an inactive interval of the target virtual register;
[0032] Starting from each read pseudo instruction corresponding to the target virtual register, searching reversely along the control flow chart of the instruction to be processed for the write pseudo instruction of the target virtual register includes:
[0033] Starting from each read pseudo instruction corresponding to the target virtual register, searching in reverse along the control flow graph of the instruction to be processed;
[0034] When an implicit fixed value instruction is found, the search along the current path of the control flow graph is stopped;
[0035] When the insert implicit value instruction is not found, the search along the current path of the control flow graph is continued until a write pseudo instruction of the target virtual register is obtained.
[0036] In one embodiment, inserting an implicit fixed value instruction in the control flow graph includes:
[0037] Obtain the target instruction block where the write pseudo instruction corresponding to each target virtual register is located in the control flow chart of the instruction to be processed, and use the instruction block that can be reached by the target instruction block and the target instruction block as the first instruction block;
[0038] Using the instruction blocks in the control flow chart other than the first instruction block as the second instruction block;
[0039] Marking the read pseudo instruction corresponding to the target virtual register in the second instruction block as undefined, whereby the undefined read pseudo instruction is ignored during the search process;
[0040] Starting from the read pseudo instruction of the target virtual register in the first instruction block, searching for the write pseudo instruction of the target virtual register in reverse along the control flow graph;
[0041] During the search process, when the second instruction block is reached from the first instruction block, the search is stopped and an implicit constant instruction is inserted at the end of the second instruction block.
[0042] In one embodiment, after allocating a corresponding general physical register to each of the target virtual registers based on the sub-register index, the method includes:
[0043] Converting a pseudo instruction of the target virtual register allocated to the general physical register into a read and write instruction for the general physical register;
[0044] The pseudo instruction of the target virtual register that is not allocated to the general physical register is converted into a memory read / write instruction.
[0045] In a second aspect, the present application further provides a register allocation device, the device comprising:
[0046] An array variable determination module, used for obtaining instructions to be processed and determining array variables in the instructions to be processed;
[0047] A virtual register creation module, used for creating corresponding target virtual registers for each array variable;
[0048] An instruction conversion module, used for converting the read and write instructions of each array variable into pseudo instructions of each target virtual register, wherein the pseudo instructions are used for reading and writing the target virtual register of the array variable;
[0049] A sub-register index setting module, used for setting the sub-register index of the operand of each target virtual register according to the size of each array variable;
[0050] An allocation module is used to allocate a corresponding general physical register to each of the target virtual registers based on the sub-register index.
[0051] In a third aspect, the present application further provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method in any one of the above-mentioned embodiments when executing the computer program.
[0052] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method in any one of the above-mentioned embodiments.
[0053] In a fifth aspect, the present application also provides a computer program product, including a computer program, which implements the steps of the method in any one of the above embodiments when executed by a processor.
[0054] The above-mentioned register allocation method, device, computer equipment, computer-readable storage medium and computer program product, after obtaining the instructions to be processed, determine the array variables in the instructions to be processed; create corresponding target virtual registers for each of the array variables; convert the read and write instructions of each of the array variables into pseudo-instructions of each of the target virtual registers, and the pseudo-instructions are used to read and write the target virtual registers of the array variables; according to the size of each of the array variables, set the sub-register index of the operand of each of the target virtual registers; based on the sub-register index, allocate the corresponding general physical register to each of the target virtual registers, so that the register allocation of the array variables is converted into the allocation process of the general physical registers for the target virtual registers, thereby realizing the dynamic allocation of the general physical registers of the array variables and improving the GPU efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0056] FIG1 is a schematic diagram of a flow chart of a register allocation method in one embodiment;
[0057] FIG2 is a schematic diagram of an intermediate expression instruction after instruction selection in one embodiment;
[0058] FIG3 is a control flow chart of a program in one embodiment;
[0059] FIG4 is a control flow diagram after a memory read / write instruction is converted into a virtual register read / write instruction in one embodiment;
[0060] FIG5 is a diagram showing an example of instruction numbering in one embodiment;
[0061] FIG6 is a flow chart of a register allocation algorithm in one embodiment;
[0062] FIG7 is a schematic diagram of a register allocation result in one embodiment;
[0063] FIG8 is a schematic diagram of a register allocation result in another embodiment;
[0064] FIG9 is a schematic diagram of an example code in one embodiment;
[0065] FIG10 is a block diagram of a register allocation device in one embodiment;
[0066] FIG. 11 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION
[0067] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0068] In one embodiment, as shown in FIG1 , a register allocation method is provided. This embodiment is illustrated by applying the method to a terminal. It is understandable that the method can also be applied to a server, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. In this embodiment, the method includes the following steps:
[0069] S102: Obtain the instruction to be processed, and determine the array variable in the instruction to be processed.
[0070] The instructions to be processed include array variables, as shown in Figure 2. The code is the intermediate expression instruction after the instruction selection. Each instruction has been numbered. BCOND is a conditional jump, B is an unconditional jump, PM_RD and PM_WR are memory read and write instructions, and fi# records the memory information to be accessed by the current instruction, including the memory address and size. The array variable exists in the form of fi# after the instruction selection. The PM_RD instruction numbered 32 reads a DWORD data from the memory location with fi0 as the base and vreg2 as the offset and puts it into vreg7. At the same time, this instruction also indicates reading the vreg2th element of array variable 0. Non-array variables exist in the form of virtual register vreg#. The address of fi0 is 0 and the size is 24 bytes. The address of fi1 is 24 and the size is 28 bytes. The memory size is consistent with the size of the array variable. In the code in Figure 3, there are two array variables that need to be allocated registers fi0 and fi1.
[0071] An array variable is a variable that includes multiple variables.
[0072] S104: Create corresponding target virtual registers for each array variable.
[0073] The target virtual register is the object of register allocation. In order to implement register allocation for array variables, a new register type is defined in this application.
[0074] In one optional embodiment, each target virtual register includes N consecutive general physical registers, the N general physical registers are sub-registers of the target virtual register, and N is a positive integer.
[0075] For example, the new register type may be V32REG, whose members include V32R0 to V32R224, a total of 225. V32R0 is essentially a combination of 32 consecutive general physical registers R0, R1, R2, R3, ..., R31, and general physical registers R0 to R31 are the 32 sub-registers of V32R0; V32R1 is a combination of 32 consecutive general physical registers R1, R2, R3, R4, ..., R32, and general physical registers R1 to R32 are the 32 sub-registers of V32R1; V32R224 is a combination of 32 consecutive general physical registers R224, R225, R226, R227, ..., R255, and general physical registers R224 to R255 are the 32 sub-registers of V32R224; and the same applies to the others. The hardware has 256 consecutive general physical registers R0, R1, R2, R3, ..., R255, so the members of V32REG include V32R0, V32R1, V32R2, V32R3, V32R4, ..., V32R224, a total of 225. Each V32REG type register has 32 sub-registers, and there are 32 sub-register indexes sub0, sub1, sub2, ..., sub31, which represent the index of the sub-register in the parent register. V32R0:sub0 means the first subregister R0 of V32R0, V32R0:sub1 means the second subregister R1 of V32R0, V32R0:sub2 means R2, V32R0:sub31 means R31, V32R5:sub31 means R36, V32R5:sub30 means R35, V32R4:sub31 means R35. Generally, V32Ri:subj means R(i+j). Multiple subregister indexes can be combined and spliced to form a new subregister index, for example, sub0 and sub1 are spliced to obtain sub0_sub1, and V32R3:sub0_sub1 represents R0 and R1; sub0, sub1, sub2, sub3 and sub4 are spliced to form sub0_sub4, and V32R3:sub0_sub4 represents R0, R1, R2, R3 and R4; in general, V32Ri:subj_subk represents R(i+j) to R(i+k), a total of k-j+1 subregisters. The combination and splicing of subregister indexes can only be continuous, for example, sub0 and sub2 cannot be spliced because they span sub1. One point that needs to be explained is that each target virtual register includes 32 subregisters for explanation here. In other embodiments, the number of subregisters included in each target virtual register can be other values, and the number of general physical registers can also be other values, which are not specifically limited here.
[0076] As shown in FIG. 3 , two target virtual registers vreg11 and vreg12 of the V32REG type are created for fi0 and fi1 respectively.
[0077] S106: Convert the read and write instructions of each array variable into pseudo instructions of each target virtual register, where the pseudo instructions are used to read and write the target virtual register of the array variable.
[0078] Define two pseudo instructions extract and insert to read and write virtual registers of array variables, and convert memory read and write instructions into register read and write instructions.
[0079] S108: According to the size of each array variable, set the sub-register index of the operand of each target virtual register.
[0080] The size of an array variable is the number of variables in the array variable, the operand is the data to be stored in the target virtual register, and the subregister index is the subregister of the target virtual register corresponding to the operand. The subregister index can be used to determine the location where the data to be written is to be written, or the location of the data to be read.
[0081] Taking instruction 8 in Figure 3 as an example, vreg1 is the data to be written, vreg2 is the memory address where the data will be written, and the memory size recorded in fi0 is 24 bytes. Converted to instruction 8 in Figure 4, each general physical register R# is of DWORD type, so fi0 needs to use the first 6 sub-registers of vreg11. vreg11:sub0_sub5 represents the first 6 consecutive general sub-registers of vreg11. vreg1 is the data to be written, which is of DWORD type. vreg2 represents the index number of one of the 6 consecutive general sub-registers, that is, the location where the data vreg1 to be written is to be written. The value range of vreg2 is 0 to 5.
[0082] Instruction 32 in Figure 4 is converted from instruction 32 in Figure 3. PM_RD reads a DWORD data from the memory at address vreg2 and writes it to vreg7. Instruction 32 in Figure 2 takes the general subregister with index number vreg2 from the first 6 consecutive general subregisters of vreg11 and writes the result to vreg7. The semantics are the same before and after the instruction conversion. The only difference is that the reading and writing of 24-byte memory is replaced by the reading and writing of 6 consecutive general physical registers.
[0083] S110: Allocate a corresponding general physical register to each target virtual register based on the sub-register index.
[0084] After the target virtual register corresponding to each array variable and the sub-register index of the operand corresponding to the target virtual register are determined, the corresponding general physical register can be allocated to each target virtual register.
[0085] Specifically, based on the sub-register index, a corresponding general physical register is allocated to each target virtual register, including: determining a unique general physical register based on the target virtual register index and the sub-register index, and allocating the target virtual register to the corresponding general physical register.
[0086] As mentioned above, V32Ri:subj_subk indicates that there are k-j+1 sub-registers from R(i+j) to R(i+k). In this way, based on the relationship between the sub-registers and the general physical registers, the target virtual register is allocated to the corresponding general physical register.
[0087] The register allocation method, apparatus, computer device, computer-readable storage medium and computer program product described above, after obtaining the instructions to be processed, determine the array variables in the instructions to be processed; create corresponding target virtual registers for each array variable; convert the read and write instructions of each array variable into pseudo-instructions of each target virtual register, the pseudo-instructions being used to read and write the target virtual registers of the array variables; set the sub-register index of the operand of each target virtual register according to the size of each array variable; and allocate corresponding general physical registers to each target virtual register based on the sub-register index, so that the register allocation of the array variables is converted into the process of allocating general physical registers to the target virtual registers, thereby realizing the dynamic allocation of general physical registers of the array variables and improving the GPU efficiency.
[0088] In one of the optional embodiments, a corresponding universal physical register is allocated to each target virtual register based on a sub-register index, including: detecting whether there is a conflict when allocating the target virtual register to the current universal physical register based on the sub-register index; if there is no conflict, allocating the target virtual register to the current universal physical register; if there is a conflict and all universal physical registers have not been traversed, obtaining the next universal physical register as the current universal physical register, until there is no conflict, at which point the target virtual register is allocated to the current universal physical register.
[0089] In one of the optional embodiments, the method also includes: in the case where there is a conflict and all general physical registers have been traversed, obtaining a first weight corresponding to the virtual register to which the general physical register has been allocated, the first weight being determined based on the usage frequency of the array variable corresponding to the virtual register to which the general physical register has been allocated; in the case where the first weight is less than the second weight corresponding to the target virtual register, releasing the general physical register corresponding to the virtual register to which the general physical register has been allocated, and allocating the target virtual register to the released general physical register.
[0090] Among them, when allocating registers, it is possible to detect whether there is a conflict when allocating the target virtual register to the current general physical register based on the sub-register index. The conflict here may include a conflict in the active interval. If there is no conflict, the target virtual register is allocated to the current general physical register.
[0091] When there is a conflict and all general physical registers have not been traversed, the next general physical register is obtained as the current general physical register until there is no conflict, and the target virtual register is allocated to the current general physical register.
[0092] In the case of a conflict and all general physical registers have been traversed, the first weight corresponding to the virtual register to which the general physical register has been allocated is obtained, and the first weight is determined based on the use frequency of the array variable corresponding to the virtual register to which the general physical register has been allocated, so that in the case where the first weight is less than the second weight corresponding to the target virtual register, the general physical register corresponding to the virtual register to which the general physical register has been allocated is released, and the target virtual register is allocated to the released general physical register. In the case where the first weight is greater than or equal to the second weight corresponding to the target virtual register, the target virtual register is overflowed to the memory.
[0093] In one of the optional embodiments, a corresponding general physical register is allocated to each target virtual register based on a subregister index, including: obtaining an active interval of each target virtual register; setting a mask for active subregisters in each active interval based on the subregister index; in the case where masks of subregisters overlap, detecting whether there is a conflict between active intervals of subregisters; and allocating a corresponding general physical register to each target virtual register based on the conflict detection result.
[0094] For ease of understanding, FIG. 5 and FIG. 6 are combined, where FIG. 5 is an example diagram of instruction encoding in an embodiment, and FIG. 6 is a schematic diagram of a register allocation step in an embodiment.
[0095] Before register allocation, the compiler first numbers all instructions in ascending order, as shown in Figure 5. The compiler creates a virtual register for each non-array variable. The virtual register is the object of the register allocation algorithm. Then the compiler calculates the active range for each virtual register. The active range is the range of use of the virtual register in the program. Taking vreg0 and vreg3 in Figure 1 as examples, their active ranges are [0, 48), [80, 128) and [16, 48) respectively.
[0096] As shown in FIG6 , all virtual registers will be put into a queue, and then they will be taken out from the queue in turn to be assigned general physical registers. First, the current virtual register will be tried to be assigned to the general physical register R0, and then the active interval conflicts between the virtual registers that have been assigned to the general physical register R0 and the current target virtual register will be checked. The so-called conflict check is to see whether the two active intervals overlap. If the conflict check passes, it means that the current virtual register can be assigned to the physical register Ri, and then the active interval of the current virtual register is placed in the active interval set corresponding to Ri. If the conflict check fails, the current target virtual register will be tried to be assigned to the general physical registers R0, R1, R2, etc. in turn. If all general physical registers fail to be assigned, try to evict other virtual registers with small weights, that is, put the virtual registers that have been assigned to the general physical registers back into the queue, and assign the general physical register Rx that has been assigned to it to the current virtual register. If the eviction is successful, the active interval of the current virtual register will be added to the active interval set corresponding to the general physical register Rx. If the eviction fails, it means that the weight of the current virtual register is the smallest and it overflows into the memory, and the current virtual register allocation ends. The above process is repeated for all virtual registers in the queue until the queue is empty.
[0097] In one of the optional embodiments, the active interval of each target virtual register is obtained, including: starting from each read pseudo-instruction corresponding to the target virtual register, reversely searching for the write pseudo-instruction of the target virtual register along the control flow graph of the instruction to be processed; when the write pseudo-instruction of the target virtual register is searched, the active interval of the target virtual register is obtained based on each read pseudo-instruction and the searched write pseudo-instruction.
[0098] Before register allocation, the active interval of each virtual register must be calculated. The basic logic of the calculation is to start from each use instruction (instruction that uses the current register) of the virtual register and search all def instructions (instructions that write the current register) of the current virtual register in reverse along the CFG. When a def instruction is encountered, the current path search is stopped. The instructions scanned in the middle are all in the active interval of the current virtual register. The use instruction here is a read pseudo instruction, and the def instruction is a write pseudo instruction.
[0099] Take vreg12 as an example. The only use instruction of vreg12 is instruction 36 in Figure 4. Starting from instruction 36 in Figure 4, reverse search is performed. Instructions 32 and 28 are not def instructions of vreg12. Then it is divided into two paths B1 and B2. Instruction 12 of B1 is def instruction of vreg12. The search of B1 path is stopped and the search of B2 path is started. Instruction 20 of B2 is def instruction of vreg12 and the search is stopped. Therefore, the final active interval of vreg12 is [12, 36].
[0100] Basic block B3 uses virtual registers vreg11 and vreg12 of array variables. The entry basic block is B0. There are two paths from B0 to B3, namely B0-B1-B3 and B0-B2-B3. For vreg12, there are fixed values on both paths, which are instructions 12 and 20 in Figure 4.
[0101] In one of the optional embodiments, starting from each read pseudo-instruction corresponding to the target virtual register, before reversely searching for the write pseudo-instruction of the target virtual register along the control flow graph of the instruction to be processed, it also includes: inserting an implicit fixed value instruction in the control flow graph, the implicit fixed value instruction is used to remove the inactive interval of the target virtual register; starting from each read pseudo-instruction corresponding to the target virtual register, reversely searching for the write pseudo-instruction of the target virtual register along the control flow graph of the instruction to be processed, including: starting from each read pseudo-instruction corresponding to the target virtual register, reversely searching along the control flow graph of the instruction to be processed; in the case of searching for the inserted implicit fixed value instruction, stopping the search along the current path of the control flow graph; in the case of searching for the inserted implicit fixed value instruction, continuing the search along the current path of the control flow graph until the write pseudo-instruction of the target virtual register is obtained.
[0102] Among them, for vreg11, there is only one path with a constant value, which is instruction 8 in Figure 4. According to the above active interval calculation logic, B2 will be included in the active interval of vreg11, but according to the original semantics, vreg11 is only active in B1 and B3. This situation will expand the active interval of vreg11 and increase the pressure of register allocation. Therefore, it is necessary to insert an implicit constant instruction implicit_def before the jump instruction 24 in B2, so that when the instruction 22 of B2 is searched during the calculation of the active interval, the search will stop, which can reduce the active interval of vreg11.
[0103] Therefore, in the process of detecting the active interval, starting from each read pseudo instruction corresponding to the target virtual register, the control flow chart of the instruction to be processed is searched in reverse. If an implicit fixed value instruction is found, the search of the current path is stopped. If no implicit fixed value instruction is found, the search of the current path is continued until the write pseudo instruction is found. Then, based on the position of each read pseudo instruction and the position of the write pseudo instruction, the active interval corresponding to the target virtual register is determined.
[0104] The insertion position of the implicit fixed value instruction mentioned above can be determined in advance. In one of the optional embodiments, the implicit fixed value instruction is inserted into the control flow chart, including: obtaining the target instruction block where the write pseudo-instruction corresponding to each target virtual register in the control flow chart of the instruction to be processed is located, and taking the instruction block that can be reached by the target instruction block and the target instruction block as the first instruction block; taking the instruction blocks in the control flow chart except the first instruction block as the second instruction block; marking the read pseudo-instruction corresponding to the target virtual register in the second instruction block as undefined, and the undefined read pseudo-instruction is ignored during the search process; starting from the read pseudo-instruction of the target virtual register in the first instruction block, reversely searching for the write pseudo-instruction of the target virtual register along the control flow chart; during the search process, when the second instruction block is reached from the first instruction block, stop the search and insert the implicit fixed value instruction at the end of the second instruction block.
[0105] Among them, the instruction block block where all def instructions (i.e., write pseudo instructions) of the current target virtual register in the control flow graph CFG are located is taken as the target instruction block, for example, dyed with the first color, such as black, and then the instruction block block that can be reached by the target instruction block in the control flow graph CFG, such as the black instruction block block, is also dyed with the first color, i.e., black, and these instruction blocks dyed black are the first instruction blocks. Then the remaining instruction blocks in the control flow graph CFG are taken as the second instruction block, for example, dyed with the second color, such as white. All use instructions of the current virtual register in the white instruction block block are marked as undefined, wherein the undefined use is ignored when calculating the active interval, and then the def instruction of the current virtual register is searched in reverse along the control flow graph CFG starting from the use instruction of the current virtual register in the black instruction block block. When the def instruction is encountered, the current path search is stopped. If the white instruction block block is encountered from the black instruction block block, the current path search is stopped, and the implicit constant instruction implicit_def is inserted at the end of the white instruction block block encountered.
[0106] According to the above method, live intervals are created for vreg11 and vreg12 respectively. Liveinterval11 is equal to [[8,20):0x3F,[28, 36):0x3F], and liveinterval12 is equal to [[12, 36]:0xFF]. The mask of liveinterval11 of vreg11 is 0x3F. Because its subregister index is sub0_sub5, only the first 6 subregisters are used, so the lower 6 bits of the mask are 1. Similarly, the mask of liveinterval12 of vreg12 is 0xFF.
[0107] During the register allocation process, when an active interval is allocated to a physical register, the register allocation algorithm will put the active interval into the active interval set corresponding to the subregister of the physical register. Assume that the active interval liveinterval11 of vreg11 has been allocated to V32R7, then liveinterval11 will be put into the active interval set corresponding to the subregisters R7, R8, R9, R10, R11 and R12 of V32R7. liveinterval11 will not be put into the container corresponding to the subregisters R13 to R38 of V32R7, because the mask of liveinterval11 is 0x3F, which means that only the first 6 subregisters are used.
[0108] When allocating physical registers for the active interval liveinterval12 of vreg12, it is necessary to test from V32R0 to V32R223 in sequence. When trying to allocate liveinterval12 to V32R0, according to the mask 0xFF of liveinterval12, it is only necessary to check the conflicts between all active intervals in the containers corresponding to the subregisters R0 to R7 of V32R0 and liveinterval12. There is no need to check R8 to R31, because the mask 0xFF means that only the first 8 subregisters of V32R0 are used. According to the above assumptions, liveinterval11 is already in the container corresponding to R7, and liveinterval11 and liveinterval12 conflict, so liveinterval12 cannot be allocated to V32R0. When trying to assign liveinterval12 to V32R1, liveinterval11 is already in the containers corresponding to R7 and R8, and liveinterval11 conflicts with liveinterval12, so liveinterval12 cannot be assigned to V32R1. After testing one by one, all active intervals corresponding to subregisters R13 to R20 of V32R13 do not conflict with liveinterval12, so liveinterval12 is assigned to V32R13.
[0109] As shown in FIG. 7 , FIG. 7 is a result of the register allocation algorithm allocating physical registers to each virtual register, and the virtual registers vreg11 and vreg12 of the array variable are allocated to the physical registers V32R7 and V32R13 respectively.
[0110] In one of the optional embodiments, after allocating a corresponding universal physical register to each target virtual register based on the sub-register index, the method includes: converting the pseudo instructions of the target virtual register allocated to the universal physical register into read and write instructions for the universal physical register; and converting the pseudo instructions of the target virtual register not allocated to the universal physical register into memory read and write instructions.
[0111] The pseudo instructions insert and extract in FIG4 are converted into read and write instructions of general physical registers, and the result is shown in FIG8. Taking instruction 8 in FIG4 as an example, it is converted into instruction 8 in FIG8, vreg1 is assigned to physical register R1, vreg2 is assigned to physical register R2, and the MOV instruction writes R1 into the general physical register indexed by R2+7, where 7 represents the number of the first general sub-register R7 of V32R7. Taking instruction 36 in FIG4 as an example, it is converted into instruction 36 in FIG8, vreg9 and vreg10 are assigned to physical registers R1 and R3 respectively, and the MOV instruction writes the general physical register indexed by R3+13 into R1, where 13 represents the number of the first general sub-register R13 of V32R13.
[0112] The sample code in FIG9 is very common in shaders. Assuming that the memory size of fi0 is 16 bytes, there are 5 available physical registers, namely R0, R1, R2, R3 and R4. If the existing array variable register allocation method is used, physical registers R0, R1, R2 and R3 will be allocated to the array variable fi0, then vreg0 will be allocated to R4, and vreg1 will overflow to the memory. Obviously, this is extremely unreasonable, because fi0 is read and written twice in the entire program, and vreg1 is read and written 20 times. vreg1 has a higher weight, and the final number of memory accesses by the program is 20. If the method of this application is used, vreg1 has a higher weight and will be allocated to the physical register first, and fi0 will remain in the memory. Finally, the number of memory accesses of the entire program is 2, which will have better performance.
[0113] In the above embodiment, array variables can also participate in the register algorithm, and which variables are placed in the register and which variables are placed in the memory are determined according to the weight, so as to more effectively utilize the physical registers.
[0114] It should be understood that, although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.
[0115] Based on the same inventive concept, the embodiment of the present application also provides a register allocation device for implementing the register allocation method involved above. The implementation solution provided by the device to solve the problem is similar to the implementation solution recorded in the above method, so the specific limitations in one or more register allocation device embodiments provided below can refer to the limitations of the register allocation method above, and will not be repeated here.
[0116] In an exemplary embodiment, as shown in FIG. 10 , a register allocation device is provided, comprising: an array variable determination module 1001, a virtual register creation module 1002, an instruction conversion module 1003, a sub-register index setting module 1004 and an allocation module 1005, wherein:
[0117] An array variable determination module 1001 is used to obtain the instruction to be processed and determine the array variables in the instruction to be processed;
[0118] A virtual register creation module 1002 is used to create corresponding target virtual registers for each array variable;
[0119] An instruction conversion module 1003, used to convert the read and write instructions of each array variable into each pseudo instruction of each target virtual register, where the pseudo instruction is used to read and write the target virtual register of the array variable;
[0120] A sub-register index setting module 1004, used to set the sub-register index of the operand of each target virtual register according to the size of each array variable;
[0121] The allocation module 1005 is used to allocate a corresponding general physical register to each target virtual register based on the sub-register index.
[0122] In one of the optional embodiments, each target virtual register includes N consecutive general physical registers, the N general physical registers are sub-registers of the target virtual register, and N is a positive integer; the above-mentioned allocation module 1005 is specifically used to determine a unique general physical register based on the target virtual register index and the sub-register index, and allocate the target virtual register to the corresponding general physical register.
[0123] In one of the optional embodiments, the allocation module 1005 is specifically used to detect whether there is a conflict when allocating the target virtual register to the current general physical register based on the sub-register index; if there is no conflict, the target virtual register is allocated to the current general physical register; if there is a conflict and all general physical registers have not been traversed, the next general physical register is obtained as the current general physical register, until there is no conflict, the target virtual register is allocated to the current general physical register.
[0124] In one of the optional embodiments, the allocation module 1005 is specifically used to obtain a first weight corresponding to a virtual register to which a general physical register has been allocated when there is a conflict and all general physical registers have been traversed, the first weight being determined based on a usage frequency of an array variable corresponding to the virtual register to which a general physical register has been allocated; when the first weight is less than a second weight corresponding to a target virtual register, release the general physical register corresponding to the virtual register to which a general physical register has been allocated, and allocate the target virtual register to the released general physical register.
[0125] In one of the optional embodiments, the allocation module 1005 is specifically used to obtain the active interval of each target virtual register; based on the sub-register index, set a mask for the active sub-registers in each active interval; when the masks of the sub-registers overlap, detect whether there is a conflict between the active intervals of the sub-registers; and allocate a corresponding general physical register to each target virtual register based on the conflict detection result.
[0126] In one of the optional embodiments, the above-mentioned allocation module 1005 is specifically used to start from each read pseudo-instruction corresponding to the target virtual register, and reversely search for the write pseudo-instruction of the target virtual register along the control flow graph of the instruction to be processed; when the write pseudo-instruction of the target virtual register is searched, the active interval of the target virtual register is obtained based on each read pseudo-instruction and the searched write pseudo-instruction.
[0127] In one of the optional embodiments, the above-mentioned allocation module 1005 is specifically used to insert implicit fixed value instructions in the control flow graph, and the implicit fixed value instructions are used to remove the inactive interval of the target virtual register; starting from each read pseudo-instruction corresponding to the target virtual register, reverse search along the control flow graph of the instruction to be processed; when the insert implicit fixed value instruction is found, stop searching along the current path of the control flow graph; when the insert implicit fixed value instruction is not found, continue searching along the current path of the control flow graph until the write pseudo-instruction of the target virtual register is obtained.
[0128] In one of the optional embodiments, the above-mentioned allocation module 1005 is specifically used to obtain the target instruction block where the write pseudo-instruction corresponding to each target virtual register is located in the control flow chart of the instruction to be processed, and take the instruction block that can be reached by the target instruction block and the target instruction block as the first instruction block; take the instruction block other than the first instruction block in the control flow chart as the second instruction block; mark the read pseudo-instruction corresponding to the target virtual register in the second instruction block as undefined, and the undefined read pseudo-instruction is ignored during the search process; starting from the read pseudo-instruction of the target virtual register in the first instruction block, reversely search for the write pseudo-instruction of the target virtual register along the control flow chart; during the search process, when the second instruction block is reached from the first instruction block, stop the search and insert an implicit constant instruction at the end of the second instruction block.
[0129] In one of the optional embodiments, the above-mentioned device also includes: a conversion module, which is used to convert pseudo instructions of target virtual registers allocated to general physical registers into read and write instructions for general physical registers; and convert pseudo instructions of target virtual registers not allocated to general physical registers into memory read and write instructions.
[0130] Each module in the register allocation device can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.
[0131] In an exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be shown in FIG11. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, the memory, and the input / output interface are connected via a system bus, and the communication interface, the display unit, and the input device are connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner may be implemented through WIFI, a mobile cellular network, near field communication (NFC) or other technologies. When the computer program is executed by the processor, a register allocation method is implemented. The display unit of the computer device is used to form a visually visible picture, which may be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.
[0132] Those skilled in the art will understand that the structure shown in FIG. 11 is merely a block diagram of a partial structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.
[0133] In one embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above method embodiments when executing the computer program.
[0134] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.
[0135] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.
[0136] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.
[0137] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.
[0138] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.
Claims
1. A register allocation method, characterized in that: The method comprises: Obtaining instructions to be processed, and determining array variables in the instructions to be processed; Creating corresponding target virtual registers for each of the array variables; Converting the read and write instructions of each array variable into pseudo instructions of each target virtual register, wherein the pseudo instructions are used to read and write the target virtual register of the array variable; According to the size of each array variable, setting the sub-register index of the operand of each target virtual register; Based on the sub-register index, a corresponding general physical register is allocated to each of the target virtual registers.
2. The method according to claim 1, characterized in that Each of the target virtual registers includes N consecutive general physical registers, the N general physical registers are sub-registers of the target virtual register, and N is a positive integer; The allocating a corresponding general physical register to each of the target virtual registers based on the sub-register index includes: A unique general physical register is determined based on the target virtual register index and the sub-register index, and the target virtual register is allocated to the corresponding general physical register.
3. The method according to claim 2, characterized in that The allocating a corresponding general physical register to each of the target virtual registers based on the sub-register index includes: detecting whether there is a conflict when allocating the target virtual register to the current general physical register based on the sub-register index; In the absence of a conflict, allocating the target virtual register to the current general physical register; If there is a conflict and all the general physical registers have not been traversed, the next general physical register is obtained as the current general physical register, until there is no conflict, the target virtual register is allocated to the current general physical register.
4. The method according to claim 3, characterized in that The method further comprises: In the case where there is a conflict and all the general physical registers have been traversed, obtaining a first weight corresponding to the virtual register to which the general physical register has been allocated, wherein the first weight is determined based on a usage frequency of an array variable corresponding to the virtual register to which the general physical register has been allocated; When the first weight is less than the second weight corresponding to the target virtual register, the general physical register corresponding to the virtual register to which the general physical register has been allocated is released, and the target virtual register is allocated to the released general physical register.
5. The method according to any one of claims 1 to 4, characterized in that: The allocating a corresponding general physical register to each of the target virtual registers based on the sub-register index includes: Obtaining an active interval of each of the target virtual registers; Based on the subregister index, setting a mask for each active subregister in the active interval; In case the masks of the sub-registers overlap, detecting whether there is a conflict between active intervals of the sub-registers; A corresponding general physical register is allocated to each of the target virtual registers based on the conflict detection result.
6. The method according to claim 5, characterized in that The obtaining of the active interval of each of the target virtual registers includes: Starting from each read pseudo instruction corresponding to the target virtual register, searching for a write pseudo instruction of the target virtual register in reverse order along the control flow graph of the instruction to be processed; In the case where a write pseudo instruction of the target virtual register is searched, an active range of the target virtual register is obtained based on each of the read pseudo instructions and the searched write pseudo instruction.
7. The method according to claim 6, characterized in that Before the step of starting from each read pseudo instruction corresponding to the target virtual register and searching for a write pseudo instruction of the target virtual register in reverse order along the control flow chart of the instruction to be processed, the step further includes: Inserting an implicit fixed value instruction in the control flow graph, wherein the implicit fixed value instruction is used to remove an inactive interval of the target virtual register; Starting from each read pseudo instruction corresponding to the target virtual register, searching reversely along the control flow chart of the instruction to be processed for the write pseudo instruction of the target virtual register includes: Starting from each read pseudo instruction corresponding to the target virtual register, searching in reverse along the control flow graph of the instruction to be processed; When an implicit fixed value instruction is found, the search along the current path of the control flow graph is stopped; When the insert implicit value instruction is not found, the search along the current path of the control flow graph is continued until a write pseudo instruction of the target virtual register is obtained.
8. The method according to claim 7, characterized in that The inserting of an implicit fixed value instruction into the control flow chart comprises: Obtain the target instruction block where the write pseudo instruction corresponding to each target virtual register is located in the control flow chart of the instruction to be processed, and use the instruction block that can be reached by the target instruction block and the target instruction block as the first instruction block; Using the instruction blocks in the control flow chart other than the first instruction block as the second instruction block; Marking the read pseudo instruction corresponding to the target virtual register in the second instruction block as undefined, whereby the undefined read pseudo instruction is ignored during the search process; Starting from the read pseudo instruction of the target virtual register in the first instruction block, searching for the write pseudo instruction of the target virtual register in reverse along the control flow graph; During the search process, when the second instruction block is reached from the first instruction block, the search is stopped and an implicit constant instruction is inserted at the end of the second instruction block.
9. The method according to any one of claims 1 to 4, characterized in that: After allocating a corresponding general physical register to each of the target virtual registers based on the sub-register index, the method includes: Converting a pseudo instruction of the target virtual register allocated to the general physical register into a read and write instruction for the general physical register; The pseudo instruction of the target virtual register that is not allocated to the general physical register is converted into a memory read / write instruction.
10. A register allocation device, characterized in that: The device comprises: An array variable determination module, used for obtaining instructions to be processed and determining array variables in the instructions to be processed; A virtual register creation module, used for creating corresponding target virtual registers for each array variable; An instruction conversion module, used for converting the read and write instructions of each array variable into pseudo instructions of each target virtual register, wherein the pseudo instructions are used for reading and writing the target virtual register of the array variable; A sub-register index setting module, used for setting the sub-register index of the operand of each target virtual register according to the size of each array variable; An allocation module is used to allocate a corresponding general physical register to each of the target virtual registers based on the sub-register index.
11. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 9 are implemented.
12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.
13. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.