Image data caching device and method, electronic equipment and storage medium

Abstract

The invention provides an image data caching device and method, electronic equipment and a storage medium, and particularly relates to the technical field of image data caching. The device comprises a first Data Mover module which is used for acquiring a write-in instruction sent by a DSP (Digital Signal Processor) module; the second Data Mover module is used for acquiring a reading instruction sent by the DSP module; the second Data Mover module is further used for reading the image data in the DDR module into the first FIFO module according to the reading instruction; the DSP module is used for reading the image data in the first FIFO module if the first FIFO module has the readable data identifier; the DSP module is also used for generating target position information according to the image data; the DSP module is also used for sending the target position information to the second FIFO module; and the first Data Mover module is also used for writing the target position information in the second FIFO module into the DDR module according to the writing instruction if the second FIFO module is not empty. According to the device, the reading and writing work of the DSP module can be carried out at the same time, and the efficiency of data transmission between the DSP module and the DDR module is improved.

Description

Technical Field

[0001] The present application relates to the technical field of image data caching, and in particular to an image data caching device, method, electronic device and storage medium. Background Art

[0002] In the infrared guidance system, the capture, tracking, and identification of image targets are its main tasks, and tracking and identification are achieved through real-time processing of high-reliability digital images by the control and processing board. Therefore, high-speed and reliable image transmission is one of the important indicators that affect the performance of tracking and identification. The control and processing board realizes the reception, processing, and output of digital images. The control and processing board sends the acquired image data to DDR for storage. The DSP (Digital Signal Processing) module reads the image data from the DDR (Double Data Rate) module, processes the image data, obtains the processing results, and then writes the processing results into the DDR double data rate synchronous dynamic random access memory module so that DDR can send the processing results to the integrated control machine for further processing.

[0003] However, in practical applications, the DSP digital signal processing module cannot read image data from the DDR double data rate synchronous dynamic random access memory module and write processing results to the DDR double data rate synchronous dynamic random access memory module at the same time, which affects the efficiency of data transmission.

[0004] Therefore, the reading and writing work of the DSP digital signal processing module cannot be performed simultaneously, and low data transmission efficiency is an existing problem.

[0005] Application Contents

[0006] In view of this, the purpose of the present application is to provide an image data caching device, method, electronic device and storage medium to solve the above-mentioned problems, realize the simultaneous reading and writing of the DSP digital signal processing module, and improve the data transmission efficiency.

[0007] In a first aspect, an embodiment of the present application provides an image data cache device, the device comprising: an FPGA field programmable gate array module, a first end of the FPGA field programmable gate array module is connected to a DSP digital signal processing module, and a second end is connected to a DDR double data rate synchronous dynamic random access memory module; the FPGA field programmable gate array module comprises a first Data Mover transport module, a second Data Mover transport module, a first FIFO first-in first-out queue module, and a second FIFO first-in first-out queue module;

[0008] The first Data Mover transport module is used to obtain the write instruction sent by the DSP digital signal processing module;

[0009] The second Data Mover transport module is used to obtain the read instruction sent by the DSP digital signal processing module, and read the image data in the DDR double data rate synchronous dynamic random access memory module into the first FIFO first-in first-out queue module according to the read instruction; wherein the image data is used to characterize the characteristics of the target object;

[0010] The DSP digital signal processing module is used to read the image data in the first FIFO first-in first-out queue module if the first FIFO first-in first-out queue module has a readable data identifier, and generate target position information according to the image data; wherein the target position information is used to characterize the moving trajectory of the target object, and the target position information is sent to the second FIFO first-in first-out queue module;

[0011] The first Data Mover transport module is further used to write the target location information in the second FIFO first-in first-out queue module into the DDR double data rate synchronous dynamic random access memory module according to the write instruction if the second FIFO first-in first-out queue module is not empty.

[0012] Preferably, the write instruction includes a first destination address and a first data length; the first destination address is the location of the target location information in the DDR double data rate synchronous dynamic random access memory module, and the first data length is the memory occupied by the target location information; the FPGA field programmable gate array module also includes: a MIG memory interface generator interface;

[0013] The first Data Mover transport module is specifically used to determine the first base address corresponding to the target location information in the DDR double data rate synchronous dynamic random access memory module through the first destination address, take the first base address as the starting point, divide the memory of the DDR double data rate synchronous dynamic random access memory module according to the first data length, obtain a first memory space, and write the target location information into the first memory space in the DDR double data rate synchronous dynamic random access memory module through the MIG memory interface generator interface.

[0014] Preferably, the read instruction includes a second destination address and a second data length; the second destination address is the location of the image data in the DDR double data rate synchronous dynamic random access memory module, and the second data length is the memory occupied by the image data;

[0015] The second Data Mover transport module is specifically used to determine the second base address corresponding to the image data in the DDR double data rate synchronous dynamic random access memory module through the second destination address, and to obtain the image data from the DDR double data rate synchronous dynamic random access memory module through the MIG memory interface generator interface according to the second data length, taking the second base address as the starting point.

[0016] Preferably, the DSP digital signal processing module is further configured to stop reading the image data in the first FIFO first-in first-out queue module if the first FIFO first-in first-out queue module does not have the readable data identifier.

[0017] Preferably, the first Data Mover transport module is further used to stop writing the target location information in the second FIFO first-in first-out queue module into the DDR double data rate synchronous dynamic random access memory module according to the write instruction if the second FIFO first-in first-out queue module is empty.

[0018] Preferably, the FPGA field programmable gate array module further includes an LVDS low voltage differential signal interface, and the LVDS low voltage differential signal interface is connected to the imager;

[0019] The LVDS low voltage differential signal interface is used to obtain the image data sent by the imager;

[0020] The LVDS low voltage differential signal interface is also used to send the image data to the DDR double rate synchronous dynamic random access memory module.

[0021] Preferably, the DDR double data rate synchronous dynamic random access memory module is used to send the target location information to the integrated control machine, so that the integrated control machine controls the drone to track the target object according to the target location information.

[0022] The image data caching device provided by the present application brings the following beneficial effects:

[0023] The present application provides an image data caching device, in which the second Data Mover transport module reads image data from the DDR double rate synchronous dynamic random access memory module according to the read instruction sent by the DSP digital signal processing module, and sends the image data to the first FIFO first-in first-out queue module. The DSP digital signal processing module reads the image data, performs further analysis such as identification and compression, obtains target position information, and sends the target position information to the second FIFO first-in first-out queue module. The first Data Mover transport module writes the target position information in the second FIFO first-in first-out queue module into the DDR double rate synchronous dynamic random access memory module for caching, so that the subsequent DDR double rate synchronous dynamic random access memory module sends the target position information to the integrated control machine for further processing. The device realizes the simultaneous reading and writing of the DSP digital signal processing module, and improves the efficiency of data transmission between the DSP digital signal processing module and the DDR double rate synchronous dynamic random access memory module.

[0024] In a second aspect, the present application further provides an image data caching method, which is applied to an FPGA field programmable gate array module, wherein a first end of the FPGA field programmable gate array module is connected to a DSP digital signal processing module, and a second end is connected to a DDR double data rate synchronous dynamic random access memory module; the FPGA field programmable gate array module includes a first Data Mover transport module, a second Data Mover transport module, a first FIFO first-in first-out queue module, and a second FIFO first-in first-out queue module;

[0025] The first Data Mover transport module obtains a write instruction sent by the DSP digital signal processing module;

[0026] The second Data Mover transport module obtains the read instruction sent by the DSP digital signal processing module, and reads the image data in the DDR double data rate synchronous dynamic random access memory module into the first FIFO first-in first-out queue module according to the read instruction; wherein the image data is used to characterize the characteristics of the target object;

[0027] If the first FIFO first-in first-out queue module has a readable data identifier, the DSP digital signal processing module reads the image data in the first FIFO first-in first-out queue module, and generates target position information according to the image data; wherein the target position information is used to characterize the moving trajectory of the target object, and the target position information is sent to the second FIFO first-in first-out queue module;

[0028] If the second FIFO queue module is not empty, the first Data Mover transport module writes the target location information in the second FIFO queue module into the DDR double data rate synchronous dynamic random access memory module according to the write instruction.

[0029] The image data caching method provided in the embodiment of the present application has the same technical features as the image data caching device provided in the above embodiment, so it can also solve the same technical problems and achieve the same technical effects.

[0030] In a third aspect, the present application also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the beneficial effects of the above-mentioned image data caching method are achieved, which will not be elaborated here.

[0031] In a fourth aspect, the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the beneficial effects of the above-mentioned image data caching method are achieved, which will not be repeated here.

[0032] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The purpose and other advantages of the present application are realized and obtained by the structures particularly pointed out in the description and the drawings.

[0033] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0035] Figure 1 A schematic diagram of the structure of an image data caching device provided by the present application;

[0036] Figure 2 A schematic diagram of the DDR module structure provided in an embodiment of the present application;

[0037] Figure 3 A schematic diagram of a flow chart of an image data caching method provided in an embodiment of the present application;

[0038] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution of the present application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application.

[0040] To facilitate understanding of this embodiment, the embodiments of the present application are described in detail below.

[0041] The present application embodiment provides an image data caching device, such as Figure 1 As shown, Figure 1 A schematic diagram of the structure of an image data cache device provided in the present application. The device is applied to an FPGA (Field-Programmable Gate Array) module 200, the first end of the FPGA module 200 is connected to the DSP module 300, and the second end is connected to the DDR module 400; the FPGA module 200 includes a first Data Mover module 201, a second Data Mover module 202, a first FIFO (First In-First Out) module 203 and a second FIFO module 204; the first Data Mover module 201 is used to obtain a write instruction sent by the DSP module 300; the second Data Mover module 202 is used to obtain a read instruction sent by the DSP module 300; the second Data Mover module 203 is used to obtain a read instruction sent by the DSP module 300; the second Data Mover module 204 is used to obtain a read instruction sent by the DSP module 300; the second Data Mover module 204 is used to obtain a read instruction sent by the DSP module 300; the first Data Mover module 201 is used to obtain a write instruction sent by the DSP module 300; the second Data Mover module 202 is used to obtain a read instruction sent by the DSP module 300; the second Data Mover module 203 is used to obtain a read instruction sent by the DSP module 300; the second Data Mover module 204 is used to obtain a read instruction sent by the DSP module 300; the first Data Mover module 201 ... write instruction sent by the DSP module 300; the second Data M The mover module 202 is also used to read the image data in the DDR module 400 into the first FIFO module 203 according to the read instruction; wherein the image data is used to characterize the characteristics of the target object; the DSP module 300 is used to read the image data in the first FIFO module 203 if the first FIFO module 203 has a readable data identifier; the DSP module 300 is also used to generate target position information based on the image data; wherein the target position information is used to characterize the moving trajectory of the target object; the DSP module 300 is also used to send the target position information to the second FIFO module 204; the first Data Mover module 201 is also used to write the target position information in the second FIFO module 204 into the DDR module 400 according to the write instruction if the second FIFO module 204 is not empty.

[0042] In the image data cache device provided in the embodiment of the present application, the DSP module 300 is a microprocessor specially used for digital signal (audio, video, image, communication) processing, which has a powerful digital signal processing capability and can efficiently perform various complex mathematical operations and algorithms to meet the needs of filtering, enhancing, compressing, identifying and other processing of signals. The DDR module 400 is a synchronous dynamic random access memory with large capacity, high storage rate, low power consumption and small size. The first FIFO module 203 and the second FIFO module 204 can be read in the order in which the data is written.

[0043] The second Data Mover module 202 reads the image data from the DDR module 400 according to the read instruction sent by the DSP module 300, and sends the image data to the first FIFO module 203. The DSP module 300 reads the image data, performs further analysis such as identification and compression, obtains the target position information, and sends the target position information to the second FIFO module 204. The first Data Mover module 201 writes the target position information in the second FIFO module 204 into the DDR module 400 for buffering, so that the DDR module 400 can subsequently send the target position information to the integrated control machine for further processing. In the prior art, the process of the DSP module 300 reading the image data from the DDR module 400 and the DSP module 300 writing the processing result (target position information) into the DDR module 400 cannot be performed at the same time. Compared with the prior art, the device adds the first FIFO module 203, the second FIFO module 204, the first Data Mover module 201 and the second Data Mover module 202. Due to the data first-in-first-out mechanism of the first FIFO module 203 and the second FIFO module 204 and the timely reading and writing mechanism of the first Data Mover module 201 and the second Data Mover module 202, the reading and writing work of the DSP module 300 can be performed simultaneously.

[0044] In the method, the first FIFO module 203 and the second Data Mover module 202 ensure the sequential nature of the process in which the DSP module 300 writes the target location information into the DDR module 400. The second FIFO module 204 and the first Data Mover module 201 ensure the sequential nature of the process in which the DSP module 300 reads the image data from the DDR module 400. The reading and writing operations of the DSP module 300 are performed simultaneously, thereby improving the efficiency of data transmission between the DSP module 300 and the DDR module 400. The method realizes high bandwidth and high access speed of the DSP module 300 to the memory of the DDR module 400 through the read-write arbitration control mechanism of the first FIFO module 203 and the second FIFO module 204. The DSP realizes high-speed read and write control of the parallel data cache in the DDR.

[0045] The first Data Mover module 201 is introduced below. Figure 2 As shown, Figure 2 A schematic diagram of the DDR module structure provided for an embodiment of the present application. The above-mentioned write instruction includes a first destination address and a first data length; the first destination address is the location of the target location information in the DDR module 400, and the first data length is the memory occupied by the target location information; the FPGA module 200 also includes: a MIG (Memory Interface Generator) interface 205; the first DataMover module 201 is specifically used to determine the first base address corresponding to the target location information in the DDR module 400 through the first destination address, and divide the memory of the DDR module 400 according to the first data length with the first base address as the starting point to obtain a first memory space 401, and write the target location information into the first memory space 401 in the DDR module 400 through the MIG interface 205.

[0046] Specifically, the first Data Mover module 201 and the MIG interface 205 and the second FIFO module 204 all exchange data through the AXI communication protocol. The AXI communication protocol is an on-chip bus protocol for high performance, high bandwidth, and low latency, and is used to achieve efficient data transmission between the first Data Mover module 201 and the MIG interface 205, and efficient data transmission between the first Data Mover module 201 and the second FIFO module 204. The target location information obtained by the first Data Mover module 201 from the second FIFO module 204 conforms to the AXI communication protocol format. Before writing the target location information into the DDR module 400, the first Data Mover module 201 needs to determine the location where the target location information is written into the DDR module 400, that is, the first destination address, and divide the first memory space 401 in the DDR module 400 with the first base address corresponding to the first destination address as the starting point, so as to store the target location information through the MIG interface 205, so as to avoid that part or all of the target location information cannot be written into the DDR module 400 due to the failure to divide the first memory space 401.

[0047] The first Data Mover module 201 in the device can divide a first memory space 401 in the DDR module 400 according to the write instruction (the first destination address and the first data length), and write the target location information into the first memory space 401. The target location information written into the DDR module 400 is kept in an orderly arrangement, and it is avoided that part or all of the target location information cannot be written into the DDR module 400.

[0048] The second Data Mover module 202 is introduced below. Figure 2 As shown, Figure 2 A schematic diagram of the DDR module structure provided in an embodiment of the present application. The above-mentioned read instruction includes a second destination address and a second data length; the second destination address is the location of the image data in the DDR module 400, and the second data length is the memory occupied by the image data; the second Data Mover module 202 is specifically used to determine the second base address corresponding to the image data in the DDR module 400 through the second destination address, and obtain the image data from the DDR module 400 through the MIG interface 205 according to the second data length, starting from the second base address.

[0049] Specifically, the above-mentioned AXI communication protocol is an intra-chip bus protocol for high performance, high bandwidth, and low latency, and is used to achieve efficient data transmission between the second Data Mover module 202 and the first FIFO module 203, and efficient data transmission between the second Data Mover module 202 and the MIG interface 205. The image data read by the second Data Mover module 202 from the DDR module 400 through the MIG interface 205 conforms to the AXI (Advanced eXtensible Interface, high-performance extended bus interface) communication protocol format. Before reading the image data from the DDR module 400, the second Data Mover module 202 needs to determine the position of the image data in the DDR module 400, that is, the second destination address, and find the image data that meets the second data length with the second base address corresponding to the second destination address as the starting point. The image data is stored in the second memory space 402, and the size of the second space memory 402 is equal to the second data length. The second Data Mover module 202 reads the image data from the DDR module 400 to avoid incomplete image data read out due to uncertainty of the second data length.

[0050] The second Data Mover module 202 in the device can read the image data that meets the second data length from the DDR module 400 according to the read instruction (the second destination address and the second data length). The above read instruction enables the second Data Mover module 202 to accurately determine the position and data length of the image data in the DDR module 400, thereby ensuring the accuracy of the image data reading and the integrity of the read image data.

[0051] In one implementation, the DSP module 300 is further configured to stop reading the image data in the first FIFO module 203 if the first FIFO module 203 does not have a readable data identifier.

[0052] Specifically, when the DSP module 300 obtains image data from the first FIFO module 203 (the first FIFO module 203 sends image data to the DSP module 300), the first FIFO module 203 will generate a readable data identifier. If the DSP module 300 does not check the readable data identifier, it means that there is no image data in the first FIFO module 203 that can be sent to the DSP module 300 at this time. The DSP module 300 cannot obtain the image data and stops reading the image data.

[0053] The DSP module 300 in the device can determine whether to stop reading image data based on the readable data identifier to avoid the DSP module 300 being in working state for a long time, which will increase the burden on the FPGA module 200, thereby reducing the workload of the FPGA module 200.

[0054] In one implementation, the first Data Mover module 201 is further configured to stop writing the target location information in the second FIFO module 204 into the DDR module 400 according to the write instruction if the second FIFO module 204 is empty.

[0055] Specifically, when the target position information does not exist in the second FIFO module 204 (is empty), it means that the DSP module 300 does not send the target position information to the second FIFO module 204 at this time. At this time, the first Data Mover module 201 cannot obtain the target position information from the second FIFO module 204, that is, it stops writing the target position information in the second FIFO module 204 into the DDR module 400 according to the write instruction.

[0056] The first Data Mover module 201 in the device can determine whether the second FIFO module 204 is empty, and then decide whether to stop writing the target location information in the second FIFO module 204 into the DDR module 400 according to the write instruction. This method avoids the situation where the first Data Mover module 201 is in a working state for a long time, which causes an increase in the burden of the FPGA module 200, and reduces the work burden of the FPGA module 200.

[0057] In one implementation, the FPGA module 200 further includes an LVDS interface, which is connected to the imager 206 ; the LVDS interface is used to obtain image data sent by the imager 206 ; the LVDS interface is also used to send the image data to the DDR module 400 .

[0058] Specifically, the LVDS (Low-Voltage Differential Signaling) interface (not shown in the figure) is a standard electrical interface for high-speed data transmission, which has the characteristics of anti-electromagnetic interference and anti-radio frequency interference. Transmitting image data through the LVDS interface can avoid bit errors or packet loss caused by electromagnetic interference or radio frequency interference.

[0059] In the device, due to the anti-electromagnetic interference and anti-radio frequency interference characteristics of the LVDS interface, the image data acquired by the FPGA module 200 is more accurate, and the packet loss rate and bit error rate of the image data are effectively reduced.

[0060] In one embodiment, the DDR module 400 is used to send the target location information to the integrated control machine, so that the integrated control machine controls the UAV to track the target object according to the target location information.

[0061] Specifically, the DDR module 400 supports the second FIFO module 204 to write the target location information and also supports other devices (integrated control machine) to obtain the target location information. After the integrated control machine obtains the target location information, it analyzes the target location information, selects the target object data in the target location information that meets the characteristics of the target object, and tracks the target object according to the target object data.

[0062] The DDR module 400 in the device simultaneously supports the writing of target position information and the acquisition of target position information by the integrated control machine, and the real-time data reading improves the efficiency of data transmission in the FPGA module 200.

[0063] Based on the above method embodiment, the present application embodiment also provides an image data caching method, such as Figure 3 As shown, Figure 3 A flowchart of an image data caching method provided in an embodiment of the present application. Applied to an FPGA module, the first end of the FPGA module is connected to the DSP module, and the second end is connected to the DDR module; the FPGA module includes a first Data Mover module, a second Data Mover module, a first FIFO module, and a second FIFO module; the method includes the following steps:

[0064] S301: The first Data Mover module obtains a write instruction sent by a DSP module.

[0065] S302: The second Data Mover module obtains a read instruction sent by the DSP module.

[0066] S303, the second Data Mover module reads the image data in the DDR module into the first FIFO module according to the read instruction; wherein the image data is used to characterize the features of the target object.

[0067] S304: If the first FIFO module has a readable data identifier, the DSP module reads the image data in the first FIFO module.

[0068] S305, the DSP module generates target position information according to the image data; wherein the target position information is used to characterize the moving trajectory of the target object.

[0069] S306, the DSP module sends the target position information to the second FIFO module.

[0070] S307: If the second FIFO module is not empty, the first Data Mover module writes the target location information in the second FIFO module into the DDR module according to the write instruction.

[0071] The image data caching method provided in the embodiment of the present application has the same technical features as the image data caching device provided in the above embodiment, so it can also solve the same technical problems and achieve the same technical effects.

[0072] An embodiment of the present application also provides an electronic device, including a processor and a memory, wherein the memory stores machine executable instructions that can be executed by the processor, and the processor executes the machine executable instructions to implement the above-mentioned image data caching method.

[0073] See also Figure 4 As shown, the electronic device includes a processor 100 and a memory 101. The memory 101 stores machine executable instructions that can be executed by the processor 100. The processor 100 executes the machine executable instructions to implement the above-mentioned image data caching method.

[0074] Further, Figure 4 The electronic device shown further includes a bus 102 and a communication interface 103 , and the processor 100 , the communication interface 103 and the memory 101 are connected via the bus 102 .

[0075] Among them, the memory 101 may include a high-speed random access memory (RAM), and may also include a non-volatile memory (non-volatile memory), such as at least one disk storage. The communication connection between the system network element and at least one other network element is realized through at least one communication interface 103 (which can be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. can be used. The bus 102 can be an ISA (Industrial Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus or an EISA (Enhanced Industry Standard Architecture) bus, etc. The above-mentioned bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 Only one bidirectional arrow is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0076] The processor 100 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit or software instructions in the processor 100. The above processor 100 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application can be directly embodied as a hardware decoding processor for execution, or a combination of hardware and software modules in the decoding processor for execution. The software module may be located in a storage medium mature in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 101, and the processor 100 reads the information in the memory 101 and completes the steps of the method of the above embodiment in combination with its hardware.

[0077] This embodiment further provides a machine-readable storage medium, which stores machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement the above-mentioned image data caching method.

[0078] The computer program product of the image data caching method, device, and electronic device provided in the embodiments of the present application includes a computer-readable storage medium storing program code, and the instructions included in the program code can be used to execute the method described in the previous method embodiment. The specific implementation can refer to the method embodiment, which will not be repeated here. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the previous method embodiment, which will not be repeated here.

[0079] In addition, in the description of the embodiments of the present application, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances. If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a non-volatile computer-readable storage medium that can be executed by a processor. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program codes.

[0080] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0081] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. An image data caching device, characterized in that: The device comprises: an FPGA field programmable gate array module, wherein a first end of the FPGA field programmable gate array module is connected to a DSP digital signal processing module, and a second end is connected to a DDR double data rate synchronous dynamic random access memory module; the FPGA field programmable gate array module comprises a first Data Mover transport module, a second Data Mover transport module, a first FIFO first-in first-out queue module, and a second FIFO first-in first-out queue module; The first Data Mover handling module is used to obtain the write instruction sent by the DSP digital signal processing module; The second Data Mover transport module is used to obtain the read instruction sent by the DSP digital signal processing module, and read the image data in the DDR double data rate synchronous dynamic random access memory module into the first FIFO first-in first-out queue module according to the read instruction; wherein the image data is used to characterize the characteristics of the target object; The DSP digital signal processing module is used to read the image data in the first FIFO first-in first-out queue module if the first FIFO first-in first-out queue module has a readable data identifier, and generate target position information according to the image data; wherein the target position information is used to characterize the moving trajectory of the target object, and the target position information is sent to the second FIFO first-in first-out queue module; The first Data Mover transport module is further used to write the target location information in the second FIFO first-in first-out queue module into the DDR double data rate synchronous dynamic random access memory module according to the write instruction if the second FIFO first-in first-out queue module is not empty.

2. The image data caching device according to claim 1, characterized in that: The write instruction includes a first destination address and a first data length; the first destination address is the location of the target location information in the DDR double data rate synchronous dynamic random access memory module, and the first data length is the memory occupied by the target location information; the FPGA field programmable gate array module also includes: a MIG memory interface generator interface; The first Data Mover transport module is specifically used to determine the first base address corresponding to the target location information in the DDR double data rate synchronous dynamic random access memory module through the first destination address, take the first base address as the starting point, divide the memory of the DDR double data rate synchronous dynamic random access memory module according to the first data length, obtain a first memory space, and write the target location information into the first memory space in the DDR double data rate synchronous dynamic random access memory module through the MIG memory interface generator interface.

3. The image data caching device according to any one of claims 1 to 2, characterized in that: The read instruction includes a second destination address and a second data length; the second destination address is the location of the image data in the DDR double data rate synchronous dynamic random access memory module, and the second data length is the memory occupied by the image data; The second Data Mover transport module is specifically used to determine the second base address corresponding to the image data in the DDR double data rate synchronous dynamic random access memory module through the second destination address, and to obtain the image data from the DDR double data rate synchronous dynamic random access memory module through the MIG memory interface generator interface according to the second data length, taking the second base address as the starting point.

4. The image data caching device according to claim 1, characterized in that: The DSP digital signal processing module is further configured to stop reading the image data in the first FIFO first-in first-out queue module if the first FIFO first-in first-out queue module does not have the readable data identifier.

5. The image data caching method according to claim 1, characterized in that: The first Data Mover transport module is further used to stop writing the target location information in the second FIFO first-in first-out queue module into the DDR double data rate synchronous dynamic random access memory module according to the write instruction if the second FIFO first-in first-out queue module is empty.

6. The image data caching device according to claim 1, characterized in that: The FPGA field programmable gate array module also includes an LVDS low voltage differential signal interface, and the LVDS low voltage differential signal interface is connected to the imager; The LVDS low voltage differential signal interface is used to obtain the image data sent by the imager; The LVDS low voltage differential signal interface is also used to send the image data to the DDR double data rate synchronous dynamic random access memory module.

7. The image data caching device according to claim 1, characterized in that: The DDR double data rate synchronous dynamic random access memory module is used to send the target position information to the integrated control machine, so that the integrated control machine controls the drone to track the target object according to the target position information.

8. A method for caching image data, characterized in that: Applied to an FPGA field programmable gate array module, the first end of the FPGA field programmable gate array module is connected to a DSP digital signal processing module, and the second end is connected to a DDR double data rate synchronous dynamic random access memory module; the FPGA field programmable gate array module includes a first Data Mover transport module, a second Data Mover transport module, a first FIFO first-in first-out queue module and a second FIFO first-in first-out queue module; The first Data Mover transport module obtains a write instruction sent by the DSP digital signal processing module; The second Data Mover transport module obtains the read instruction sent by the DSP digital signal processing module, and reads the image data in the DDR double data rate synchronous dynamic random access memory module into the first FIFO first-in first-out queue module according to the read instruction; wherein the image data is used to characterize the characteristics of the target object; If the first FIFO first-in first-out queue module has a readable data identifier, the DSP digital signal processing module reads the image data in the first FIFO first-in first-out queue module, and generates target position information according to the image data; wherein the target position information is used to characterize the moving trajectory of the target object, and the target position information is sent to the second FIFO first-in first-out queue module; If the second FIFO queue module is not empty, the first Data Mover transport module writes the target location information in the second FIFO queue module into the DDR double data rate synchronous dynamic random access memory module according to the write instruction.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method according to claim 8 are implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method according to claim 8 are executed.

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