Multi-level image reconstruction using one or more neural networks

Abstract

The invention relates to multi-level image reconstruction using one or more neural networks. And a plurality of processors having logic units for training one or more neural networks to image construct image data from a region of interest (ROI) at least in part using the established one or more compression levels.

Description

[0001] Divisional Application Information

[0002] This invention patent application is a divisional application of an invention patent application with an application date of September 13, 2019, application number 201980075021.0, and invention name “Multi-level image reconstruction using one or more neural networks”.

[0003] Related Applications

[0004] This application is related to and claims priority to U.S. Provisional Application No. 62 / 731,082, filed on September 13, 2018, entitled “Multi-level Image Reconstruction,” which is also related to U.S. Provisional Application No. 62 / 700,071, filed on July 18, 2018, entitled “Virtualized Computing Platform for Image Reasoning,” and to U.S. Provisional Application No. 62 / 721,517, filed on August 22, 2018, entitled “Algorithmic Weighting System for Image Reconstruction,” the subject matter of each of which is incorporated herein by reference in its entirety for all intents and purposes. Technical Field

[0005] At least one embodiment relates to processing resources for reconstructing an image. In at least one embodiment, at least one embodiment relates to determining optimal parameters in a compression space using an architecture with multiple graphics processing units (GPUs) according to various novel techniques described herein, and to reconstructing an image using the optimal parameters. Background Art

[0006] A tomography system includes a source that projects X-rays through tissue or an object to a detector. Such systems, when used in medical applications, require the patient to remain within the system and be exposed to radiation for an extended period of time until data from the detector is properly collected and processed. For example, the data is then used to reconstruct an image that includes features within the tissue. Using the data for reconstruction, the clarity of the image depends on efficient processing of the data, such as by maintaining as much data as possible and the relationships between the data features. Processing the data and reconstructing the image requires a lot of computation, resource investment, and time. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various embodiments according to the present disclosure will be described with reference to the accompanying drawings, in which:

[0008] Figure 1 is a block diagram of an example tomography system incorporating the multi-level reconstruction using multiple graphics processing units (GPUs) for medical applications in accordance with at least one embodiment;

[0009] Figure 2is a characteristic diagram of certain steps followed in a tomography process that is subjected to the processing steps described in at least one embodiment;

[0010] Figure 3 is a feature map of an example multi-level reconstruction using multiple GPUs to reconstruct an image during a tomography process according to at least one embodiment;

[0011] Figure 4 is a feature graph illustrating example computational features in each stage of a multi-stage tomography process for reconstructing an image using multiple GPUs in accordance with at least one embodiment;

[0012] Figure 5 is a process flow of steps that may be used for multi-level tomographic reconstruction of an image according to at least one embodiment;

[0013] Fig. 6A An example data center is shown where data from Figure 1-5 at least one embodiment of;

[0014] Figure 6B , Figure 6C Inference and / or training logic for enabling and / or supporting multi-level image reconstruction according to various embodiments is shown, such as in Fig. 6A and reasoning and / or training logic used in at least one embodiment of the present disclosure;

[0015] Fig. 7A is a block diagram illustrating an exemplary computer system, which may be a system having interconnected devices and components, a system on a chip (SOC), or some combination thereof formed together with a processor, wherein the processor may include an execution unit for executing instructions to support and / or implement multi-level image reconstruction as described herein, according to at least one embodiment;

[0016] Figure 7B is a block diagram illustrating an electronic device for utilizing a processor to support and / or implement multi-level image reconstruction as described herein, according to at least one embodiment;

[0017] Figure 7C A block diagram of an electronic device for utilizing a processor to support and / or implement multi-level image reconstruction as described herein is shown according to at least one embodiment;

[0018] Figure 8 Another exemplary computer system for implementing various processes and methods for multi-level image reconstruction described throughout this disclosure is shown in accordance with at least one embodiment;

[0019] Fig. 9AAn exemplary architecture is shown in accordance with at least one embodiment of the present disclosure, wherein a GPU is communicatively coupled to a multi-core processor via a high-speed link to implement and / or support multi-level image reconstruction;

[0020] Fig. 9B shows additional details of the interconnection between a multi-core processor and a graphics acceleration module according to an exemplary embodiment;

[0021] Fig. 9C Another exemplary embodiment according to at least one embodiment of the present disclosure is shown, wherein an accelerator integrated circuit is integrated within a processor for implementing and / or supporting multi-level image reconstruction;

[0022] Fig.9D An exemplary accelerator integrated chip 990 for implementing and / or supporting multi-level image reconstruction according to at least one embodiment of the present disclosure is shown;

[0023] Fig.9E Additional details of an exemplary embodiment of a shared model for implementing and / or supporting multi-level image reconstruction in accordance with at least one embodiment of the present disclosure are shown;

[0024] Fig.9F shows additional details of an exemplary embodiment of a unified memory addressable by a common virtual memory address space for accessing physical processor memory and GPU memory to implement and / or support multi-level image reconstruction in accordance with at least one embodiment of the present disclosure;

[0025] Fig. 10A An exemplary integrated circuit and associated graphics processor for multi-level image reconstruction according to embodiments described herein are shown;

[0026] Figures 10B-10C An exemplary integrated circuit and associated graphics processor for supporting and / or implementing multi-level image reconstruction according to at least one embodiment are shown;

[0027] Figures 10D-10E Additional exemplary graphics processor logic for supporting and / or implementing multi-level image reconstruction in accordance with at least one embodiment is shown;

[0028] Fig.11A is a block diagram illustrating a computing system for supporting and / or implementing multi-level image reconstruction according to at least one embodiment;

[0029] Fig. 11B A parallel processor for supporting and / or implementing multi-level image reconstruction according to at least one embodiment is shown;

[0030] Fig. 11Cis a block diagram of a partitioning unit according to at least one embodiment;

[0031] Fig.11D is a block diagram of a processing cluster within a parallel processing unit according to at least one embodiment;

[0032] Fig.11E A graphics multiprocessor for multi-level image reconstruction according to at least one embodiment is shown;

[0033] Fig. 12A A multi-GPU computing system is shown in accordance with at least one embodiment;

[0034] Fig. 12B is a block diagram of a graphics processor according to at least one embodiment;

[0035] Fig.13 is a block diagram illustrating a microarchitecture for a processor, which may include logic circuitry for executing instructions, according to at least one embodiment;

[0036] Fig.14 A deep learning application processor according to at least one embodiment is shown;

[0037] Fig.15 shows a block diagram of a neuromorphic processor according to at least one embodiment;

[0038] Fig.16A is a block diagram of a processing system according to at least one embodiment;

[0039] Fig. 16B is a block diagram of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor according to at least one embodiment;

[0040] Fig. 16C is a block diagram of the hardware logic of a graphics processor core according to at least one embodiment;

[0041] Figures 16D-16E Thread execution logic is shown that includes an array of processing elements of a graphics processor core in accordance with at least one embodiment.

[0042] Fig.17A illustrates a parallel processing unit according to at least one embodiment;

[0043] Fig. 17B illustrates a general processing cluster in accordance with at least one embodiment;

[0044] Fig. 17C A memory partitioning unit of a parallel processing unit according to at least one embodiment is shown; and

[0045] Fig.17DA streaming multiprocessor in accordance with at least one embodiment is shown. DETAILED DESCRIPTION

[0046] Radiation is provided from a source, such as an X-ray source, and data is obtained from the projection of the radiation through a tissue or an object using one or more detectors. The detector may include an array of detectors, and unless otherwise specified, references to the detector may be considered references to the array of detectors. Data may be obtained at different angles by moving the source and detector, or using multiple detectors for different source angles. The motion is around a subject or around an object in a medical application. For example, the motion may be at a region of interest (ROI) of interest of a subject or object. Data from different angles at each lateral position around which the motion occurs is combined and represents a slice of the data. When combined, the data may be represented as an image volume having a width, height, and depth. A transformation process may be applied to find pixel values ​​of the image volume, for example, at each intersection of the data of the slice at different angles contained in the slice. In at least one embodiment, the pixel value may be the light intensity of a pixel at different angular positions for the lateral position of the source and detector. When completed, the transformation process generates an image representing a backprojection of the data across angles, and may also contain lateral features.

[0047] In addition, unlike back-projection, which is a non-iterative reconstruction, iterative reconstruction can also be used to reconstruct an image. In iterative reconstruction, the data obtained by the detector can be compared with simulated data originally established for the tissue (or underlying features of the tissue) using the same source and assuming parameters for transmitting radiation through the tissue to the detector. The difference between the projection data and the simulated data can be considered as an error fed back to the simulated data to require convergence between the two types of data at each pixel or pixel block. Since this is an iterative process, the result after converging the differences is an image reconstructed using the underlying features of the tissue or object. Iterative reconstruction has been shown to have lower noise (e.g., signal-to-noise ratio (SNR) and contrast-to-noise ratio (CNR)) than non-iterative reconstruction, such as back-projection or its variants.

[0048] The calculations used for iteration are complex, time consuming, and processor intensive. In addition, at least in medical applications, patients may be required to endure long periods of radiation. The present disclosure uses a multi-GPU or multi-processor architecture to determine the best initialization for the image reconstruction process and reduce the number of iterations required to converge the data set. According to at least one embodiment of the present disclosure, multiple compression levels are used in the iterative process. Optimal initialization is the goal of the iterative process of the present disclosure. Optimal initialization ensures that the simulated data is initially as close as possible to the data obtained from the detector.

[0049] In at least one embodiment, simulated data is obtained by iteratively testing a data slice representing the highest compression level. In turn, the highest compression level has the least amount of data, but represents important features in the data set. Then, during the iterative testing, different parameters and algorithms are used in each of multiple GPUs or processors, and at least one parameter and at least one algorithm can be selected to achieve convergence of the data slice. In at least one embodiment, the simulated data based on an arbitrary value is iteratively adjusted based in part on the difference between the arbitrary value and the measured value in the data slice after each iteration cycle. The adjusted simulated data obtained is an image body, which can be used as an initializer image in subsequent compression levels. Since the compression level is the most compressed in this case, there are fewer data points to achieve convergence. The parameters and algorithms used for the highest compression level can be used for subsequent levels with lower compression data points in the data. In one example, the process represents a neural network application, which is used to learn parameters and algorithms suitable for different compression levels. In at least one embodiment, each compression level can be regarded as a hidden layer associated with a neural network. The upsampled output from each compression level is fed into the subsequent algorithm as an initializer image to represent, for example, feedforward propagation in a neural network.

[0050] Since the data at the lower compression level is a version of the data at the higher compression level, as more information is added, the parameters and algorithms are expected to converge at the lower compression level and subsequent compression levels. When completed, the number of iterations to converge the error or difference between the simulation data and the projection data at each subsequent level is reduced because the simulation data is adjusted. Therefore, the optimal initialization can be represented by one or more selected algorithms, the selected algorithms having selected parameters and initializer images, which are generated in the first (highest) compression level and used as the basis for subsequent initializer images during each iteration of the lower compression level.

[0051] Thus, according to at least one embodiment of the present invention, a system and a computer-implemented method for image reconstruction are disclosed. As described in the full text of the present disclosure, data is obtained from radiation passing through tissue. A compression level for the data is established by at least distributing (e.g., allocating, organizing, and selecting) data points in the data to subsets of the data. The subset can represent a slice of the data, which can be obtained at different angles of a specific cross-section or transverse position of the tissue, for example. In addition, the subset includes data points representing individual data items from within the data. The compression level includes increasing the number of data points in the data subset. In at least one embodiment, the first compression level can be the highest compression level relative to the second or subsequent compression level. Therefore, the first compression level and the first subset in the data subset have the least number of data points. This can be achieved by selectively collecting data, so that a spare detector that forms part of a detector array and functions entirely as a single detector of a tomography system provides a first subset of data. Alternatively, a portion of the data is allocated to the first subset of the data. In this data collection manner, for example, the data points collected in each data slice can be reduced. Thus, the first compression level has less data, but also has the most relevant data, which primarily represents one or more slices (or one or more subsets) of the data collected during the radiation phase of the tomography procedure.

[0052] At least one reconstruction parameter and reconstruction algorithm for a first compression level are established. Since the first compression level represents the highest compression level of the data, it also represents a smaller subset of the data that can converge in an iterative process using simulated data from a simulated data set. In at least one embodiment, an algorithm for reconstruction can be determined by testing one or more iterative or non-iterative algorithms using a subset of data from the first compression level. Multiple GPUs in a multi-GPU architecture can be used to perform the tests in parallel. When convergence is achieved in one of the tests using one of the available algorithms, the number of data points in the subset of data used to cause convergence is noted. For a non-iterative algorithm, the image volume obtained after filtering to remove blur and other noise can be used to determine whether a reconstruction algorithm and at least one reconstruction parameter can be established using a non-iterative algorithm and the applied filtering. Since the number can be a test number, for example, the number can be extrapolated or upsampled for use with the entire subset of data. The number of data points in the first subset of the data can be considered as the optimal number for the first and subsequent subsets of the data representing the first and subsequent compression levels. Then, the number of data points represents the reconstruction parameters established in the reconstruction phase of the image of the underlying features of the tissue. The algorithm used to achieve convergence with the optimal number of data points is considered as the reconstruction algorithm in the reconstruction phase.

[0053] Alternatively, a non-iterative algorithm such as FBP can be used as a reconstruction algorithm instead of an iterative algorithm. In the case of a non-iterative algorithm, the use of a specific filter to prevent blurring can be considered as an applicable reconstruction parameter. The reconstruction algorithm and reconstruction parameters are used to represent the entire subset of data at the first compression level. The first image body can be generated in each iteration or in a step associated with each compression level, the first image body corresponding to an iteration involving the first compression level or corresponding to an intermediate image body in the applied non-iterative algorithm. It can be determined that one of the first image bodies generated during the iteration meets a predetermined criterion. In at least one embodiment, the predetermined criterion can be that the first image body is generated once convergence is achieved, or that the image body is generated after FBP is performed using the first data subset. This determination qualifies the first image body as the first initializer image body for the second compression level.

[0054] Compared to the first compression level, the second compression level has a higher number of data points in the data. Thus, an upsampling step is performed to upsample the first initializer image volume to the requirement of the second compression level. In at least one embodiment, the upsampling step can insert singular values ​​(such as applying zero (0)) to fill the space in the array or data set, but it is also possible to use extrapolation, interpolation or interpolation of adjacent values ​​of the data set from the current compression level to obtain a similar number of data points to the subsequent compression level. In a similar manner, the present disclosure requires iterating through the remaining compression levels in the compression level after the second compression level. After upsampling from each previous level to the subsequent level, the image volume of the previous level is used for the subsequent level in the various levels. In addition, using at least one reconstruction parameter, iteration can be started at least for the subsequent level. In this way, the image volume of the previous level that is upsampled becomes the subsequent initializer image volume for the subsequent level. A final image volume is generated after iteration. The final image volume shows convergence to the simulated image volume, thereby enabling reconstruction of the image of the tissue.

[0055] The multi-level reconstruction performed in the multi-GPU architecture ensures that the core and computationally intensive iterations are performed in the highest compression space and can be performed between multiple GPUs of the multi-GPU architecture. Reconstruction parameters, reconstruction algorithms and / or the first image volume established and confirmed in the highest compression space using the multi-GPU architecture can be stored as the optimal output for use in data from subsequent compression levels. In addition, the first image volume is also the optimal output for representing the significant features of the data. The multi-level reconstruction in this article can be repeated until the original reconstruction level (e.g., non-compressed space) is reached, at which point the continuously optimized initializer is also the optimal initializer from which image reconstruction occurs. Therefore, the present disclosure enables determination of the optimal initializer for image reconstruction, especially for tomography systems. When there are multiple algorithms and related parameters, they represent the most appropriate ranking and weights of several algorithms available in the highest compression space of the multi-GPU architecture. The most appropriate ranking and weights (which represent the established and confirmed reconstruction algorithms and parameters) can be used for final image generation in the original reconstruction space.

[0056] Figure 1 is a block diagram of an example tomography system 100 incorporating multi-level reconstruction using multiple graphics processing units (GPUs) for medical applications in accordance with at least one embodiment of the present disclosure. A person of ordinary skill reading the present disclosure will recognize the application of at least one embodiment of the present disclosure, modified or combined with the embodiments herein, to establish similar multi-level image reconstructions for other imaging techniques. In at least one embodiment, in addition to tomography, any imaging system capable of sorting images in a compressed space can benefit from the present systems and methods. Figure 1 In the embodiment of the present invention, a subject 106 or an object can be arranged to face a radiation source 102. In particular, a region of interest (ROI) 106A of the subject 106 can be exposed to the radiation source 102. In at least one embodiment, the radiation source 102 is an X-ray source that produces a parallel beam, a cone beam, or a fan beam projection to the ROI. By moving one or more of the source 102 and / or the detector 108, data related to the ROI is captured or obtained at different angles around the subject 106A in a transverse cross-section. In at least one embodiment of the present disclosure, the detector 108 can be stationary and can be formed as a detector array, which includes a plurality of detectors (or sub-detectors) for capturing data at different source angles of the radiation source 102 around the subject 106A.

[0057] If the detector is configured for movement, one or more system controllers 110 may be provided to control the movement of the source 102 and the detector 108. The system controller 110 may use input signals to the source 102 to control the movement of the source 102. The input may include timing and power signals. The processing module 114 may determine the angle and power of the radiation from the source 102 and the detector 108 and other requirements, and may provide instructions to the system controller 110 to make the required movements and adjustments to collect data related to the ROI 106A. Timing and power signals may also be provided to the source 102, and may also be provided to the detector 108, so that any relative movement between the source and the detector is synchronized and properly implemented. The detector 108 provides data from different angles for processing. In at least one embodiment, the data is obtained at the reconstruction module 112 and may also be obtained in the processing module 114. The data may then be combined using a transformation process applied to different pixel values ​​in the data, such as in the case of having multiple GPUs 112A support in the reconstruction module 112. In at least one embodiment, data may be acquired and stored in a data array from which slices such as those shown by reference numeral 118 are determined. For example, the slice is a portion of the image volume that represents a cross-section of a feature in the ROI. In at least one embodiment, the data may be acquired directly as slices, which are also configured as an array, but are labeled to represent certain transverse cross-sections of the subject 106.

[0058] In at least one embodiment, a reconstructed image is generated from the reconstruction module 112 and provided to the input / output (I / O) module 116 via the processing module 114. The reconstructed image includes a representation of the internal organs as the underlying features of the tissue and within the cross-sectional view of the torso 106A (in at least one embodiment, an example ROI). The reconstructed image can be presented as a computed tomography (CT) output from the system 100. In at least one embodiment, although a two-dimensional (2D) representation is shown, the data can support a three-dimensional (3D) representation. In at least one embodiment, the image from the I / O module 116 includes a representation of the ROI of the object. In at least one embodiment, in order to analyze the ROI, such as to measure size, shape or other such aspects, a portion of the image corresponding to the ROI can be determined and used to generate initial values, which can be extrapolated based on the features from the ROI. The I / O module 116 can be any suitable electronic and / or computing device that enables a user to generate and send a request to the tomography system. In at least one embodiment, the I / O modules 116 may include desktop computers, laptop computers, computer servers, smart phones, tablet computers, game consoles (portable or otherwise), computer processors, computing logic, set-top boxes, etc. In at least one embodiment, the processing module 114 communicates with the I / O modules 116 via any suitable network to transmit requests or other data, such as the Internet, an intranet, an Ethernet network, a cellular network, a local area network (LAN), a network with direct wireless connections between nodes, and the like.

[0059] In at least one embodiment, a user may indicate a set of points corresponding to the surface of an object or subject to define an ROI. In at least one embodiment, the data from detector 108 may include extreme points indicated for an object or subject. In at least one embodiment, there may be a topmost point, a bottommost point, a leftmost point, and a rightmost point for establishing an ROI of an image or object. In at least one embodiment, if the data obtained is for a 3D image, the reference points may also include the frontmost and last (or rear and front, etc.) points. In at least one embodiment, additional points may be included. These points may be referred to as extreme points because they indicate at least the extreme position of the desired representation of an ROI (e.g., ROI 106A) for an object or subject 106 along a specific dimension. In at least one embodiment, the reference points may be used to determine the segmentation of a subject 106 or an object.

[0060] In at least one embodiment, any portion of the instructions of the various modules 110-114 and / or data storage may be internal or external to one or more processors or other hardware logic devices or circuits, such as GPU 112A or CPU in module 114. In at least one embodiment, the instructions and / or code and / or data storage may be part of a cache memory (or other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory), dynamic random access memory ("DRAM"), static random access memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. The instructions and / or code in any of the above-referenced storage components form a non-transitory computer-readable medium that can be used with a processor to cause the instructions and / or code to execute and complete the processes described throughout this disclosure. In at least one embodiment, the choice of whether instructions and / or code and / or data storage is internal or external to the processor, e.g., comprising DRAM, SRAM, flash memory, or some other storage type, can depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being executed, the batch size of the data used in inference and / or training of the self-learning network, or some combination of these factors.

[0061] Figure 2 is a characteristic diagram of certain steps 200 followed in a tomography process that is subject to the processing steps described in at least one embodiment of the present disclosure. The transmission of radiation through the ROI produces projection data, referred to herein as data 202. Data 202 is obtained from Figure 1The detector referenced in is captured, acquired or generated. The data represents the amount of radiation remaining after absorption, reflection or refraction based on tissue or object. The data is shown as rows of scan information, for example, which can be pixel brightness values. For example, this can represent sampled and quantized data, and after the processing steps disclosed in this article are completed, an image can be reconstructed from the sampled and quantized data. In at least one embodiment, the data is represented in rows and / or columns of multiple arrays 202, including representations of features within the ROI. Each array 202 represents one or more views of features within the ROI from an angle at a transverse cross-section. Some tomography systems acquire views in increments of 1°, but other larger increments can also be used. The source can be subjected to parameter changes to generate the radiation intensity required to perform the tomography process. In addition, depending on the requirements of the tomography process, the source current (mA) can be an adjustable parameter. In at least one embodiment, the voltage (kV) and source current (mA) values ​​can be adjusted according to the subject (also organs, fat content, water content, etc.), the object, or the ROI of interest. In at least one embodiment, for an x-ray source, mA multiplied by the rotation time of the source can be used to determine the x-ray picture for each or all scans generated as the source rotates. Thus, one aspect of the present disclosure is the use of multi-level reconstruction of images in x-ray imaging. For a tomographic process, the photons required for a tomographic image can be understood to be proportional to the mA value.

[0062] Furthermore, the type of projection of radiation from the source is another parameter that can be adjusted during a tomography procedure. Figure 1 A cone beam projection is shown, but parallel beam projection, axial source fan projection, and detector fan projection also benefit from the present disclosure for image reconstruction. In another aspect of the present disclosure, beam filtering can be applied to shape the energy distribution through the ROI, but a beam collimator can be used on the detector side, for example, to reduce scattering of the beam radiation. In at least one embodiment, each data slice includes a row-by-row and column-by-column expansion of pixel values ​​and may include a thickness value. In at least one embodiment, a data slice from the projection data may include 512×512 pixels and a thickness (or width) of 8 or 16 bits. The combination of each data point in the 512x512 pixel distribution and the thickness at the data point represents a voxel. When the source (and / or detector) moves around the ROI, each detector in the multiple detector configuration can acquire different angles of the data slice or a single data slice. Preprocessing can be performed in module 204. For example, several steps can be taken to convert the exponential value from the detector to a linear value and adjust for the multi-color value from the detector.

[0063] Filtered back projection (FBP) may be performed in module 206. FBP is an example algorithm that may be used to find slices of an image volume from array 202. As discussed elsewhere in this disclosure, there are other algorithms that may be used in place of FBP. The goal of FBP is to determine data slices (e.g., slice 118) from multiple values ​​in array 202, corresponding to light rays passing through different portions of the ROI at different angles. Different slices (from different views of the ROI) including different angles may be combined to provide an image volume. In at least one embodiment, at the horizontal position of subject 106, slice 118 includes different views of a cross section obtained from a configuration in which source 102 and detector 108 are opposite to each other and subject 106 is located between them. As noted elsewhere in this disclosure, source 102 and detector 108 are in relative motion to enable 360-degree capture of features at a cross section of the ROI. In at least one embodiment, slices may be determined from different views using the data in array 202. The value of the view may be obtained by summing all pixels in a cell of a first angle (first view) along the available angles to obtain a set of one-dimensional (1D) values ​​for the first angle (first view). Slices may then be obtained by combining the one-dimensional values ​​according to various algorithmic processes, such as described in further detail below. In at least one embodiment, the slices may be formed by an iterative reconstruction technique, although other computationally intensive techniques, such as simultaneous linear equations, may be used.

[0064] In at least one embodiment, an iterative reconstruction technique can be applied by setting pixels in a predefined slice (e.g., simulated or expected data) to have a starting pixel value. Since the measured or actual values ​​obtained from the ROI scan (unlike the simulated or expected data) have no reference point, the use of an iterative reconstruction technique provides such a reference by starting with an arbitrary value, for example, adjusting iteratively (as described below) to obtain an accurate slice to achieve image reconstruction of the ROI. For example, the starting pixel value can be an arbitrary value representing simulated, neutral, or expected data. For example, theoretically, the expected data can be determined for a slice of a specific cross section. In at least one embodiment, the starting pixel value in the slice can be determined using known components of the tissue and its known response to radiation. Then, the actual or measured data can be used to compare with the starting pixel value of the corresponding cell of the predetermined slice, and the actual or measured data includes the actual value preprocessed from the array 202 and the actual value is obtained by summing the pixel values ​​along an angle (as described above). The comparison can be a statistical comparison, such as to determine the error or difference between the starting pixel value and the actual value, or for all values ​​of all cells, individual values ​​of individual cells, the maximum value of all cells, the minimum value of all cells, or other statistically significant values. This error or difference can be used to correct the starting pixel value (or all values ​​of all cells), and the process is repeated for each predefined slice using the actual value until the error is minimized or non-existent, indicating convergence of the iterative process. At the end of the iterative process, the predefined slices are converted into slices that form an image volume, which is used to reconstruct an image showing the underlying features of the ROI.

[0065] The iterative process is also computationally intensive. Therefore, the fewer the number of iterations, the faster the tomography system processes the received data and displays the image reconstructed from the data. In order to reduce the number of iterations of the above process, it is most appropriate if the tomography system can start with a predefined slice, and the starting pixel value of the predefined slice is close to the actual value. As a result, the error is small at the beginning and continues to decrease as the iteration proceeds, but a fewer number of iterations are required to generate the reconstructed image. The FBP process of module 206 is different from the iterative process. Initially, a simple back-projection process can obtain each view from the actual value, which is pre-processed from array 202 and obtained by the sum of pixel values ​​along an angle. The actual value is adjusted to a singular value along the angle. The final back-projected image is formed by the sum or combination of the back-projected views. FBP is a process that performs additional features in the simple back-projection process. In FBP, each view is first filtered to solve the blurring problem that may exist in the simple back-projection process. In at least one embodiment, each one-dimensional view is convolved with a one-dimensional filter to create a filtered view. The filtered view is back-projected in module 206 to provide an image volume 208 comprising the slices. The image volume 208 is used to render a reconstructed image 210.

[0066] Since image reconstruction is a time-consuming process, an appropriate initializer image volume can help the rapid convergence of the iterative process, and the appropriate initializer image volume has a starting pixel value as close to the actual value as possible. The process of determining an appropriate initializer image volume may be challenging. The present disclosure compresses the original reconstruction space into several levels. On a multi-GPU architecture with different reconstruction parameters, the reconstruction of the image volume is performed at the lowest compression level using a singular algorithm or using different reconstruction algorithms. Based on a predetermined or predefined criterion, the best image volume is selected from the reconstruction of the lowest compression level. The selected image volume is upsampled to serve as an initializer image volume for one or more subsequent compression levels, and the subsequent compression level represents a lower compression level. Repeat this process on a multi-GPU architecture until the initializer image volume of the original reconstruction space is determined. The image can be reconstructed from the initializer image volume for the original reconstruction space. The benefit of this process is that it does not iterate in the mostly uncompressed original reconstruction space. As the iteration occurs in the compressed space, the iteration is then improved, and the initializer image volume of the lowest (or first) compression level is improved as it grows in the compression level until the original (or uncompressed) space is reached. In this way, the present process enables selection of a suitable algorithm and associated parameters such as sequence and weights for finding a suitable initializer image volume.

[0067] Figure 3It is a characteristic diagram of an exemplary multi-level tomography process 300 for reconstructing an image according to at least one embodiment of the present disclosure. As before, the data in array 302 is obtained from radiation passing through tissue. In module 304, compression levels are established. The compression levels include subsets with increasing numbers of data points having data. Each subset can be associated with a data slice with a different view. In at least one embodiment, the first compression level can be the highest compression level relative to the second or subsequent compression level. This can be achieved by selectively collecting data around different views at a specific cross-section of the subject, so that only spare detectors forming part of the detector array provide a subset of data for the slice. Alternatively, even if all detectors are collecting data, data from selected detectors of the detector array are used, thereby reducing the number of data points used in the processing stage. For example, these methods reduce the data points collected in each data slice. After reading this disclosure, ordinary technicians will also recognize that deep learning techniques can be used to fill in the data gaps caused by alternating detectors. The process and the system based on the process, in addition to benefiting from faster processing time, also benefit from reduced data scanning costs. Any suitable learning network can be used to facilitate deep learning, such as a deep neural network (DNN), a recurrent neural network (RNN), or a convolutional neural network (CNN). For example, once the network is trained and successfully evaluated to identify data in, for example, a subset or slice, the trained network can provide similar representative data for use with the collected data.

[0068] In at least one embodiment, a computer-implemented method for reconstructing an image using a neural network is disclosed. The method includes establishing one or more compression levels for image data from a region of interest (ROI). An image volume may be generated from a first compression level using a subset of the image data. One or more neural networks (such as the exemplary neural network above) may be used to generate a subsequent image volume of one or more hidden layers, the one or more hidden layers representing a subsequent level in the one or more compression levels. An image associated with a base feature of the ROI is generated from the final image volume of the one or more neural networks. In addition, when it is determined that the image volume of the first compression level meets a predetermined criterion, it is suitable for use as an initializer image for one or more neural networks, for example. This can be achieved via filtered back projection (FBP), which is applied to confirm the quality of the image volume at each level (or neural network layer). In another aspect, processing in the first compression level (and subsequent compression levels) can occur simultaneously to determine at least one parameter and an algorithm for the neural network. In at least one embodiment, a subset of the image data can be processed simultaneously according to the at least one parameter and using a predetermined algorithm to form one or more neural networks. The processing is performed simultaneously in multiple graphics processing units (GPUs) of a multi-GPU architecture to determine that the parameters are suitable for implementing constrained optimization in the first level of compression. Thereafter, the parameters may be applied in at least one subsequent level of one or more neural networks.

[0069] In at least one embodiment, the upsampling step used in the present disclosure can be a way to provide a comparable data set for processing. Extrapolation, interpolation, or interpolation can be used to adjust the data set to the required number of data points for processing at each subsequent processing level. In at least one embodiment, since the data can be obtained from a spare detector, the data can be smoother because the data includes extrapolated, interpolated, or interpolated data from adjacent pixels or groups of pixels. Compared to a zero value (which is a possible case of upsampling), the value of the extrapolated, interpolated, or interpolated data may be closer to the true value in the measured data or actual data. Unless otherwise stated, the present disclosure can use any of upsampling, extrapolation, interpolation, or interpolation to obtain a data set for the second and each subsequent compression level.

[0070] The geometric modeling module 304 is used to determine the appropriate space and geometric features of the tomography system. The image volume is formed by voxels, which are part of a slice of one or more cross sections across the subject. Each slice is divided into a voxel matrix. In this way, the voxels provide data to enable reconstruction of images of features within the ROI of the body. According to the subject and the ROI in question, it is necessary to use a suitable geometry for each ROI. In at least one embodiment, size constraints and organ constraints may be useful for defining the geometry of the compression level so that data can be appropriately allocated according to the geometry of the organ under scanning. In addition, the simulation data with arbitrary values ​​used in the iterative process can be adjusted to include data points for the expected organ shape (for example, sparse). The simulation data can be represented at a compression level and adjusted in the iterative process. In addition, the size of the voxel may have an impact on various aspects of the geometry, including causing blur and additional noise in the data. As a result, for each slice, the field of view, slice thickness, and the number of pixels or voxels are established to achieve the desired reconstruction of the image with features from the ROI in question. With these requirements in mind, module 304 enables geometric modeling, and may also determine the compression level expected for the subject and / or expected for the ROI. In at least one embodiment, the compression level may vary based in part on the field of view, slice thickness, and the number of pixels or voxels required to achieve convergence of the image reconstruction and iterative process using the present systems and methods, depending on the one or more organs to be scanned in the ROI in question.

[0071] The first compression level is the highest compression level and has the least number of data points among the other compression levels from the geometric modeling module 304. When determining to organize the data into compression levels, the detector can be instructed to collect the data in a certain manner. For example, the module 304 can communicate with Figure 1 The system controller discussed in is bidirectional. The first compression level also has the most relevant data, which primarily represents one or more slices (or one or more subsets) of the data collected during the radiation phase of the tomography process. Because the data includes subsets, references to the smallest number of subsets can interchangeably refer to the smallest number of data points. In at least one embodiment, the first compression level is determined from the subset of the data (having the smallest number of data points in the data), including based in part on how the data was collected and the configuration of active detectors during data collection. In at least one embodiment, the subset of data that skips adjacent data groups can have the most relevant or most discriminating features because the data subset is determined at a higher level viewpoint and minor differences in boundaries between colors and brightness at lower level viewpoints can be ignored. In at least one embodiment, using a configuration in which selected detectors in the detector array are active rather than activating all detectors can result in a smaller number of data points, but still accommodate the most relevant and most discriminating features in the ROI.

[0072] In the optimal parameterization module 308, at least one reconstruction parameter and reconstruction algorithm are established for the first compression level. The reconstruction parameters and reconstruction algorithm are provided from the optimal parameterization module 306 to the core reconstruction module 308. In at least one embodiment, one of many available algorithms can be used to test the number of data subsets (e.g., the data subset associated with the first compression level). In at least one embodiment, the regularized ordered subset expectation maximization (OSEM) algorithm is an available algorithm that can be used to find the optimal number of data points in the data subset required to achieve convergence. OSEM can be used with a regularization parameter. The number of iterations, calculations, or loops required to determine an appropriate regularization parameter may be excessive, but using a smaller number of data points in the first compression level, this exercise may be more manageable. When two or more such regularization parameters are obtained, the parameters and number of iterations can be applied to subsequent compression levels to converge the data at the corresponding subsequent compression levels. When two or more such regularization parameters are used in a subsequent compression level, and it is determined that the two or more such regularization parameters may benefit from a revision to create two or more revised regularization parameters, the revised regularization parameters may be used with the algorithm and may be used for subsequent compression levels after the revision. In addition, different regularization parameters or other parameters may also be used in place of previously used parameters for subsequent compression levels of the applied algorithm. This may depend, for example, on whether the subsequent compression level results in an optimization through an iterative process of the applied algorithm.

[0073] Other iterative algorithms and their associated parameters can be used to test the number of data subsets in multiple GPUs of a multi-GPU architecture. GPUs have thousands of cores and are designed to handle massive parallel workloads. In the present disclosure, portions of the processes explained throughout the present disclosure are executed on multiple GPUs in real-time communication with a processing module such as Figure 1 Module 114) includes a central processing unit (CPU). Optionally, a GPU (such as Figure 1The GPU 112A of the module 112 in the embodiment of the present invention can be used to perform the entire process for multi-level image reconstruction disclosed herein. However, because the GPU has different performance and cost characteristics from the CPU, running a service that offloads a portion of the process to the GPU may require that its design is different and effective from that of a normal CPU-based service. In at least one embodiment, the GPU may be able to process thousands of parameters and algorithms concurrently via different hardware threads. In at least one embodiment, multiple graphics processing units (GPUs) using a multi-GPU architecture simultaneously perform iterative processing of selecting parameters and one or more algorithms in a first compression level to test different parameters and different algorithms using one or more subsets of the image data captured by the ROI. When constrained optimization is achieved in the first compression level, including, for example, convergence of iterative processing of one of the parameter and algorithm combinations, the process stops, and the parameters and algorithms can be used for all data of the first compression level and subsequent compression levels.

[0074] The optimal number of data points is one of many other regularization parameters that can be used as reconstruction parameters in the first compression level. In at least one embodiment, a test can be first applied to determine the iterative convergence of a test portion of a subset of data associated with the first compression level. The test can be performed for simulated or expected data as a reference. The result of the test is the convergence achieved, which represents the optimal number of data points required for the algorithm to achieve convergence. In this way, the algorithm can be established as a reconstruction algorithm, and the optimal number of data subsets can be established as at least one reconstruction parameter for the first compression level. In at least one embodiment, the above test can be performed using the entire data subset associated with the first compression level. In at least one embodiment of the iterative process, after each iteration cycle, an error is generated by comparing at least a portion of the data subset with the simulated or expected data, and the error can be applied to the increasing or decreasing value in the simulated or expected data. Ultimately, the error becomes smaller as the iteration cycle increases until the simulated or expected data converges to the data subset associated with the first compression level.

[0075] Since the first compression level represents the highest compression level of the data, the data subset for the first compression level includes the least number of data points compared to the data subsets for subsequent compression levels. Once the reconstruction algorithm and reconstruction parameters are established, this information can be stored in the optimal parameterization module 306. The core reconstruction module 308 uses the established reconstruction algorithm and the established reconstruction parameters to process the entire data subset of the first compression level. Using the established reconstruction algorithm and the established reconstruction parameters, a first image volume for the first compression level is determined at the end of each iteration. When a portion of the data subset associated with the first compression level is tested, the established reconstruction algorithm that uses the test portion of the subset to achieve convergence to simulated or expected data is expected to also achieve convergence to the entire subset by extrapolation, interpolation or upsampling. Once convergence is achieved, it can be determined that the first image volume from a plurality of first image volumes meets a predetermined criterion. On the one hand, the predetermined criterion can be to generate the first image volume after achieving convergence or when convergence. In at least one embodiment, the first image volume is an image volume that indicates an iterative cycle of convergence, which represents a constrained optimization in the first compression level. This determination qualifies the first image volume as a first initializer image volume for a second compression level.The first image volume may be stored in the initializer module block 310 for use in subsequent compression levels.

[0076] The second compression level has a higher number of data points than the first compression level, and is a compression level lower than the first compression level. Therefore, an upsampling step is applied in the core reconstruction module 308 to upsample the first initializer image volume to the requirement of the second compression level. In a similar manner, the present disclosure requires that after the second compression level, each level in the remaining compression level is iterated through. This is performed in the core reconstruction module 308, wherein the initializer module 310 stores the initializer image 310A after achieving convergence in each compression level or when achieving convergence. After upsampling to subsequent levels from each previous level, the image volume from the previous level is used for the subsequent levels in each level. In addition, using at least one reconstruction parameter, iteration can be started at least for the subsequent level. In this way, the image volume of the previous level that is upsampled becomes the subsequent initializer image volume for the subsequent level. After iteration, a final image volume 312 is generated. The final image volume 312 shows convergence to the simulated image volume, so that the image 312 of the basic features of the tissue can be reconstructed.

[0077] In addition, for a given set of algorithms and their associated parameters, the present disclosure is able to use different compression levels representing different data sets with different numbers of data points to determine which parameters are appropriate for each of the multiple data sets. Thereafter, only certain parameters and certain algorithms may be used on certain data sets. Prior to the tomography process, this may be an experimental process to determine which algorithms and parameters are best suited for scanning of the intended organ (e.g., relative to other organs or objects).

[0078] Figure 4 4 is a feature diagram showing an example of a calculated feature 400 in each stage of a multi-level tomography process according to at least one embodiment of the present disclosure, the multi-level tomography process using multiple GPUs to reconstruct an image. The compression level can be established before or after the data is captured. The compression level can indicate how the data is collected and stored for processing. In at least one embodiment, if the detector array is configured to provide data from alternating detectors of the detector array, the data can be captured after the compression level indicates the manner of the data, as previously discussed, the data received from the detector is stored in the data array. When the tomography system is configured to selectively use the data in the data array after all detectors provide data, the compression level is established after the data is captured. In at least one embodiment, the compression level is based in part on the geometry of the ROI. The geometry may change when the detector moves to different cross-sections or slices to cover the ROI. The geometry may also change according to the organs within different parts of the ROI. In at least one embodiment, boxes 402A-402N include geometries established for different compression levels, and the different compression levels are shown as spatial level 1 (geometry 1) to spatial level N (geometry N).

[0079] Based in part on the geometry, the core reconstruction first performs core reconstruction 1 402B. Core reconstruction 1 block 402B includes instructions for performing a first iterative process on a subset of data representing a first compression level provided from block 402A. The first iterative process uses parameters associated with one or more algorithms selected for the first compression level to generate a first data set represented by block 402B entitled Reconstruction Volume 1. Figure 2 , 4Parameters and one or more algorithms are selected in a similar manner as discussed in the aspects of FIG. The first data set may be a first initializer image volume for a first compression level. As previously discussed, the first data set is upsampled via box 408A so that it has enough data for slicing, which matches the size of the second data slice contained in box 404B titled Core Reconstruction 2. Box 404B receives a second slice representing a second compression level from box 402B titled Space Level 2 (Geometry 2). As previously described, the same parameters and algorithms as the first compression level may be used here, because the parameters and algorithms were previously selected to be able to iterate the most important features at the highest compression level. Optionally, different parameters and different algorithms may be used by first testing a portion of the second subset of data from box 402B. The different parameters may be completely different from the parameters previously used for the first or second data subsets, but may also be improvements to the previously used parameters (e.g., reducing the number of iterations, in at least one embodiment). As described elsewhere herein, the parameter may be the number of cycles used to achieve optimal performance of the algorithm (e.g., constrained optimization), or may be the minimum number of data points required to achieve optimal performance of the algorithm. Thus, the improvement may be a reduction in the number of loops or a reduction in the number of data points required in a subsequent compression level in order to achieve optimal performance of the algorithm in the subsequent compression level. As previously described elsewhere in this disclosure, testing may be performed in multiple GPUs until convergence is reached in at least one of the available algorithms that processes a portion of the second data subset. The at least one of the available algorithms then becomes the reconstruction algorithm for the second compression level, and at least the relevant parameters for iteratively processing the entire second data subset from block 402B.

[0080] Frame 406B shows the output of core reconstruction 2 frame 404B. Output 406B is a second data set, which can be a second initializer image volume for a second compression level. As in the case of frame 408A, the second initializer image volume is upsampled to include enough data in the associated slice, and the data can be used for a compression level lower than the second compression level. Repeat this process until frame 402N is used to select the geometry in the uncompressed space. Frame 404N uses N-1 initializer image volumes sampled via frame 408N-1 from the previous compression level to perform core reconstruction. The final image volume N in frame 406N represents the image volume of the image of the representation used to reconstruct the ROI.

[0081] Figure 5500 is a process flow of steps that can be used for multi-level tomographic reconstruction of images according to at least one embodiment of the present disclosure. In subprocess 502, data is obtained from radiation passing through tissue. Subprocess 504 establishes a compression level for the data. As described throughout the present disclosure, the compression level can be established first, and then the data is obtained according to subprocess 502, so that the data is obtained at the highest to lowest compression level. In this way, the data can be obtained first or after the compression level is established. The compression level can be established by assigning the data into data subsets. In this way, the compression level includes increasing the number of data points in the subset. Each subset of the data can correspond to a data slice that includes a different view at a cross-section of the tissue. Therefore, the first compression level can have the least number of data points in the subset. Subprocess 506 establishes reconstruction parameters and a reconstruction algorithm for the first compression level.

[0082] Subprocess 508 performs a determination step for determining a first image volume using reconstruction parameters and a reconstruction algorithm. Subprocess 510 determines a first image volume among a plurality of first image volumes. The process can be completed by verifying that the first image volume meets a predetermined criterion via subprocess 512 to make the first image volume qualified as a first initializer image volume for a second compression level via subprocess 514. In at least one embodiment, the predetermined criterion can be that the first image volume is generated after the iteration is completed and convergence is achieved for the compression level in question. Otherwise, iteration is continued via subprocess 510. Alternatively, for non-iterative processing within a compression level, if a filter is applied using an FBP process and the resulting image volume has a minimum amount of blur, the image volume can be used as an initializer image for a second compression level via subprocess 514. Otherwise, the image volume is filtered via subprocess 510. Subprocess 516 upsamples the first initializer image volume to meet the requirements of the second compression level. For example, this can include injecting insignificant data into cells of an array of appropriate size for second-level compression.

[0083] Subprocess 518 shows that process 500 performs subprocesses 508-516 at least iteratively. In at least one embodiment, subprocess 518 iterates through each level in the remaining compression levels after the second compression level. Subprocess 518 uses the image volume from the previous level as the subsequent initializer image volume for the subsequent level in each level, and uses at least one reconstruction parameter. The image volume of the previous level is first upsampled to the subsequent initializer image volume. Subprocess 520 generates the final image volume after iteration. The final image volume converges to the simulated image volume and enables the image of the basic features of the tissue to be reconstructed.

[0084] Data Center

[0085] Fig. 6A It shows that you can use Figure 1-5 In at least one embodiment, the data center 600 includes a data center infrastructure layer 610, a framework layer 620, a software layer 630, and an application layer 640. In at least one embodiment, with respect to Figure 1 In at least one embodiment described in, features such as in components 110-116 may be performed within or in cooperation with the example data center 600. In at least one embodiment, the image 108 captured from the detector may be partially or fully processed in the processing module 114 and the reconstruction module 112, but may also be partially or fully processed in one or more components of the data center infrastructure layer 610. This allows advanced computations to occur at high speed in a dedicated computing environment that may (or may not) need to be locally available.

[0086] In at least one embodiment, Fig. 6A As shown, the data center infrastructure layer 610 may include a resource coordinator 612, group computing resources 614, and node computing resources ("node CRs") 616 (1)-616 (N), where "N" represents any complete positive integer. In at least one embodiment, the node CRs 616 (1)-616 (N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node CRs 616 (1)-616 (N) may be a server having one or more of the above-mentioned computing resources.

[0087] In at least one embodiment, the grouped computing resources 614 may include a separate grouping (not shown) of node CRs housed in one or more racks, or many racks (also not shown) housed in data centers at various geographic locations. The separate grouping of node CRs within the grouped computing resources 614 may include computing, networks, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including a CPU or processor may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0088] In at least one embodiment, resource coordinator 612 may configure or otherwise control one or more nodes CR 616(1)-616(N) and / or grouped computing resources 614. In at least one embodiment, resource coordinator 612 may include a software design infrastructure ("SDI") management entity for data center 600. In at least one embodiment, resource coordinator 612 may include hardware, software, or some combination thereof.

[0089] In at least one embodiment, Fig. 6A As shown, the framework layer 620 includes a job scheduler 622, a configuration manager 624, a resource manager 626, and a distributed file system 628. In at least one embodiment, the framework layer 620 may include a framework that supports software 632 of the software layer 630 and / or one or more applications 642 of the application layer 640. In at least one embodiment, the software 632 or the application 642 may include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 620 may be, but is not limited to, a free and open source software network application framework, such as Apache SparkTM (hereinafter referred to as "Spark") that can utilize the distributed file system 628 for large-scale data processing (e.g., "big data"). In at least one embodiment, the job scheduler 622 may include a Spark driver to facilitate scheduling of workloads supported by various layers of the data center 600. In at least one embodiment, the configuration manager 624 may be able to configure different layers, such as the software layer 630 and the framework layer 620 including Spark and a distributed file system 628 for supporting large-scale data processing. In at least one embodiment, the resource manager 626 can manage clustered or grouped computing resources that are mapped to or allocated to support the distributed file system 628 and the job scheduler 622. In at least one embodiment, the clustered or grouped computing resources can include grouped computing resources 614 on the data center infrastructure layer 610. In at least one embodiment, the resource manager 626 can coordinate with the resource coordinator 612 to manage these mapped or allocated computing resources.

[0090] In at least one embodiment, software 632 included in software layer 630 may include software used by at least a portion of node CRs 616(1)-616(N), grouped computing resources 614, and / or distributed file system 628 of framework layer 620. One or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0091] In at least one embodiment, one or more applications 642 included in the application layer 640 may include one or more types of applications used by at least a portion of the node CRs 616(1)-616(N), the grouped computing resources 614, and / or the distributed file system 628 of the framework layer 620. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0092] In at least one embodiment, any of configuration manager 624, resource manager 626, and resource coordinator 612 can implement any number and type of self-modification actions based on any number and type of data acquired in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 600 from making potentially bad configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0093] In at least one embodiment, data center 600 may include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information according to one or more embodiments herein. In at least one embodiment, a machine learning model can be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 600. In at least one embodiment, using the weight parameters calculated by one or more training techniques herein, the resources described above with respect to data center 600 can be used to infer or predict information using a trained machine learning model corresponding to one or more neural networks. As previously discussed, deep learning techniques can be used to fill in the gaps between the detectors (e.g., Figure 1 The data gaps caused by the detector 108 in the data center 600 are used to provide multiple levels of compression that are subsequently processed in one aspect disclosed herein. Any suitable learning network and computing capabilities of the data center 600 can be used to advance deep learning. Thus, in this way, the hardware in the data center can be used to simultaneously or concurrently support a deep neural network (DNN), a recurrent neural network (RNN), or a convolutional neural network (CNN). For example, once the network is trained and successfully evaluated to identify data in a subset or slice, the trained network can provide similar representative data for use with the collected data.

[0094] In at least one embodiment, the data center 600 can use a CPU, an application-specific integrated circuit (ASIC), a GPU, an FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0095] Reasoning and training logic

[0096] Reasoning and / or training logic 615 may be used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, reasoning and / or training logic 615 may be used in the system Fig. 6A Inference and / or training logic 615 may be used to reason or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases herein. In at least one embodiment, reasoning and / or training logic 615 may include, but is not limited to, hardware logic in which computing resources are dedicated or otherwise uniquely used in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, reasoning and / or training logic 615 may be used in conjunction with an application specific integrated circuit (ASIC), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel Corp (e.g. "LakeCrest") processor.

[0097] In at least one embodiment, the reasoning and / or training logic 615 can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (e.g., field programmable gate array (FPGA)). In at least one embodiment, the reasoning and / or training logic 615 includes, but is not limited to, a code and / or data storage model that can be used to store code (e.g., graphics code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameters or hyperparameter information. In at least one embodiment, each code and / or data storage module is associated with a dedicated computing resource. In at least one embodiment, the dedicated computing resource includes computing hardware that also includes one or more ALUs that perform mathematical functions (e.g., linear algebra functions) only on information stored in the code and / or data storage module, and stores the results stored therefrom in an activated storage module of the reasoning and / or training logic 615.

[0098] Figure 6B , Figure 6CInference and / or training logic according to at least one embodiment is shown, such as in Fig. 6A The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with at least one embodiment of the present disclosure. Figure 6B and / or Figure 6C Provides details about the inference and / or training logic 615. Distinguished from the computational hardware 602, 606 by the use of an arithmetic logic unit (ALU) 610 Figure 6B and Figure 6C In at least one embodiment, each of computing hardware 602 and computing hardware 606 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) on information stored in code and / or data memory 601 and information stored in code and / or data memory 605, respectively, with the results stored in activation memory 620. Thus, unless otherwise specified, Figure 6B and Figure 6C may be substituted and used interchangeably.

[0099] In at least one embodiment, the inference and / or training logic 615 may include, but is not limited to, code and / or data storage 601 to store forward and / or output weights and / or input / output data and / or other parameters of neurons or layers of a neural network trained and / or used for inference in at least one embodiment. As previously described elsewhere in this disclosure, these layers may be used with a certain degree of compression. In at least one embodiment, the training logic 615 may include or be coupled to code and / or data storage 601 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, the code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, the code and / or data storage 601 stores the weight parameters and / or input / output data for each layer of the neural network trained or used in conjunction with at least one embodiment during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of at least one embodiment. In at least one embodiment, any portion of code and / or data storage 601 may be included in other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0100] In at least one embodiment, any portion of code and / or data storage 601 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data storage 601 may be cache memory, dynamic random addressable memory ("DRAM"), static random addressable memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 601 is internal or external to a processor, for example, or includes DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage space on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the data batch size used in inference and / or training of a neural network, or some combination of these factors.

[0101] In at least one embodiment, the inference and / or training logic 615 may include, but is not limited to, code and / or data storage 605 to store backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in at least one embodiment aspect of the neural network. In at least one embodiment, the code and / or data storage 605 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with at least one embodiment during backpropagation of input / output data and / or weight parameters during training and / or inference using at least one embodiment. In at least one embodiment, the training logic 615 may include or be coupled to code and / or data storage 605 for storing graph code or other software to control the timing and / or order in which weights and / or other parameter information is loaded to configure logic including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).

[0102] In at least one embodiment, code (such as graph code) loads weights or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of the code and / or data storage 605 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 605 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 605 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 605 is internal or external to the processor, for example, including DRAM, SRAM, flash memory, or some other storage type, depends on whether the available storage is on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in the inference and / or training of the neural network, or some combination of these factors.

[0103] In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be separate storage structures. In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be the same storage structure. In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be partially the same storage structure and partially separate storage structures. In at least one embodiment, any portion of code and / or data storage 601 and code and / or data storage 605 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0104] In at least one embodiment, inference and / or training logic 615 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 610, ALUs 610 comprising integer and / or floating point units for performing logic and / or mathematical operations based at least in part on or as directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from a layer or neuron within a neural network) stored in activation storage 620, which are functions of input / output and / or weight parameter data stored in code and / or data storage 601 and / or code and / or data storage 605. In at least one embodiment, activations are performed in response to executing instructions or other code, linear algebra and / or matrix-based mathematics performed by ALU 610 to generate activations stored in activation storage 620, where weight values ​​stored in code and / or data storage 605 and / or in code and / or data storage 601 are used as operands with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 605 and / or code and / or data storage 601 or other on-chip or off-chip storage.

[0105] In at least one embodiment, one or more ALUs 610 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 610 may be outside a processor or other hardware logic device or circuit that uses them (e.g., a coprocessor). In at least one embodiment, one or more ALUs 610 may be included within an execution unit of a processor, or otherwise included in a group of ALUs accessible by an execution unit of a processor, which may be within the same processor or distributed between different processors of different types (e.g., a central processing unit, a graphics processing unit, a fixed function unit, etc.). In at least one embodiment, code and / or data storage 601, code and / or data storage 605, and activation storage 620 may be on the same processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 620 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to a processor or other hardware logic or circuitry and may be retrieved and / or processed using the processor's fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0106] In at least one embodiment, activation storage 620 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 620 may be completely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, activation storage 620 may be selected to be internal or external to a processor, for example, or to include DRAM, SRAM, flash memory, or other storage types, depending on the storage available on-chip or off-chip, the latency requirements for performing training and / or inference functions, the batch size of data used in inferencing and / or training neural networks, or some combination of these factors. In at least one embodiment, Figure 6B The inference and / or training logic 615 shown in FIG. 6 may be used in conjunction with an application specific integrated circuit (“ASIC”), such as the ASIC from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel Corp (e.g., "Lake Crest") processor. In at least one embodiment, Figure 6B The illustrated inference and / or training logic 615 may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as a field programmable gate array (“FPGA”).

[0107] In at least one embodiment, Figure 6C Inference and / or training logic 615 is shown, which may include, but is not limited to, hardware logic, wherein computing resources are dedicated or otherwise uniquely used in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network, in accordance with at least one various embodiment. In at least one embodiment, Figure 6C The inference and / or training logic 615 shown in FIG. 6 can be used in conjunction with an application specific integrated circuit (ASIC), such as the ASIC from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel Corp (e.g., "Lake Crest") processor. In at least one embodiment, Figure 6CThe inference and / or training logic 615 shown in can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (e.g., field programmable gate array (FPGA)). In at least one embodiment, the inference and / or training logic 615 includes, but is not limited to, code and / or data storage 601 and code and / or data storage 605, which can be used to store code (e.g., chart code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 6C In at least one embodiment shown in , code and / or data store 601 and code and / or data store 605 are each associated with a dedicated computing resource (eg, computing hardware 602 and computing hardware 606 ), respectively.

[0108] In at least one embodiment, each of the code and / or data stores 601 and 605 and the corresponding computing hardware 602 and 606 corresponds to a different layer of the neural network, such that activations from one "storage / compute pair 601 / 602" of the code and / or data store 601 and computing hardware 602 are provided as inputs to the next "storage / compute pair 605 / 606" of the code and / or data store 605 and computing hardware 606, so as to reflect the conceptual organization of the neural network. In at least one embodiment, each storage / compute pair 601 / 602 and 605 / 606 can correspond to more than one neural network layer. In at least one embodiment, additional storage / compute pairs (not shown) can be included in the inference and / or training logic 615 after or in parallel with the storage / compute pairs 601 / 602 and 605 / 606.

[0109] Computer Systems

[0110] Fig. 7A A block diagram of an exemplary computer system 700A is shown, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof with a processor, which may include an execution unit to execute instructions to support and / or enable multi-level image reconstruction herein, in accordance with at least one embodiment. In at least one embodiment, the computer system 700A may include, but is not limited to, components (such as processor 702) to execute algorithms for process data using execution units including logic in accordance with the present disclosure (such as the embodiments herein). In at least one embodiment, the computer system 700A may include a processor, such as an Intel® processor available from Intel Corporation of Santa Clara, California. Processor family, XeonTM, XScaleTM and / or StrongARMTM, Core TM or Nervana TM microprocessor, but other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 700B may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0111] In at least one embodiment, the exemplary computer system 700A may combine components 110-116 (from Figure 1 ) to support processing aspects for multi-level image reconstruction. At least for this reason, in one embodiment, Fig. 7A The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Fig. 7A An exemplary system-on-chip SoC may be shown. In at least one embodiment, Fig. 7A The devices shown in the figure may be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 700B are interconnected using a compute express link (CXL) interconnect. Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments, for example, as previously described with respect to Fig. 6A -C discussed below. Fig. 6A -C provides details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 may be implemented in the system Fig. 7A for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases herein.

[0112] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (Internet Protocol) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0113] In at least one embodiment, the computer system 700A may include, but is not limited to, a processor 702, which may include, but is not limited to, one or more execution units 708 to perform machine learning model training and / or reasoning according to the techniques described herein. In at least one embodiment, the computer system 700A is a single-processor desktop or server system, but in another embodiment, the computer system 700A may be a multi-processor system. In at least one embodiment, the processor 702 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements an instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 702 may be coupled to a processor bus 710, which may transmit data signals between the processor 702 and other components in the computer system 700A.

[0114] In at least one embodiment, processor 702 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 704. In at least one embodiment, processor 702 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 702. Other embodiments may also include a combination of internal and external caches, depending on the particular implementation and needs. In at least one embodiment, register file 706 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and instruction pointer registers.

[0115] In at least one embodiment, an execution unit 708, including but not limited to logic to perform integer and floating point operations, is also located in the processor 702. In at least one embodiment, the processor 702 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 708 may include logic for processing a packed instruction set 709. In at least one embodiment, by including the packed instruction set 709 in the instruction set of a general-purpose processor, and the associated circuitry to execute the instructions, packed data in the general-purpose processor 702 may be used to perform operations used by many multimedia applications. In one or more embodiments, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on the packed data, which may not require the transfer of smaller units of data on the processor's data bus to perform one or more operations one data element at a time.

[0116] In at least one embodiment, execution unit 708 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 700A may include, but is not limited to, memory 720. In at least one embodiment, memory 720 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other storage device. In at least one embodiment, memory 720 may store instructions 719 and / or data 721 represented by data signals that may be executed by processor 702.

[0117] In at least one embodiment, the system logic chip may be coupled to the processor bus 710 and the memory 720. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub ("MCH") 716, and the processor 702 may communicate with the MCH 716 via the processor bus 710. In at least one embodiment, the MCH 716 may provide a high bandwidth memory path 718 to the memory 720 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 716 may initiate data signals between the processor 702, the memory 720, and other components in the computer system 700A, and bridge data signals between the processor bus 710, the memory 720, and the system I / O 722. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 716 may be coupled to the memory 720 via a high bandwidth memory path 718 , and the graphics / video card 712 may be coupled to the MCH 716 via an Accelerated Graphics Port (“AGP”) interconnect 714 .

[0118] In at least one embodiment, the computer system 700A can use the system I / O 722 as a proprietary hub interface bus to couple the MCH 716 to an I / O controller hub ("ICH") 730. In at least one embodiment, the ICH 730 can provide direct connections to certain I / O devices through a local I / O bus. In at least one embodiment, the local I / O bus can include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to the memory 720, the chipset, and the processor 702. Examples can include, but are not limited to, an audio controller 729, a firmware hub ("Flash BIOS") 728, a wireless transceiver 726, a data store 724, a traditional I / O controller 723 including a user input and keyboard interface, a serial expansion port 727 (e.g., a universal serial bus (USB) port), and a network controller 734. The data store 724 can include a hard drive, a floppy drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0119] Figure 7B 7 is a block diagram illustrating an electronic device 700B for utilizing a processor 710 to support and / or enable multi-level image reconstruction as described herein, according to at least one embodiment. In at least one embodiment, the electronic device 700B may be, for example but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device. In at least one embodiment, the exemplary electronic device 700B may be combined with components 110-116 (from Figure 1 ) to support processing aspects for multi-level image reconstruction.

[0120] In at least one embodiment, system 700B may include, but is not limited to, a processor 710 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 710 is coupled using a bus or interface, such as an I2C bus, a system management bus ("SMBus"), a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high-definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a universal serial bus ("USB") (versions 1, 2, 3), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Figure 7B A system is shown that includes interconnected hardware devices or "chips", while in other embodiments, Figure 7B An exemplary system on a chip ("SoC") may be shown. In at least one embodiment, Figure 7BThe devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 7B One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0121] In at least one embodiment, Figure 7B The display 724, the touch screen 725, the touch pad 730, the near field communication unit ("NFC") 745, the sensor hub 740, the thermal sensor 746, the fast chipset ("EC") 735, the trusted platform module ("TPM") 738, the BIOS / firmware / flash memory ("BIOS, FW Flash") 722, the DSP 760, the drive 720 (such as a solid state disk ("SSD") or a hard disk drive ("HDD")), the wireless local area network unit ("WLAN") 750, the Bluetooth unit 752, the wireless wide area network unit ("WWAN") 756, the global positioning system (GPS) unit 755, the camera ("USB 3.0 camera") 754 (such as a USB 3.0 camera) and / or the low power double data rate ("LPDDR") memory unit ("LPDDR3") 715 implemented in, for example, the LPDDR3 standard. Each of these components can be implemented in any suitable manner.

[0122] In at least one embodiment, other components may be communicatively coupled to the processor 710 via the following components. In at least one embodiment, the accelerometer 741, ambient light sensor (“ALS”) 742, compass 743, and gyroscope 744 may be communicatively coupled to the sensor hub 740. In at least one embodiment, the thermal sensor 739, fan 737, keyboard 746, and touchpad 730 may be communicatively coupled to the EC 735. In at least one embodiment, the speaker 763, earphone 764, and microphone (“mic”) 765 may be communicatively coupled to the audio unit (“audio codec and class D amplifier”) 762, which in turn may be communicatively coupled to the DSP 760. In at least one embodiment, the audio unit 764 may include, for example, but not limited to, an audio encoder / decoder (“codec”) and a class D amplifier. In at least one embodiment, the SIM card (“SIM”) 757 may be communicatively coupled to the WWAN unit 756. In at least one embodiment, components such as the WLAN unit 750 and the Bluetooth unit 752 and the WWAN unit 756 may be implemented as a next generation form factor (NGFF).

[0123] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6B and / or Figure 6CProvides details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 may be implemented in the system Figure 7B for use in reasoning or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases herein.

[0124] Figure 7C A computer system 700C is shown according to at least one embodiment for supporting and / or implementing the multi-level image reconstruction described herein. In at least one embodiment, the computer system 700C includes, but is not limited to, a computer 771 and a USB disk 770. In at least one embodiment, the computer 771 may include, but is not limited to, any number and type of processors (not shown) and memories (not shown). In at least one embodiment, the computer 771 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0125] In at least one embodiment, the USB disk 770 includes, but is not limited to, a processing unit 772, a USB interface 774, and a USB interface logic 773. In at least one embodiment, the processing unit 772 can be any instruction execution system, device, or device capable of executing instructions. In at least one embodiment, the processing unit 772 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit or core 772 includes an application specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing core 772 is a tensor processing unit ("TPC") that is optimized to perform machine learning reasoning operations. In at least one embodiment, the processing core 772 is a visual processing unit ("VPU") that is optimized to perform machine vision and machine learning reasoning operations.

[0126] In at least one embodiment, the USB interface 774 can be any type of USB connector or USB socket. For example, in at least one embodiment, the USB interface 774 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, the USB interface 774 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 773 can include any number and type of logic that enables the processing unit 772 to connect to a device (e.g., computer 771) via the USB connector 774.

[0127] Reasoning and / or training logic 615 (e.g., regarding Figure 6B and Figure 6C The invention is described in detail and is used to perform reasoning and / or training operations related to one or more embodiments. Figure 6B and Figure 6C Provides details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 can be used to Figure 7C In a system of the present invention, operations can be inferred or predicted based at least in part on weight parameters calculated using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0128] Figure 8 A further exemplary computer system 800 for implementing the various processes and methods of multi-level image reconstruction described throughout the present disclosure is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 800 includes, but is not limited to, at least one central processing unit ("CPU") 802 connected to a communication bus 810 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 800 includes, but is not limited to, a main memory 804 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data may be stored in the main memory 804 in the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 822 provides an interface to other computing devices and networks for receiving data from the computer system 800 and transmitting data to other systems.

[0129] In at least one embodiment, computer system 800 includes, but is not limited to, input device 808, parallel processing system 812, and display device 806, which may be implemented using cathode ray tubes ("CRT"), liquid crystal displays ("LCD"), light emitting diodes ("LED"), plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 808 (such as a keyboard, mouse, touch pad, microphone, and more). In at least one embodiment, each of the above modules may be located on a single semiconductor platform to form a processing system.

[0130] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments, such as those previously described with respect to Fig. 6A -C discussed. The following combination Fig. 6A -C provides details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 may be implemented in the system Figure 8In at least one embodiment, the inference and / or training logic 615 may be used in the system to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases herein. Figure 8 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases herein.

[0131] Fig. 9A An exemplary architecture is shown in which multiple GPUs 910-913 are communicatively coupled to multiple multi-core processors 940-943 via high-speed links 905-906 (e.g., bus / point-to-point interconnect, etc.). In one embodiment, the high-speed links 940-943 support 4GB / s, 30GB / s, 80GB / s, or higher communication throughput. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0132] Furthermore, in one embodiment, two or more GPUs 910-913 are interconnected via high-speed links 929-930, which may be implemented using the same or different protocols / links as used for high-speed links 940-943. Similarly, two or more multi-core processors 905-906 may be connected via high-speed link 928, which may be a symmetric multiprocessor (SMP) bus running at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, the same protocol / links may be used (e.g., via a common interconnect fabric) to accomplish the above. Fig. 9A All communications between the various system components shown in .

[0133] In one embodiment, each multi-core processor 905-906 is communicatively coupled to processor memory 901-902 via memory interconnects 926-927, respectively, and each GPU 910-913 is communicatively coupled to GPU memory 920-923 via GPU memory interconnects 950-953, respectively. The memory interconnects 926-927 and 950-953 may utilize the same or different memory access technologies. By way of example and not limitation, the processor memory 901-902 and the GPU memory 920-923 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram. In one embodiment, some portion of the processor memory 901-902 may be volatile memory, while another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0134] As follows, although the various processors 905-906 and GPUs 910-913 may be physically coupled to specific memories 901-902, 920-923, respectively, a unified memory architecture may be implemented in which a virtual system address space (also referred to as an "effective address" space) is distributed among the various physical memories. In at least one embodiment, the processor memories 901-902 may each include 64GB of system memory address space, and the GPU memories 920-923 may each include 32GB of system memory address space (resulting in a total addressable memory size of 256GB in this example).

[0135] As discussed elsewhere in this disclosure, at least one reconstruction parameter and reconstruction algorithm are established for the first compression level. Because the first compression level represents the highest compression level for the data, it also represents a smaller subset of data that can be converged in an iterative process using simulated data from a simulated data set. In at least one embodiment, an algorithm for reconstruction can be determined by testing one or more iterative or non-iterative algorithms using a subset of data from the first compression level. Fig. 9AThe tests are performed in parallel on multiple GPUs of a multi-GPU architecture in the example. When convergence is achieved in one of the tests using one of the available algorithms, the number of data points in the data subset used to cause convergence is recorded. For non-iterative algorithms, the resulting image volume after filtering to remove blur and other noise can be used to determine whether the non-iterative algorithm and the applied filtering can be used to establish a reconstruction algorithm and at least one reconstruction parameter. Since the quantity can be a test quantity, for example, the quantity can be extrapolated or upsampled for use in the entire data subset. The number of data points in the first subset of the data can be considered as the optimal number for the first subset of the data and subsequent subsets, the data representing the first and subsequent compression levels. The number of data points is then represented as the reconstruction parameters established in the reconstruction phase of the image of the underlying features of the tissue. The algorithm used to achieve convergence with the optimal number of data points is considered to be the reconstruction algorithm of the reconstruction phase.

[0136] Fig. 9B Additional details for interconnection between multi-core processor 907 and graphics acceleration module 946 are shown according to an exemplary embodiment. Graphics acceleration module 946 may include one or more GPU chips integrated on a line card that is coupled to processor 907 via high-speed link 940. Optionally, graphics acceleration module 946 may be integrated with processor 907 on the same package or chip.

[0137] In at least one embodiment, the processor 907 shown includes multiple cores 960A-960D, each core having a translation lookaside buffer 961A-961D and one or more caches 962A-962D. In at least one embodiment, the cores 960A-960D may include various other components not shown for executing instructions and processing data. The caches 962A-962D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 956 may be included in the caches 962A-962D and shared by each group of cores 960A-960D. In at least one embodiment, one embodiment of the processor 907 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. The processor 907 and the graphics acceleration module 946 are connected to the system memory 914, which may include Fig. 9A Processor memory 901-902 in.

[0138] Coherence is maintained for data and instructions stored in the various caches 962A-962D, 956 and system memory 914 via inter-core communications over the coherence bus 964. In at least one embodiment, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 964 in response to detecting a read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over the coherence bus 964 to snoop cache accesses.

[0139] In at least one embodiment, the proxy circuit 925 communicatively couples the graphics acceleration module 946 to the coherence bus 964, thereby allowing the graphics acceleration module 946 to participate in a cache coherence protocol as a peer of the cores 960A-960D. In particular, in at least one embodiment, the interface 935 provides a connection to the proxy circuit 925 via a high-speed link 940 (e.g., a PCIe bus, NVLink, etc.), and the interface 937 connects the graphics acceleration module 946 to the link 940.

[0140] In one implementation, the accelerator integrated circuit 936 provides cache management, memory access, context management, and interrupt management services on behalf of multiple graphics processing engines 931, 932, N of the graphics acceleration module. The graphics processing engines 931, 932, N may each include a separate graphics processing unit (GPU). In at least one embodiment, the graphics processing engines 931, 932, N may selectively include different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 946 may be a GPU having multiple graphics processing engines 931-932, N, or the graphics processing engines 931-932, N may be individual GPUs integrated on a common package, line card, or chip. As appropriate, the graphics processing engines 931-932, N may be integrated into a common package, line card, or chip. Fig. 9B The above determination of the reconstruction parameters and the reconstruction algorithm is performed in the GPU 931-N.

[0141] In one embodiment, the accelerator integrated circuit 936 includes a memory management unit (MMU) 939 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation), and also includes a memory access protocol for accessing the system memory 914. The MMU 939 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective to physical / real address translations. In one implementation, the cache 938 may store commands and data for efficient access by the graphics processing engine 931-932, N. In at least one embodiment, the data stored in the cache 938 and the graphics memory 933-934, M may be kept consistent with the core caches 962A-962D, 956 and the system memory 914. As before, this task may be accomplished via proxy circuitry 925 acting on behalf of cache 938 and graphics memory 933-934, M (e.g., sending updates related to modifications / accesses of cache lines on processor caches 962A-962D, 956 to cache 938 and receiving updates from cache 938).

[0142] A set of registers 945 stores context data for threads executed by the graphics processing engines 931-932, N, and context management circuitry 948 manages thread contexts. In at least one embodiment, context management circuitry 948 may perform save and restore operations to save and restore contexts for various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). In at least one embodiment, context management circuitry 948 may store current register values ​​to a specified area in memory (e.g., identified by a context pointer) upon context switching. The register values ​​may then be restored when returning to context. In one embodiment, interrupt management circuitry 947 receives and processes interrupts received from system devices.

[0143] In one implementation, the MMU 939 converts virtual / effective addresses from the graphics processing engine 931 into real / physical addresses in the system memory 914. One embodiment of the accelerator integrated circuit 936 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 946 and / or other accelerator devices. The graphics accelerator module 946 can be dedicated to a single application executed on the processor 907, or can be shared between multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 931-932, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on processing requirements and priorities associated with VMs and / or applications.

[0144] In at least one embodiment, the accelerator integrated circuit 936 performs as a bridge to the system of graphics acceleration modules 946 and provides address translation and system memory cache services. In addition, the accelerator integrated circuit 936 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management of the graphics processing engines 931-932, N.

[0145] Since the hardware resources of the graphics processing engines 931-932, N are explicitly mapped to the real address space seen by the host processor 907, any host processor can directly address these resources using effective address values. In at least one embodiment, one function of the accelerator integrated circuit 936 is to physically separate the graphics processing engines 931-932, N so that they appear to the system as independent units.

[0146] In at least one embodiment, one or more graphics memories 933-934, M are respectively coupled to each graphics processing engine 931-932, N. The graphics memories 933-934, M store instructions and data, which are processed by each graphics processing engine 931-932, N. The graphics memories 933-934, M may be volatile memories, such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories, such as 3DXPoint or Nano-Ram.

[0147] In one embodiment, to reduce data traffic on link 940, biasing techniques are used to ensure that data stored in graphics memory 933-934, M is data that is most frequently used by graphics processing engines 931-932, N, and that may not be used (at least not frequently) by cores 960A-960D. Similarly, the biasing mechanism attempts to keep data that is needed by a core (and may not be graphics processing engine 931-932, N) in cache 962A-962D, core 956, and system memory 914.

[0148] Fig. 9C Another exemplary embodiment is shown in which an accelerator integrated circuit 936 is integrated into the processor 907 for enabling and / or supporting multi-level image reconstruction according to at least one embodiment disclosed herein. In at least this embodiment, the graphics processing engines 931-932, N communicate directly with the accelerator integrated circuit 936 via the interface 937 and the interface 935 (again, any form of bus or interface protocol can be used) through the high-speed link 940. The accelerator integrated circuit 936 can perform related Fig. 9BThe operations described above are similar to the operations described above. However, due to its close proximity to the coherence bus 964 and caches 962A-962D, 956, it may have a higher throughput. At least one embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), and the programming models may include a programming model controlled by the accelerator integrated circuit 936 and a programming model controlled by the graphics acceleration module 946.

[0149] In at least one embodiment, the graphics processing engines 931-932, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to the graphics processing engines 931-932, N, thereby providing virtualization within a VM / partition.

[0150] In at least one embodiment, the graphics processing engines 931-932, N can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a system hypervisor to virtualize the graphics processing engines 931-932, N to allow each operating system to access. For a single partition system without a hypervisor, the operating system owns the graphics processing engines 931-932, N. In at least one embodiment, the operating system can virtualize the graphics processing engines 931-932, N to provide access to each process or application.

[0151] In at least one embodiment, the graphics acceleration module 946 or individual graphics processing engines 931-932, N use a process handle to select a process element. In at least one embodiment, the process element is stored in the system memory 914 and can be addressed using the effective address to real address conversion technology of this article. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 931-932, N (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the process element linked list.

[0152] Fig.9DAn exemplary accelerator integrated slice 990 for implementing and / or supporting multi-level image reconstruction according to at least one embodiment disclosed herein is shown. As used herein, a "slice" includes a specified portion of the processing resources of the accelerator integrated circuit 936. The application is an effective address space 982 in the system memory 914, which stores a process element 983. In at least one embodiment, the process element 983 is stored in response to a GPU call 981 from an application 980 executed on the processor 907. The process element 983 contains the process state of the corresponding application 980. The work descriptor (WD) 984 contained in the process element 983 can be a single job requested by the application, or can contain a pointer to a job queue. In at least one embodiment, the WD 984 is a pointer to a job request queue in the address space 982 of the application.

[0153] Graphics acceleration module 946 and / or individual graphics processing engines 931-932, N can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure for setting process state and sending WD 984 to graphics acceleration module 946 to start a job in a virtualized environment can be included.

[0154] In at least one embodiment, the dedicated process programming model is implementation specific. In this model, a single process owns a graphics acceleration module 946 or an individual graphics processing engine 931. When the graphics acceleration module 946 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 946 is assigned, the operating system initializes the accelerator integrated circuit 936 for the owned process.

[0155] In operation, the WD acquisition unit 991 in the accelerator integrated slice 990 acquires the next WD 984, which includes an indication of the work to be completed by one or more graphics processing engines of the graphics acceleration module 946. Data from the WD 984 can be stored in registers 945 and used by the MMU 939, interrupt management circuits 947, and / or context management circuits 948, as shown. In at least one embodiment, an embodiment of the MMU 939 includes a segment / page roaming circuit for accessing a segment / page table 986 within the OS virtual address space 985. The interrupt management circuit 947 can handle interrupt events 992 received from the graphics acceleration module 946. In at least one embodiment, when performing graphics operations, the effective address 993 generated by the graphics processing engine 931-932, N is converted to a real address by the MMU 939.

[0156] In one embodiment, the same register set 945 is replicated for each graphics processing engine 931-932, N and / or graphics acceleration module 946, and the same register set 945 can be initialized by a hypervisor or operating system. Each of these replicated registers can be included in an accelerator integrated slice 990. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0157] Table 1 – Hypervisor Initialization Registers

[0158] 1 Slice Control Register 2 Real address (RA) dispatch process area pointer 3 Permission Mask Override Register 4 Interrupt vector table entry offset 5 Interrupt Vector Table Entry Limits 6 Status Register 7 Logical partition ID 8 Real Address (RA) Hypervisor Accelerator Utilizes Record Pointers 9 Storage Description Register

[0159] Example registers that may be initialized by the operating system are shown in Table 2.

[0160] Table 2 – Operating System Initialization Registers

[0161] 1 Process and thread identification 2 Effective Address (EA) context save / restore pointer 3 Virtual Address (VA) Accelerator Utilizes Record Pointers 4 Virtual Address (VA) Segment Table Pointer 5 Permission shielding 6 Job Descriptor

[0162] In at least one embodiment, each WD 984 is specific to a particular graphics acceleration module 946 and / or graphics processing engine 931-932, N. It contains all the information needed by the graphics processing engine 931-932, N to complete the work, or it can be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0163] Fig.9E Additional details of an exemplary embodiment of a sharing model are shown. This embodiment includes a hypervisor real address space 998 in which a process element list 999 is stored. The hypervisor real address space 998 can be accessed via a hypervisor 996, which virtualizes a graphics acceleration module engine for an operating system 995.

[0164] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 946. There are two programming models where the graphics acceleration module 946 is shared by multiple processes and partitions, namely, time-sliced ​​sharing and graphics-directed sharing.

[0165] In this model, the hypervisor 996 owns the graphics acceleration module 946 and makes its functionality available to all operating systems 995. For the graphics acceleration module 946 to support virtualization through the hypervisor 996, the graphics acceleration module 946 may comply with the following requirements: (1) the application's job request must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 946 must provide a context save and restore mechanism, (2) the graphics acceleration module 946 guarantees that the application's job request is completed within a specified amount of time, including any transition errors, or the graphics acceleration module 946 provides the ability to preempt job processing, and (3) fairness between graphics acceleration module 946 processes must be ensured when operating in a directed shared programming model.

[0166] In one embodiment, the application 980 is required to use the graphics acceleration module type, work descriptor (WD), permission mask register (AMR) value and context save / restore region pointer (CSRP) to make an operating system 995 system call. The graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 946 and can take the form of a graphics acceleration module 946 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure describing the work to be completed by the graphics acceleration module 946. In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that sets the AMR. If the implementation of the accelerator integrated circuit 936 and the graphics acceleration module 946 does not support the user permission mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 996 may apply the current privilege mask overwrite register (AMOR) value before placing the AMR into the process element 983. In at least one embodiment, the CSRP is one of the registers 945 that contains the effective address of an area in the application's effective address space 982 for the graphics acceleration module 946 to save and restore context state. This pointer is used in at least one embodiment and is optional if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be fixed system memory.

[0167] Upon receiving the system call, the operating system 995 may verify that the application 980 has been registered and granted permission to use the graphics acceleration module 946. The operating system 995 then calls the hypervisor 996 using the information shown in Table 3.

[0168] Table 3 – OS to hypervisor call parameters

[0169] 1 Work Descriptor (WD) 2 Access Mask Register (AMR) value (potentially masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Usage Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0170] Upon receiving the hypervisor call, the hypervisor 996 verifies that the operating system 995 has registered and is granted permission to use the graphics acceleration module 946. The hypervisor 996 then places the process element 983 into a linked list of process elements of the corresponding graphics acceleration module 946 type. The process element may include the information shown in Table 4.

[0171] Table 4 – Process element information

[0172] 1 Work Descriptor (WD) 2 The authority mask register (AMR) value (potentially masked). 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Usage Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt vector table, derived from the hypervisor call parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) Hypervisor Accelerator Using Record Pointers 12 Storage Descriptor Register (SDR)

[0173] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 990 registers 945 .

[0174] like Fig.9F As shown, in at least one embodiment, a unified memory is used, and the unified memory can be addressed via a common virtual memory address space for accessing physical processor memories 901-902 and GPU memories 920-923. In this implementation, operations executed on GPUs 910-913 use the same virtual / effective memory address space to access processor memories 901-902, and vice versa, thereby simplifying programmability. In one embodiment, the first part of the virtual / effective address space is allocated to processor memory 901, the second part is allocated to the second processor memory 902, the third part is allocated to GPU memory 920, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed in each of processor memories 901-902 and GPU memories 920-923, thereby allowing any processor or GPU to access the memory using a virtual address mapped to any physical memory.

[0175] In one embodiment, bias / coherency management circuits 994A-994E within one or more MMUs 939A-939E ensure cache coherency between caches of one or more host processors (e.g., 905) and GPUs 910-913 and implement biasing techniques that indicate physical memory where certain types of data should be stored. Fig.9FMultiple instances of bias / consistency management circuits 994A- 994E are shown in , but bias / consistency circuits may be implemented within an MMU of one or more host processors 905 and / or within an accelerator integrated circuit 936 .

[0176] One embodiment allows the GPU additional memory 920-923 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) technology, but without suffering from the performance defects associated with full system cache coherence. In at least one embodiment, the ability to access the GPU additional memory 920-923 as system memory without heavy cache coherence overhead provides a favorable operating environment for GPU offloading. This arrangement allows the host processor 905 software to set operands and access calculation results without the overhead of traditional I / O DMA data copying. Such traditional copies include driver calls, interrupts, and memory mapped I / O (MMIO) accesses, which are all less efficient than simple memory accesses. In at least one embodiment, the ability to access the GPU additional memory 920-923 without cache coherence overhead may be critical to the execution time of the offloaded calculation. For example, in the case of a large amount of streaming write memory traffic, the cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 910-913. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU calculation may play a role in determining the effectiveness of GPU offloading.

[0177] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU attached memory page. In at least one embodiment, the bias table can be implemented in the stolen memory range of one or more GPU attached memories 920-923 with or without a bias cache in the GPU 910-913 (e.g., to cache frequently / recently used entries of the bias table). Alternatively, the entire bias table can be maintained within the GPU.

[0178] In at least one embodiment, before actually accessing the GPU memory, the bias table entry associated with each access to the GPU additional memory 920-923 is accessed, resulting in the following operations. Local requests from GPUs 910-913 that find their pages in the GPU bias are forwarded directly to the corresponding GPU memory 920-923. Local requests from GPUs that find their pages in the host bias are forwarded to processors 905 (e.g., through high-speed links as above). In one embodiment, the request from processor 905 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request pointing to a GPU bias page can be forwarded to GPUs 910-913. In at least one embodiment, if the GPU is not currently using the page, the GPU can then migrate the page to the host processor bias. In at least one embodiment, the bias state of the page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or in limited cases by a purely hardware-based mechanism.

[0179] One mechanism for changing the bias state employs an API call (e.g., OpenCL) that in turn calls the GPU's device driver, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in some migrations, performs a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 905 bias to GPU bias, but not for the reverse migration.

[0180] In one embodiment, cache coherency is maintained by temporarily rendering GPU biased pages that cannot be cached by the host processor 905. To access these pages, the processor 905 may request access from the GPU 910, which may or may not immediately grant access. Therefore, in order to reduce communication between the processor 905 and the GPU 910, it is beneficial to ensure that the GPU biased pages are the pages required by the GPU and not the pages required by the host processor 905, and vice versa.

[0181] Reasoning and / or training logic 615 is used to perform one or more embodiments. Figure 6B and / or Figure 6C Details regarding the inference and / or training logic 615 are provided.

[0182] Fig. 10AAn exemplary integrated circuit and associated graphics processor according to various embodiments of the present invention are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0183] Fig. 10A 1 is a block diagram illustrating an exemplary system on a chip integrated circuit 1000A that may be manufactured using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1000A includes one or more application processors 1005 (e.g., CPU), at least one graphics processor 1010, and may additionally include an image processor 1015 and / or a video processor 1020, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1000A includes peripheral or bus logic, which includes a USB controller 1025, a UART controller 1030, an SPI / SDIO controller 1035, and an I 2 S / I 2 C controller 1040. In at least one embodiment, the integrated circuit 1000A may include a display device 1045 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1050 and a mobile industry processor interface (MIPI) display interface 1055. In at least one embodiment, storage may be provided by a flash memory subsystem 1060, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1065 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1070.

[0184] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6B and / or Figure 6C Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 may be used in the integrated circuit 1000A to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0185] Figures 10B-10C An exemplary integrated circuit and associated graphics processor according to various embodiments of the present invention are shown, which can be manufactured using one or more IP cores to support and / or implement multi-level image reconstruction. In addition to the illustrations, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0186] Figures 10B-10C is a block diagram illustrating an exemplary graphics processor for use within a SoC to support and / or implement multi-level image reconstruction according to embodiments described herein. Fig. 10B An exemplary graphics processor 1010 of a system on a chip integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Fig. 10C Another exemplary graphics processor 1040 of a system on a chip integrated circuit is shown, which can be manufactured using one or more IP cores according to at least one embodiment. In at least one embodiment, Fig. 10B The graphics processor 1010 is a low power graphics processor core. In at least one embodiment, Fig. 10C The graphics processor 1040 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1010, 1040 can be Fig. 10A A variant of graphics processor 1010.

[0187] In at least one embodiment, the graphics processor 1010 includes a vertex processor 1005 and one or more fragment processors 1015A-1015N (e.g., 1015A, 1015B, 1015C, 1015D to 1015N-1 and 1015N). In at least one embodiment, the graphics processor 1010 can execute different shader programs via separate logic, so that the vertex processor 1005 is optimized to perform operations for the vertex shader program, while one or more fragment processors 1015A-1015N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 1005 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1015A-1015N use the primitives and vertex data generated by the vertex processor 1005 to generate a frame buffer displayed on a display device. In at least one embodiment, one or more fragment processors 1015A-1015N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0188] In at least one embodiment, graphics processor 1010 additionally includes one or more memory management units (MMUs) 1020A-1020B, one or more caches 1025A-1025B, and one or more circuit interconnects 1030A-1030B. In at least one embodiment, one or more MMUs 1020A-1020B provide a mapping of virtual to physical addresses for graphics processor 1010, including for vertex processor 1005 and / or fragment processors 1015A-1015N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1025A-1025B. In at least one embodiment, one or more MMUs 1020A-1020B may synchronize with other MMUs within the system, including with Fig. 10A One or more MMUs associated with one or more application processors 1005, image processor 1015, and / or video processor 1020 enable each processor 1005-1020 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1030A-1030B enable graphics processor 1010 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0189] In at least one embodiment, graphics processor 1040 includes Fig. 10A One or more MMUs 1020A-1020B, caches 1025A-1025B, and circuit interconnects 1030A-1030B of graphics processor 1010. In at least one embodiment, graphics processor 1040 includes one or more shader cores 1055A-1055N (e.g., 1055A, 1055B, 1055C, 1055D, 1055E, 1055F to 1055N-1 and 1055N), such as Fig. 10B As shown, it provides a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, multiple shader cores can vary. In at least one embodiment, the graphics processor 1040 includes an inter-core task manager 1045 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1055A-1055N and a blocking unit 1058 to accelerate tile-based rendering operations, in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial consistency within a scene or to optimize the use of internal caches.

[0190] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6B and / or Figure 6C Provides details about the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 may be implemented in an integrated circuit. Fig. 10A and / or Fig. 10B for performing inference or prediction operations based at least in part on weight parameters computed using a neural network training operation, a neural network function or architecture, or a neural network use case herein.

[0191] Figures 10D-10E Additional exemplary graphics processor logic is shown to support and / or implement multi-level image reconstruction according to embodiments described herein. In at least one embodiment, Fig. 10D shows that it can be included in Fig. 10A The graphics core 1000D within the graphics processor 1010 of FIG. 1000B may be a graphics core 1000D of FIG. 1000D. Fig. 10C Unified shader cores 1055A-1055N are shown. Fig. 10B A highly parallel general purpose graphics processing unit ("GPGPU") 1030 suitable for deployment on a multi-chip module in at least one embodiment is shown.

[0192] In at least one embodiment, graphics core 1000D may include multiple slices 1001A-1001N or partitions of each core, and a graphics processor may include multiple instances of graphics core 1000D. In at least one embodiment, slices 1001A-1001N may include support logic including local instruction caches 1004A-1004N, thread schedulers 1006A-1006N, thread dispatchers 1008A-1008N, and a set of registers 1010A-1010N. In at least one embodiment, slices 1001A-1001N may include a set of additional function units (AFUs 1012A-1012N), floating point units (FPUs 1014A-1014N), integer arithmetic logic units (ALUs 109A-109N), address calculation units (ACUs 1013A-1013N), double precision floating point units (DPFPUs 1015A-1015N), and matrix processing units (MPUs 1017A-1017N).

[0193] In at least one embodiment, the FPU 1014A-1014N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 1015A-1015N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 1016A-1016N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 1017A-1017N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 1017A-1010N can perform various matrix operations to accelerate machine learning application frameworks, including enabling general matrix-to-matrix multiplication (GEMM) to support acceleration. In at least one embodiment, the AFU 1012A-1012N can perform additional logical operations that are not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0194] As discussed elsewhere in this disclosure, the reasoning and / or training logic 615 (at least in Figure 6B , Figure 6C Reference) is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6B and / or Figure 6C Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in graphics core 1000D to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions, and / or architectures or neural network use cases herein.

[0195] Fig.11AA block diagram of a computer system 1100A according to at least one embodiment is shown. In at least one embodiment, the computer system 1100A includes a processing subsystem 1101 having one or more processors 1102 and a system memory 1104, which communicates via an interconnect path that may include a memory hub 1105. In at least one embodiment, the memory hub 1105 may be a separate component within a chipset component, or may be integrated within one or more processors 1102. In at least one embodiment, the memory hub 1105 is coupled to an I / O subsystem 1111 via a communication link 1106. In one embodiment, the I / O subsystem 1111 includes an I / O hub 1107, which may enable the computer system 1100A to receive input from one or more input devices 1108. In at least one embodiment, the I / O hub 1107 may enable a display controller, which may be included in one or more processors 1102, to provide output to the one or more display devices 1110A. In at least one embodiment, the one or more display devices 1110A coupled to the I / O hub 1107 may include local, internal, or embedded display devices.

[0196] In at least one embodiment, the processing subsystem 1101 includes one or more parallel processors 1112 coupled to the memory hub 1105 via a bus or other communication link 1113. In at least one embodiment, the communication link 1113 can use any of a number of standard-based communication link technologies or protocols, such as but not limited to PCI Express, or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 1112 form a parallel or vector processing system in a computing concentration, and the system can include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In at least one embodiment, the one or more parallel processors 1112 form a graphics processing subsystem, which can output pixels to one of the one or more display devices 1110A coupled via the I / O hub 1107. In at least one embodiment, the one or more parallel processors 1112 can also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1110B.

[0197] In at least one embodiment, a system storage unit 1114 can be connected to the I / O hub 1107 to provide a storage mechanism for the computer system 1100A. In at least one embodiment, an I / O switch 1116 can be used to provide an interface mechanism to enable connections between the I / O hub 1107 and other components, such as a network adapter 1118 and / or a wireless network adapter 1119 that can be integrated into one or more platforms, as well as various other devices that can be added through one or more additional devices 1120. In at least one embodiment, the network adapter 1118 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 1119 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0198] In at least one embodiment, the computer system 1100A may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc. Other components may also be connected to the I / O hub 1107. In at least one embodiment, the interconnection may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol. Fig.11A The communication paths between the various components in the NV-Link high-speed interconnect or interconnect protocol.

[0199] In at least one embodiment, one or more parallel processors 1112 include circuits optimized for graphics and video processing, including, for example, video output circuits, and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1112 include circuits optimized for general processing. In at least one embodiment, the components of the computer system 1100A can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1112, memory hub 1105, one or more processors 1102, and I / O hub 1107 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of the computer system 1100A can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computer system 1100A can be integrated into a multi-chip module (MCM), and the multi-chip module can be interconnected with other multi-chip modules into a modular computer system.

[0200] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6B and / or Figure 6C Provide details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 may be Fig.11A for use in a system for performing inference or prediction operations based at least in part on weight parameters computed using a neural network training operation, a neural network function and / or architecture, or a neural network use case herein.

[0201] processor

[0202] Fig. 11B 100B according to at least one embodiment. In at least one embodiment, the various components of the parallel processor 1100B may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the parallel processor 1100B shown is a processor according to an exemplary embodiment. Fig. 11B A variation of the one or more parallel processors 1112 is shown.

[0203] In at least one embodiment, parallel processor 1100B includes parallel processing unit 1102. In at least one embodiment, parallel processing unit 1102 includes I / O unit 1104, which enables communication with other devices, including other instances of parallel processing unit 1102. In at least one embodiment, I / O unit 1104 can be directly connected to other devices. In at least one embodiment, I / O unit 1104 is connected to other devices by using a hub or switch interface (e.g., memory hub 1105). In at least one embodiment, the connection between memory hub 1105 and I / O unit 1104 forms communication link 1113. In at least one embodiment, I / O unit 1104 is connected to host interface 1106 and memory crossbar switch 1116, wherein host interface 1106 receives commands for performing processing operations and memory crossbar switch 1116 receives commands for performing memory operations.

[0204] In at least one embodiment, when the host interface 1106 receives the command buffer via the I / O unit 1104, the host interface 1106 can direct work operations to execute those commands to the front end 1108. In at least one embodiment, the front end 1108 is coupled with a scheduler 1110, which is configured to distribute commands or other work items to the processing cluster array 1112. In at least one embodiment, the scheduler 1110 ensures that the processing cluster array 1112 is properly configured and in a valid state before assigning tasks to the processing cluster array 1112. In at least one embodiment, the scheduler 1110 is implemented by firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1110 can be configured to perform complex scheduling and work distribution operations at coarse and fine granularity, thereby achieving fast preemption and context switching of threads executed on the processing array 1112. In at least one embodiment, the host software can prove the workload for scheduling on the processing array 1112 through one of the multiple graphics processing doorbells. In at least one embodiment, the workload may then be automatically distributed across the processing array 1112 by scheduler 1110 logic within a microcontroller that includes scheduler 1110 .

[0205] In at least one embodiment, the processing cluster array 1112 may include up to "N" processing clusters (e.g., cluster 1114A, cluster 1114B, through cluster 1114N). In at least one embodiment, each cluster 1114A-1114N of the processing cluster array 1112 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 1110 may allocate work to the clusters 1114A-1114N of the processing cluster array 1112 using various scheduling and / or work allocation algorithms, which may vary depending on the workload generated by each program or type of calculation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 1110, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 1112. In at least one embodiment, different clusters 1114A-1114N of the processing cluster array 1112 may be allocated to process different types of programs or to perform different types of calculations.

[0206] In at least one embodiment, processing cluster array 1112 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 1112 is configured to perform general-purpose parallel computing operations. In at least one embodiment, processing cluster array 1112 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0207] In at least one embodiment, processing cluster array 1112 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 1112 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 1112 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing units 1102 may transfer data from system memory via I / O units 1104 for processing. In at least one embodiment, during processing, the transferred data may be stored to on-chip memory (e.g., parallel processor memory 1122) during processing and then written back to system memory.

[0208] In at least one embodiment, when parallel processing unit 1102 is used to perform graphics processing, scheduler 1110 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 1114A-1114N of processing cluster array 1112. In at least one embodiment, portions of processing cluster array 1112 can be configured to perform different types of processing. In at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 1114A-1114N can be stored in a buffer to allow the intermediate data to be transferred between clusters 1114A-1114N for further processing.

[0209] In at least one embodiment, the processing cluster array 1112 can receive processing tasks to be performed via the scheduler 1110, which receives commands defining the processing tasks from the front end 1108. In at least one embodiment, the processing tasks can include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 1110 can be configured to obtain an index corresponding to a task, or can receive the index from the front end 1108. In at least one embodiment, the front end 1108 can be configured to ensure that the processing cluster array 1112 is configured to a valid state before starting a workload specified by an incoming command buffer (e.g., a batch-buffer, a push buffer, etc.).

[0210] In at least one embodiment, each of the one or more instances of parallel processing unit 1102 can be coupled to parallel processor memory 1122. In at least one embodiment, parallel processor memory 1122 can be accessed via memory crossbar switch 1116, which can receive memory requests from processing cluster array 1112 and I / O unit 1104. In at least one embodiment, memory crossbar switch 1116 can access parallel processor memory 1122 via memory interface 1118. In at least one embodiment, memory interface 1118 can include multiple partition units (e.g., partition unit 1120A, partition unit 1120B to partition unit 1120N), which can each be coupled to a portion of parallel processor memory 1122 (e.g., memory units). In at least one embodiment, the plurality of partition units 1120A-1120N are configured to be equal to the number of memory cells, such that the first partition unit 1120A has a corresponding first memory cell 1124A, the second partition unit 1120B has a corresponding memory cell 1124B, and the Nth partition unit 1120N has a corresponding Nth memory cell 1124N. In at least one embodiment, the number of partition units 1120A-1120N may not be equal to the number of memory devices.

[0211] In at least one embodiment, memory units 1124A-1124N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 1124A-1124N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory units 1124A-1124N, allowing partition units 1120A-1120N to write portions of each rendering target in parallel to efficiently use the available bandwidth of parallel processor memory 1122. In at least one embodiment, local instances of parallel processor memory 1122 may be excluded to facilitate a unified memory design that utilizes system memory in combination with local cache memory.

[0212] In at least one embodiment, any of the clusters 1114A-1114N of the processing cluster array 1112 can process data to be written to any memory unit 1124A-1124N within the parallel processor memory 1122. In at least one embodiment, the memory crossbar 1116 can be configured to transmit the output of each cluster 1114A-1114N to any partition unit 1120A-1120N or another cluster 1114A-1114N, and the cluster 1114A-1114N can perform other processing operations on the output. In at least one embodiment, each cluster 1114A-1114N can communicate with the memory interface 1118 through the memory crossbar 1116 to read from or write to various external storage devices. In at least one embodiment, memory crossbar switch 1116 has connections to memory interface 1118 to communicate with I / O unit 1104, and connections to local instances of parallel processor memory 1102, thereby enabling processing units within different processing clusters 1114A-1114N to communicate with system memory or other memory that is not local to parallel processing unit 1102. In at least one embodiment, memory crossbar switch 1116 may use virtual channels to separate traffic flows between clusters 1114A-1114N and partition units 1120A-1120N.

[0213] In at least one embodiment, multiple instances of parallel processing unit 1102 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 1102 may be configured to interoperate, even if different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. In at least one embodiment, some instances of parallel processing unit 1102 may include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 1102 or parallel processor 1100B may be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0214] Fig. 11C is a block diagram of a partition unit 1120 according to at least one embodiment. In at least one embodiment, the partition unit 1120 is Fig. 11B1120N. In at least one embodiment, partition unit 1120 includes L2 cache 1121, frame buffer interface 1125, and ROP 1126 (raster operation unit). L2 cache 1121 is a read / write cache that is configured to perform load and store operations received from memory crossbar switch 1116 and ROP 1126. In at least one embodiment, L2 cache 1121 outputs read misses and urgent write-back requests to frame buffer interface 1125 for processing. In at least one embodiment, updates can also be sent to the frame buffer via frame buffer interface 1125 for processing. In at least one embodiment, frame buffer interface 1125 communicates with memory units (such as ROPs) in parallel processor memory. Fig. 11B interacts with one of the memory units 1124A-1124N (e.g., within parallel processor memory 1122).

[0215] In at least one embodiment, ROP 1126 is a processing unit that performs raster operations such as stenciling, z-testing, blending, and the like. In at least one embodiment, ROP 1126 then outputs processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 1126 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. The compression logic performed by ROP 1126 can vary based on the statistical characteristics of the data to be compressed. In at least one embodiment, incremental color compression is performed based on the depth and color data on a per-tile basis.

[0216] In at least one embodiment, ROP 1126 is included within each processing cluster (e.g., Fig. 11B In at least one embodiment, read and write requests for pixel data are transmitted through memory crossbar 1116 rather than pixel fragment data transmission. In at least one embodiment, the processed graphics data can be displayed on a display device (such as Fig.11A 110), routed by processor 1102 for further processing, or by Fig. 11B One of the processing entities within parallel processor 1100B is routed for further processing.

[0217] Fig.11D is a block diagram of a processing cluster 1114 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is Fig. 11BIn at least one embodiment, one or more processing clusters 1114 can be configured to execute many threads in parallel, where a "thread" refers to an instance of a specific program executed on a specific set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of synchronized threads, which uses a common instruction unit that is configured to issue instructions to a set of processing engines within each processing cluster.

[0218] In at least one embodiment, the operation of the processing cluster 1114 can be controlled by a pipeline manager 1132 that allocates processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 1132 Fig. 11B The scheduler 1110 receives instructions and manages the execution of these instructions through the graphics multiprocessor 1134 and / or the texture unit 1136. In at least one embodiment, the graphics multiprocessor 1134 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included in the processing cluster 1114. In at least one embodiment, one or more instances of the graphics multiprocessor 1134 may be included in the processing cluster 1114. In at least one embodiment, the graphics multiprocessor 1134 may process data, and the data crossbar 1140 may be used to distribute the processed data to one of a plurality of possible destinations (including other shader units). In at least one embodiment, the pipeline manager 1132 may facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossbar 1140.

[0219] In at least one embodiment, each graphics multiprocessor 1134 within a processing cluster 1114 may include the same set of function execution logic (e.g., arithmetic logic units, load store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions are completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0220] In at least one embodiment, the instructions transmitted to the processing cluster 1114 constitute threads. In at least one embodiment, a group of threads executed across a group of parallel processing engines is a thread group. In at least one embodiment, the thread group executes the program on different input data. In at least one embodiment, each thread in the thread group can be assigned to a different processing engine in the graphics multiprocessor 1134. In at least one embodiment, the thread group may include fewer threads than the number of processing engines in the graphics multiprocessor 1134. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during the cycle of the thread group being processed. In at least one embodiment, the thread group may also include more threads than the number of processing engines in the graphics multiprocessor 1134. In at least one embodiment, when the thread group includes more threads than the processing engines in the graphics multiprocessor 1134, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 1134.

[0221] In at least one embodiment, graphics multiprocessor 1134 includes internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor 1134 can abandon the internal cache and use cache memory (e.g., L1 cache 1148) within processing cluster 1114. In at least one embodiment, each graphics multiprocessor 1134 can also access partition units (e.g., Fig. 11B 1120N) that are shared between all processing clusters 1114 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 1134 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 1102 can be used as global memory. In at least one embodiment, processing cluster 1114 includes multiple instances of graphics multiprocessor 1134, which can share common instructions and data that can be stored in L1 cache 1148.

[0222] In at least one embodiment, each processing cluster 1114 may include a memory management unit ("MMU") 1145 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 1145 may reside in Fig. 11B1148. In at least one embodiment, the MMU 1145 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles and, in at least one embodiment, to cache line indices. In at least one embodiment, the MMU 1145 may include an address translation lookaside buffer (TLB) or a cache that may reside within the graphics multiprocessor 1134 or the L1 cache 1148 or the processing cluster 1114. In at least one embodiment, the physical addresses are processed to assign surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0223] In at least one embodiment, the processing clusters 1114 can be configured such that each graphics multiprocessor 1134 is coupled to a texture unit 1136 to perform texture mapping operations, operations to determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 1134, and texture data is retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 1134 outputs one or more processed tasks to a data crossbar 1140 to provide the processed tasks to another processing cluster 1114 for further processing or to store the processed one or more tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 1116. In at least one embodiment, a preROP 1142 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 1134, direct the data to a ROP unit, which can communicate with a partition unit (e.g., Fig. 11B In at least one embodiment, the PreROP 1142 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0224] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6B and / or Figure 6C Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in graphics processing cluster 1114 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions, and / or architectures or neural network use cases described herein.

[0225] Fig.11E A graphics multiprocessor 1134 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 1134 is coupled to a pipeline manager 1132 of a processing cluster 1114. In at least one embodiment, the graphics multiprocessor 1134 has an execution pipeline that includes, but is not limited to, an instruction cache 1152, an instruction unit 1154, an address mapping unit 1156, a register file 1158, one or more general purpose graphics processing unit (GPGPU) cores 1162, and one or more load / store units 1166. The one or more GPGPU cores 1162 and the one or more load / store units 1166 are coupled to a cache memory 1172 and a shared memory 1170 via a memory and cache interconnect 1168.

[0226] In at least one embodiment, the instruction cache 1152 receives a stream of instructions to be executed from the pipeline manager 1132. In at least one embodiment, the instructions are cached in the instruction cache 1152 and dispatched for execution by the instruction unit 1154. In one embodiment, the instruction unit 1154 can dispatch instructions as thread groups (e.g., warps), each thread group being assigned to a different execution unit within one or more GPGPU cores 1162. In at least one embodiment, the instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 1156 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by one or more load / store units 1166.

[0227] In at least one embodiment, register file 1158 provides a set of registers for the functional units of graphics multiprocessor 1134. In at least one embodiment, register file 1158 provides temporary storage for operands for data paths connected to the functional units (e.g., GPGPU core 1162, load / store unit 1166) of graphics multiprocessor 1134. In at least one embodiment, register file 1158 is divided between each functional unit such that a dedicated portion of register file 1158 is allocated to each functional unit. In at least one embodiment, register file 1158 is divided between different warps being executed by graphics multiprocessor 1134.

[0228] In at least one embodiment, the GPGPU cores 1162 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 1134. The GPGPU cores 1162 may be similar in architecture or the architecture may be different. In at least one embodiment, the first portion of the GPGPU core 1162 includes a single-precision FPU and an integer ALU, while the second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 1134 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0229] In at least one embodiment, the GPGPU core 1162 includes SIMD logic capable of executing a single instruction to multiple sets of data. In one embodiment, the GPGPU core 1162 can physically execute SIMD4, SIMD8 and SIMD16 instructions, and logically execute SIMD1, SIMD2 and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads that perform the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0230] In at least one embodiment, the memory and cache interconnect 1168 is an interconnect network that connects each functional unit of the graphics multiprocessor 1134 to the register file 1158 and the shared memory 1170. In at least one embodiment, the memory and cache interconnect 1168 is a crossbar interconnect that allows the load / store unit 1166 to implement load and store operations between the shared memory 1170 and the register file 1158. In at least one embodiment, the register file 1158 can operate at the same frequency as the GPGPU core 1162, so that the latency of data transfer between the GPGPU core 1162 and the register file 1158 is very low. In at least one embodiment, the shared memory 1170 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 1134. In at least one embodiment, the cache memory 1172 can be used as, for example, a data cache to cache texture data communicated between the functional units and the texture unit 1136. In at least one embodiment, the shared memory 1170 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 1172, threads executing on GPGPU core 1162 may programmatically store data in shared memory.

[0231] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (inside the package or chip, in at least one embodiment). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0232] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6B and / or Figure 6CDetails are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in graphics multiprocessor 1134 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0233] 12A illustrates a multi-GPU computing system 1200A according to at least one embodiment. In at least one embodiment, the multi-GPU computing system 1200A may include a processor 1202 coupled to a plurality of general purpose graphics processing units (GPGPUs) 1206A-D via a host interface switch 1204. In at least one embodiment, the host interface switch 1204 is a PCI Express switch device that couples the processor 1202 to a PCI Express bus, and the processor 1202 may communicate with the GPGPUs 1206A-D via the PCI Express bus. The GPGPUs 1206A-D may be interconnected via a set of high-speed P2P GPU-to-GPU links 1216. In at least one embodiment, the GPU-to-GPU links 1216 are connected to each of the GPGPUs 1206A-D via a dedicated GPU link. In at least one embodiment, the P2P GPU links 1216 enable direct communication between each GPGPU 1206A-D without communicating through the host interface bus 1204 to which the processor 1202 is connected. In at least one embodiment, host interface bus 1204 remains available for system memory access or communication with other instances of multi-GPU computing system 1200A, e.g., via one or more network devices, with GPU-to-GPU traffic directed to P2P GPU link 1216. While in at least one embodiment, GPGPUs 1206A-D are connected to processor 1202 via host interface switch 1204, in at least one embodiment, processor 1202 includes direct support for P2P GPU link 1216 and can connect directly to GPGPUs 1206A-D.

[0234] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6B and / or Figure 6C Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in multi-GPU computing system 1200A to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0235] Fig. 12B is a block diagram of a graphics processor 1200B according to at least one embodiment. In at least one embodiment, graphics processor 1200B includes ring interconnect 1202, pipeline front end 1204, media engine 1237, and graphics cores 1280A-1280N. In at least one embodiment, ring interconnect 1202 couples graphics processor 1200B to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 1200B is one of many processors integrated within a multi-core processing system.

[0236] In at least one embodiment, graphics processor 1200B receives batches of commands via ring interconnect 1202. In at least one embodiment, the incoming commands are interpreted by command streamer 1203 in pipeline front end 1204. In at least one embodiment, graphics processor 1200B includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 1280A-1280N. In at least one embodiment, for 3D geometry processing commands, command streamer 1203 provides commands to geometry pipeline 1236. In at least one embodiment, for at least some media processing commands, command streamer 1203 provides commands to video front end 1234, which is coupled to media engine 1237. In at least one embodiment, media engine 1237 includes video quality engine (VQE) 1230 for video and image post-processing, and multi-format encoding / decoding (MFX) 1233 engine for providing hardware accelerated media data encoding and decoding. In at least one embodiment, geometry pipeline 1236 and media engine 1237 each generate execution threads for thread execution resources provided by at least one graphics core 1280A.

[0237] In at least one embodiment, the graphics processor 1200B includes scalable thread execution resources featuring modular cores 1280A-1280N (sometimes referred to as core slices), each graphics core having multiple sub-cores 1250A-1250N, 1260A-1260N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 1200B can have any number of graphics cores 1280A. In at least one embodiment, the graphics processor 1200B includes a graphics core 1280A having at least a first sub-core 1250A and a second sub-core 1260A. In at least one embodiment, the graphics processor 1200B is a low-power processor having a single sub-core (e.g., 1250A). In at least one embodiment, the graphics processor 1200B includes multiple graphics cores 1280A-1280N, each graphics core including a group of first sub-cores 1250A-1250N and a group of second sub-cores 1260A-1260N. In at least one embodiment, each of the first sub-cores 1250A-1250N includes at least a first set of execution units 1252A-1252N and media / texture samplers 1254A-1254N. In at least one embodiment, each of the second sub-cores 1260A-1260N includes at least a second set of execution units 1262A-1262N and samplers 1264A-1264N. In at least one embodiment, each of the sub-cores 1250A-1250N, 1260A-1260N shares a set of shared resources 1270A-1270N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0238] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6B and / or Figure 6C Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in graphics processor 1200B to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0239] Fig.13is a block diagram of a microarchitecture for a processor 1300 that may include logic circuitry for executing instructions, according to an illustration of at least one embodiment. In at least one embodiment, the processor 1300 may execute instructions, including x86 instructions, ARM instructions, special instructions for an application-specific integrated circuit (ASIC), and the like. In at least one embodiment, the processor 1300 may include registers for storing packed data, such as 64-bit wide MMXTM registers in a microprocessor enabled with MMX technology by Intel Corporation of Santa Clara, California. In at least one embodiment, the MMX registers available in integer and floating point form may operate with packed data elements that accompany single instruction multiple data (“SIMD”) and streaming SIMD extension (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (generally referred to as “SSEx”) technology may hold such packed data operands. In at least one embodiment, the processor 1300 may execute instructions to accelerate machine learning or deep learning algorithms, training, or reasoning.

[0240] In at least one embodiment, the processor 1300 includes an in-order front end ("front end") 1301 to fetch instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, the front end 1301 may include several units. In at least one embodiment, an instruction prefetcher 1326 fetches instructions from memory and provides the instructions to an instruction decoder 1328, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 1328 decodes the received instructions into one or more operations of so-called "microinstructions" or "microoperations" (also referred to as "micro-operations" or "microinstructions") that the machine can execute. In at least one embodiment, the instruction decoder 1328 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, the trace cache 1330 can assemble the decoded microinstructions into a program-ordered sequence or trace in the microinstruction queue 1334 for execution. In at least one embodiment, when trace cache 1330 encounters a complex instruction, microcode ROM 1332 provides the microinstructions necessary to complete the operation.

[0241] In at least one embodiment, some instructions may be converted into a single micro-operation, while other instructions may require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-operations are required to complete an instruction, the instruction decoder 1328 may access the microcode ROM 1332 to execute the instruction. In at least one embodiment, the instruction may be decoded into a small number of micro-operations for processing at the instruction decoder 1328. In at least one embodiment, if multiple micro-operations are required to complete the operation, the instruction may be stored in the microcode ROM 1332. In at least one embodiment, the trace cache 1330 references the entry point programmable logic array ("PLA") to determine the correct micro-instruction pointer for reading the microcode sequence from the microcode ROM 1332 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 1332 completes the micro-operation sequencing of the instruction, the front end 1301 of the machine may resume fetching micro-operations from the trace cache 1330.

[0242] In at least one embodiment, an out-of-order execution engine ("out-of-order engine") 1303 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions go down the pipeline and are scheduled for execution. In at least one embodiment, the out-of-order execution engine 1303 includes, but is not limited to, an allocator / register renamer 1340, a memory microinstruction queue 1342, an integer / floating point microinstruction queue 1344, a memory scheduler 1346, a fast scheduler 1302, a slow / general purpose floating point scheduler ("slow / general purpose FP scheduler") 1304, and a simple floating point scheduler ("simple FP scheduler") 1306. In at least one embodiment, the fast scheduler 1302, the slow / general purpose floating point scheduler 1304, and the simple floating point scheduler 1306 are also collectively referred to as "microinstruction schedulers 1302, 1304, 1306". In at least one embodiment, the allocator / register renamer 1340 allocates machine buffers and resources required for each microinstruction to execute in sequence. In at least one embodiment, the allocator / register renamer 1340 renames logical registers into entries in the register file. In at least one embodiment, the allocator / register renamer 1340 also allocates entries for each microinstruction in one of the two microinstruction queues, the memory microinstruction queue 1342 for memory operations and the integer / floating point microinstruction queue 1344 for non-memory operations, in front of the memory scheduler 1346 and the microinstruction schedulers 1302, 1304, 1306. In at least one embodiment, the microinstruction schedulers 1302, 1304, 1306 determine when the microinstructions are ready to execute based on the readiness of their slave input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 1302 of at least one embodiment can be scheduled on each half of the main clock cycle, while the slow / general floating point scheduler 1304 and the simple floating point scheduler 1306 can be scheduled once per main processor clock cycle. In at least one embodiment, microinstruction schedulers 1302, 1304, 1306 arbitrate dispatch ports to schedule microinstructions for execution.

[0243] In at least one embodiment, execution block 1311 includes, but is not limited to, integer register file / bypass network 1308, floating point register file / bypass network ("FP register file / bypass network") 1310, address generation units ("AGUs") 1312 and 1314, fast arithmetic logic units ("fast ALUs") 1316 and 1318, slow arithmetic logic unit ("slow ALU") 1320, floating point ALU ("FP") 1322, and floating point move unit ("FP move") 1324. In at least one embodiment, integer register file / bypass network 1308 and floating point register file / bypass network 1310 are also referred to herein as "register files 1308, 1310". In at least one embodiment, AGUs 1312 and 1314, fast ALUs 1316 and 1318, slow ALU 1320, floating point ALU 1322, and floating point move unit 1324 are also referred to herein as "execution units 1312, 1314, 1316, 1318, 1320, 1322, and 1324." In at least one embodiment, execution block 1311 may include, but is not limited to, any number (including zero) and type of register files, bypass networks, address generation units, and execution units (in any combination).

[0244] In at least one embodiment, register networks 1308, 1310 may be arranged between microinstruction schedulers 1302, 1304, 1306 and execution units 1312, 1314, 1316, 1318, 1320, 1322, and 1324. In at least one embodiment, integer register file / bypass network 1308 performs integer operations. In at least one embodiment, floating point register file / bypass network 1310 performs floating point operations. In at least one embodiment, each of register networks 1308, 1310 may include, but is not limited to, a branch network that may bypass or forward a just completed result that has not yet been written to the register file to a new slave object. In at least one embodiment, register networks 1308, 1310 may communicate data with each other. In at least one embodiment, integer register file / bypass network 1308 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data, and a second register file for high-order 32-bit data. In at least one embodiment, floating point register file / bypass network 1310 may include, but is not limited to, 128-bit wide entries, since floating point instructions typically have operands that are 64 to 128 bits wide.

[0245] In at least one embodiment, execution units 1312, 1314, 1316, 1318, 1320, 1322, 1324 can execute instructions. In at least one embodiment, register files 1308, 1310 store integer and floating point data operand values ​​that microinstructions need to execute. In at least one embodiment, processor 1300 may include, but is not limited to, any number of execution units 1312, 1314, 1316, 1318, 1320, 1322, 1324 and combinations thereof. In at least one embodiment, floating point ALU 1322 and floating point move unit 1324 can perform floating point, MMX, SIMD, AVX and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating point ALU 1322 may include, but is not limited to, a 64-bit by 64-bit floating point divider to perform division, square root and remainder micro-operations. In at least one embodiment, floating point hardware may be used to process instructions involving floating point values. In at least one embodiment, ALU operations can be passed to fast ALUs 1316, 1318. In at least one embodiment, fast ALUs 1316, 1318 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 1320 because slow ALU 1320 can include, but is not limited to, integer execution hardware for long-latency type operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by AGUs 1312, 1314. In at least one embodiment, fast ALU 1316, fast ALU 1318, and slow ALU 1320 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 1316, fast ALU 1318, and slow ALU 1320 can be implemented to support various data bit sizes including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, the floating point ALU 1322 and floating point move unit 1324 can be implemented to support a range of operands having bits of various widths. In at least one embodiment, the floating point ALU 1322 and floating point move unit 1324 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0246] In at least one embodiment, microinstruction schedulers 1302, 1304, 1306 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed in processor 1300, processor 1300 can also include logic for handling memory misses. In at least one embodiment, if the data load in the data cache misses, there may be dependent operations running in the pipeline, which temporarily prevents the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0247] In at least one embodiment, "register" may refer to an onboard processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. On the contrary, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented using a variety of different techniques by circuits within the processor, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packaging data.

[0248] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6B and / or Figure 6C Details are provided regarding the inference and / or training logic 615. In at least one embodiment, part or all of the inference and / or training logic 615 may be incorporated into the execution block 1311 and other memories or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs shown in the execution block 1311. In addition, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of the execution block 1311 to perform one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0249] Fig.14A deep learning application processor 1400 is shown in accordance with at least one embodiment. In at least one embodiment, the deep learning application processor 1400 uses instructions that, if executed by the deep learning application processor 1400, cause the deep learning application processor 1400 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 1400 is an application specific integrated circuit (ASIC). In at least one embodiment, the application processor 1400 performs matrix multiplication operations or is "hardwired" into hardware as a result of executing one or more instructions, or both. In at least one embodiment, the deep learning application processor 1400 includes, but is not limited to, processing clusters 1410(1)-1410(12), inter-chip links (“ICLs”) 1420(1)-1420(12), inter-chip controllers (“ICCs”) 1430(1)-1430(2), memory controllers (“Mem Ctrlr”) 1442(1)-1442(4), high bandwidth memory physical layer (“HBM PHY”) 1444(1)-1444(4), a management controller central processing unit (“management controller CPU”) 1450, serial peripheral interface, inter-integrated circuit, and general purpose input / output blocks (“SPI, I2C, GPIO”), peripheral component interconnect express controller and direct memory access block (“PCIe controller and DMA”) 1470, and sixteen-lane peripheral component interconnect express port (“PCI Express x 16”) 1480.

[0250] In at least one embodiment, the processing cluster 1410 may perform deep learning operations, including inference or prediction operations based on weight parameters calculated based on one or more training techniques, including those of this article. In at least one embodiment, each processing cluster 1410 may include, but is not limited to, any number and type of processors. In at least one embodiment, the deep learning application processor 1400 may include any number and type of processing clusters 1400. In at least one embodiment, the inter-chip link 1420 is bidirectional. In at least one embodiment, the inter-chip link 1420 and the inter-chip controller 1430 enable multiple deep learning application processors 1400 to exchange information, including activation information generated from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 1400 may include any number (including zero) and type of ICL 1420 and ICC 1430.

[0251] In at least one embodiment, HBM2 1440 provides a total of 32GB of memory. HBM2 1440(i) is associated with both memory controller 1442(i) and HBM PHY 1444(i). In at least one embodiment, any number of HBM2 1440 can provide any type and total amount of high bandwidth memory and can be associated with any number (including zero) and type of memory controller 1442 and HBM PHY 1444. In at least one embodiment, SPI, I2C, GPIO 3360, PCIe controller 1460 and DMA 1470 and / or PCIe1480 can be replaced with any number and type of blocks to implement any number and type of communication standards in any technically feasible manner.

[0252] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6B and / or Figure 6C Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the deep learning application processor is used to train a machine learning model (e.g., a neural network) to predict or infer information provided to the deep learning application processor 1400. In at least one embodiment, the deep learning application processor 1400 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 1400. In at least one embodiment, the processor 1400 can be used to perform one or more of the neural network use cases described herein.

[0253] Fig.15 1 is a block diagram of a neuromorphic processor 1500 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 1500 may receive one or more inputs from a source external to the neuromorphic processor 1500. In at least one embodiment, these inputs may be transmitted to one or more neurons 1502 within the neuromorphic processor 1500. In at least one embodiment, the neurons 1502 and their components may be implemented using circuits or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 1500 may include, but is not limited to, thousands of instances of neurons 1502, although any suitable number of neurons 1502 may be used. In at least one embodiment, each instance of a neuron 1502 may include a neuron input 1504 and a neuron output 1506. In at least one embodiment, a neuron 1502 may generate an output that may be transmitted to the inputs of other instances of the neuron 1502. In at least one embodiment, the neuron input 1504 and the neuron output 1506 may be interconnected via a synapse 1508.

[0254] In at least one embodiment, the neurons 1502 and synapses 1508 may be interconnected such that the neuromorphic processor 1500 operates to process or analyze information received by the neuromorphic processor 1500. In at least one embodiment, the neuron 1502 may send an output pulse (or "trigger" or "spike") when the input received through the neuron input 1504 exceeds a threshold. In at least one embodiment, the neuron 1502 may sum or integrate the signal received at the neuron input 1504. For example, in at least one embodiment, the neuron 1502 may be implemented as a leaky integrate-trigger neuron, where if the sum (referred to as the "membrane potential") exceeds a threshold, the neuron 1502 may generate an output (or "trigger") using a transfer function such as a sigmoid or threshold function. In at least one embodiment, the leaky integrate-trigger neuron may sum the signal received at the neuron input 1504 into a membrane potential, and may apply an application attenuation factor (or leakage) to reduce the membrane potential. In at least one embodiment, a leaky integrate-and-trigger neuron may trigger if multiple input signals are received at the neuron input 1504 fast enough to exceed a threshold (in at least one embodiment, before the membrane potential decays too low to trigger). In at least one embodiment, the neuron 1502 may be implemented using circuitry or logic that receives inputs, integrates the inputs into a membrane potential, and decays the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. In addition, in at least one embodiment, the neuron 1502 may include, but is not limited to, a comparator circuit or logic that generates an output spike at the neuron output 1506 when the result of applying the transfer function to the neuron input 1504 exceeds a threshold. In at least one embodiment, once the neuron 1502 triggers, it may ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, the neuron 1502 may resume normal operation after a suitable period of time (or recovery period).

[0255] In at least one embodiment, neurons 1502 may be interconnected via synapses 1508. In at least one embodiment, synapses 1508 may be operable to transmit a signal from an output of a first neuron 1502 to an input of a second neuron 1502. In at least one embodiment, a neuron 1502 may transmit information over more than one instance of synapse 1508. In at least one embodiment, one or more instances of a neuron output 1506 may be connected to an instance of a neuron input 1504 in the same neuron 1502 via an instance of synapse 1508. In at least one embodiment, an instance of a neuron 1502 that produces an output to be transmitted over an instance of synapse 1508 may be referred to as a "pre-synaptic neuron" relative to that instance of synapse 1508. In at least one embodiment, an instance of a neuron 1502 that receives an input transmitted through an instance of synapse 1508 may be referred to as a "post-synaptic neuron" relative to an instance of synapse 1508. In at least one embodiment, with respect to various instances of synapses 1508, because an instance of neuron 1502 can receive input from one or more instances of synapses 1508 and can also transmit output through one or more instances of synapses 1508, a single instance of neuron 1502 can be both a "pre-synaptic neuron" and a "post-synaptic neuron."

[0256] In at least one embodiment, neurons 1502 can be organized into one or more layers. Each instance of a neuron 1502 can have a neuron output 1506 that can fan out to one or more neuron inputs 1504 through one or more synapses 1508.

[0257] In at least one embodiment, neuron outputs 1506 of neurons 1502 in a first layer 1510 may be connected to neuron inputs 1504 of neurons 1502 in a second layer 1512. In at least one embodiment, layer 1510 may be referred to as a "feed-forward layer." In at least one embodiment, each instance of a neuron 1502 in an instance of the first layer 1510 may fan out to each instance of a neuron 1502 in the second layer 1512. In at least one embodiment, the first layer 1510 may be referred to as a "fully connected feed-forward layer." In at least one embodiment, each instance of a neuron 1502 in each instance of the second layer 1512 fans out to less than all instances of neurons 1502 in a third layer 1514. In at least one embodiment, the second layer 1512 may be referred to as a "sparsely connected feed-forward layer." In at least one embodiment, a neuron 1502 in the (same) second layer 1512 may fan out to neurons 1502 in multiple other layers, including also fanning out to neurons 1502 in the second layer 1512. In at least one embodiment, the second layer 1512 may be referred to as a "recurrent layer." In at least one embodiment, the neuromorphic processor 1500 may include, but is not limited to, any suitable combination of recurrent layers and feed-forward layers, including but not limited to sparsely connected feed-forward layers and fully connected feed-forward layers.

[0258] In at least one embodiment, the neuromorphic processor 1500 may include, but is not limited to, a reconfigurable interconnect architecture or a dedicated hardwired interconnect to connect the synapses 1508 to the neurons 1502. In at least one embodiment, the neuromorphic processor 1500 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 1502 as needed, depending on the neural network topology and neuron fan-in / fan-out. For example, in at least one embodiment, the synapses 1508 may be connected to the neurons 1502 using an interconnect architecture such as a network on a chip or through dedicated connections. In at least one embodiment, the synaptic interconnects and their components may be implemented using circuitry or logic.

[0259] Fig.16A A processing system according to at least one embodiment is shown. In at least one embodiment, system 1600A includes one or more processors 1602 and one or more graphics processors 1608, and can be a single processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 1602 or processor cores 1607. In at least one embodiment, system 1600A is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0260] In at least one embodiment, the system 1600A may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console for gaming and media consoles. In at least one embodiment, the system 1600A is a mobile phone, a smart phone, a tablet computing device, or a mobile Internet device. In at least one embodiment, the processing system 1600A may also include a wearable device coupled to or integrated in a wearable device, such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 1600A is a television or set-top box device having one or more processors 1602 and a graphical interface generated by one or more graphics processors 1608.

[0261] In at least one embodiment, one or more processors 1602 each include one or more processor cores 1607 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 1607 is configured to process a specific instruction set 1609. In at least one embodiment, the instruction set 1609 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing through very long instruction words (VLIW). In at least one embodiment, the processor cores 1607 can each process a different instruction set 1609, which can include instructions that help emulate other instruction sets. In at least one embodiment, the processor cores 1607 can also include other processing devices, such as digital signal processors (DSPs).

[0262] In at least one embodiment, the processor 1602 includes a cache memory 1604. In at least one embodiment, the processor 1602 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared between various components of the processor 1602. In at least one embodiment, the processor 1602 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which can be shared between the processor cores 1607 using known cache coherence techniques. In at least one embodiment, the processor 1602 additionally includes a register file 1606, and the processor may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, the register file 1606 may include general registers or other registers.

[0263] In at least one embodiment, one or more processors 1602 are coupled to one or more interface buses 1610 to transmit communication signals, such as address, data, or control signals, between the processor 1602 and other components in the system 1600A. In at least one embodiment, the interface bus 1610 can be a processor bus in one embodiment, such as a version of a direct media interface (DMI) bus. In at least one embodiment, the interface bus 1610 is not limited to a DMI bus, and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 1602 includes an integrated memory controller 1616 and a platform controller hub 1630. In at least one embodiment, the memory controller 1616 facilitates communication between memory devices and other components of the processing system 1600A, while the platform controller hub (PCH) 1630 provides connections to input / output (I / O) devices through a local I / O bus.

[0264] In at least one embodiment, the memory device 1620 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or have appropriate performance to be used as a processor memory. In at least one embodiment, the memory device 1620 may be used as a system memory of the processing system 1600A to store data 1622 and instructions 1621 for use when one or more processors 1602 execute applications or processes. In at least one embodiment, the memory controller 1616 is also coupled to an external graphics processor 1612 of at least one embodiment, which may communicate with one or more graphics processors 1608 in the processor 1602 to perform graphics and media operations. In at least one embodiment, the display device 1611 may be connected to the processor 1602. In at least one embodiment, the display device 1611 may include one or more of the internal display devices, such as in a mobile electronic device or laptop device or an external display device connected via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 1611 may include a head mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0265] In at least one embodiment, the platform controller hub 1630 enables peripheral devices to be connected to the storage device 1620 and the processor 1602 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 1646, a network controller 1634, a firmware interface 1628, a wireless transceiver 1626, a touch sensor 1625, a data storage device 1624 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 1624 can be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 1625 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 1626 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or long-term evolution (LTE) transceiver. In at least one embodiment, the firmware interface 1628 enables communication with the system firmware and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, the network controller 1634 can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 1610. In at least one embodiment, the audio controller 1646 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 1600A includes a legacy I / O controller 1640 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system 1600A. In at least one embodiment, the platform controller hub 1630 can also be connected to one or more universal serial bus (USB) controllers 1642, which connect input devices such as a keyboard and mouse 1643 combination, a camera 1644, or other USB input devices.

[0266] In at least one embodiment, instances of memory controller 1616 and platform controller hub 1630 may be integrated into a discrete external graphics processor, such as external graphics processor 1612. In at least one embodiment, platform controller hub 1630 and / or memory controller 1616 may be external to one or more processors 1602. In at least one embodiment, system 1600A may include external memory controller 1616 and platform controller hub 1630, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with processor 1602.

[0267] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6B and / or Figure 6C1600A. In at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs that are embodied in graphics processor 1612. In addition, in at least one embodiment, the inference and / or training operations described herein may use additional ALUs. Figure 6B and / or Figure 6C In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 1600A to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0268] Fig. 16B is a block diagram of a processor 1600B having one or more processor cores 1602A-1602N, an integrated memory controller 1614, and an integrated graphics processor 1608, according to at least one embodiment. In at least one embodiment, the processor 1600B may include additional cores, up to and including the additional core 1602N represented by the dashed box. In at least one embodiment, each processor core 1602A-1602N includes one or more internal cache units 1604A-1604N. In at least one embodiment, each processor core may also have access to one or more shared cache units 1606.

[0269] In at least one embodiment, the internal cache units 1604A-1604N and the shared cache unit 1606 represent a cache memory hierarchy within the processor 1600B. In at least one embodiment, the cache memory units 1604A-1604N may include at least one level of instruction and data cache within each processor core and one or more levels of cache in a shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as LLC. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 1606 and 1604A-1604N.

[0270] In at least one embodiment, the processor 1600B may also include a set of one or more bus controller units 1616 and a system agent core 1610. In at least one embodiment, the one or more bus controller units 1616 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 1610 provides management functions for various processor components. In at least one embodiment, the system agent core 1610 includes one or more integrated memory controllers 1614 to manage access to various external memory devices (not shown).

[0271] In at least one embodiment, one or more processor cores 1602A-1602N include support for multiple threads simultaneously. In at least one embodiment, system agent core 1610 includes components for coordinating and operating cores 1602A-1602N during multithreaded processing. In at least one embodiment, system agent core 1610 may additionally include a power control unit (PCU) that includes logic and components for regulating one or more power states of processor cores 1602A-1602N and graphics processor 1608.

[0272] In at least one embodiment, the processor 1600B also includes a graphics processor 1608 for performing image processing operations. In at least one embodiment, the graphics processor 1608 is coupled to a shared cache unit 1606 and a system agent core 1610 including one or more integrated memory controllers 1614. In at least one embodiment, the system agent core 1610 also includes a display controller 1611 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 1611 may also be a separate module coupled to the graphics processor 1608 via at least one interconnect, or may be integrated within the graphics processor 1608.

[0273] In at least one embodiment, a ring-based interconnect unit 1612 is used to couple the internal components of the processor 1600B. In at least one embodiment, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 1608 is coupled to the ring interconnect 1612 via an I / O link 1613.

[0274] In at least one embodiment, I / O link 1613 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory modules 1618 (e.g., eDRAM modules). In at least one embodiment, each of processor cores 1602A-1602N and graphics processor 1608 uses embedded memory modules 1618 as a shared last level cache.

[0275] In at least one embodiment, the processor cores 1602A-1602N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 1602A-1602N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more processor cores 1602A-1602N execute a common instruction set, while one or more other processor cores 1602A-1602N execute a subset or a different instruction set of the common instruction set. In at least one embodiment, the processor cores 1602A-1602N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 1600B can be implemented on one or more chips or implemented as a SoC integrated circuit.

[0276] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6B and / or Figure 6C 615. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into the processor 1600B. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs embodied in Fig.16A In addition, in at least one embodiment, the inference and / or training operations described herein may use the inference and / or training operations described herein. Figure 6B and / or Figure 6C In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 1600B to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0277] Fig. 16Cis a block diagram of the hardware logic of a graphics processor core 1600C according to at least one embodiment herein. In at least one embodiment, graphics processor core 1600C is included in a graphics core array. In at least one embodiment, graphics processor core 1600C (sometimes referred to as a core slice) may be one or more graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core 1600C is an example of a graphics core slice, and the graphics processor herein may include multiple graphics core slices based on a target power and performance envelope. In at least one embodiment, each graphics core 1600C may include a fixed function block 1630 coupled to multiple sub-cores 1601A-1601F, also referred to as a sub-slice, which includes modular blocks of general and fixed function logic.

[0278] In at least one embodiment, fixed function block 1630 includes a geometry fixed function pipeline 1636, which can be shared by all sub-cores in graphics processor 1600C, for example, in lower performance and / or lower power graphics processor implementations. In at least one embodiment, geometry and fixed function pipeline 1636 includes a 3D fixed function pipeline, a video front end unit, a thread generator and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0279] In at least one fixed embodiment, the fixed function block 1630 also includes a graphics SoC interface 1637, a graphics microcontroller 1638, and a media pipeline 1639. In at least one embodiment, the fixed graphics SoC interface 1637 provides an interface between the graphics core 1600C and other processor cores in the on-chip integrated circuit system. In at least one embodiment, the graphics microcontroller 1638 is a programmable subprocessor that can be configured to manage various functions of the graphics processor 1600C, including thread dispatching, scheduling, and preemption. In at least one embodiment, the media pipeline 1639 includes logic that helps decode, encode, pre-process, and / or post-process multimedia data including image and video data. In at least one embodiment, the media pipeline 1639 implements media operations via requests to calculation or sampling logic within the sub-cores 1601-1601F.

[0280] In at least one embodiment, the SoC interface 1637 enables the graphics core 1600C to communicate with a general application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as a shared last level cache, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 1637 may also enable communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline), and enable the use and / or implementation of global memory atomics that can be shared between the graphics core 1600C and the CPU within the SoC. In at least one embodiment, the SoC interface 1637 may also implement power management controls for the graphics core 1600C and enable interfaces between the clock domain of the graphics core 1600C and other clock domains within the SoC. In at least one embodiment, the SoC interface 1637 enables command buffers to be received from a command stream converter and a global thread dispatcher, which is configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, commands and instructions may be dispatched to media pipeline 1639 when media operations are to be performed, or may be assigned to geometry and fixed function pipelines (e.g., geometry and fixed function pipeline 1636, geometry and fixed function pipeline 1614) when graphics processing operations are to be performed.

[0281] In at least one embodiment, the graphics microcontroller 1638 can be configured to perform various scheduling and management tasks for the graphics core 1600C. In at least one embodiment, the graphics microcontroller 1638 can perform graphics and / or computing workload scheduling on various graphics parallel engines within the execution unit (EU) arrays 1602A-1602F, 1604A-1604F in the sub-cores 1601A-1601F. In at least one embodiment, host software executing on the CPU core of the SoC including the graphics core 1600C can submit a workload to one of the multiple graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operations include determining which workload to run next, submitting the workload to the command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In at least one embodiment, graphics microcontroller 1638 may also facilitate low power or idle states for graphics core 1600C, thereby providing graphics core 1600C with the ability to save and restore registers across low power state transitions within graphics core 1600C independent of the operating system and / or graphics driver software on the system.

[0282] In at least one embodiment, graphics core 1600C may have up to N modular sub-cores more or less than the sub-cores 1601A-1601F shown. For each set of N sub-cores, in at least one embodiment, graphics core 1600C may also include shared function logic 1610, shared and / or cache memory 1612, geometry / fixed function pipelines 1614, and additional fixed function logic 1616 to accelerate various graphics and compute processing operations. In at least one embodiment, shared function logic 1610 may include logic units (e.g., samplers, math and / or inter-thread communication logic) that may be shared by each of the N sub-cores within graphics core 1600C. In at least one embodiment, fixed, shared and / or cache memory 1612 may be the last level cache for the N sub-cores 1601A-1601F within graphics core 1600C, and may also be used as a shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 1614 may be included in place of geometry / fixed function pipeline 1636 within fixed function block 1630 and may include similar logic units.

[0283] In at least one embodiment, the graphics core 1600C includes additional fixed function logic 1616, which may include various fixed function acceleration logic for use by the graphics core 1600C. In at least one embodiment, the additional fixed function logic 1616 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are at least two geometry pipelines, and in the full geometry pipeline and culling pipeline within the geometry and fixed function pipelines 1614, 1636, it is an additional geometry pipeline that may be included in the additional fixed function logic 1616. In at least one embodiment, the culling pipeline is a trimmed version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of an application, each with a separate environment. In at least one embodiment, position-only shading can hide long culling runs for discarded triangles, so that shading can be completed earlier in some cases. In at least one embodiment, the culling pipeline logic in the additional fixed function logic 1616 can execute the position shader in parallel with the main application and generate critical results faster than the full pipeline because the culling pipeline obtains and masks the position attributes of the vertex without performing rasterization and rendering the pixels to the frame buffer. In at least one embodiment, the culling pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether they are culled. In at least one embodiment, the full pipeline (which can be called a replay pipeline in this case) can consume visibility information to skip culled triangles to mask only visible triangles that are ultimately passed to the rasterization stage.

[0284] In at least one embodiment, the additional fixed function logic 1616 may also include machine learning acceleration logic, such as fixed function matrix multiplication logic, for implementing optimizations including for machine learning training or inference.

[0285] In at least one embodiment, a set of execution resources is included within each graphics sub-core 1601A-1601F, which can be used to perform graphics, media, and compute operations in response to requests from a graphics pipeline, a media pipeline, or a shader program. In at least one embodiment, the graphics sub-core 1601A-1601F includes multiple EU arrays 1602A-1602F, 1604A-1604F, thread dispatch and inter-thread communication (TD / IC) logic 1603A-1603F, 3D (e.g., texture) samplers 1605A-1605F, media samplers 1606A-1606F, shader processors 1607A-1607F, and shared local memory (SLM) 1608A-1608F. Each of the EU arrays 1602A-1602F, 1604A-1604F includes a plurality of execution units, which are general purpose graphics processing units capable of servicing graphics, media, or compute operations, performing floating point and integer / fixed point logic operations, including graphics, media, or compute shader programs. In at least one embodiment, the TD / IC logic 1603A-1603F performs local thread dispatch and thread control operations for the execution units within the sub-core and facilitates communication between threads executed on the execution units of the sub-core. In at least one embodiment, the 3D samplers 1605A-1605F can read data associated with textures or other 3D graphics into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the configured sampling state and texture format associated with a given texture. In at least one embodiment, the media samplers 1606A-1606F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics sub-core 1601A-1601F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each sub-core 1601A-1601F may utilize shared local memory 1608A-1608F within each sub-core to enable threads executing within a thread group to execute using a common pool of on-chip memory.

[0286] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6B and / or Figure 6C615. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into the graphics processor 1610. In at least one embodiment, the training and / or inference techniques described herein may be used in Fig. 16B In addition, in at least one embodiment, the inference and / or training operations described herein may use the addition of Figure 6B and / or Figure 6C In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of the graphics processor 1600C to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0287] Figures 16D-16E Thread execution logic 1600D is shown for an array of processing elements including a graphics processor core, according to at least one embodiment. Fig.16D At least one embodiment is shown in which thread execution logic 1600D is used. Fig.16E Exemplary internal details of an execution unit in accordance with at least one embodiment are shown.

[0288] like Fig.16DAs shown in , in at least one embodiment, thread execution logic 1600D includes a shader processor 1602, a thread dispatcher 1604, an instruction cache 1606, a scalable execution unit array including a plurality of execution units 1608A-1608N, one or more samplers 1610, a data cache 1612, and a data port 1614. In at least one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any one of execution units 1608A, 1608B, 1608C, 1608D, 1608N-1, and 1608N), for example, based on the computational requirements of the workload. In at least one embodiment, the scalable execution units are interconnected by an interconnect structure that links to each execution unit. In at least one embodiment, thread execution logic 1600D includes one or more connections to a memory (such as system memory or cache memory) through instruction cache 1606, data port 1614, sampler 1610, and one or more of execution units 1608A-1608N. In at least one embodiment, each execution unit (e.g., 1608A) is an independent programmable general-purpose computing unit that is capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In at least one embodiment, the array of execution units 1608A-1608N is scalable to include any number of separate execution units.

[0289] In at least one embodiment, execution units 1608A-1608N are primarily used to execute shader programs. In at least one embodiment, shader processor 1602 can process various shader programs and dispatch execution threads associated with shader programs via thread dispatcher 1604. In at least one embodiment, thread dispatcher 1604 includes logic for arbitrating thread initialization celebrations from graphics and media pipelines and instantiating requested threads on one or more execution units in execution units 1608A-1608N. In at least one embodiment, in at least one embodiment, the geometry pipeline can dispatch vertices, tessellation or geometry shaders to thread execution logic for processing. In at least one embodiment, thread dispatcher 1604 can also process runtime thread generation requests from executing shader programs.

[0290] In at least one embodiment, the execution units 1608A-1608N support an instruction set that includes native support for many standard 3D graphics shader instructions, allowing shader programs in graphics libraries (such as Direct 3D and OpenGL) to execute with minimal conversion. In at least one embodiment, the execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., compute and media shaders). In at least one embodiment, each execution unit 1608A-1608N includes one or more arithmetic logic units (ALUs) capable of performing multiple-issue single instruction multiple data (SIMD), and multi-threaded operations enable an efficient execution environment despite higher latency memory access. In at least one embodiment, each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. In at least one embodiment, execution is multiple issues per clock to the pipeline, which is capable of integer, single-precision and double-precision floating point operations, SIMD branch functions, logical operations, prior operations, and other other operations. In at least one embodiment, while waiting for data from memory or one of the shared functions, dependency logic within execution units 1608A-1608N causes the waiting thread to sleep until the requested data is returned. In at least one embodiment, while the waiting thread is sleeping, hardware resources can be dedicated to processing other threads. In at least one embodiment, during the delay associated with the vertex shader operation, the execution unit can perform operations on a pixel shader, a fragment shader, or another type of shader program (including a different vertex shader).

[0291] In at least one embodiment, each of the execution units 1608A-1608N operates on an array of data elements. In at least one embodiment, the number of data elements is the "execution size" or number of lanes of an instruction. In at least one embodiment, an execution lane is a logical unit used for the execution of data element access, masking, and flow control within an instruction. In at least one embodiment, the multiple lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) for a particular graphics processor. In at least one embodiment, the execution units 1608A-1608N support integer and floating point data types.

[0292] In at least one embodiment, the execution unit instruction set includes SIMD instructions. In at least one embodiment, various data elements can be stored in registers as packed data types, and the execution unit will process various elements based on the data size of those elements. In at least one embodiment, in at least one embodiment, when operating on a 256-bit wide vector, 256 bits of the vector are stored in registers, and the execution unit operates on the vector as four separate 64-bit packed data elements (quadword (QW) size data elements), eight separate 32-bit packed data elements (doubleword (DW) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements) or thirty-two separate 8-bit data elements (byte (B) size data elements). However, in at least one embodiment, different vector widths and register sizes are possible.

[0293] In at least one embodiment, one or more execution units may be combined into fused execution units 1609A-1609N having thread control logic (1607A-1607N) for executing fused EUs. In at least one embodiment, multiple EUs may be merged into one EU group. In at least one embodiment, each EU in the fused EU group may be configured to execute a separate SIMD hardware thread. The number of EUs in the fused EU group may vary according to various embodiments. In at least one embodiment, each EU may execute various SIMD widths, including but not limited to SIMD8, SIMD16, and SIMD32. In at least one embodiment, each fused graphics execution unit 1609A-1609N includes at least two execution units. In at least one embodiment, in at least one embodiment, the fused execution unit 1609A includes a first EU 1608A, a second EU 1608B, and a thread control logic 1607A shared by the first EU 1608A and the second EU 1608B. In at least one embodiment, thread control logic 1607A controls threads executing on fused graphics execution unit 1609A, allowing each EU within fused execution units 1609A-1609N to execute using a common instruction pointer register.

[0294] In at least one embodiment, one or more internal instruction caches (e.g., 1606) are included in the thread execution logic 1600D to cache thread instructions for the execution unit. In at least one embodiment, one or more data caches (e.g., 1612) are included to cache thread data during thread execution. In at least one embodiment, a sampler 1610 is included to provide texture sampling for 3D operations and media sampling for media operations. In at least one embodiment, the sampler 1610 includes a specialized texture or media sampling function to process the texture or media data during the sampling process before providing the sampled data to the execution unit.

[0295] During execution, in at least one embodiment, the graphics and media pipeline sends thread initiation requests to the thread execution logic 1600D through the thread generation and dispatch logic. In at least one embodiment, once a set of geometric objects have been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 1602 is called to further calculate output information and cause the results to be written to the output surface (e.g., color buffer, depth buffer, template buffer, etc.). In at least one embodiment, the pixel shader or fragment shader calculates the values ​​of various vertex attributes to be interpolated on the rasterized object. In at least one embodiment, the pixel processor logic within the shader processor 1602 then executes the pixel or fragment shader program provided by the application program interface (API). In at least one embodiment, in order to execute the shader program, the shader processor 1602 dispatches the thread to the execution unit (e.g., 1608A) via the thread dispatcher 1604. In at least one embodiment, the shader processor 1602 uses the texture sampling logic in the sampler 1610 to access the texture data in the texture map stored in the memory. In at least one embodiment, arithmetic operations on texture data and input geometry data calculate pixel color data for each geometry fragment, or discard one or more pixels for further processing.

[0296] In at least one embodiment, data port 1614 provides a memory access mechanism for thread execution logic 1600D to output processed data to memory for further processing on the graphics processor output pipeline. In at least one embodiment, data port 1614 includes or is coupled to one or more cache memories (e.g., data cache 1612) to cache data for memory access via the data port.

[0297] like Fig.16EAs shown, in at least one embodiment, graphics execution unit 1608 may include instruction fetch unit 1637, general register file array (GRF) 1624, architectural register file array (ARF) 1626, thread arbiter 1622, issue unit 1630, branch unit 1632, a set of SIMD floating point units (FPUs) 1634, and in at least one embodiment, a set of dedicated integer SIMD ALUs 1635. In at least one embodiment, GRF 1624 and ARF 1626 include a set of general register files and architectural register files associated with each simultaneous hardware thread that can be active in graphics execution unit 1608. In at least one embodiment, per-thread architectural state is maintained in ARF 1626, while data used during thread execution is stored in GRF 1624. In at least one embodiment, the execution state of each thread, including the instruction pointer of each thread, may be saved in thread-specific registers in ARF 1626.

[0298] In at least one embodiment, graphics execution unit 1608 has an architecture that is a combination of simultaneous multithreading (SMT) and fine-grained interleaved multithreading (IMT). In at least one embodiment, the architecture has a modular configuration that can be fine-tuned at design time based on the target number of simultaneous threads and the number of registers per execution unit, where execution unit resources are logically allocated for executing multiple simultaneous threads.

[0299] In at least one embodiment, the graphics execution unit 1608 may issue multiple instructions together, each of which may be a different instruction. In at least one embodiment, the thread arbiter 1622 of the graphics execution unit thread 1608 may dispatch the instruction to one of the issue unit 1630, the branch unit 1632, or the SIMD FPU 1632 for execution. In at least one embodiment, each execution thread may access 128 general registers in the GRF 1624, each of which may store 32 bytes and may be accessed as a SIMD 8-element vector of 32-bit data elements. In at least one embodiment, each execution unit thread may access 4KB in the GRF 1624, although the embodiment is not limited thereto, and more or less register resources may be provided in other embodiments. In at least one embodiment, although the number of threads per execution unit may also vary depending on the embodiment, up to seven threads may be executed simultaneously. In at least one embodiment in which seven threads may access 4KB, the GRF 1624 may store a total of 28KB. In at least one embodiment, flexible addressing modes may allow registers to be addressed together to efficiently build wider registers or rectangular block data structures representing strides.

[0300] In at least one embodiment, memory operations, sampler operations, and other longer latency system communications are scheduled via "send" instructions executed by message passing send unit 1630. In at least one embodiment, dispatching branch instructions to a dedicated branch unit 1632 facilitates SIMD divergence and eventual convergence.

[0301] In at least one embodiment, the graphics execution unit 1608 includes one or more SIMD floating point units (FPUs) 1634 to perform floating point operations. In at least one embodiment, one or more FPUs 1634 also support integer calculations. In at least one embodiment, one or more FPUs 1634 can SIMD perform up to M 32-bit floating point (or integer) operations, or SIMD perform up to 2M 16-bit integer or 16-bit floating point operations. In at least one embodiment, at least one of the one or more FPUs provides extended math capabilities to support high throughput a priori math functions and double-precision 64-bit floating points. In at least one embodiment, there is also a set of 8-bit integer SIMD ALUs 1635, and can be specifically optimized to perform operations related to machine learning calculations.

[0302] In at least one embodiment, an array of multiple instances of graphics execution unit 1608 may be instantiated in graphics sub-core groupings (e.g., sub-slices). In at least one embodiment, execution unit 1608 may execute instructions across multiple execution lanes. In at least one embodiment, each thread executing on graphics execution unit 1608 executes on a different lane.

[0303] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6B and / or Figure 6C Provides details about the reasoning and / or training logic 615. In at least one embodiment, some or all of the reasoning and / or training logic 615 can be incorporated into the execution logic 1600D. In addition, in at least one embodiment, other than Figure 6B and / or Figure 6C In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of execution logic 1600D to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0304] Fig.17AA parallel processing unit ("PPU") 1700A is shown according to at least one embodiment. In at least one embodiment, the PPU 1700A is configured with machine-readable code that, if executed by the PPU 1700A, causes the PPU 1700A to perform some or all of the processes and techniques described throughout the present disclosure. In at least one embodiment, the PPU 1700A is a multithreaded processor implemented on one or more integrated circuit devices, and utilizes multithreading as a latency hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of a group of instructions configured to be executed by the PPU 1700A. In at least one embodiment, the PPU 1700A is a graphics processing unit ("GPU") configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data to generate two-dimensional ("2D") image data for display on a display device (such as a liquid crystal display ("LCD") device). In at least one embodiment, PPU 1700A is used to perform computations, such as linear algebra operations and machine learning operations. Fig.17A The example parallel processor is shown for illustrative purposes only, and should be construed as a non-limiting example of a processor architecture contemplated within the scope of the present disclosure, and any suitable processor may be employed in addition and / or in place thereof.

[0305] In at least one embodiment, one or more PPUs 1700A are configured to accelerate high performance computing ("HPC"), data center, and machine learning applications. In at least one embodiment, PPU 1700A is configured to accelerate deep learning systems and applications, including the following non-limiting examples: autonomous vehicle platforms, deep learning, high-precision speech, image, text recognition systems, intelligent video analysis, molecular simulation, drug discovery, disease diagnosis, weather forecasting, big data analysis, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimization, and personalized user recommendations, etc.

[0306] In at least one embodiment, the PPU 1700A includes, but is not limited to, an input / output ("I / O") unit 1706, a front end unit 1710, a scheduler unit 1712, a work distribution unit 1714, a hub 1716, a crossbar switch ("Xbar") 1720, one or more general processing clusters ("GPCs") 1718, and one or more partitioning units ("memory partitioning units") 1722. In at least one embodiment, the PPU 1700A is connected to a host processor or other PPUs 1700A via one or more high-speed GPU interconnects ("GPU interconnects") 1708. In at least one embodiment, the PPU 1700A is connected to a host processor or other peripheral devices via interconnect 1702. In one embodiment, the PPU 1700A is connected to a local memory including one or more memory devices ("memory") 1704. In at least one embodiment, the memory devices 1704 include, but are not limited to, one or more dynamic random access memory ("DRAM") devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as a high bandwidth memory ("HBM") subsystem with multiple DRAM dies stacked within each device.

[0307] In at least one embodiment, high-speed GPU interconnect 1708 may refer to a wire-based multi-channel communication link that a system uses to scale and includes one or more PPUs 1700A in conjunction with one or more central processing units ("CPUs"), supporting cache coherence between PPU 1700A and CPUs and CPU mastering. In at least one embodiment, high-speed GPU interconnect 1708 transmits data and / or commands to other units of PPU 1700A, such as one or more copy engines, video encoders, video decoders, power management units, and / or other units in PPU 1700A via hub 1716. Fig.17A Other components that may not be explicitly shown.

[0308] In at least one embodiment, I / O unit 1706 is configured to receive data from a host processor ( Fig.17A1700A). In at least one embodiment, I / O unit 1706 communicates with a host processor directly through interconnect 1702 or through one or more intermediate devices (e.g., a memory bridge). In at least one embodiment, I / O unit 1706 can communicate with one or more other processors (e.g., one or more PPUs 1700A) via interconnect 1702. In at least one embodiment, I / O unit 1706 implements a Peripheral Component Interconnect Express ("PCIe") interface for communicating over a PCIe bus. In at least one embodiment, I / O unit 1706 implements an interface for communicating with external devices.

[0309] In at least one embodiment, I / O unit 1706 decodes packets received via interconnect 1702. In at least one embodiment, at least some of the packets represent commands configured to cause PPU 1700A to perform various operations. In at least one embodiment, I / O unit 1706 sends the decoded commands to various other units of PPU 1700A as specified by the commands. In at least one embodiment, the commands are sent to front end unit 1710 and / or to hub 1716 or other units of PPU 1700A, such as one or more replication engines, video encoders, video decoders, power management units, etc. ( Fig.17A In at least one embodiment, I / O unit 1706 is configured to route communications between various logical units of PPU 1700A.

[0310] In at least one embodiment, a program executed by a host processor encodes a command stream in a buffer that provides a workload to the PPU 1700A for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is an area in memory that is accessible (e.g., read / write) by both the host processor and the PPU 1700A—the host interface unit can be configured to access the buffer in the system memory connected to the interconnect 1702 via memory requests transmitted via the I / O unit 1706 through the interconnect 1702. In at least one embodiment, the host processor writes the command stream to the buffer and then sends a pointer indicating the beginning of the command stream to the PPU 1700A, so that the front end unit 1710 receives pointers to one or more command streams and manages one or more command streams, reads commands from the command streams and forwards the commands to the various units of the PPU 1700A.

[0311] In at least one embodiment, the front end unit 1710 is coupled to a scheduler unit 1712 that configures the various GPCs 1718 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 1712 is configured to track state information related to the various tasks managed by the scheduler unit 1712, where the state information may indicate which GPC 1718 the task is assigned to, whether the task is active or inactive, a priority associated with the task, etc. In at least one embodiment, the scheduler unit 1712 manages multiple tasks that are executed on one or more GPCs 1718.

[0312] In at least one embodiment, the scheduler unit 1712 is coupled to a work distribution unit 1714, which is configured to dispatch tasks for execution on the GPCs 1718. In at least one embodiment, the work distribution unit 1714 tracks a plurality of scheduled tasks received from the scheduler unit 1712 and the work distribution unit 1714 manages a pending task pool and an active task pool for each GPC 1718. In at least one embodiment, the pending task pool includes a plurality of time slots (e.g., 16 time slots) containing tasks assigned to be processed by a particular GPC 1718; the active task pool may include a plurality of time slots (e.g., 4 time slots) for tasks actively processed by the GPC 1718, such that as one of the tasks in the GPC 1718 completes execution, the task is evicted from the active task pool of the GPC 1718 and one of the other tasks is selected from the pending task pool and scheduled for execution on the GPC 1718. In at least one embodiment, if the active task is idle on GPC 1718, such as while waiting for data dependencies to be resolved, the active task is evicted from GPC 1718 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled for execution on GPC 1718.

[0313] In at least one embodiment, work distribution unit 1714 communicates with one or more GPCs 1718 via XBar 1720. In at least one embodiment, XBar 1720 is an interconnect network that couples many units of PPU 1700A to other units of PPU 1700A and can be configured to couple work distribution unit 1714 to a specific GPC 1718. In at least one embodiment, one or more other units of PPU 1700A can also be connected to XBar 1716 via hub 1716.

[0314] In at least one embodiment, tasks are managed by a scheduler unit 1712 and assigned to one of the GPCs 1718 by a work distribution unit 1714. The GPC 1718 is configured to process tasks and produce results. In at least one embodiment, the results can be consumed by other tasks in the GPC 1718, routed to a different GPC 1718 via an XBar 1716, or stored in memory 1704. In at least one embodiment, the results can be written to the memory 1704 via a partition unit 1722, which implements a memory interface for writing data to or reading data from the memory 1704. In at least one embodiment, the results can be transmitted to another PPU 1704 or a CPU via a high-speed GPU interconnect 1708. In at least one embodiment, the PPU 1700A includes, but is not limited to, U partition units 1722, which are equal to the number of separate and distinct memory devices 1704 coupled to the PPU 1700A. In at least one embodiment, the following will be combined with Fig. 17C The partition unit 1722 is described in more detail.

[0315] In at least one embodiment, the host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 1700A. In one embodiment, multiple computing applications are executed simultaneously by the PPU 1700A, and the PPU 1700A provides isolation, quality of service (“QoS”), and independent address spaces for the multiple computing applications. In at least one embodiment, the application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by the PPU 1700A, and the driver core outputs the tasks to one or more streams processed by the PPU 1700A. In at least one embodiment, each task includes one or more related groups of threads, which may be referred to as warps. In at least one embodiment, a warp includes multiple related threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, a cooperative thread may refer to multiple threads, including instructions for executing tasks and exchanging data through shared memory, combined with Fig. 17C Threads and cooperating threads are described in greater detail according to at least one embodiment.

[0316] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6B and / or Figure 6CDetails are provided regarding the inference and / or training logic 615. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the PPU 1700A. In at least one embodiment, the PPU 1700A is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or the PPU 1700A. In at least one embodiment, the PPU 1700A can be used to perform one or more of the neural network use cases described herein.

[0317] Fig. 17B A general processing cluster ("GPC") 1700B is shown in accordance with at least one embodiment. In at least one embodiment, GPC 1700B is Fig.17A 1700B. In at least one embodiment, each GPC 1700B includes, but is not limited to, a plurality of hardware units for processing tasks, and each GPC 1700B includes, but is not limited to, a pipeline manager 1702, a pre-raster operations unit ("PROP") 1704, a raster engine 1708, a work distribution crossbar ("WDX") 1716, a memory management unit ("MMU") 1718, one or more data processing clusters ("DPCs") 1706, and any suitable combination of components.

[0318] In at least one embodiment, the operation of the GPC 1700B is controlled by a pipeline manager 1702. In at least one embodiment, the pipeline manager 1702 manages the configuration of one or more DPCs 1706 to process tasks assigned to the GPC 1700B. In at least one embodiment, the pipeline manager 1702 configures at least one of the one or more DPCs 1706 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, the DPC 1706 is configured to execute vertex shader programs on a programmable streaming multiprocessor (“SM”) 1714. In at least one embodiment, the pipeline manager 1702 is configured to route packets received from the work distribution unit to appropriate logic units within the GPC 1700B, and in at least one embodiment, some packets may be routed to fixed function hardware units in the PROP 1704 and / or the raster engine 1708, while other packets may be routed to the DPC 1706 for processing by the primitive engine 1712 or the SM 1714. In at least one embodiment, pipeline manager 1702 configures at least one of DPCs 1706 to implement a neural network model and / or a computational pipeline.

[0319] In at least one embodiment, PROP unit 1704 is configured to route data generated by raster engine 1708 and DPC 1706 to a raster operations ("ROP") unit in partition unit 1722 in at least one embodiment, in conjunction with Fig.17A Described in more detail. In at least one embodiment, the PROP unit 1704 is configured to perform optimizations for color blending, organize pixel data, perform address translation, and the like. In at least one embodiment, the raster engine 1708 includes, but is not limited to, a plurality of fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, the raster engine 1708 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are transmitted to the coarse raster engine to generate coverage information for the base primitives (e.g., an x, y coverage mask for the tile); the output of the coarse raster engine is transmitted to the culling engine, where fragments associated with primitives that fail the z test are culled, and to the clipping engine, where the fragments that are outside the frustum are clipped. In at least one embodiment, the clipped and culled fragments are passed to the fine raster engine to generate properties for the pixel fragments based on the plane equations generated by the setup engine. In at least one embodiment, the output of raster engine 1708 includes fragments to be processed by any appropriate entity (e.g., by a fragment shader implemented within DPC 1706).

[0320] In at least one embodiment, each DPC 1706 included in GPC 1700B includes, but is not limited to, an M-pipeline controller ("MPC") 1710; a primitive engine 1712; one or more SMs 1714; and any suitable combination thereof. In at least one embodiment, MPC 1710 controls the operation of DPC 1706, routing packets received from pipeline manager 1702 to appropriate units in DPC 1706. In at least one embodiment, packets associated with vertices are routed to primitive engine 1712, which is configured to fetch vertex attributes associated with the vertices from memory; conversely, packets associated with shader programs may be sent to SM 1714.

[0321] In at least one embodiment, SM 1714 includes, but is not limited to, a programmable stream processor configured to process tasks represented by multiple threads. In at least one embodiment, SM 1714 is multithreaded and configured to execute multiple threads (e.g., 32 threads) from a particular thread group simultaneously, and implements a single instruction, multiple data ("SIMD") architecture, wherein each thread in a group of threads (e.g., a warp) is configured to process different data sets based on the same instruction set. In at least one embodiment, all threads in a thread group execute the same instruction. In at least one embodiment, SM 1714 implements a single instruction, multiple thread ("SIMT") architecture, wherein each thread in a group of threads is configured to process different data sets based on the same instruction set, but wherein individual threads in a thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp, thereby achieving concurrency between warps and serial execution within the warp when threads in the warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby enabling equal concurrency between all threads within and between warps. In at least one embodiment, execution state is maintained for each individual thread, and threads of the same instruction can be converged and executed in parallel to improve efficiency. At least one embodiment of SM 1714 is described in more detail below.

[0322] In at least one embodiment, MMU 1718 is used between GPC 1700B and memory partition unit (e.g., Fig.17A The MMU 1718 provides an interface between the partition unit 1722 of the memory, and provides virtual address to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, the MMU 1718 provides one or more translation lookaside buffers ("TLBs") for performing translation of virtual addresses to physical addresses in memory.

[0323] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6B and / or Figure 6C Details are provided regarding inference and / or training logic 615. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the GPC 1700B. In at least one embodiment, the GPC 1700B is used to infer or predict information based on a machine learning model (e.g., a neural network) that has been trained by another processor or system or the GPC 1700B. In at least one embodiment, the GPC 1700B can be used to perform one or more of the neural network use cases described herein.

[0324] Fig. 17C A memory partition unit 1700C of a parallel processing unit ("PPU") according to at least one embodiment is shown. In at least one embodiment, the memory partition unit 1700C includes, but is not limited to, a raster operation ("ROP") unit 1702; a level 2 ("L2") cache 1704; a memory interface 1706; and any suitable combination thereof. In at least one embodiment, the memory interface 1706 is coupled to a memory. In at least one embodiment, the memory interface 1706 may implement a 32, 64, 128, 1024 bit data bus, or a similar implementation for high speed data transfer. In at least one embodiment, the PPU includes U memory interfaces 1706, one memory interface 1706 for each pair of partition units 1700C, wherein each pair of partition units 1700C is connected to a corresponding memory device. In at least one embodiment, in at least one embodiment, the PPU may be connected to up to Y memory devices, such as a high bandwidth memory stack or a graphics double data rate version 5 synchronous dynamic random access memory ("GDDR5 SDRAM").

[0325] In at least one embodiment, the memory interface 1706 implements a high bandwidth memory second generation ("HBM2") memory interface, and Y is equal to half of U. In at least one embodiment, the HBM2 memory stack is located on the same physical package as the PPU, providing significant power and area savings compared to a GDDR5 SDRAM system. In at least one embodiment, each HBM2 stack includes, but is not limited to, four memory dies, and Y=4, each HBM2 stack includes two 128-bit channels per die for a total of 8 channels and a data bus width of 1024 bits. In at least one embodiment, the memory supports single error correction double error detection ("SECDED") error correction code ("ECC") to protect data. In at least one embodiment, ECC provides higher reliability for computing applications that are sensitive to data corruption.

[0326] In at least one embodiment, the PPU implements a multi-level memory hierarchy. In at least one embodiment, the memory partition unit 1700C supports unified memory to provide a single unified virtual address space for the central processing unit ("CPU") and the PPU memory, thereby enabling data sharing between virtual memory systems. In at least one embodiment, the frequency of accesses by the PPU to memory located on other processors is tracked to ensure that memory pages are moved to the physical memory of the PPU that accesses the page more frequently. In at least one embodiment, the high-speed GPU interconnect 1708 supports address translation services that allow the PPU to directly access the CPU's page tables and provide full access to the CPU memory through the PPU.

[0327] In at least one embodiment, the copy engine transfers data between multiple PPUs or between a PPU and a CPU. In at least one embodiment, the copy engine can generate a page fault for an address that is not mapped in a page table, and the memory partition unit 1700C then services the page fault, maps the address into a page table, and then the copy engine performs the transfer. In at least one embodiment, fixed (in at least one embodiment, non-pageable) memory is used for multiple copy engine operations between multiple processors, thereby substantially reducing the available memory. In at least one embodiment, in the event of a hardware page fault, the address can be passed to the copy engine without regard to whether it resides in a memory page, and the copy process is transparent.

[0328] According to at least one embodiment, from Fig.17A Data from memory 1704 or other system memory is retrieved by memory partition unit 1700C and stored in L2 cache 1704, which is located on the chip and shared between various GPCs. In at least one embodiment, each memory partition unit 1700C includes, but is not limited to, at least a portion of the L2 cache associated with the corresponding memory device. In at least one embodiment, lower-level caches are implemented in various units within the GPC. In at least one embodiment, each SM 1714 can implement a level 1 ("L1") cache, where the L1 cache is private memory dedicated to a particular SM 1714, and data is retrieved from the L2 cache 1704 and stored in each L1 cache for processing in the functional units of the SM 1714. In at least one embodiment, the L2 cache 1704 is coupled to the memory interface 1706 and the XBar 1720.

[0329] In at least one embodiment, ROP unit 1702 performs graphics raster operations related to pixel color, such as color compression, pixel blending, etc. In at least one embodiment, ROP unit 1702 performs depth testing in conjunction with raster engine 1708, receiving the depth of a sample position associated with a pixel fragment from a culling engine of raster engine 1708. In at least one embodiment, the depth is tested against a corresponding depth in a depth buffer of the sample position associated with the fragment. In at least one embodiment, if the fragment passes the depth test for the sample position, ROP unit 1702 updates the depth buffer and sends the result of the depth test to raster engine 1708. It will be appreciated that the number of partition units 1700C can be different than the number of GPCs, and therefore, each ROP unit 1702 can be coupled to each GPC in at least one embodiment. In at least one embodiment, ROP unit 1702 tracks packets received from different GPCs and determines to which result the result generated by ROP unit 1702 is routed via XBar 1720.

[0330] Fig.17D Streaming multiprocessor ("SM") 1700D is shown in accordance with at least one embodiment. In at least one embodiment, SM 1700D is Fig. 17BSMs. In at least one embodiment, SM 1700D includes, but is not limited to, instruction cache 1702; one or more scheduler units 1704; register file 1708; one or more processing cores ("cores") 1710; one or more special function units ("SFUs") 1712; one or more load / store units ("LSUs") 1714; interconnect network 1716; shared memory / level 1 ("L1") cache 1718; and any suitable combination thereof. In at least one embodiment, a work distribution unit schedules tasks for execution on a general processing cluster ("GPC") of a parallel processing unit ("PPU"), and each task is assigned to a specific data processing cluster ("DPC") within the GPC, and if the task is associated with a shader program, the task is assigned to one of SMs 1700D. In at least one embodiment, scheduler unit 1704 receives tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM 1700D. In at least one embodiment, the scheduler unit 1704 schedules thread blocks to execute as warps of parallel threads, where each thread block is assigned at least one warp. In at least one embodiment, each warp executes a thread. In at least one embodiment, the scheduler unit 1704 manages a plurality of different thread blocks, assigns warps to different thread blocks, and then dispatches instructions from a plurality of different cooperative groups to various functional units (e.g., processing cores 1710, SFUs 1712, and LSUs 1714) in each clock cycle.

[0331] In at least one embodiment, a cooperative group may refer to a programming model for organizing groups of communicating threads that allows developers to express the granularity at which threads are communicating, thereby enabling the expression of richer and more efficient parallel decompositions. In at least one embodiment, a cooperative launch API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, the application of the programming model provides a single, simple construct for synchronizing cooperative threads: a barrier across all threads of a thread block (e.g., a syncthreads() function). However, in at least one embodiment, programmers can define thread groups at a granularity smaller than a thread block and synchronize within the defined group to achieve higher performance, design flexibility, and software reuse in the form of a collective group-wide functional interface. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at sub-block (in at least one embodiment, as small as a single thread) and multi-block granularity, and perform collective operations, such as synchronizing threads in a cooperative group. In at least one embodiment, the programming model supports clean composition across software boundaries, so that libraries and utility functions can be safely synchronized in their local environment without having to make assumptions about convergence. In at least one embodiment, the cooperation group primitives enable new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization over an entire grid of thread blocks.

[0332] In at least one embodiment, the scheduling unit 1706 is configured to send instructions to one or more of the functional units, and the scheduler unit 1704 includes, but is not limited to, two scheduling units 1706 that enable two different instructions from the same thread warp to be scheduled per clock cycle. In at least one embodiment, each scheduler unit 1704 includes a single scheduling unit 1706 or additional scheduling units 1706.

[0333] In at least one embodiment, each SM 1700D includes, in at least one embodiment, but is not limited to, a register file 1708 that provides a set of registers for the functional units of the SM 1700D. In at least one embodiment, the register file 1708 is divided between each functional unit, so that a dedicated portion of the register file 1708 is allocated to each functional unit. In at least one embodiment, the register file 1708 is divided between different thread warps executed by the SM 1700D, and the register file 1708 provides temporary storage for operands of data paths connected to the functional units. In at least one embodiment, each SM 1700D includes, in at least one embodiment, but is not limited to, a plurality of L processing cores 1710. In at least one embodiment, the SM 1700D includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 1710. In at least one embodiment, each processing core 1710 includes, but is not limited to, a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, including, but not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements IEEE 802.11 for floating-point arithmetic.

[0334] 754-2008 Standard. In at least one embodiment, processing cores 1710 include, but are not limited to, 64 single precision (32-bit) floating point cores, 64 integer cores, 32 double precision (64-bit) floating point cores, and 8 tensor cores.

[0335] According to at least one embodiment, the tensor core is configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in processing core 1710. In at least one embodiment, the tensor core is configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and reasoning. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiplication and accumulation operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

[0336] In at least one embodiment, the matrix multiplication inputs A and B are 16-bit floating point matrices, and the accumulation matrices C and D are 16-bit floating point or 32-bit floating point matrices. In at least one embodiment, the tensor core performs a 32-bit floating point accumulation operation on the 16-bit floating point input data. In at least one embodiment, the 16-bit floating point multiplication uses 64 operations and obtains a full-precision product, which is then accumulated with other intermediate products using 32-bit floating point addition to perform a 4x4x4 matrix multiplication. In at least one embodiment, the tensor core is used to perform larger two-dimensional or higher dimensional matrix operations composed of these smaller elements. In at least one embodiment, an API (such as a CUDA 9C++ API) exposes specialized matrix loads, matrix multiplications and accumulations, and matrix storage operations to efficiently use tensor cores from CUDA-C++ programs. In at least one embodiment, at the CUDA level, the warp level interface assumes a 16×16 size matrix across all 32 warp threads.

[0337] In at least one embodiment, each SM 1700D includes, but is not limited to, M SFUs 1712 that perform special functions (e.g., attribute evaluation, reciprocal square root, etc.). In at least one embodiment, the SFUs 1712 include, but are not limited to, tree traversal units configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFUs 1712 include, but are not limited to, texture units configured to perform texture map filtering operations. In at least one embodiment, the texture units are configured to load texture maps (e.g., 2D arrays of texture pixels) from memory and sample the texture maps to generate sampled texture values ​​for use by shader programs executed by the SM 1700D. In at least one embodiment, the texture maps are stored in a shared memory / L1 cache 1718. In at least one embodiment, according to at least one embodiment, the texture units use mip-maps (e.g., texture maps with different levels of detail) to implement texture operations (such as filtering operations). In at least one embodiment, each SM 1700D includes, but is not limited to, two texture units.

[0338] In at least one embodiment, each SM 1700D includes, but is not limited to, N LSUs 1714 that implement load and store operations between shared memory / L1 cache 1718 and register file 1708. In at least one embodiment, an interconnect network 1716 connects each functional unit to register file 1708, and the LSUs 1714 connect to register file 1708 and shared memory / L1 cache 1718. In at least one embodiment, the interconnect network 1716 is a crossbar switch that can be configured to connect any functional unit to any register in register file 1708, and to connect the LSUs 1714 to memory locations in register file 1708 and shared memory / L1 cache 1718.

[0339] In at least one embodiment, shared memory / L1 cache 1718 is an array of on-chip memory that allows data storage and communication between SM 1700D and primitive engines and between threads in SM 1700D in at least one embodiment. In at least one embodiment, shared memory / L1 cache 1718 includes, but is not limited to, 128KB of storage capacity and is located in the path from SM 1700D to the partition unit. In at least one embodiment, shared memory / L1 cache 1718 is used in at least one embodiment for caching reads and writes. In at least one embodiment, one or more of shared memory / L1 cache 1718, L2 cache, and memory is a backing store.

[0340] In at least one embodiment, data cache and shared memory functionality are combined into a single memory block, providing improved performance for both types of memory accesses. In at least one embodiment, the capacity is used by programs that do not use the shared memory or use it as a cache, for example if the shared memory is configured to use half of the capacity, and texture and load / store operations can use the remaining capacity. According to at least one embodiment, the integration within the shared memory / L1 cache 1718 enables the shared memory / L1 cache 1718 to be used as a high throughput pipeline for streaming data while providing high bandwidth and low latency access to frequently reused data. In at least one embodiment, when configured for general parallel computing, a simpler configuration can be used compared to graphics processing. In at least one embodiment, the fixed-function graphics processing unit is bypassed, thereby creating a simpler programming model. In at least one embodiment, in a general parallel computing configuration, the work distribution unit directly allocates and distributes blocks of threads to DPCs. In at least one embodiment, the threads in the block execute a common program, use unique thread IDs in computations to ensure that each thread generates unique results, use SM 1700D to execute the program and perform computations, use shared memory / L1 cache 1718 to communicate between threads, and use LSU 1714 to read and write global memory through shared memory / L1 cache 1718 and memory partitioning units. In at least one embodiment, when configured for general parallel computation, SM 1700D writes commands to scheduler unit 1704 that can be used to start new work on the DPC.

[0341] In at least one embodiment, the PPU is included in or coupled to a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smartphone (e.g., wireless, handheld device), a personal digital assistant ("PDA"), a digital camera, a vehicle, a head mounted display, a handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system on a chip ("SoC") along with one or more other devices (e.g., additional PPUs, memory, a reduced instruction set computer ("RISC") CPU, one or more memory management units ("MMU"), a digital-to-analog converter ("DAC"), etc.).

[0342] In at least one embodiment, the PPU may be included on a graphics card that includes one or more storage devices. The graphics card may be configured to connect to a PCIe slot on a desktop computer motherboard. In at least one embodiment, the PPU may be an integrated graphics processing unit ("iGPU") included in a chipset of the motherboard.

[0343] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations related to one or more embodiments. Figure 6B and / or Figure 6C Provides details about reasoning and / or training logic 615. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or reason about information provided to the SM 1700D. In at least one embodiment, the SM 1700D is used to reason or predict information based on a machine learning model (e.g., a neural network) that has been trained by another processor or system or by the SM 1700D. In at least one embodiment, the SM 1700D can be used to perform one or more of the neural network use cases herein.

[0344] In at least one embodiment, a single semiconductor platform may refer to a unique single semiconductor-based integrated circuit or chip. In at least one embodiment, a multi-chip module with increased connectivity may be used that emulates on-chip operations and provides substantial improvements over implementations utilizing a central processing unit ("CPU") and bus. In at least one embodiment, the various modules may also be placed separately or in various combinations of semiconductor platforms, depending on the needs of the user.

[0345] In at least one embodiment, a computer program in the form of a machine-readable executable code or a computer control logic algorithm is stored in the main memory 4ee04 and / or the auxiliary storage. According to at least one embodiment, if executed by one or more processors, the computer program enables the system 4ee00 to perform various functions. In at least one embodiment, the memory 4ee04, storage and / or any other storage are possible examples of computer-readable media. In at least one embodiment, the auxiliary storage can refer to any suitable storage device or system, such as a hard disk drive and / or a removable storage drive, which represents a floppy disk drive, a tape drive, an optical disk drive, a digital versatile disk ("DVD") drive, a recording device, a universal serial bus ("USB") flash memory, etc. In at least one embodiment, the architecture and / or functions of each of the previous figures are implemented in the environment of CPU 4ee02; parallel processing system 4ee12; an integrated circuit capable of having at least part of the capabilities of two CPUs 4ee02; parallel processing system 4ee12; a chipset (e.g., a group of integrated circuits designed to work and sell as a unit that performs related functions, etc.); and any appropriate combination of integrated circuits.

[0346] In at least one embodiment, the architecture and / or functionality of the various previous figures are implemented in the context of a general purpose computer system, a circuit board system, a game console system dedicated to entertainment purposes, a dedicated system, etc. In at least one embodiment, the computer system 4ee00 can take the form of a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smart phone (e.g., wireless, handheld device), a personal digital assistant ("PDA"), a digital camera, a vehicle, a head mounted display, a handheld electronic device, a mobile telephone device, a television, a workstation, a game console, an embedded system, and / or any other type of logic.

[0347] In at least one embodiment, the parallel processing system 4ee12 includes, but is not limited to, a plurality of parallel processing units ("PPUs") 4ee14 and associated memory 4ee16. In at least one embodiment, the PPUs 4ee14 are connected to a host processor or other peripheral device via an interconnect 4ee18 and a switch 4ee20 or multiplexer. In at least one embodiment, the parallel processing system 4ee12 distributes computational tasks across parallelizable PPUs 4ee14, for example, as part of a distribution of computational tasks across multiple graphics processing unit ("GPU") thread blocks. In at least one embodiment, memory (e.g., for read and / or write access) is shared and accessed between some or all of the PPUs 4ee14, although such shared memory may incur a performance penalty relative to the use of local memory and registers resident on the PPUs 4ee4ee. In at least one embodiment, the operation of the PPUs 4ee14 is synchronized by using a command (such as __syncthreads()), where all threads in a block (e.g., executing across multiple PPUs 4ee14) reach a certain code execution point before proceeding.

[0348] Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described in detail above. However, it should be understood that there is no intention to limit the disclosure to one or more specific forms disclosed, but on the contrary, it is intended to cover all modifications, alternative constructions, and equivalents that fall within the spirit and scope of the present disclosure as ...

Claims

1. A computer-implemented method for reconstructing an image using compression levels, characterized in that: establishing (504) one or more of said compression levels for image data from a region of interest (ROI); generating (506-510) an image volume from a first compression level using the subset of the image data; upsampling (516) the image volume to a second compression level; as well as At least one parameter used to generate the image volume is applied (518, 520) to one or more subsequent subsets of the image data to reconstruct the image associated with the features underlying the ROI.

2. The computer-implemented method of claim 1, further characterized in that: Using filtered back projection (FBP), it is determined (512) that the image volume satisfies predetermined criteria such that the image volume qualifies for the second compression level.

3. The computer-implemented method of claim 1 , further characterized by: The subset of the image data is simultaneously processed (508) based on at least one parameter and using a predetermined algorithm in a plurality of graphics processing units (GPUs) of a multi-GPU architecture to determine that the parameter is suitable for implementing constrained optimization in the first compression level.

4. The computer-implemented method of claim 1, wherein the first compression level is a highest compression compared to the second compression level and subsequent compression levels.

5. The computer-implemented method of claim 1 , further characterized by: An image volume from among the plurality of image volumes generated after each cycle of the iterative process is determined to converge simulation data having arbitrary values ​​to first data associated with the first compression level.

6. The computer-implemented method of claim 1, further characterized by: Filtered back projection (FBP) is used to determine that the image volume satisfies predetermined criteria to qualify the image volume as a first initializer image volume for the second compression level.

7. A computer-implemented method for reconstructing an image using compression levels, characterized in that: obtaining (502) data from radiation that has passed through tissue; establishing (504) the compression level for the data by distributing the data into subsets; establishing (506) at least one reconstruction parameter and a reconstruction algorithm for a first compression level, the first compression level including a minimum number of data points in the subset; determining (508) a plurality of first image volumes using the at least one reconstruction parameter and the reconstruction algorithm; determining (510, 512, 514) that a first image volume from the plurality of first image volumes satisfies a predetermined criterion such that the first image volume qualifies as a first initializer image volume for a second compression level; a requirement to upsample (516) said first initializer image volume to said second compression level; after the second compression level, using an image volume of a previous level as a subsequent initializer image volume for a subsequent level in each of the remaining ones of the compression levels and iterating (518) through the levels using the at least one reconstruction parameter to upsample the image volume of the previous level into the subsequent initializer image volume; and A final image volume is generated (520) after the iterations to enable reconstruction of an image of features underlying the tissue.

8. The computer-implemented method of claim 7, further characterized by: Using filtered back projection (FBP), it is determined that a first image volume from the plurality of first image volumes satisfies a predetermined criterion to qualify the first image volume as the first initializer image volume for the second compression level.

9. The computer-implemented method of claim 7, It is further characterized by: processing first data from the subset associated with the first compression level according to predetermined parameters and a predetermined algorithm to achieve a constrained optimization indicating the minimum number of data points in the subset required to determine the plurality of first image volumes; as well as The at least one reconstruction parameter and the reconstruction algorithm for the first compression level are selected from predetermined parameters and the algorithms based in part on at least one of the predetermined parameters and at least one of the predetermined algorithms that implement the constrained optimization.

10. The computer-implemented method of claim 9, further characterized by: The first data is simultaneously processed according to the predetermined parameters and using the predetermined algorithms in multiple graphics processing units (GPUs) of a multi-GPU architecture to determine that at least one of the predetermined parameters and at least one of the predetermined algorithms implement the constrained optimization.

Images