Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a first driving circuit; the first driving circuit comprises a multi-stage shifting register, and the shifting register at least comprises a first input unit, a second input unit and a first output unit; the control end of the first input unit is connected with a first trigger end, the input end is connected with a first signal end, and the output end is connected with a first node; the control end of the second input unit is connected with the second trigger end, the input end is connected with the second signal end, and the output end is connected with the first node; the control end of the first output unit is connected with the first node, the input end is connected with a third signal end, and the output end is connected with a shift output end; the first electric signal is a first clock signal, and / or the second electric signal is a second clock signal. According to the invention, at least one of the plurality of clock signal lines in the first driving circuit can be multiplexed to provide the clock signal for the first signal end or the second signal end, thereby facilitating the realization of a narrow frame.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In a display panel, a driving circuit arranged in a non-display area is an indispensable circuit structure, which is used to realize the display, touch and other functions of the display panel.

[0003] The driving circuit is usually composed of a cascade of multiple shift registers. The driving chip provides a driving signal to each shift register in the driving circuit through a signal line so that the driving circuit can operate normally.

[0004] However, the driving circuit in the existing display panel requires many signal lines, which is not conducive to the realization of a narrow frame. Summary of the invention

[0005] The present invention provides a display panel and a display device to achieve a narrow frame.

[0006] According to one aspect of the present invention, there is provided a display panel, comprising: a first driving circuit; the first driving circuit comprises a multi-stage shift register, the shift register comprises at least a first input unit, a second input unit and a first output unit;

[0007] The control end of the first input unit is connected to the first trigger end, the input end of the first input unit is connected to the first signal end, and the output end of the first input unit is connected to the first node, so as to adjust the signal of the first node according to the first electrical signal provided by the first signal end in response to the control of the first trigger end;

[0008] The control end of the second input unit is connected to the second trigger end, the input end of the second input unit is connected to the second signal end, and the output end of the second input unit is connected to the first node, so as to adjust the signal of the first node according to the second electrical signal provided by the second signal end in response to the control of the second trigger end;

[0009] The control end of the first output unit is connected to the first node, the input end of the first output unit is connected to the third signal end, and the output end of the first output unit is connected to the shift output end, and is used to adjust the signal of the shift output end according to the third clock signal provided by the third signal end in response to the control of the first node;

[0010] The first electrical signal is a first clock signal, and / or the second electrical signal is a second clock signal.

[0011] According to another aspect of the present invention, a display device is provided, comprising: the display panel as described above.

[0012] In the present invention, the first signal end of the first input unit of the shift register provides a first electrical signal, and the second signal end of the second input unit of the shift register provides a second electrical signal. At least one of the first electrical signal and the second electrical signal is a clock signal, and at least one of the multiple clock signal lines in the first drive circuit can be reused to provide a clock signal to the first signal end or the second signal end, thereby reducing the number of signal lines of the first drive circuit, which is beneficial to the display panel to achieve a narrow frame and a full screen. In addition, the first clock signal and the second clock signal are both high-low level alternating jumps, which can reduce the time length of the transistor in the input unit in the negative bias state during the shift register scanning process, and correspondingly can reduce the threshold voltage shift (Vth shift) of the transistor in the input unit, which is beneficial to improve the working stability and reliability of the shift register; and the leakage time length of the high level of the first clock signal or the high level of the second clock signal to the first node can also be halved, thereby improving the problem of easy failure of the shift register at high temperature and extending the service life of the shift register.

[0013] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention;

[0016] Figure 2 is a schematic diagram of a shift register provided by an embodiment of the present invention;

[0017] Figure 3 is a schematic diagram of a shift register provided for comparison;

[0018] Figure 4 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0019] Figure 5 yes Figure 4 The timing diagram of the shift register performing forward scanning is shown;

[0020] Figure 6 yes Figure 4The timing diagram of the shift register performing reverse scanning is shown;

[0021] Figure 7 is a schematic diagram of a first driving circuit provided by an embodiment of the present invention;

[0022] Figure 8 yes Figure 7 A schematic diagram of a clock signal of the first driving circuit in a forward scanning mode;

[0023] Fig. 9 yes Figure 7 A schematic diagram of a clock signal of the first driving circuit in a reverse scanning mode is shown;

[0024] Fig.10 is a schematic diagram of another first driving circuit provided by an embodiment of the present invention;

[0025] Fig.11 yes Fig.10 A schematic diagram of a clock signal of the first driving circuit in a forward scanning mode;

[0026] Fig.12 yes Fig.10 A schematic diagram of a clock signal of the first driving circuit in a reverse scanning mode is shown;

[0027] Fig.13 It is a timing diagram of the forward scanning of the shift register (ASG7(1)) in the first driving circuit based on the unilateral 6-phase ASG structure;

[0028] Fig.14 It is a timing diagram of reverse scanning of the shift register (ASG7(1)) in the first driving circuit based on the unilateral 6-phase ASG structure;

[0029] Fig.15 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0030] Fig.16 yes Fig.15 The timing diagram of the shift register performing forward scanning is shown;

[0031] Fig.17 yes Fig.15 The timing diagram of the shift register performing reverse scanning is shown;

[0032] Fig.18 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0033] Fig.19 yes Fig.18 The timing diagram of the shift register performing forward scanning is shown;

[0034] Fig. 20 yes Fig.18 The timing diagram of the shift register performing reverse scanning is shown;

[0035] Fig.21 is a schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0037] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0038] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention, Figure 2 is a schematic diagram of a shift register provided by an embodiment of the present invention. Figure 1 and Figure 2As shown, the display panel includes: a first driving circuit 100; the first driving circuit 100 includes a multi-stage shift register 101, and the shift register 101 includes at least a first input unit 111, a second input unit 112 and a first output unit 113; the control end of the first input unit 111 is connected to the first trigger terminal IN1, the input end of the first input unit 111 is connected to the first signal terminal SG1, and the output end of the first input unit 111 is connected to the first node N1, which is used to respond to the control of the first trigger terminal IN1 and adjust the signal of the first node N1 according to the first electrical signal provided by the first signal terminal SG1; the control end of the second input unit 112 is connected to the second trigger terminal IN2, and the input end of the second input unit 112 is connected to the first trigger terminal IN2. The end is connected to the second signal terminal SG2, and the output end of the second input unit 112 is connected to the first node N1, and is used for responding to the control of the second trigger terminal IN2 and adjusting the signal of the first node N1 according to the second electrical signal provided by the second signal terminal SG2; the control end of the first output unit 113 is connected to the first node N1, the input end of the first output unit 113 is connected to the third signal terminal SG3, and the output end of the first output unit 113 is connected to the shift output terminal GOUT, and is used for responding to the control of the first node N1 and adjusting the signal of the shift output terminal GOUT according to the third clock signal CK3 provided by the third signal terminal SG3; the first electrical signal is the first clock signal CK1, and / or the second electrical signal is the second clock signal.

[0039] In this embodiment, the display panel includes a first area 201 and a second area 202. The first area 201 is used for display, and the first area 201 includes a plurality of sub-pixels 203. Optionally, the sub-pixels 203 in the first area 201 are arranged in an array, and the plurality of sub-pixels 203 are arranged along the first direction F1 to form a row of sub-pixels 203, and the plurality of sub-pixels 203 are arranged along the second direction F2 to form a column of sub-pixels 203, and the first direction F1 and the second direction F2 intersect; however, the arrangement of the sub-pixels in the first area can also be other arrangements, not limited to the array arrangement. The second area 202 includes a circuit structure for driving the sub-pixels 203 in the first area 201 for display. Specifically, the second area 202 includes at least a first driving circuit 100, and the first driving circuit 100 is used to drive the sub-pixels 203 in the first area 201 for display. The first area 201 of the optional display panel is the display area of ​​the display panel, and the second area 202 is the non-display area of ​​the display panel; the sub-pixel 203 in the display area can be an organic light-emitting display unit, a micro light-emitting diode display unit, or other types of sub-pixels, without specific restrictions, for example, a liquid crystal display unit, etc.; the first driving circuit 100 in the non-display area is a gate driving circuit, which is used to control the sub-pixel 203 in the display area to perform row-by-row scanning.

[0040] The first driving circuit 100 includes a multi-stage shift register 101. The shift register 101 includes a shift output terminal GOUT, and a stage of the shift register 101 is electrically connected to one or more rows of sub-pixels 203 through the shift output terminal GOUT. The shift register 101 provides a gate driving signal to the electrically connected sub-pixels 203 through the shift output terminal GOUT, so as to drive the sub-pixels 203 to work. Figure 1 In the embodiment, a first-level shift register 101 can be electrically connected to a row of sub-pixels 203, and the shift register 101 provides a gate drive signal to the corresponding row of sub-pixels 203; however, in other embodiments, a first-level shift register can be electrically connected to multiple rows of sub-pixels, and the first-level shift register provides gate drive signals to multiple rows of sub-pixels at the same time.

[0041] The shift register 101 includes a first input unit 111, a control end of the first input unit 111 is connected to a first trigger end IN1, an input end of the first input unit 111 is connected to a first signal end SG1, and an output end of the first input unit 111 is connected to a first node N1. Specifically, the electrical signal provided by the first trigger end IN1 is a signal of alternating high and low levels, thereby controlling the on-off state of the first input unit 111. It can be understood that one of the high level and the low level of the first trigger end IN1 is an on-level that can turn on the first input unit 111, and the other is an off-level that can turn off the first input unit 111. If the electrical signal provided by the first trigger end IN1 is an on-level, the first input unit 111 is controlled to switch to an on-state, and the first electrical signal provided by the first signal end SG1 is written into the first node N1; conversely, if the electrical signal provided by the first trigger end IN1 is an off-level, the first input unit 111 is controlled to switch to an off-state, and the transmission path between the first signal end SG1 and the first node N1 is disconnected. Therefore, the first input unit 111 adjusts the signal of the first node N1 according to the first electrical signal provided by the first signal terminal SG1 in response to the control of the first trigger terminal IN1.

[0042] The shift register 101 includes a second input unit 112, a control end of the second input unit 112 is connected to the second trigger end IN2, an input end of the second input unit 112 is connected to the second signal end SG2, and an output end of the second input unit 112 is connected to the first node N1. Specifically, the electrical signal provided by the second trigger end IN2 is a signal of alternating high and low levels, thereby controlling the on-off state of the second input unit 112. It can be understood that the high level and the low level of the second trigger end IN2, one of which is the on-level that can turn on the second input unit 112, and the other is the off-level that can turn off the second input unit 112. If the electrical signal provided by the second trigger end IN2 is the on-level, the second input unit 112 is controlled to switch to the on-state, and the second electrical signal provided by the second signal end SG2 is written into the first node N1; conversely, if the electrical signal provided by the second trigger end IN2 is the off-level, the second input unit 112 is controlled to switch to the off-state, and the transmission path between the second signal end SG2 and the first node N1 is disconnected. Therefore, the second input unit 112 adjusts the signal of the first node N1 according to the second electrical signal provided by the second signal terminal SG2 in response to the control of the second trigger terminal IN2.

[0043] The shift register 101 includes a first output unit 113, a control end of the first output unit 113 is connected to the first node N1, an input end of the first output unit 113 is connected to the third signal end SG3, and an output end of the first output unit 113 is connected to the shift output end GOUT. Specifically, the signal of the first node N1 is controlled by the first input unit 111 and the second input unit 112, and the high and low levels alternately jump, thereby controlling the on and off state of the first output unit 113. The electrical signal provided by the third signal end SG3 is a clock signal, and the clock signal is defined as a third clock signal CK3. It can be understood that the high level and the low level of the first node N1, one of which is a conduction level that can turn on the first output unit 113, and the other is a turn-off level that can turn off the first output unit 113. If the signal of the first node N1 is at the on level, the first output unit 113 is controlled to switch to the on state, and the third clock signal CK3 provided by the third signal terminal SG3 is written into the shift output terminal GOUT; conversely, if the signal of the first node N1 is at the off level, the first output unit 113 is controlled to switch to the off state, and the transmission path between the third signal terminal SG3 and the shift output terminal GOUT is disconnected. Therefore, the first output unit 113 responds to the control of the first node N1 and adjusts the signal of the shift output terminal GOUT according to the third clock signal CK3 provided by the third signal terminal SG3.

[0044] The optional shift register 101 further includes: a second output unit 114; a control end of the second output unit 114 is connected to the fourth signal end SG4, an input end of the second output unit 114 is connected to the first power supply end VG1, and an output end of the second output unit 114 is connected to the shift output end GOUT, and is used to respond to the control of the fourth clock signal CK4 provided by the fourth signal end SG4, and adjust the signal of the shift output end GOUT according to the first power supply signal provided by the first power supply end VG1. Specifically, the electrical signal provided by the fourth signal end SG4 is a clock signal, and the clock signal is defined as the fourth clock signal CK4, which can control the on-off state of the second output unit 114. It can be understood that the high level and the low level of the fourth signal end SG4, one of which is the on-level that can turn on the second output unit 114, and the other is the off-level that can turn off the second output unit 114. If the electric signal provided by the fourth signal terminal SG4 is at a conduction level, the second output unit 114 is controlled to switch to a conduction state, and the first power signal provided by the first power terminal VG1 is written to the shift output terminal GOUT; conversely, if the electric signal provided by the fourth signal terminal SG4 is at an off level, the second output unit 114 is controlled to switch to a off state, and the transmission path between the first power terminal VG1 and the shift output terminal GOUT is disconnected. Therefore, the second output unit 114 responds to the control of the fourth clock signal CK4 provided by the fourth signal terminal SG4, and adjusts the signal of the shift output terminal GOUT according to the first power signal provided by the first power terminal VG1.

[0045] The optional shift register 101 also includes: a reset unit 115 and a node control unit 116; the reset unit 115 is connected to the reset control terminal RST, the first power supply terminal VG1, the first node N1 and the shift output terminal GOUT, and is used to respond to the control of the reset control terminal RST and adjust the signals of the first node N1 and the shift output terminal GOUT according to the first power supply signal provided by the first power supply terminal VG1; the node control unit 116 is connected to the first node N1, the first power supply terminal VG1 and the shift output terminal GOUT, and is used to respond to the control of the first node N1 and adjust the signals of the first node N1 and the shift output terminal GOUT according to the first power supply signal.

[0046] Specifically, the control end of the reset unit 115 is connected to the reset control end RST, and the electrical signal provided by the reset control end RST is a signal of alternating high and low levels, thereby controlling the on-off state of the reset unit 115. It can be understood that one of the high level and the low level of the reset control end RST is an on-level that can turn on the reset unit 115, and the other is an off-level that can turn off the reset unit 115. If the electrical signal provided by the reset control end RST is an on-level, the reset unit 115 is controlled to switch to the on-state, and the first power signal provided by the first power end VG1 is written into the first node N1 and the shift output end GOUT respectively; on the contrary, if the electrical signal provided by the reset control end RST is an off-level, the reset unit 115 is controlled to switch to the off-state, and the transmission paths between the first power end VG1 and the first node N1 and the first power end VG1 and the shift output end GOUT are disconnected. Therefore, the reset unit 115 adjusts the signals of the first node N1 and the shift output terminal GOUT according to the first power signal provided by the first power terminal VG1 in response to the control of the reset control terminal RST.

[0047] Specifically, at least one control terminal of the node control unit 116 is connected to the first node N1. The signal of the first node N1 will alternately jump between high and low levels, thereby affecting the on-off state of the node control unit 116. If the node control unit 116 is switched to the on state, the first power supply signal provided by the first power supply terminal VG1 is written into the first node N1 and the shift output terminal GOUT respectively; conversely, if the node control unit 116 is switched to the off state, the transmission paths between the first power supply terminal VG1 and the first node N1 and the first power supply terminal VG1 and the shift output terminal GOUT are disconnected. Therefore, the node control unit 116 responds to the control of the first node N1 and adjusts the signals of the first node N1 and the shift output terminal GOUT according to the first power supply signal.

[0048] In this embodiment, the first driving circuit 100 can realize bidirectional scanning (i.e., forward scanning and reverse scanning). In the forward scanning mode, the signal of the first node N1 is controlled by the first input unit 111. If the first input unit 111 is turned on, the first electrical signal provided by the first signal terminal SG1 is written into the first node N1, and the shift register 101 controls the output of the shift output terminal GOUT according to the potential signal of the first node N1. Specifically, when the first node N1 is at the on level, the shift register 101 transmits the third clock signal CK3 to the shift output terminal GOUT through the turned-on first output unit 113. In the reverse scanning mode, the signal of the first node N1 is controlled by the second input unit 112. If the second input unit 112 is turned on, the second electrical signal provided by the second signal terminal SG2 is written into the first node N1. The shift register 101 controls the output of the shift output terminal GOUT according to the potential signal of the first node N1. Specifically, when the first node N1 is at the on level, the shift register 101 transmits the third clock signal CK3 to the shift output terminal GOUT through the turned-on first output unit 113.

[0049] At least one of the first electrical signal and the second electrical signal may be a clock signal. In this embodiment, both the first electrical signal and the second electrical signal may be clock signals. The clock signal of the first electrical signal is defined as the first clock signal CK1, and the clock signal of the second electrical signal is defined as the second clock signal CK2. In other embodiments, the first electrical signal may be a clock signal, but the second electrical signal is not a clock signal; or, the first electrical signal may not be a clock signal, but the second electrical signal is a clock signal; or, the first electrical signal may be a clock signal, and the second electrical signal may be a clock signal. At least one of the first electrical signal and the second electrical signal may be a clock signal, which can achieve a narrow frame and improve the reliability of the shift register with forward and reverse scanning functions.

[0050] Figure 2In the shift register 101 shown, the first electrical signal provided by the optional first signal terminal SG1 is the first clock signal CK1, and the second electrical signal provided by the second signal terminal SG2 is the second clock signal CK2. The first drive circuit 100 itself has a plurality of clock signal lines, each of which provides a clock signal. The plurality of clock signal lines provide a plurality of clock signals to the shift register 101 to drive the shift register 101 to work. The plurality of clock signals provided to the shift register 101 by the plurality of clock signal lines include at least the first clock signal CK1 and the second clock signal CK2. Based on this, under the premise of ensuring the normal operation of the shift register 101, the first clock signal CK1 can be derived from the existing clock signal line in the first drive circuit 100, and the second clock signal CK2 can be derived from the existing clock signal line in the first drive circuit 100, that is, the clock signal line in the first drive circuit 100 that can provide the first clock signal CK1 can be connected to the first signal terminal SG1 of the shift register 101, and the clock signal line in the first drive circuit 100 that can provide the second clock signal CK2 can be connected to the second signal terminal SG2 of the shift register 101.

[0051] Figure 3 is a schematic diagram of a shift register provided in proportion to the Figure 2 for comparison. Figure 3 The first electrical signal provided by the first signal terminal SG1 of the shift register 101' is a DC signal DIR1 instead of a clock signal, and the second electrical signal provided by the second signal terminal SG2 is a DC signal DIR2 instead of a clock signal. Based on the multi-stage shift register 101' forming a gate drive circuit, the gate drive circuit needs to additionally add a DIR1 signal line and a DIR2 signal line. The DIR1 signal line is used to provide the DC signal DIR1 to the first signal terminal SG1 of the shift register 101', and the DIR2 signal line is used to provide the DC signal DIR2 to the second signal terminal SG2 of the shift register 101'. Obviously, the gate drive circuit and its signal lines will occupy more frame space.

[0052] It can be seen from this that in this embodiment, the first driving circuit 100 does not need to be provided with the DIR1 signal line and the DIR2 signal line. Figure 3 compared to, Figure 1 The frame space occupied by the first driving circuit 100 is reduced, which is conducive to the display panel to achieve a narrow frame and a full screen. It should be noted that the clock signal line connected to the first signal terminal SG1 and / or the clock signal line connected to the second signal terminal SG2 is directly connected, that is, the first signal terminal SG1 is directly connected to the clock signal line through a via or a connecting line, and the second signal terminal SG2 is directly connected to the clock signal line through a via or a connecting line.

[0053] refer to Figure 3As shown, the shift register 101' includes a plurality of transistors. When the shift register 101' performs forward scanning, the DC signal DIR1 is a high level signal and the DC signal DIR2 is a low level signal; conversely, when the shift register 101' performs reverse scanning, the DC signal DIR1 is a low level signal and the DC signal DIR2 is a high level signal. Based on this, when the shift register 101' performs scanning, the transistors in the first input unit 111' will be in a negative bias state for a long time, and the corresponding transistors in the first input unit 111' will have a threshold voltage shift (Vth shift); or, the transistors in the second input unit 112' will be in a negative bias state for a long time, and the corresponding transistors in the second input unit 112' will have a threshold voltage shift (Vthshift). In this way, when the shift register 101' switches the scanning direction, the threshold voltage offset of the transistor may cause the shift register 101' to work abnormally, affecting the working stability and reliability of the shift register 101'; and, the long-term constant high-level DC signal will continue to leak to the first node N1. The leakage time is long, which may easily cause the shift register 101' to fail in high-temperature operation.

[0054] and Figure 2 In the example, the first clock signal CK1 will alternate between high and low levels, so the high level duty cycle of the first clock signal CK1 may be about 50%; the second clock signal CK2 will alternate between high and low levels, so the high level duty cycle of the second clock signal CK2 may be about 50%. Figure 3 Compared with the above, when the shift register 101 is scanning, the duration of the transistor in the first input unit 111 being in a negative bias state can be halved, and the corresponding threshold voltage shift (Vth shift) of the transistor in the first input unit 111 is reduced; and the duration of the transistor in the second input unit 112 being in a negative bias state can be halved, and the corresponding threshold voltage shift (Vth shift) of the transistor in the second input unit 112 is reduced. Based on this, by reducing the threshold voltage shift of the transistor, the problem of abnormal operation due to the switching of the scanning direction of the shift register can be prevented, and the working stability and reliability of the shift register 101 can be improved; and the duration of the high level of the first clock signal CK1 or the high level of the second clock signal CK2 leaking to the first node N1 can also be halved, which can improve the problem of easy failure of the shift register 101 when working at high temperatures and extend the service life of the shift register 101.

[0055] Understandably, if Figure 2 In the shift register 101 shown, the first electrical signal or the second electrical signal is a clock signal, and the other is a non-clock signal. Figure 3In comparison, the first driving circuit 100 based on the shift register 101 can reduce one DC signal transmission line, achieve a narrow frame, and improve the reliability of the shift register with forward and reverse scanning functions.

[0056] The optional shift register includes a plurality of transistors; the plurality of transistors are all N-type transistors, or the plurality of transistors are all P-type transistors. The optional shift register includes a plurality of transistors; the semiconductor layer of the transistor is an amorphous silicon semiconductor layer or an oxide semiconductor layer. Exemplarily, the N-type transistor in the shift register may be an IGZO-TFT. The P-type transistor in the shift register may be an LTPS-TFT. But it is not limited thereto.

[0057] In the present invention, the first signal end of the first input unit of the shift register provides a first electrical signal, and the second signal end of the second input unit of the shift register provides a second electrical signal. At least one of the first electrical signal and the second electrical signal is a clock signal, and at least one of the multiple clock signal lines in the first drive circuit can be reused to provide a clock signal to the first signal end or the second signal end, thereby reducing the number of signal lines of the first drive circuit, which is beneficial to the display panel to achieve a narrow frame and a full screen. In addition, the first clock signal and the second clock signal are both high-low level alternating jumps, which can reduce the time length of the transistor in the input unit in the negative bias state during the shift register scanning process, and correspondingly can reduce the threshold voltage shift (Vth shift) of the transistor in the input unit, which is beneficial to improve the working stability and reliability of the shift register; and the leakage time length of the high level of the first clock signal or the high level of the second clock signal to the first node can also be halved, thereby improving the problem of easy failure of the shift register at high temperature and extending the service life of the shift register.

[0058] Figure 4 is a schematic diagram of another shift register provided by an embodiment of the present invention. Figure 4 As shown, the optional first input unit 111 includes a first transistor M1, the gate of which is connected to the first trigger terminal IN1, and the first transistor M1 is connected between the first signal terminal SG1 and the first node N1; the second input unit 112 includes a second transistor M2, the gate of which is connected to the second trigger terminal IN2, and the second transistor M2 is connected between the second signal terminal SG2 and the first node N1.

[0059] In this embodiment, the first transistor M1 and the second transistor M2 can be both N-type transistors. Specifically, when the electrical signal provided by the first trigger terminal IN1 is at a high level, the first transistor M1 is turned on, and the first clock signal CK1 provided by the first signal terminal SG1 is written into the first node N1; conversely, when the electrical signal provided by the first trigger terminal IN1 is at a low level, the first transistor M1 is turned off. When the electrical signal provided by the second trigger terminal IN2 is at a high level, the second transistor M2 is turned on, and the second clock signal CK2 provided by the second signal terminal SG2 is written into the first node N1; conversely, when the electrical signal provided by the second trigger terminal IN2 is at a low level, the second transistor M2 is turned off. However, it is not limited to this. In other embodiments, under the premise of ensuring the normal operation of the shift register, at least one of the first transistor and the second transistor can also be selected as a P-type transistor.

[0060] like Figure 4 As shown, the optional first output unit 113 includes a third transistor M3, the gate of the third transistor M3 is connected to the first node N1, and the third transistor M3 is connected between the third signal terminal SG3 and the shift output terminal GOUT; the second output unit 114 includes a fourth transistor M4, the gate of the fourth transistor M4 is connected to the fourth signal terminal SG4, and the fourth transistor M4 is connected between the first power supply terminal VG1 and the shift output terminal GOUT.

[0061] In this embodiment, the third transistor M3 and the fourth transistor M4 are both N-type transistors. Specifically, when the potential of the first node N1 is high, the third transistor M3 is turned on, and the third clock signal CK3 provided by the third signal terminal SG3 is written into the shift output terminal GOUT; conversely, when the potential of the first node N1 is low, the third transistor M3 is turned off. When the fourth clock signal CK4 provided by the fourth signal terminal SG4 is high, the fourth transistor M4 is turned on, and the first power supply signal provided by the first power supply terminal VG1 is written into the shift output terminal GOUT; conversely, when the fourth clock signal CK4 provided by the fourth signal terminal SG4 is low, the fourth transistor M4 is turned off. Figure 4 The first power supply terminal VG1 may be a low voltage signal (VGL). However, the present invention is not limited thereto. In other embodiments, under the premise of ensuring the normal operation of the shift register, at least one of the third transistor and the fourth transistor may be a P-type transistor.

[0062] like Figure 4As shown, the optional reset unit 115 includes a fifth transistor M5 and a sixth transistor M6, the gate of the fifth transistor M5 and the gate of the sixth transistor M6 are both connected to the reset control terminal RST, the fifth transistor M5 is connected between the first power supply terminal VG1 and the first node N1, and the sixth transistor M6 is connected between the first power supply terminal VG1 and the shift output terminal GOUT; the node control unit 116 includes a seventh transistor M7, an eighth transistor M8 and a ninth transistor M9, the gate of the seventh transistor M7 is connected to the first node N1, the seventh transistor M7 is connected between the first power supply terminal VG1 and the second node N2, the gate of the eighth transistor M8 and the gate of the ninth transistor M9 are both connected to the second node N2, the eighth transistor M8 is connected between the first power supply terminal VG1 and the first node N1, and the ninth transistor M9 is connected between the first power supply terminal VG1 and the shift output terminal GOUT.

[0063] In this embodiment, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8 and the ninth transistor M9 can be selected as N-type transistors. Based on this, for any one of the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8 and the ninth transistor M9, when the potential of the gate of the transistor is high, the transistor is turned on, and the transmission path between the source and the drain of the transistor is turned on; conversely, for any one of the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8 and the ninth transistor M9, when the potential of the gate of the transistor is low, the transistor is turned off, and the transmission path between the source and the drain of the transistor is turned off. However, it is not limited to this. In other embodiments, under the premise of ensuring the normal operation of the shift register, at least one of the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor and the ninth transistor can also be selected as a P-type transistor.

[0064] like Figure 4 As shown, the optional shift register 101 further includes: a first capacitor C1 and a second capacitor C2; the first capacitor C1 is coupled between the first node N1 and the shift output terminal GOUT; the second capacitor C2 is coupled between the second node N2 and the third signal terminal SG3.

[0065] In this embodiment, the first capacitor C1 is coupled between the first node N1 and the shift output terminal GOUT. When the first node N1 is in a floating state, the potential change of the shift output terminal GOUT affects the potential change of the first node N1. Specifically, when the potential of the shift output terminal GOUT jumps from a high level to a low level, the potential of the first node N1 is pulled down; or, when the potential of the shift output terminal GOUT jumps from a low level to a high level, the potential of the first node N1 is bootstrapped.

[0066] The second capacitor C2 is coupled between the second node N2 and the third signal terminal SG3. When the second node N2 is in a floating state, the potential change of the third clock signal CK3 of the third signal terminal SG3 affects the potential change of the second node N2. Specifically, when the third clock signal CK3 jumps from a high level to a low level, the potential of the second node N2 is pulled down; or, when the third clock signal CK3 jumps from a low level to a high level, the potential of the second node N2 is bootstrapped and raised.

[0067] It can be understood that the structure of the shift register in the present invention includes but is not limited to Figure 4 For the 9T2C structure shown, relevant practitioners can reasonably design the structure of the shift register according to product requirements and application scenarios of the shift register. Other shift register structures are not described in detail in the present invention.

[0068] In this embodiment, Figure 4 The shift register 101 is taken as an example to describe its working process. Optionally, each transistor is NMOS, and the first power supply signal provided by the first power supply terminal VG1 is a low voltage signal VGL. The display panel can perform forward scanning and reverse scanning.

[0069] Figure 5 yes Figure 4 The timing diagram of the shift register performing forward scanning is shown in FIG. Figure 6 yes Figure 4 It should be noted that only the timing of one shift register of the first driving circuit is used for illustration. The forward scanning timing of the shift register is shown in FIG. Figure 5 As shown and the reverse scan timing is as Figure 6 shown.

[0070] Combination Figure 4 and Figure 5 As shown, the forward scanning process of the shift register 101 includes at least the following stages:

[0071] In the first stage t11, the electrical signal received by the first trigger terminal IN1 of the shift register 101 is a high-level signal, so that the first transistor M1 is turned on; the first clock signal CK1 provided by the first signal terminal SG1 jumps from a low level to a high level, and the potential of the first node N1 jumps from a low level to a high level, so that the third transistor M3 is turned on; the third clock signal CK3 provided by the third signal terminal SG3 is a low level, and the shift output terminal GOUT output is a low level; the electrical signal received by the second trigger terminal IN2 is a low level, so that the second transistor M2 is turned off; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is a high level, so that the fourth transistor M4 is turned on, and the low-level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0072] In the second stage t12, the electric signal received by the first trigger terminal IN1 of the shift register 101 is a low-level signal, so that the first transistor M1 is turned off, and the potential of the second trigger terminal IN2 remains at a low level to keep the second transistor M2 turned off, then the first node N1 is in a floating state, and the potential of the first node N1 maintains the high level of the first stage t11, so that the third transistor M3 remains turned on; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is at a low level, so that the fourth transistor M4 is turned off; the third clock signal CK3 provided by the third signal terminal SG3 is at a high level, then the shift output terminal GOUT jumps from the low level of the first stage t11 to a high level output; the low level of the shift output terminal GOUT jumps to a high level signal, and after being coupled through the first capacitor C1, the first node N1 is lifted based on the bootstrap effect of the first capacitor C1.

[0073] In the third stage t13, the first transistor M1 remains turned off; the electrical signal received by the second trigger terminal IN2 of the shift register 101 is a high-level signal, so that the second transistor M2 is turned on, and the second clock signal CK2 provided by the second signal terminal SG2 jumps from a high level to a low level, then the potential of the first node N1 is pulled down and reduced, so that the third transistor M3 is switched from on to off; before the third transistor M3 is turned off, the low level of the third clock signal CK3 is written to the shift output terminal GOUT; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is a high level, so that the fourth transistor M4 is turned on, and the low level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0074] As described above, the shift output terminal GOUT of the shift register 101 outputs a high level signal in the second stage t12, and the high level signal is a valid pulse signal for scanning and driving the corresponding row of sub-pixels. The shift register 101 keeps outputting a low level signal in and after the third stage t13 until the first trigger terminal IN1 receives a high level signal again.

[0075] Combination Figure 4 and Figure 6 As shown, the reverse scanning process of the shift register 101 includes at least the following stages:

[0076] In the first stage t21, the electrical signal received by the second trigger terminal IN2 of the shift register 101 is a high-level signal, so that the second transistor M2 is turned on; the second clock signal CK2 provided by the second signal terminal SG2 jumps from a low level to a high level, and the potential of the first node N1 jumps from a low level to a high level, so that the third transistor M3 is turned on; the third clock signal CK3 provided by the third signal terminal SG3 is a low level, and the shift output terminal GOUT output is a low level; the electrical signal received by the first trigger terminal IN1 is a low level, so that the first transistor M1 is turned off; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is a high level, so that the fourth transistor M4 is turned on, and the low-level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0077] In the second stage t22, the electric signal received by the second trigger terminal IN2 of the shift register 101 is a low-level signal, so that the second transistor M2 is turned off; the potential of the first trigger terminal IN1 remains at a low level to turn off the first transistor M1, and the first node N1 is in a floating state, and the potential of the first node N1 maintains the high level of the first stage t21, so that the third transistor M3 remains turned on; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is at a low level, so that the fourth transistor M4 is turned off; the third clock signal CK3 provided by the third signal terminal SG3 is at a high level, and the shift output terminal GOUT jumps from the low level of the first stage t21 to a high level output; the low level of the shift output terminal GOUT jumps to a high level signal, and after being coupled through the first capacitor C1, the first node N1 is lifted based on the bootstrap effect of the first capacitor C1.

[0078] In the third stage t23, the second transistor M2 remains turned off; the electrical signal received by the first trigger terminal IN1 of the shift register 101 is a high-level signal, so that the first transistor M1 is turned on, and the first clock signal CK1 provided by the first signal terminal SG1 jumps from a high level to a low level, then the potential of the first node N1 is pulled down and reduced, so that the third transistor M3 is switched from on to off; before the third transistor M3 is turned off, the low level of the third clock signal CK3 is written to the shift output terminal GOUT; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is a high level, so that the fourth transistor M4 is turned on, and the low level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0079] As described above, the shift output terminal GOUT of the shift register 101 outputs a high level signal in the second stage t22, and the high level signal is a valid pulse signal for scanning and driving the corresponding row of sub-pixels. The shift register 101 keeps outputting a low level signal in and after the third stage t23 until the second trigger terminal IN2 receives a high level signal again.

[0080] Based on this, the display panel can perform forward scanning and reverse scanning, and can switch between forward scanning and reverse scanning.

[0081] In this embodiment, the first electrical signal provided by the first signal terminal SG1 is the first clock signal CK1, and the second electrical signal provided by the second signal terminal SG2 is the second clock signal CK2, which does not affect the normal output of the shift register 101. Therefore, the original clock signal line of the first drive circuit can be used to provide the first clock signal CK1 and the second clock signal CK2 for the shift register 101, so that the first drive circuit does not need to set up additional SG1 signal lines and SG2 signal lines, which is conducive to achieving a narrow frame. On the other hand, the duty cycle of the first clock signal CK1 can be about 50%, and the duty cycle of the second clock signal CK2 can be about 50%, so the device bias time of the first transistor M1 can be halved, and the device bias time of the second transistor M2 can be halved, and the corresponding threshold voltage shift Vth shift of the first transistor M1 and the second transistor M2 is weakened, so that the reliability of the shift register 101 can be improved. In addition, the duration of the first clock signal CK1 leaking into the high level to the first node N1 is halved, and the duration of the second clock signal CK2 leaking into the high level to the first node N1 is halved, which can improve the problem of the shift register 101 being prone to failure when working at high temperatures.

[0082] It should be noted that the input end of the first transistor M1 is connected to the first signal end SG1, the input end of the second transistor M2 is connected to the second signal end SG2, the first signal end SG1 receives the first clock signal CK1, the second signal end SG2 receives the second clock signal CK2, the first clock signal CK1 is different from the second clock signal CK2, so the clock signal line connected to the first signal end SG1 is different from the clock signal line connected to the second signal end SG2. Based on this, when the first transistor M1 or the second transistor M2 is turned on, the clock signal line connected to the first signal end SG1 or the clock signal line connected to the second signal end SG2 can directly charge the first node N1, ensuring that the first node N1 can have a longer charging time, thereby ensuring that the third transistor M3 can have a longer turn-on time, so as to enhance the charging effect of the shift output end GOUT. It is found through testing that the output duration of the high level of the shift output end GOUT (reference t12 or t22) is greater than TA / 3 and less than TA / 2, where TA is the period of the first clock signal CK1.

[0083] The optional first driving circuit includes a multi-stage shift register circuit and Y clock signal lines, Y≥4; the shift register circuit includes Ya cascaded shift registers, and the third signal terminals of the Ya shift registers are respectively connected to Ya clock signal lines among the Y clock signal lines, Y≥Ya≥4. Among the optional Y clock signal lines, the clock signals provided by any two clock signal lines have the same frequency but different phases. The optional Y clock signal lines include the 1st clock signal line to the Yth clock signal line; the first driving circuit includes a forward scanning mode and a reverse scanning mode; in the forward scanning mode, the phase of the clock signal provided by the i-th clock signal line is earlier than the phase of the clock signal provided by the (i+1)th clock signal line, and the phase difference between the two is a. H; In the reverse scanning mode, the phase of the clock signal provided by the (i+1)th clock signal line is earlier than the phase of the clock signal provided by the i-th clock signal line, and the phase difference between the two is b H; 1≤i≤Y, a and b are both positive integers, and H is equal to the scanning time of a row of sub-pixels in the display panel. The first trigger end of the n-th shift register can be connected to the shift output end of the (nm)-th shift register; the second trigger end of the n-th shift register is connected to the shift output end of the (n+m)-th shift register; n is a positive integer, and m is an integer greater than or equal to 2.

[0084] In this embodiment, the first driving circuit can be a double-sided driving circuit or a single-sided driving circuit. For the first driving circuit, its single-sided structure can be a 4-phase ASG structure or a 6-phase ASG structure.

[0085] It is understood that the clock signal provided by the same clock signal line during forward scanning may be different from the clock signal provided during reverse scanning. ” is the multiplication sign.

[0086] Figure 7 is a schematic diagram of a first driving circuit provided by an embodiment of the present invention, such as Figure 7As shown, the single-side structure of the first driving circuit is a 4-phase ASG structure. The optional Y clock signal lines include the first clock signal line CKL1 to the fourth clock signal line CKL4, and the shift register circuit 121 includes four cascaded shift registers 101; the first driving circuit 100 includes a first circuit group, and the first circuit group includes at least one shift register circuit 121; the shift register circuit 121 in the first circuit group satisfies the following conditions: the first clock signal line CKL1 is respectively connected to the third signal terminal SG3 of the first-stage shift register ASG(1), the first signal terminal SG1 of the second-stage shift register ASG(2), the fourth signal terminal SG4 of the third-stage shift register ASG(3) and the second signal terminal SG2 of the fourth-stage shift register ASG(4); the second clock signal line CKL2 is respectively connected to the second signal terminal SG2 of the first-stage shift register ASG(1), the first signal terminal SG1 of the second-stage shift register ASG(2), the fourth signal terminal SG4 of the third-stage shift register ASG(3) and the second signal terminal SG2 of the fourth-stage shift register ASG(4); The third clock signal line CKL3 is respectively connected to the fourth signal terminal SG4 of the first-stage shift register ASG(1), the second signal terminal SG2 of the second-stage shift register ASG(2), the third signal terminal SG3 of the third-stage shift register ASG(3) and the first signal terminal SG1 of the fourth-stage shift register ASG(4); the fourth clock signal line CKL4 is respectively connected to the first signal terminal SG1 of the first-stage shift register ASG(1), the fourth signal terminal SG4 of the second-stage shift register ASG(2), the second signal terminal SG2 of the third-stage shift register ASG(3) and the third signal terminal SG3 of the fourth-stage shift register ASG(4). The optional first driving circuit 100 includes a forward scanning mode and a reverse scanning mode; in the forward scanning mode, the phase of the clock signal provided by the i-th clock signal line is earlier than the phase of the clock signal provided by the (i+1)-th clock signal line, and the phase difference between the two is H; in the reverse scanning mode, the phase of the clock signal provided by the (i+1)-th clock signal line is earlier than the phase of the clock signal provided by the i-th clock signal line, and the phase difference between the two is H; 1≤i≤3,2 H is equal to the effective pulse width outputted from the shift output terminal GOUT of the shift register 101 .

[0087] In this embodiment, the four cascaded shift registers 101 in the first driving circuit 100 constitute a shift register circuit 121. The first driving circuit 100 includes a multi-stage shift register circuit 121. Figure 7Only the first stage shift register circuit 121 / 1 and the second stage shift register circuit 121 / 2 in the first driving circuit 100 are shown, and the third stage and subsequent stage shift register circuits in the first driving circuit 100 are not shown. A first circuit group (not shown) includes one or more shift register circuits 121 .

[0088] The multiple stages of shift registers 101 in the first driving circuit 100 are marked as ASG1, ASG2, ASG3, ASG4, ASG5, ASG6, ... in sequence, and the nth stage shift register 101 is marked as ASG n . The first driving circuit 100 includes a forward scanning mode and a reverse scanning mode. Specifically, the forward scanning mode can be scanning along the direction from ASG1 to ASG6, and correspondingly, the reverse scanning mode is scanning along the direction from ASG6 to ASG1. Here, shift register ASG1 to shift register ASG4 constitute the first-stage shift register circuit 121 / 1, shift register ASG5 to shift register ASG8 constitute the second-stage shift register circuit 121 / 2, and so on. For any shift register circuit 121, the 4-stage shift register 101 is sequentially connected in a cascade relationship to be the first-stage shift register ASG(1) to the fourth-stage shift register ASG(4) of the shift register circuit 121. Therefore, shift register ASG1 to shift register ASG4 are respectively the first-stage shift register ASG(1) to the fourth-stage shift register ASG(4) in the first-stage shift register circuit 121 / 1; shift register ASG5 to shift register ASG8 are respectively the first-stage shift register ASG(1) to the fourth-stage shift register ASG(4) in the second-stage shift register circuit 121 / 2; and so on.

[0089] The first driving circuit 100 includes 4 or more clock signal lines, including at least a first clock signal line CKL1, a second clock signal line CKL2, a third clock signal line CKL3 and a fourth clock signal line CKL4. Each clock signal line is used to provide a clock signal. The clock signals provided by any two clock signal lines have the same frequency but different phases.

[0090] Figure 8 yes Figure 7 FIG. 4 is a schematic diagram of a clock signal of the first driving circuit in the forward scanning mode. Figure 8 As shown, in the forward scanning mode, the phase of the clock signal provided by the first clock signal line CKL1 is earlier than the phase of the clock signal provided by the second clock signal line CKL2, and the phase difference between the two is 1 H; the phase of the clock signal provided by the second clock signal line CKL2 is earlier than the phase of the clock signal provided by the third clock signal line CKL3, and the phase difference between the two is 1 H; the phase of the clock signal provided by the third clock signal line CKL3 is earlier than the phase of the clock signal provided by the fourth clock signal line CKL4, and the phase difference between the two is 1 H; the phase of the clock signal provided by the fourth clock signal line CKL4 is earlier than the phase of the clock signal provided by the first clock signal line CKL1, and the phase difference between the two is 1 H.

[0091] Fig. 9 yes Figure 7 FIG. 4 is a schematic diagram of a clock signal of the first driving circuit in the reverse scanning mode. Fig. 9 As shown, in the reverse scanning mode, the phase of the clock signal provided by the fourth clock signal line CKL4 is earlier than the phase of the clock signal provided by the third clock signal line CKL3, and the phase difference between the two is 1 H; the phase of the clock signal provided by the third clock signal line CKL3 is earlier than the phase of the clock signal provided by the second clock signal line CKL2, and the phase difference between the two is 1 H; The phase of the clock signal provided by the second clock signal line CKL2 is earlier than the phase of the clock signal provided by the first clock signal line CKL1, and the phase difference between the two is 1 H; The phase of the clock signal provided by the first clock signal line CKL1 is earlier than the phase of the clock signal provided by the fourth clock signal line CKL4, and the phase difference between the two is 1 H.

[0092] like Figure 7 As shown, the first trigger terminal IN1 of the nth shift register 101 can be connected to the shift output terminal GOUT of the (n-2)th shift register 101; the second trigger terminal IN2 of the nth shift register 101 is connected to the shift output terminal GOUT of the (n+2)th shift register 101. For the case where n is less than or equal to 2, that is, including the shift register ASG1 and the shift register ASG2, the signal received by the first trigger terminal IN1 of the two can be directly from the STV signal line, for example, the STV1 signal line directly provides an electrical signal to the first trigger terminal IN1 of the first-stage shift register ASG1, and the STV2 signal line directly provides an electrical signal to the first trigger terminal IN1 of the second-stage shift register ASG2. But not limited to this, in other embodiments, two stages of dummy shift registers may be optionally provided on the shift register ASG1, respectively marked as dummy-ASG1 and dummy-ASG2, dummy-ASG1 provides an electrical signal to the first trigger terminal IN1 of the first stage shift register ASG1, and dummy-ASG2 provides an electrical signal to the first trigger terminal IN1 of the second stage shift register ASG2.

[0093] Similarly, the first driving circuit 100 includes X stages of shift registers, and the last two stages of shift registers are ASG X-1 and ASG X , optional ASG X-1 and ASG X The signal received by the second trigger terminal IN2 can come directly from the STV signal line, for example, the STV3 signal line directly feeds the (X-1)th stage shift register ASG. X-1 The second trigger terminal IN2 provides an electrical signal, and the STV4 signal line directly supplies the X-th stage shift register ASG X The second trigger terminal IN2 provides an electrical signal. However, it is not limited to this. In other embodiments, the shift register ASG may also be selected. X There are two stages of dummy shift registers, marked as dummy-ASG3 and dummy-ASG4, respectively. Dummy-ASG3 is used for the (X-1)th stage shift register ASG X-1 The second trigger terminal IN2 provides an electrical signal to dummy-ASG4 to the X-th stage shift register ASG X The second trigger terminal IN2 provides an electrical signal.

[0094] When the first driving circuit 100 performs forward scanning or reverse scanning, the working timing of the first-stage shift register ASG(1) of any shift register circuit 121 is as follows: the first clock signal CK1 received by the first signal terminal SG1 is derived from the fourth clock signal line CKL4, the second clock signal CK2 received by the second signal terminal SG2 is derived from the second clock signal line CKL2, the third clock signal CK3 received by the third signal terminal SG3 is derived from the first clock signal line CKL1, and the fourth clock signal CK4 received by the fourth signal terminal SG4 is derived from the third clock signal line CKL3. For example, the working timing of the first-stage shift register ASG(1), i.e., ASG5(1) in the second-stage shift register circuit 121 / 2 in the forward scanning mode can be referred to. Figure 5 As shown, the operating timing of ASG5(1) in reverse scan mode can be referred to Figure 6 No further details will be given here.

[0095] The operating timing of the second-stage shift register ASG(2) of any shift register circuit 121 is as follows: the first clock signal CK1 received by the first signal terminal SG1 is derived from the first clock signal line CKL1, the second clock signal CK2 received by the second signal terminal SG2 is derived from the third clock signal line CKL3, the third clock signal CK3 received by the third signal terminal SG3 is derived from the second clock signal line CKL2, and the fourth clock signal CK4 received by the fourth signal terminal SG4 is derived from the fourth clock signal line CKL4.

[0096] The operating timing of the third-stage shift register ASG(3) of any shift register circuit 121 is as follows: the first clock signal CK1 received by the first signal terminal SG1 is derived from the second clock signal line CKL2, the second clock signal CK2 received by the second signal terminal SG2 is derived from the fourth clock signal line CKL4, the third clock signal CK3 received by the third signal terminal SG3 is derived from the third clock signal line CKL3, and the fourth clock signal CK4 received by the fourth signal terminal SG4 is derived from the first clock signal line CKL1.

[0097] The operating timing of the 4th-stage shift register ASG(4) of any shift register circuit 121 is as follows: the first clock signal CK1 received by the first signal terminal SG1 is derived from the 3rd clock signal line CKL3, the second clock signal CK2 received by the second signal terminal SG2 is derived from the 1st clock signal line CKL1, the third clock signal CK3 received by the third signal terminal SG3 is derived from the 4th clock signal line CKL4, and the fourth clock signal CK4 received by the fourth signal terminal SG4 is derived from the 2nd clock signal line CKL2.

[0098] In this embodiment, for the unilateral 4-phase ASG structure of the first driving circuit 100, the existing clock signal line of the first driving circuit 100 is used to multiplex the first clock signal CK1 to the first signal terminal SG1 and the second clock signal CK2 to the second signal terminal SG2. The shift register 101 can output normally and the first driving circuit 100 can realize forward and reverse scanning. Figure 3 In comparison, two DC signal lines are reduced; and the device bias time of either the first transistor M1 or the second transistor M2 is halved, and the severity of Vth shift is reduced, which can improve the output stability, reliability and trustworthiness of the shift register 101; in addition, the high-level leakage time of the first node N1 is halved, which can improve the problem of the shift register being prone to failure when working at high temperatures.

[0099] Fig.10 is a schematic diagram of another first driving circuit provided by an embodiment of the present invention, such as Fig.10As shown, the single-side structure of the first driving circuit 300 is a 6-phase ASG structure. The optional Y clock signal lines include the first clock signal line CKL1 to the sixth clock signal line CKL6, and the shift register circuit 310 includes six cascaded shift registers 101; the first driving circuit 300 includes a second circuit group, and the second circuit group includes at least one shift register circuit 310; the shift register circuit 310 in the second circuit group meets the following conditions: the first clock signal line CKL1 is respectively connected to the third signal terminal SG3 of the first-stage shift register ASG(1), the first signal terminal SG1 of the third-stage shift register ASG(3), and the fourth-stage shift register ASG(4) The first clock signal line CKL2 is connected to the second signal terminal SG2 of the first shift register ASG(1), the third signal terminal SG3 of the second shift register ASG(2), the first signal terminal SG1 of the fourth shift register ASG(4) and the fourth signal terminal SG4 of the fifth shift register ASG(5); the third clock signal line CKL3 is connected to the second signal terminal SG2 of the second shift register ASG(2), the third signal terminal SG3 of the second shift register ASG(2), the first signal terminal SG1 of the fourth shift register ASG(4) and the fourth signal terminal SG4 of the fifth shift register ASG(5); the third clock signal line CKL4 is connected to the second signal terminal SG2 of the second shift register ASG(2), the third signal terminal SG3 of the third shift register ASG( The fourth clock signal line CKL4 is respectively connected to the fourth signal terminal SG4 of the first-stage shift register ASG(1), the second signal terminal SG2 of the third-stage shift register ASG(3), the third signal terminal SG3 of the fourth-stage shift register ASG(4) and the first signal terminal SG1 of the sixth-stage shift register ASG(6); the fifth clock signal line CKL5 is respectively connected to the fourth signal terminal SG4 of the first-stage shift register ASG(1), the second signal terminal SG2 of the third-stage shift register ASG(3), the third signal terminal SG3 of the fourth-stage shift register ASG(4) and the first signal terminal SG1 of the sixth-stage shift register ASG(6); the fifth clock signal line CKL6 is respectively connected to the fourth signal terminal SG4 of the first-stage shift register ASG(1), the second signal terminal SG2 of the third-stage shift register ASG(3), the third signal terminal SG3 of the fourth-stage shift register ASG(4) and the first signal terminal SG1 of the sixth-stage shift register ASG(6); the fifth clock signal line CKL7 is respectively connected to the fourth signal terminal SG4 of the first-stage shift register ASG(1), the second signal terminal SG2 of the third-stage shift register ASG(3), the third signal terminal SG3 of the fourth-stage shift register ASG(4) and the first signal terminal SG1 of the sixth-stage shift register ASG(6); the fifth clock signal line CKL8 is respectively connected to the fourth signal terminal SG4 of the first-stage shift register ASG(1), the second signal terminal SG2 of the third-stage shift register ASG(3), the third signal terminal SG3 of the fourth-stage shift register ASG(4) and the first signal terminal SG1 of the sixth-stage shift register ASG(6); the fifth clock signal line CKL9 is respectively connected to the fourth signal terminal SG4 of the first-stage shift register ASG(1), the second signal terminal SG2 of the third-stage shift register ASG(3), the third signal terminal SG3 of the fourth The sixth clock signal line CKL6 is connected to the first signal terminal SG1 of the second-stage shift register ASG(2), the fourth signal terminal SG4 of the third-stage shift register ASG(3), the second signal terminal SG2 of the fifth-stage shift register ASG(5) and the third signal terminal SG3 of the sixth-stage shift register ASG(6). The optional first driving circuit 300 includes a forward scanning mode and a reverse scanning mode; in the forward scanning mode, the phase of the clock signal provided by the i-th clock signal line is earlier than the phase of the clock signal provided by the (i+1)-th clock signal line, and the phase difference between the two is H; in the reverse scanning mode, the phase of the clock signal provided by the (i+1)-th clock signal line is earlier than the phase of the clock signal provided by the i-th clock signal line, and the phase difference between the two is H; 1≤i≤5,3 H is equal to the effective pulse width outputted from the shift output terminal GOUT of the shift register 101 .

[0100] In this embodiment, the six cascaded shift registers 101 in the first driving circuit 300 constitute a shift register circuit 310. The first driving circuit 300 includes a multi-stage shift register circuit 310. Fig.10 Only the first stage shift register circuit 310 / 1 and the second stage shift register circuit 310 / 2 in the first driving circuit 300 are shown, and the third stage and subsequent stage shift register circuits in the first driving circuit 300 are not shown. A second circuit group (not shown) includes one or more shift register circuits 310 .

[0101] The multiple stages of shift registers 101 in the first driving circuit 300 are marked as ASG1, ASG2, ASG3, ASG4, ASG5, ASG6, ASG7, ASG8, ASG9, ... in sequence, and the nth stage shift register 101 is marked as ASG n The first driving circuit 300 includes a forward scanning mode and a reverse scanning mode. Specifically, the forward scanning mode can scan along the direction from ASG1 to ASG9, and correspondingly, the reverse scanning mode scans along the direction from ASG9 to ASG1. Here, the shift registers ASG1 to ASG6 constitute the first stage shift register circuit 310 / 1, and the shift registers ASG7 to ASG 12 The second-stage shift register circuit 310 / 2 is formed, and so on. For any shift register circuit 310, the six-stage shift register 101 is sequentially connected to the first-stage shift register ASG(1) to the sixth-stage shift register ASG(6) of the shift register circuit 310 in a cascade relationship. Therefore, the shift registers ASG1 to ASG6 are sequentially the first-stage shift register ASG(1) to the sixth-stage shift register ASG(6) in the first-stage shift register circuit 310 / 1; the shift registers ASG7 to ASG6 are sequentially the first-stage shift register ASG(1) to the sixth-stage shift register ASG(6) in the first-stage shift register circuit 310 / 1; 12 The order is from the 1st stage shift register ASG(1) to the 6th stage shift register ASG(6) in the 2nd stage shift register circuit 310 / 2, and so on.

[0102] The first driving circuit 300 includes 6 or more clock signal lines, including at least the first clock signal line CKL1, the second clock signal line CKL2, the third clock signal line CKL3, the fourth clock signal line CKL4, the fifth clock signal line CKL5 and the sixth clock signal line CKL6. Each clock signal line is used to provide a clock signal. The clock signals provided by any two clock signal lines have the same frequency but different phases.

[0103] Fig.11 yes Fig.10FIG. 4 is a schematic diagram of a clock signal of the first driving circuit in the forward scanning mode. Fig.11 As shown, in the forward scanning mode, the phase of the clock signal provided by the first clock signal line CKL1 is earlier than the phase of the clock signal provided by the second clock signal line CKL2, and the phase difference between the two is H; the phase of the clock signal provided by the second clock signal line CKL2 is earlier than the phase of the clock signal provided by the third clock signal line CKL3, and the phase difference between the two is H; the phase of the clock signal provided by the third clock signal line CKL3 is earlier than the phase of the clock signal provided by the fourth clock signal line CKL4, and the phase difference between the two is H; the phase of the clock signal provided by the fourth clock signal line CKL4 is earlier than the phase of the clock signal provided by the fifth clock signal line CKL5, and the phase difference between the two is H; the phase of the clock signal provided by the fifth clock signal line CKL5 is earlier than the phase of the clock signal provided by the sixth clock signal line CKL6, and the phase difference between the two is H; the phase of the clock signal provided by the sixth clock signal line CKL6 is earlier than the phase of the clock signal provided by the first clock signal line CKL1, and the phase difference between the two is H. A phase difference between a phase of a clock signal provided by the i-th clock signal line and a phase of a clock signal provided by the (i+1)-th clock signal line may be less than or equal to H.

[0104] Fig.12 yes Fig.10 FIG. 4 is a schematic diagram of a clock signal of the first driving circuit in the reverse scanning mode. Fig.12 As shown, in the reverse scanning mode, the phase of the clock signal provided by the 6th clock signal line CKL6 is earlier than the phase of the clock signal provided by the 5th clock signal line CKL5, and the phase difference between the two is H; the phase of the clock signal provided by the 5th clock signal line CKL5 is earlier than the phase of the clock signal provided by the 4th clock signal line CKL4, and the phase difference between the two is H; the phase of the clock signal provided by the 4th clock signal line CKL4 is earlier than the phase of the clock signal provided by the 3rd clock signal line CKL3, and the phase difference between the two is H; the phase of the clock signal provided by the 3rd clock signal line CKL3 is earlier than the phase of the clock signal provided by the 2nd clock signal line CKL2, and the phase difference between the two is H; the phase of the clock signal provided by the 2nd clock signal line CKL2 is earlier than the phase of the clock signal provided by the 1st clock signal line CKL1, and the phase difference between the two is H; the phase of the clock signal provided by the 1st clock signal line CKL1 is earlier than the phase of the clock signal provided by the 6th clock signal line CKL6, and the phase difference between the two is H.

[0105] like Fig.10As shown, the first trigger terminal IN1 of the optional n-th shift register 101 is connected to the shift output terminal GOUT of the (n-3)-th shift register 101; the second trigger terminal IN2 of the n-th shift register 101 is connected to the shift output terminal GOUT of the (n+3)-th shift register 101. For the case where n is less than or equal to 3, i.e., including the shift registers ASG1 to ASG3, the signal received by the first trigger terminal IN1 of the three optional shift registers can be directly from the STV signal line, for example, the STV1 signal line directly provides an electrical signal to the first trigger terminal IN1 of the first-stage shift register ASG1, the STV2 signal line directly provides an electrical signal to the first trigger terminal IN1 of the second-stage shift register ASG2, and the STV3 signal line directly provides an electrical signal to the first trigger terminal IN1 of the third-stage shift register ASG3. But not limited to this, in other embodiments, three stages of dummy shift registers may be optionally provided on the shift register ASG1, which are respectively marked as dummy-ASG1 to dummy-ASG3, dummy-ASG1 provides an electrical signal to the first trigger terminal IN1 of the first stage shift register ASG1, dummy-ASG2 provides an electrical signal to the first trigger terminal IN1 of the second stage shift register ASG2, and dummy-ASG3 provides an electrical signal to the first trigger terminal IN1 of the third stage shift register ASG3.

[0106] Similarly, the first driving circuit 100 includes X-stage shift registers, and the last three stages of shift registers are ASG X-2 、ASG X-1 and ASG X , optional ASG X-2 、ASG X-1 and ASG X The signal received by the second trigger terminal IN2 can come directly from the STV signal line, for example, the STV4 signal line directly feeds the (X-2)th stage shift register ASG. X-2 The second trigger terminal IN2 provides an electrical signal, and the STV5 signal line directly supplies the (X-1)th stage shift register ASG X-1 The second trigger terminal IN2 provides an electrical signal, and the STV6 signal line directly supplies the X-th stage shift register ASG X The second trigger terminal IN2 provides an electrical signal. However, it is not limited to this. In other embodiments, the shift register ASG may also be selected. X There are three stages of dummy shift registers, marked as dummy-ASG4 and dummy-ASG6, respectively. Dummy-ASG4 is for the (X-2)th stage shift register ASG X-2 The second trigger terminal IN2 provides an electrical signal to dummy-ASG5 to the (X-1)th stage shift register ASG X-1The second trigger terminal IN2 provides an electrical signal to dummy-ASG6 to the X-th stage shift register ASG X The second trigger terminal IN2 provides an electrical signal.

[0107] When the first driving circuit 300 performs forward scanning or reverse scanning, the working timing of the first-stage shift register ASG(1) of any shift register circuit 310 is as follows: the first clock signal CK1 received by the first signal terminal SG1 is derived from the fifth clock signal line CKL5, the second clock signal CK2 received by the second signal terminal SG2 is derived from the second clock signal line CKL2, the third clock signal CK3 received by the third signal terminal SG3 is derived from the first clock signal line CKL1, and the fourth clock signal CK4 received by the fourth signal terminal SG4 is derived from the fourth clock signal line CKL4.

[0108] The operating timing of the second-stage shift register ASG(2) of any shift register circuit 310 is as follows: the first clock signal CK1 received by the first signal terminal SG1 is derived from the sixth clock signal line CKL6, the second clock signal CK2 received by the second signal terminal SG2 is derived from the third clock signal line CKL3, the third clock signal CK3 received by the third signal terminal SG3 is derived from the second clock signal line CKL2, and the fourth clock signal CK4 received by the fourth signal terminal SG4 is derived from the fifth clock signal line CKL5.

[0109] The operating timing of the third-stage shift register ASG(3) of any shift register circuit 310 is as follows: the first clock signal CK1 received by the first signal terminal SG1 is derived from the first clock signal line CKL1, the second clock signal CK2 received by the second signal terminal SG2 is derived from the fourth clock signal line CKL4, the third clock signal CK3 received by the third signal terminal SG3 is derived from the third clock signal line CKL3, and the fourth clock signal CK4 received by the fourth signal terminal SG4 is derived from the sixth clock signal line CKL6.

[0110] The operating timing of the 4th-stage shift register ASG(4) of any shift register circuit 310 is as follows: the first clock signal CK1 received by the first signal terminal SG1 is derived from the second clock signal line CKL2, the second clock signal CK2 received by the second signal terminal SG2 is derived from the fifth clock signal line CKL5, the third clock signal CK3 received by the third signal terminal SG3 is derived from the fourth clock signal line CKL4, and the fourth clock signal CK4 received by the fourth signal terminal SG4 is derived from the first clock signal line CKL1.

[0111] The operating timing of the fifth-stage shift register ASG(5) of any shift register circuit 310 is as follows: the first clock signal CK1 received by the first signal terminal SG1 is derived from the third clock signal line CKL3, the second clock signal CK2 received by the second signal terminal SG2 is derived from the sixth clock signal line CKL6, the third clock signal CK3 received by the third signal terminal SG3 is derived from the fifth clock signal line CKL5, and the fourth clock signal CK4 received by the fourth signal terminal SG4 is derived from the second clock signal line CKL2.

[0112] The operation timing of the sixth-stage shift register ASG(6) of any shift register circuit 310 is as follows: the first clock signal CK1 received by the first signal terminal SG1 is derived from the fourth clock signal line CKL4, the second clock signal CK2 received by the second signal terminal SG2 is derived from the first clock signal line CKL1, the third clock signal CK3 received by the third signal terminal SG3 is derived from the sixth clock signal line CKL6, and the fourth clock signal CK4 received by the fourth signal terminal SG4 is derived from the third clock signal line CKL3.

[0113] In this embodiment, for the unilateral 6-phase ASG structure of the first driving circuit 300, the existing clock signal line of the first driving circuit 300 is used to multiplex the first clock signal CK1 to the first signal terminal SG1 and the second clock signal CK2 to the second signal terminal SG2. The shift register 101 can output normally and the first driving circuit 300 can realize forward and reverse scanning. Figure 3 In comparison, two DC signal lines are reduced; and the device bias time of either the first transistor M1 or the second transistor M2 is halved, and the severity of Vth shift is reduced, which can improve the output stability, reliability and trustworthiness of the shift register 101; in addition, the high-level leakage time of the first node N1 is halved, which can improve the problem of the shift register being prone to failure when working at high temperatures.

[0114] For the first driving circuit 300, Figure 4 The shift register 101 is taken as an example to describe its working process. Optionally, each transistor is NMOS, and the first power supply signal provided by the first power supply terminal VG1 is a low voltage signal VGL. The display panel can perform forward scanning and reverse scanning.

[0115] Here, only the timing of one shift register (such as ASG7(1)) of the first driving circuit 300 is used for illustration. For example, the first-stage shift register ASG(1) in the second-stage shift register circuit 310 / 2, i.e., ASG7(1), receives the first clock signal CK1 at the first signal terminal SG1 from the fifth clock signal line CKL5, receives the second clock signal CK2 at the second signal terminal SG2 from the second clock signal line CKL2, receives the third clock signal CK3 at the third signal terminal SG3 from the first clock signal line CKL1, and receives the fourth clock signal CK4 at the fourth signal terminal SG4 from the fourth clock signal line CKL4. Based on this, Fig.13 This is a timing diagram of the forward scan of the shift register (ASG7(1)) in the first drive circuit based on the unilateral 6-phase ASG structure. Fig.14 FIG. 1 is a timing diagram of reverse scanning of the shift register (ASG7(1)) in the first driving circuit based on the unilateral 6-phase ASG structure.

[0116] Combination Figure 4 and Fig.13 As shown, the forward scanning process of the shift register 101 includes at least the following stages:

[0117] In the first stage t31, the electrical signal received by the first trigger terminal IN1 of the shift register 101 is a high-level signal, so that the first transistor M1 is turned on; the first clock signal CK1 provided by the first signal terminal SG1 jumps from a low level to a high level, and the potential of the first node N1 jumps from a low level to a high level, so that the third transistor M3 is turned on; the third clock signal CK3 provided by the third signal terminal SG3 is a low level, and the shift output terminal GOUT outputs a low level; the electrical signal received by the second trigger terminal IN2 is a low level, so that the second transistor M2 is turned off; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is a high level, so that the fourth transistor M4 is turned on, and the low-level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0118] In the second stage t32, the electric signal received by the first trigger terminal IN1 of the shift register 101 is a low-level signal, so that the first transistor M1 is turned off, and the potential of the second trigger terminal IN2 remains at a low level to keep the second transistor M2 turned off, then the first node N1 is in a floating state, and the potential of the first node N1 maintains the high level of the first stage t31, so that the third transistor M3 remains turned on; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is at a low level, so that the fourth transistor M4 is turned off; the third clock signal CK3 provided by the third signal terminal SG3 is at a high level, then the shift output terminal GOUT jumps from the low level of the first stage t31 to a high level output; the low level of the shift output terminal GOUT jumps to a high level signal, and after being coupled through the first capacitor C1, the first node N1 is lifted based on the bootstrap effect of the first capacitor C1.

[0119] In the third stage t33, the first transistor M1 remains turned off; the electrical signal received by the second trigger terminal IN2 of the shift register 101 is a high-level signal, so that the second transistor M2 is turned on, and the second clock signal CK2 provided by the second signal terminal SG2 jumps from a high level to a low level, then the potential of the first node N1 is pulled down and reduced, so that the third transistor M3 is switched from on to off; before the third transistor M3 is turned off, the low level of the third clock signal CK3 is written to the shift output terminal GOUT; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is a high level, so that the fourth transistor M4 is turned on, and the low level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0120] As described above, the shift output terminal GOUT of the shift register 101 outputs a high level signal in the second stage t32, and the high level signal is a valid pulse signal for scanning and driving the corresponding row of sub-pixels. The shift register 101 keeps outputting a low level signal in and after the third stage t33 until the first trigger terminal IN1 receives a high level signal again.

[0121] Combination Figure 4 and Fig.14 As shown, the reverse scanning process of the shift register 101 includes at least the following stages:

[0122] In the first stage t41, the electrical signal received by the second trigger terminal IN2 of the shift register 101 is a high-level signal, so that the second transistor M2 is turned on; the second clock signal CK2 provided by the second signal terminal SG2 jumps from a low level to a high level, and the potential of the first node N1 jumps from a low level to a high level, so that the third transistor M3 is turned on; the third clock signal CK3 provided by the third signal terminal SG3 is a low level, and the shift output terminal GOUT output is a low level; the electrical signal received by the first trigger terminal IN1 is a low level, so that the first transistor M1 is turned off; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is a high level, so that the fourth transistor M4 is turned on, and the low-level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0123] In the second stage t42, the electric signal received by the second trigger terminal IN2 of the shift register 101 is a low-level signal, so that the second transistor M2 is turned off; the potential of the first trigger terminal IN1 remains at a low level to turn off the first transistor M1, and the first node N1 is in a floating state, and the potential of the first node N1 maintains the high level of the first stage t41, so that the third transistor M3 remains turned on; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is at a low level, so that the fourth transistor M4 is turned off; the third clock signal CK3 provided by the third signal terminal SG3 is at a high level, and the shift output terminal GOUT jumps from the low level of the first stage t41 to a high level output; the low level of the shift output terminal GOUT jumps to a high level signal, and after being coupled through the first capacitor C1, the first node N1 is lifted based on the bootstrap effect of the first capacitor C1.

[0124] In the third stage t43, the second transistor M2 remains turned off; the electrical signal received by the first trigger terminal IN1 of the shift register 101 is a high-level signal, so that the first transistor M1 is turned on, and the first clock signal CK1 provided by the first signal terminal SG1 jumps from a high level to a low level, then the potential of the first node N1 is pulled down and reduced, so that the third transistor M3 is switched from on to off; before the third transistor M3 is turned off, the low level of the third clock signal CK3 is written to the shift output terminal GOUT; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is a high level, so that the fourth transistor M4 is turned on, and the low level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0125] As described above, the shift output terminal GOUT of the shift register 101 outputs a high level signal in the second stage t42, and the high level signal is a valid pulse signal for scanning and driving the corresponding row of sub-pixels. The shift register 101 keeps outputting a low level signal in and after the third stage t43 until the second trigger terminal IN2 receives a high level signal again.

[0126] Based on this, the display panel can perform forward scanning and reverse scanning, and can switch between forward scanning and reverse scanning.

[0127] In this embodiment, the first electrical signal provided by the first signal terminal SG1 is the first clock signal CK1, and the second electrical signal provided by the second signal terminal SG2 is the second clock signal CK2, which does not affect the normal output of the shift register 101. Therefore, the original clock signal line of the first drive circuit 300 can be used to provide the first clock signal CK1 and the second clock signal CK2 for the shift register 101, so that the first drive circuit 300 does not need to set up additional SG1 signal lines and SG2 signal lines, which is conducive to achieving a narrow frame. On the other hand, the duty cycle of the first clock signal CK1 can be about 50%, and the duty cycle of the second clock signal CK2 can be about 50%, so the device bias time of the first transistor M1 can be halved, and the device bias time of the second transistor M2 can be halved, and the corresponding threshold voltage shift Vth shift of the first transistor M1 and the second transistor M2 is weakened, so that the reliability of the shift register 101 can be improved. In addition, the time duration of the first clock signal CK1 leaking into the first node N1 at a high level is halved, and the time duration of the second clock signal CK2 leaking into the first node N1 at a high level is halved, which can improve the problem of the shift register 101 being prone to failure when working at high temperatures.

[0128] The first electrical signal can be a first clock signal; the second electrical signal can be a fixed voltage signal; the first driving circuit can include a forward scanning mode and a reverse scanning mode; in the forward scanning mode, the second electrical signal can be a low level signal; in the reverse scanning mode, the second electrical signal can be a high level signal.

[0129] Fig.15 is a schematic diagram of another shift register provided by an embodiment of the present invention, wherein all optional transistors are NMOS. Figure 4 The difference is that Fig.15 The first electrical signal of the first signal terminal SG1 is the first clock signal CK1, and the second electrical signal of the second signal terminal SG2 is the fixed voltage signal DIR2. Fig.15 The first driving circuit of the shift register shown has an operation mode including a forward scanning mode and a reverse scanning mode. In the forward scanning mode, the second electrical signal DIR2 is a low level signal; in the reverse scanning mode, the second electrical signal DIR2 is a high level signal.

[0130] Fig.16 yes Fig.15 The timing diagram of the shift register performing forward scanning is shown, wherein the second electrical signal DIR2 is a low-level signal vgl, and the high-level signal vgh represented by the dotted line shown in the figure is only to indicate that vgl is lower than vgh. Fig.17 yes Fig.15The timing diagram of the shift register performing reverse scanning is shown, wherein the second electrical signal DIR2 is a high-level signal vgh, and the low-level signal vgl represented by the dotted line shown in the figure is only to indicate that vgh is higher than vgl.

[0131] Combination Fig.15 and Fig.16 As shown, the forward scanning process of the shift register includes at least the following stages:

[0132] In the first stage t51, the first trigger terminal IN1 receives a high-level signal, turning on the first transistor M1; the first clock signal CK1 jumps from a low level to a high level, and the potential of the first node N1 jumps from a low level to a high level, turning on the third transistor M3; the low level of the third clock signal CK3 is output to the shift output terminal GOUT; the second transistor M2 is turned off; the high level of the fourth clock signal CK4 turns on the fourth transistor M4, and the low level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0133] In the second stage t52, the first trigger terminal IN1 receives a low-level signal, the first transistor M1 is turned off, and the second transistor M2 remains turned off, then the first node N1 is in a floating state, and the potential of the first node N1 maintains the high level of the first stage t51, so that the third transistor M3 remains turned on; the fourth transistor M4 is turned off; the high level of the third clock signal CK3 is output to the shift output terminal GOUT; the shift output terminal GOUT is outputted as a high-level signal by the low-level jump output of the first stage t51, and after coupling through the first capacitor C1, the potential of the first node N1 is raised.

[0134] In the third stage t53, the first transistor M1 remains turned off; the second trigger terminal IN2 receives a high-level signal to turn on the second transistor M2, and the second electrical signal DIR2 is a low-level signal vgl, so that the potential of the first node N1 is pulled down and the third transistor M3 is turned off; the high level of the fourth clock signal CK4 turns on the fourth transistor M4, and the low-level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0135] As described above, the shift output terminal GOUT of the shift register outputs a high level signal in the second stage t52, and the high level signal is a valid pulse signal for scanning and driving the corresponding row of sub-pixels. The shift register keeps outputting a low level signal in the third stage t53 and thereafter until the first trigger terminal IN1 receives a high level signal again.

[0136] Combination Fig.15 and Fig.17 As shown, the reverse scanning process of the shift register includes at least the following stages:

[0137] In the first stage t61, the second trigger terminal IN2 receives a high-level signal, turning on the second transistor M2, and the second electrical signal DIR2 is a high-level signal vgh, then the potential of the first node N1 jumps to a high level, turning on the third transistor M3; the low level of the third clock signal CK3 is output to the shift output terminal GOUT; the first transistor M1 is turned off; the high level of the fourth clock signal CK4 turns on the fourth transistor M4, and the low-level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0138] In the second stage t62, the second trigger terminal IN2 receives a low-level signal, turning off the second transistor M2; the first transistor M1 remains turned off, and the first node N1 is in a floating state, and the potential of the first node N1 maintains the high level of the first stage t61, so that the third transistor M3 remains turned on; the fourth transistor M4 is turned off; the high level of the third clock signal CK3 is output to the shift output terminal GOUT; the shift output terminal GOUT is outputted as a high-level signal by the low-level jump output of the first stage t61, and after being coupled through the first capacitor C1, the potential of the first node N1 is raised.

[0139] In the third stage t63, the second transistor M2 remains turned off; the first trigger terminal IN1 receives a high-level signal to turn on the first transistor M1, and the first clock signal CK1 jumps from a high level to a low level, then the potential of the first node N1 is pulled down and reduced, so that the third transistor M3 switches from on to off; before the third transistor M3 is turned off, the low level of the third clock signal CK3 is written to the shift output terminal GOUT; the high level of the fourth clock signal CK4 turns on the fourth transistor M4, and the low level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0140] As described above, the shift output terminal GOUT of the shift register outputs a high level signal in the second stage t62, and the high level signal is a valid pulse signal for scanning and driving the corresponding row of sub-pixels. The shift register keeps outputting a low level signal in and after the third stage t63 until the second trigger terminal IN2 receives a high level signal again.

[0141] Based on this, the display panel can perform forward scanning and reverse scanning, and can switch between forward scanning and reverse scanning.

[0142] In this embodiment, without affecting the normal operation of the shift register, the first signal terminal SG1 can be provided with a first clock signal by a clock signal line, and compared with the original DC signal line providing a DC signal to the first signal terminal, an additional DC signal line can be reduced, thereby achieving the effect of reducing the frame. In addition, replacing the DC signal with the AC signal of the first clock signal can improve the service life and reliability of the shift register.

[0143] The first electrical signal can be a fixed voltage signal; the second electrical signal can be a second clock signal; the first driving circuit can include a forward scanning mode and a reverse scanning mode; in the forward scanning mode, the first electrical signal can be a high level signal; in the reverse scanning mode, the first electrical signal can be a low level signal.

[0144] Fig.18 is a schematic diagram of another shift register provided by an embodiment of the present invention, wherein all optional transistors are NMOS. Figure 4 The difference is that Fig.18 The first electrical signal of the first signal terminal SG1 is a fixed voltage signal DIR1, and the second electrical signal of the second signal terminal SG2 is a second clock signal CK2. Fig.18 The first driving circuit of the shift register shown has an operation mode including a forward scanning mode and a reverse scanning mode. In the forward scanning mode, the first electrical signal DIR1 is a high level signal; in the reverse scanning mode, the first electrical signal DIR1 is a low level signal.

[0145] Fig.19 yes Fig.18 The timing diagram of the shift register performing forward scanning is shown, wherein the first electrical signal DIR1 is a high-level signal vgh, and the low-level signal vgl represented by the dotted line shown in the figure is only to indicate that vgh is higher than vgl. Fig. 20 yes Fig.18 The timing diagram of the shift register performing reverse scanning is shown, wherein the first electrical signal DIR1 is a low level signal vgl, and the high level signal vgh represented by the dotted line shown in the figure is only to indicate that vgl is lower than vgh.

[0146] Combination Fig.18 and Fig.19 As shown, the forward scanning process of the shift register includes at least the following stages:

[0147] In the first stage t71, the first trigger terminal IN1 receives a high-level signal, turning on the first transistor M1; the first electrical signal DIR1 is a high-level signal vgh, then the potential of the first node N1 jumps to a high level, turning on the third transistor M3; the low level of the third clock signal CK3 is output to the shift output terminal GOUT; the second transistor M2 is turned off; the high level of the fourth clock signal CK4 turns on the fourth transistor M4, and the low-level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0148] In the second stage t72, the first trigger terminal IN1 receives a low-level signal, the first transistor M1 is turned off, and the second transistor M2 remains turned off, then the first node N1 is in a floating state, and the potential of the first node N1 maintains the high level of the first stage t71, so that the third transistor M3 remains turned on; the fourth transistor M4 is turned off; the high level of the third clock signal CK3 is output to the shift output terminal GOUT; the shift output terminal GOUT is outputted as a high-level signal by the low-level jump of the first stage t71, and after being coupled through the first capacitor C1, the potential of the first node N1 is raised.

[0149] In the third stage t73, the first transistor M1 remains turned off; the second trigger terminal IN2 receives a high-level signal to turn on the second transistor M2, and the second clock signal CK2 jumps from a high level to a low level, then the potential of the first node N1 is pulled down to turn off the third transistor M3; the third clock signal CK3 is a low level, and the high level of the fourth clock signal CK4 turns on the fourth transistor M4, and the low-level signal VGL provided by the first power supply terminal VG1 is written into the shift output terminal GOUT.

[0150] As described above, the shift output terminal GOUT of the shift register outputs a high level signal in the second stage t72, and the high level signal is a valid pulse signal for scanning and driving the corresponding row of sub-pixels. The shift register keeps outputting a low level signal in the third stage t73 and thereafter until the first trigger terminal IN1 receives a high level signal again.

[0151] Combination Fig.18 and Fig. 20 As shown, the reverse scanning process of the shift register includes at least the following stages:

[0152] In the first stage t81, the first transistor M1 is turned off; the second trigger terminal IN2 receives a high-level signal, turning on the second transistor M2, and the second clock signal CK2 jumps from a low level to a high level, then the potential of the first node N1 jumps from a low level to a high level, turning on the third transistor M3; the low level of the third clock signal CK3 is output to the shift output terminal GOUT; the high level of the fourth clock signal CK4 turns on the fourth transistor M4, and the low level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0153] In the second stage t82, the second trigger terminal IN2 receives a low-level signal, turning off the second transistor M2; the first transistor M1 remains turned off, and the first node N1 is in a floating state, and the potential of the first node N1 maintains the high level of the first stage t81, so that the third transistor M3 remains turned on; the fourth transistor M4 is turned off; the high level of the third clock signal CK3 is output to the shift output terminal GOUT; the shift output terminal GOUT is outputted as a high-level signal by the low-level jump of the first stage t81, and after being coupled through the first capacitor C1, the potential of the first node N1 is raised.

[0154] In the third stage t83, the second transistor M2 remains turned off; the first trigger terminal IN1 receives a high-level signal to turn on the first transistor M1, and the first electrical signal DIR1 is a low-level signal vgl, so that the potential of the first node N1 is pulled down and the third transistor M3 is turned off; the high level of the fourth clock signal CK4 turns on the fourth transistor M4, and the low-level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0155] As described above, the shift output terminal GOUT of the shift register outputs a high level signal in the second stage t82, and the high level signal is a valid pulse signal for scanning and driving the corresponding row of sub-pixels. The shift register keeps outputting a low level signal in and after the third stage t83 until the second trigger terminal IN2 receives a high level signal again.

[0156] Based on this, the display panel can perform forward scanning and reverse scanning, and can switch between forward scanning and reverse scanning.

[0157] In this embodiment, without affecting the normal operation of the shift register, the second signal terminal SG2 can be provided with a second clock signal by a clock signal line, and compared with the original DC signal line providing a DC signal to the second signal terminal, an additional DC signal line can be reduced, thereby achieving the effect of reducing the frame. In addition, replacing the DC signal with the AC signal of the second clock signal can improve the service life and reliability of the shift register.

[0158] Based on the same inventive concept, an embodiment of the present invention further provides a display device, including a display panel as described in any of the above embodiments. The display panel may be an organic light-emitting display panel, a micro LED display panel, or a liquid crystal display panel, but is not limited thereto. Fig.21 4 is a schematic diagram of a display device provided by an embodiment of the present invention, and the display device can be optionally applied to an electronic device 400 such as a smart phone, a tablet computer, and a car display screen. It can be understood that any of the above embodiments only provide partial examples or partial structures of the display panel, and the display panel in actual application also includes other structures, which will not be described one by one here. The display device provided by the embodiment of the present invention has all the functions and beneficial effects of the display panel described above, and will not be described in detail.

[0159] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0160] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: A first driving circuit; the first driving circuit comprises a multi-stage shift register, the shift register comprises at least a first input unit, a second input unit and a first output unit; The control end of the first input unit is connected to the first trigger end, the input end of the first input unit is connected to the first signal end, and the output end of the first input unit is connected to the first node, so as to adjust the signal of the first node according to the first electrical signal provided by the first signal end in response to the control of the first trigger end; The control end of the second input unit is connected to the second trigger end, the input end of the second input unit is connected to the second signal end, and the output end of the second input unit is connected to the first node, so as to adjust the signal of the first node according to the second electrical signal provided by the second signal end in response to the control of the second trigger end; The control end of the first output unit is connected to the first node, the input end of the first output unit is connected to the third signal end, and the output end of the first output unit is connected to the shift output end, so as to adjust the signal of the shift output end according to the third clock signal provided by the third signal end in response to the control of the first node; The first electrical signal is a first clock signal, and / or the second electrical signal is a second clock signal.

2. The display panel according to claim 1, characterized in that: The shift register further includes: a second output unit; The control end of the second output unit is connected to the fourth signal end, the input end of the second output unit is connected to the first power supply end, and the output end of the second output unit is connected to the shift output end, and is used to respond to the control of the fourth clock signal provided by the fourth signal end, and adjust the signal of the shift output end according to the first power supply signal provided by the first power supply end.

3. The display panel according to claim 1, characterized in that: The first input unit comprises a first transistor, a gate of the first transistor is connected to the first trigger terminal, and the first transistor is connected between the first signal terminal and the first node; The second input unit includes a second transistor, a gate of the second transistor is connected to the second trigger terminal, and the second transistor is connected between the second signal terminal and the first node.

4. The display panel according to claim 2, characterized in that: The first output unit comprises a third transistor, a gate of the third transistor is connected to the first node, and the third transistor is connected between the third signal terminal and the shift output terminal; The second output unit includes a fourth transistor, a gate of the fourth transistor is connected to the fourth signal terminal, and the fourth transistor is connected between the first power supply terminal and the shift output terminal.

5. The display panel according to claim 1, characterized in that: The shift register further includes: a reset unit and a node control unit; The reset unit is connected to a reset control terminal, a first power supply terminal, the first node and the shift output terminal, and is used to adjust the signals of the first node and the shift output terminal according to a first power supply signal provided by the first power supply terminal in response to control of the reset control terminal; The node control unit is connected to the first node, the first power supply terminal and the shift output terminal, and is used for adjusting the signals of the first node and the shift output terminal according to the first power supply signal in response to the control of the first node.

6. The display panel according to claim 5, characterized in that: The reset unit includes a fifth transistor and a sixth transistor, the gate of the fifth transistor and the gate of the sixth transistor are both connected to the reset control terminal, the fifth transistor is connected between the first power supply terminal and the first node, and the sixth transistor is connected between the first power supply terminal and the shift output terminal; The node control unit includes a seventh transistor, an eighth transistor and a ninth transistor, the gate of the seventh transistor is connected to the first node, the seventh transistor is connected between the first power supply terminal and the second node, the gate of the eighth transistor and the gate of the ninth transistor are both connected to the second node, the eighth transistor is connected between the first power supply terminal and the first node, and the ninth transistor is connected between the first power supply terminal and the shift output terminal.

7. The display panel according to claim 6, characterized in that: The shift register further includes: a first capacitor and a second capacitor; The first capacitor is coupled between the first node and the shift output terminal; The second capacitor is coupled between the second node and the third signal terminal.

8. The display panel according to claim 2, characterized in that: The first driving circuit includes a multi-stage shift register circuit and Y clock signal lines, where Y≥4; The shift register circuit includes Ya shift registers connected in cascade, and the third signal terminals of the Ya shift registers are respectively connected to Ya clock signal lines among the Y clock signal lines, and Y≥Ya≥4.

9. The display panel according to claim 8, characterized in that: Among the Y clock signal lines, the clock signals provided by any two clock signal lines have the same frequency but different phases.

10. The display panel according to claim 8, characterized in that: The Y clock signal lines include the 1st clock signal line to the Yth clock signal line; The first driving circuit includes a forward scanning mode and a reverse scanning mode; In the forward scanning mode, the phase of the clock signal provided by the i-th clock signal line is earlier than the phase of the clock signal provided by the (i+1)-th clock signal line, and the phase difference between the two is a H; In the reverse scanning mode, the phase of the clock signal provided by the (i+1)th clock signal line is earlier than the phase of the clock signal provided by the i-th clock signal line, and the phase difference between the two is b H; 1≤i≤Y, a and b are both positive integers, and H is equal to the scanning time length of a row of sub-pixels in the display panel.

11. The display panel according to claim 1, characterized in that: The first trigger terminal of the shift register of the nth level is connected to the shift output terminal of the shift register of the (nm)th level; The second trigger terminal of the shift register of the nth stage is connected to the shift output terminal of the shift register of the (n+m)th stage; n is a positive integer, and m is an integer greater than or equal to 2.

12. The display panel according to claim 8, characterized in that: The Y clock signal lines include the first clock signal line to the fourth clock signal line, and the shift register circuit includes four cascaded shift registers; The first driving circuit includes a first circuit group, and the first circuit group includes at least one shift register circuit; The shift register circuit in the first circuit group satisfies the following conditions: The first clock signal line is respectively connected to the third signal terminal of the first-stage shift register, the first signal terminal of the second-stage shift register, the fourth signal terminal of the third-stage shift register, and the second signal terminal of the fourth-stage shift register; The second clock signal line is respectively connected to the second signal terminal of the first-stage shift register, the third signal terminal of the second-stage shift register, the first signal terminal of the third-stage shift register, and the fourth signal terminal of the fourth-stage shift register; The third clock signal line is respectively connected to the fourth signal terminal of the first-stage shift register, the second signal terminal of the second-stage shift register, the third signal terminal of the third-stage shift register, and the first signal terminal of the fourth-stage shift register; The fourth clock signal line is respectively connected to the first signal terminal of the first-stage shift register, the fourth signal terminal of the second-stage shift register, the second signal terminal of the third-stage shift register, and the third signal terminal of the fourth-stage shift register.

13. The display panel according to claim 12, characterized in that: The first driving circuit includes a forward scanning mode and a reverse scanning mode; In the forward scanning mode, the phase of the clock signal provided by the i-th clock signal line is earlier than the phase of the clock signal provided by the (i+1)-th clock signal line, and the phase difference between the two is H; In the reverse scanning mode, the phase of the clock signal provided by the (i+1)th clock signal line is earlier than the phase of the clock signal provided by the i-th clock signal line, and the phase difference between the two is H; 1≤i≤3,2 H is equal to the effective pulse width outputted by the shift output terminal of the shift register.

14. The display panel according to claim 8, characterized in that: The Y clock signal lines include the first clock signal line to the sixth clock signal line, and the shift register circuit includes six cascaded shift registers; The first driving circuit includes a second circuit group, and the second circuit group includes at least one shift register circuit; The shift register circuit in the second circuit group satisfies the following conditions: The first clock signal line is respectively connected to the third signal terminal of the first-stage shift register, the first signal terminal of the third-stage shift register, the fourth signal terminal of the fourth-stage shift register, and the second signal terminal of the sixth-stage shift register; The second clock signal line is respectively connected to the second signal terminal of the first-stage shift register, the third signal terminal of the second-stage shift register, the first signal terminal of the fourth-stage shift register, and the fourth signal terminal of the fifth-stage shift register; The third clock signal line is respectively connected to the second signal terminal of the second-stage shift register, the third signal terminal of the third-stage shift register, the first signal terminal of the fifth-stage shift register, and the fourth signal terminal of the sixth-stage shift register; The fourth clock signal line is respectively connected to the fourth signal terminal of the first-stage shift register, the second signal terminal of the third-stage shift register, the third signal terminal of the fourth-stage shift register, and the first signal terminal of the sixth-stage shift register; The fifth clock signal line is respectively connected to the first signal terminal of the first-stage shift register, the fourth signal terminal of the second-stage shift register, the second signal terminal of the fourth-stage shift register, and the third signal terminal of the fifth-stage shift register; The sixth clock signal line is respectively connected to the first signal terminal of the second-stage shift register, the fourth signal terminal of the third-stage shift register, the second signal terminal of the fifth-stage shift register, and the third signal terminal of the sixth-stage shift register.

15. The display panel according to claim 14, characterized in that: The first driving circuit includes a forward scanning mode and a reverse scanning mode; In the forward scanning mode, the phase of the clock signal provided by the i-th clock signal line is earlier than the phase of the clock signal provided by the (i+1)-th clock signal line, and the phase difference between the two is H; In the reverse scanning mode, the phase of the clock signal provided by the (i+1)th clock signal line is earlier than the phase of the clock signal provided by the i-th clock signal line, and the phase difference between the two is H; 1≤i≤5,3 H is equal to the effective pulse width outputted by the shift output terminal of the shift register.

16. The display panel according to claim 1, characterized in that: The first electrical signal is the first clock signal; the second electrical signal is a fixed voltage signal; The first driving circuit includes a forward scanning mode and a reverse scanning mode; In the forward scanning mode, the second electrical signal is a low level signal; In the reverse scanning mode, the second electrical signal is a high level signal.

17. The display panel according to claim 1, characterized in that: The first electrical signal is a fixed voltage signal; the second electrical signal is the second clock signal; The first driving circuit includes a forward scanning mode and a reverse scanning mode; In the forward scanning mode, the first electrical signal is a high level signal; In the reverse scanning mode, the first electrical signal is a low level signal.

18. The display panel according to claim 1, characterized in that: The shift register comprises a plurality of transistors; The plurality of transistors are all N-type transistors, or the plurality of transistors are all P-type transistors.

19. The display panel according to claim 1, characterized in that: The shift register comprises a plurality of transistors; The semiconductor layer of the transistor is an amorphous silicon semiconductor layer or an oxide semiconductor layer.

20. A display device, characterized in that: include: The display panel according to any one of claims 1 to 19.

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