Selection circuitry

Abstract

The invention relates to selection circuitry. Methods and apparatus related to using non-zero selection circuitry. For example, the non-zero selection circuitry can determine whether a first word received from a first group sense amplifier has at least one bit with a first binary value, such as logic '1'. In response to the first word being determined to have at least one bit with the first binary value, the first word can be output from the non-zero selection circuitry, and can prevent output of a second word at least when the first word is output (even if the second word is determined to have at least one bit with the first binary value).

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor memories and methods, and more particularly to apparatus, systems, and methods related to selection circuitry. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. There are many different types of memory, including volatile memory and non-volatile memory. Volatile memory may require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), etc. Non-volatile memory can provide persistent data by retaining stored data when not powered and may include NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM) and resistance variable memory (e.g., phase change random access memory (PCRAM)), resistive random access memory (RRAM) and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STTRAM), etc.

[0003] An electronic system may include processing resources (e.g., one or more processors) that can retrieve and execute instructions and store the results of the executed instructions to appropriate locations. A processor may include functional units such as arithmetic logic unit (ALU) circuitry, floating point unit (FPU) circuitry, and combinatorial logic blocks, which may be used to execute instructions by performing logical operations (e.g., AND, OR, NOT, NAND, NOR, and XOR) and invert / inversion logical operations on data (e.g., one or more operands), for example. Summary of the invention

[0004] In one aspect, the present disclosure provides a method for operating a selection circuit system, comprising: determining at the selection circuit system whether a first word received from a first group of sense amplifiers has at least one bit with a first binary value; and at least when the first word is output from the selection circuit system in response to determining that the first word has the at least one bit with the first binary value, preventing a selector configured to receive a second word from a second group of sense amplifiers from outputting the second word from the selection circuit system, regardless of whether the second word has at least one bit with the first binary value.

[0005] In another aspect, the present disclosure provides an apparatus for operating a selection circuit system, comprising: a memory array; a plurality of sense amplifiers coupled to the memory array; and a selection circuit system coupled to the plurality of sense amplifiers, the selection circuit system comprising: a first circuit block configured to receive a first word from a first group of sense amplifiers; and a second circuit block configured to receive a second word from a second group of sense amplifiers; and the first circuit block is further configured to: determine whether the first word has at least one bit with a first binary value; and in response to determining that the first word does not have the at least one bit with the first binary value, provide an enable signal to the second circuit block to allow the second word to be output from the second circuit block when it is determined at the second circuit block that the second word has at least one bit with the first binary value.

[0006] In another aspect, the present disclosure provides an apparatus for operating a selection circuit system, comprising: a plurality of sense amplifiers; and a selection circuit system coupled to the plurality of sense amplifiers and one or more local input / output (LIO) lines; and the selection circuit system is configured to determine, in response to receiving an activation signal, whether a first word received at the selection circuit system from a first group of sense amplifiers among the plurality of sense amplifiers has at least one bit with a first binary value; wherein when it is determined that the first word does not have at least one bit with the first binary value, the activation signal further causes the selection circuit system to determine whether a second word received at the selection circuit system from a second group of sense amplifiers among the plurality of sense amplifiers has the at least one bit with the first binary value. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 Block diagrams in the form of a memory system including a memory device having an array coupled to selection circuitry are illustrated in accordance with several embodiments of the present disclosure.

[0008] Figure 2 is a schematic diagram illustrating a memory array coupled to selection circuitry according to several embodiments of the present disclosure.

[0009] Figure 3 is a functional block diagram illustrating a non-zero selection circuit system including multiple circuit blocks according to several embodiments of the present disclosure.

[0010] Figure 4 is a schematic diagram illustrating at least a portion of non-zero selection circuitry including circuit blocks according to several embodiments of the present disclosure.

[0011] Figure 5 is a flow chart illustrating an example method for using selection circuitry according to several embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] Systems, apparatus, and methods related to selection circuitry are described. As an example, a method may include: determining at the selection circuitry whether a first word received from a first group of sense amplifiers has at least one bit with a first binary value; and at least when the first word is output from the selection circuitry in response to the first word being determined to have at least one bit with the first binary value, preventing a selector configured to receive a second word from a second group of sense amplifiers from outputting a second word from the selection circuitry regardless of whether the second word has at least one bit with the first binary value. The selection circuitry may be "non-zero" selection circuitry configured to recognize when a word includes one or more non-zero bits.

[0013] As used herein, the term "word" refers to a unit of data that is typically processed as a single entity and has a specific size in terms of the number of bits. Typically, a word with all constituent bits having a logical "0" (alternatively referred to as a "zero word") may not represent an actual data value; thereby indicating that valid data is not present. Even if a zero word represents an actual numerical value of "0", this numerical value may sometimes be desired to be ignored, such as when this value does not contribute to a mathematical operation. For example, if it is desired to perform one or more addition operations on multiple words, then a zero word representing a numerical value of "0" does not affect the result of the addition operation (because the result remains unchanged even if the numerical value "0" is added); therefore, utilizing a zero word is unnecessary for the addition operation. Therefore, it may be desirable that once these zero words (representing invalid data or a numerical value of "0") are determined to be zero words, the zero words are typically not transmitted out of the memory array, such as from a sense amplifier.

[0014] Therefore, several embodiments of the present disclosure provide non-zero selection circuit systems that are designed to ignore zero words among those words received from the sense amplifier. For example, the non-zero selection circuit system performs a search process for any non-zero words among those words received as input from the sense amplifier. This search process is "sequential" because the words input to the non-zero selection circuit system are sequentially checked to determine whether the corresponding word is non-zero. In addition, this process is "automatic" because (once the non-zero selection circuit system is enabled) multiple words are sequentially searched without further external intervention / signaling (e.g., from a controller external to the memory array), which would otherwise be provided for checking each input word according to existing methods. The search process can continue until a non-zero word among the words is identified. At this point, once the non-zero word is transmitted out of the sense amplifier, the non-zero word is replaced by the zero word so as to cause the non-zero selection circuit system to perform a search process on other words. In embodiments of the present disclosure, system resources can be saved by not transmitting zero words, which can avoid unnecessary power and bandwidth consumption of the memory system. Additionally, the latency associated with transferring words to the host may be reduced, thereby improving system performance.

[0015] As used herein, the singular forms "a", "an", and "the" include singular and plural referents unless the context clearly indicates otherwise. In addition, the word "may" is used throughout this application in a permissive sense (i.e., it is possible, can), rather than in a mandatory sense (i.e., must). The term "include" and its derivatives are derived to mean "including but not limited to". As used herein, "coupled to" or "coupled with..." generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without an intervening component), whether wired or wireless, including, for example, electrical, optical, magnetic, and the like. The terms "data" and "data value" are used interchangeably herein and may have the same meaning, depending on the context.

[0016] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits identify the element or component in the figure. Similar elements or components between different figures may be identified by using similar numerals. For example, element 108 may represent Figure 1 8 in , and similar elements in Figure 2 208. Similar elements in the figure may be referred to by hyphens and additional numbers or letters. As should be understood, the elements shown in the various embodiments herein may be added, exchanged and / or eliminated to provide several additional embodiments of the present disclosure. In addition, as should be understood, the proportions and relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of the present invention and should not be understood in a limiting sense.

[0017] Figure 11 is a block diagram of an apparatus in the form of a memory system 100 including a memory device having an array 106 coupled to a selection circuitry 109 in accordance with several embodiments of the present disclosure. As used herein, the memory device 104, the memory array 106, the sense amplifier ( Figure 1 "SA" in) 108 and / or selection circuit system ( Figure 1 109 is considered a "device". Figure 1 The examples shown in illustrate a system having a Von Neumann architecture, but embodiments of the invention may be implemented in a non-Von Neumann architecture (e.g., a Turing machine), which may not include one or more components typically associated with a Von Neumann architecture (e.g., a CPU, an ALU, etc.).

[0018] The computing system 100 includes a host 102 coupled (e.g., connected) to a memory device 104 including a memory array 106. The computing system 100 may be a component or resource of, for example, a personal laptop computer, a desktop computer, a digital camera, a smart phone, or a memory card reader, as well as various other types of electronic devices. The host 102 may be or include a processing device, such as a CPU. The host 102 may include a system motherboard and / or a backplane and may include one or more processing devices (e.g., one or more processors, such as a CPU, a microprocessor, a control circuit system). The computing system 100 may include the host 102 and the memory device 104 as separate and distinct integrated circuits, or include the host 102 and the memory device 104 as components on the same (single) integrated circuit (e.g., the host 102 is located on a chip with the memory device 104). In some embodiments, the memory device 104 may include components coupled to respective substrates, and those substrates may be coupled to another substrate, such as a printed circuit board (PCB). The computing system 100 may be, for example, a server system and / or a high performance computing (HPC) system and / or a component or resource of a portion thereof.

[0019] For example, the memory array 106 may be a DRAM array, an SRAM array, an STT RAM array, a PCRAM array, a TRAM array, an RRAM array, a FeRAM array, a NAND flash memory array, and / or a NOR flash memory array. The FeRAM array may include ferroelectric capacitors and may perform bit storage based on a voltage or charge amount applied thereto. The memory array 106 may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and in columns coupled by sense lines. Although in Figure 1 A single memory array 106 is shown in FIG. 1 , but embodiments are not limited thereto. For example, the memory device 104 may include one or more memory arrays 106 (eg, several banks of DRAM cells).

[0020] Memory device 104 may include address circuitry 112 to latch address signals provided by I / O circuitry 116 via an I / O bus 122 (e.g., a data bus). Address signals may be received and decoded by row decoder 118 and column decoder 120 to access memory array 106. Data may be read from memory array 106 by sensing voltage and / or current changes on digit lines using sense amplifiers 108. As described herein, sense amplifiers 108 may be one or more strips of sense amplifiers. Sense amplifiers 108 may be used to read and latch pages (e.g., rows) of data from memory array 106. I / O circuitry 116 may be used for bidirectional data communication with host 102 via I / O bus 122. Write circuitry 124 may be used to write data to memory array 106.

[0021] The controller 110 may decode signals provided from the host 102 via the control bus 126. These signals may include chip enable signals, write enable signals, and address latch signals, which are used to control operations performed on the memory array 106, including data read, data write, and data erase operations. In various embodiments, the controller 110 may be responsible for executing instructions from the host 102. The controller 110 is a state machine, a sequencer, or some other type of controller.

[0022] In some embodiments, the sense amplifiers 108 may be used to perform logic operations on the data stored in the memory array 106 and / or the results of logic operations on the data stored in the sense amplifiers 108 using the data stored in the memory array 106 and / or the data stored in the sense amplifiers 108 as inputs without transferring data via sense line address accesses (e.g., without triggering column decode signals). Thus, various computational functions may use the sense amplifiers 108 and be performed within the sense amplifiers 108 rather than by (or in association with) processing resources external to the sense amplifiers 108 (e.g., by a processor associated with the host 102 (e.g., of the controller 110 or elsewhere) and / or other processing circuitry (e.g., ALU circuitry) of the memory device 104.

[0023] The selection circuit system 109 may be coupled to the sense amplifier 108. The selection circuit system 109 may perform a search process on the words received from the sense amplifier 108 to selectively output words having at least one specific binary value (e.g., output to the host 102) while ignoring (e.g., not outputting) other words that do not contain (e.g., do not contain at all) the specific binary value among the words received from the sense amplifier 108. Although the embodiment is not limited to this, the specific binary value may be a logic "1". When a zero word is found in the words (e.g., received from the sense amplifier 108), each search process may stop. At this time, when the searched non-zero word (e.g., by the controller 110) is replaced with a zero word, the search process may be resumed, and when the search process is resumed, the zero word may be ignored. In combination Figures 2 to 5 Further details of the selection circuitry 109 and the search process are described.

[0024] Figure 2 is a diagram illustrating a method of coupling to a selection circuit system (eg, Figure 1 Schematic diagram of the memory array 206 of the selection circuit system 109 described in FIG. Logic circuits 209-1, 209-2, 209-3 (collectively referred to as logic circuits 209) may be Figure 1 109 as described in the selection circuit system 109.

[0025] Memory array 206 includes a first subset including rows of memory cells 234-m, 234-(m+1), 236-(m+2), 236-(m+3), and 236-(m+4) coupled to respective word lines, e.g., 236-m, 236-(m+1), 234-(m+2), 234-(m+3), and 236-(m+4), respectively. Memory array 206 includes a second subset portion including rows of memory cells 234-k, 234-(k+1), 234-(k+2), 234-(k+3), and 234-(k+4), respectively, coupled to respective word lines, e.g., 236-k, 236-(k+1), 234-(k+2), 234-(k+3), and 234-(k+4), respectively. As used herein, “subset” is used for identification purposes and does not necessarily imply a physical or logical characteristic (eg, boundary) of the memory array 206. The rows of the subarrays are collectively referred to as rows 234, and the wordlines of the subarrays are collectively referred to as wordlines 236.

[0026] Memory array 206 includes columns of memory cells corresponding to respective complementary digit line pairs 230-n / 231-n, 230-(n+1) / 231-(n+1), and 230-(n+2) / 231-(n+2). The columns of memory cells include respective sense amplifiers 208-n, 208-(n+1), and 208-(n+2) (collectively referred to as sense amplifiers 208) that may operate in a variety of modes according to the embodiments described herein. Memory array 206 and sense amplifiers 208 may be similar to those described herein. Figure 1 Memory array 106 and sense amplifier 108 are described in association. Figure 2 Five word lines 236 (e.g., five rows 234) are illustrated coupled to local I / O lines (e.g., LIO 238-1 and LIOF 238-2) via three digital lines 230 and three sense amplifiers 208 (e.g., three columns), but embodiments may include more or less than five word lines and more or less than three digital lines coupled to local I / O lines. Also, Figure 2 Complementary digit line pairs 230-n / 231-n, 230-(n+1) / 231-(n+1), and 230-(n+2) / 231-(n+2) in an open digit line architecture are illustrated; however, embodiments may include, for example, a folded digit line architecture.

[0027] In this example, memory array 206 includes 1T1C (one transistor one capacitor) DRAM memory cells, where each memory cell includes an access device (e.g., a transistor) and a storage element (e.g., a capacitor). In some embodiments, the memory cells may be destructive read memory cells (e.g., reading the data stored in the memory cell destroys the data such that the data originally stored in the memory cell is refreshed after being read).

[0028] Figure 2 An example configuration of the sense amplifier 208 described herein (illustrated schematically by sense amplifier 208 - n) is illustrated. Figure 2 Example sense amplifier configurations are illustrated, and may be, for example, current mode sense amplifiers and / or single-ended sense amplifiers (eg, sense amplifiers coupled to a single digital line).

[0029] Column decoder transistors 232-n and 233-n are coupled to sense amplifier 208-n, column decoder transistors 232-(n+1) and 233-(n+1) are coupled to sense amplifier 208-n+1, ​​and column decoder transistors 232-n+2 and 233-n+2 are coupled to sense amplifier 208-n+2. The memory cell columns include corresponding respective column decoding transistor pairs (e.g., 232-n and 233-n, 232-(n+1) and 233-(n+1), 232-(n+2), and 233-(n+2) (collectively referred to as column decoding transistors 232 and 233) that can be operated via respective column decoding signals (e.g., ColDec_n, ColDec_(n+1), and ColDec_(n+2), respectively). For example, one or more of the column decoding transistors 232 and 233 can be enabled to transfer data values ​​from the corresponding sense amplifier 208 and / or selection circuitry (which includes logic circuit 209) to components external to the memory array 206, such as with the local I / O lines LIO 238-1 and LIOF 238-2. Figure 1 Host 102 is described in association.

[0030] In some embodiments, the memory array 206 may include one or more sub-arrays. As used herein, a "sub-array" refers to a subset of a memory array (e.g., memory array 206). In some embodiments, the rows and columns of the memory array coupled to the local I / O lines may correspond to the sub-arrays. For example, word lines 236-m, 236-(m+1), 236-(m+2), 236-(m+3), and 236-(m+4) and digit lines 230-n, 230-(n+1), and 230-(n+2) and the memory cells coupled thereto may correspond to the sub-arrays. Word lines 236-k, 236-(k+1), 236-(k+2), 236-(k+3), and 236-(k+4) and digit lines 231-n, 231-(n+1), and 231-(n+2) and the memory cells coupled thereto may correspond to another sub-array. In some embodiments, the memory array 206 may be a bank. As used herein, a "bank" refers to a memory array of a memory device, such as Figure 1 The memory device 104 is described in association.

[0031] although Figure 2Not illustrated, but local I / O lines LIO 238-1 and LIOF 238-2 may be coupled to one or more I / O lines (e.g., global I / O lines) that provide communication between the memory array 206 and one or more components external to the memory array 206. In some embodiments, a multiplexer may couple multiple local I / O lines of the memory array 206 to a global I / O line. In some embodiments, a multiplexer may be coupled to multiple global I / O lines. For example, eight global I / O lines may be coupled to the multiplexer, where each global I / O line coupled to the multiplexer provides a respective bit of a data byte to be transferred to or from the memory array 206.

[0032] The sense amplifier 208 and logic circuit 209 may be electrically connected to the LIO 238-1 via column decoder transistors 232-n, 232-(n+1), and 232-(n+2). The sense amplifier 208 and logic circuit 209 may be connected to the LIOF 238-2 via column decoder transistors 233-n, 233-(n+1), and 233-(n+2). In some embodiments, column decoding transistors 232 and 233 may be coupled to respective sense amplifiers 208 (and respective logic circuits 209) and respective complementary digital line pairs 230-n / 231-n, 230-(n+1) / 231-(n+1), and 230-(n+2) / 231-(n+2) such that disabling one or more of column decoding transistors 232 and 233 electrically connects and / or disconnects sense amplifiers 208 and logic circuits 209 from LIO 238-1 and / or LIOF 238-2. One or more of column decoding transistors 232 and 233 may be enabled to transmit a signal corresponding to a state of a memory cell (e.g., a logic data value, such as a logic “0” or a logic “1”) and / or a logic data value stored by sense amplifier 208 to LIO 238-1 and / or LIOF 238-2.

[0033] Column decoder transistors 232 and 233 may be coupled to a column decoder (eg, Figure 1 Sense amplifier 208 and logic circuit 209 may be electrically connected to LIO 238-1 and / or LIOF 238-2 via column decoder transistors 232 and 233 in association with operating sense amplifier 208 in a sense amplifier mode.

[0034] Sense amplifier 208 may be operated to determine data values ​​(e.g., logic states) stored in the memory cell and / or represented by voltages present on complementary digital line pairs 230-n / 231-n, 230-(n+1) / 231-(n+1), and 230-(n+2) / 231-(n+2). In addition, sense amplifier 208 may be operated to perform logic functions. Figure 2 2. Although not illustrated in FIG. 2, sense amplifiers 208 may each include cross-coupled p-channel transistors (eg, PMOS transistors) and cross-coupled n-channel transistors (eg, NMOS transistors).

[0035] When sensing (e.g., reading) a memory cell, the voltage on the digit line of one of the complementary digit line pairs 230-n / 231-n, 230-(n+1) / 231-(n+1), and 230-(n+2) / 231-(n+2) may be slightly greater than the voltage on the other digit line in the pair. A positive control signal (e.g., an ACT signal) may then be driven high, and the RnIF signal may be driven low to enable one or more of the sense amplifiers 208. The digit line with the lower voltage in the pair will turn on one of the PMOS transistors to a greater degree than the other of the PMOS transistors. Thus, the digit line with the higher voltage in the pair is driven high to a greater degree than the other digit line.

[0036] Similarly, the digit line with the higher voltage in one of the complementary digit line pairs 230-n / 231-n, 230-(n+1) / 231-(n+1), and 230-(n+2) / 231-(n+2) will turn on one of the NMOS transistors to a greater degree than the other of the NMOS transistors. Thus, the digit line with the lower voltage in the pair is driven low to a greater degree than the other digit line. After a short delay, the digit line with the larger voltage in the pair can be driven to a voltage of the supply voltage (e.g., V DD ) and another digit line can be driven to a voltage of a reference voltage (e.g., ground). Thus, the NMOS transistor and the PMOS transistor function as a sense amplifier pair that amplifies the voltage difference on the complementary digit line pairs 230-n / 231-n, 230-(n+1) / 231-(n+1), and 230-(n+2) / 231-(n+2) and operates to latch the data value sensed from the memory cell.

[0037] The logic circuit 209 can operate in a collective manner to select and output a non-zero word among those logic words stored in the sense amplifier 208. Although the embodiment is not limited to this, the word may include 8 bits (1 byte), 16 bits (2 bytes), 32 bits (4 bytes), 64 bits (8 bytes), etc. For example, assuming that the word includes 16 bits, a single word can be input to the logic circuit (e.g., logic circuit 209) from sixteen sense amplifiers (e.g., sense amplifier 208). The words input to the logic circuit (e.g., logic circuit 309) respectively from the sense amplifier groups (e.g., each group corresponds to a single word) can be sequentially checked to search for each word that is non-zero. As used herein, a word is non-zero when it includes at least one bit with "non-zero" (e.g., logic "1"). Otherwise, the word is referred to as a "zero" word (e.g., all bits of the word have logic "0"). This search process is performed until a non-zero word is found. At this time, the non-zero word is output on the LIO line 238 to a component outside the memory array 206, such as a Figure 1 The host 102 described in association with this. In addition, the results of this search process are transmitted to the controller 110, which can then cause the non-zero word (input to the logic circuit 209 of the selection circuit system) to be replaced by a "zero" word so that another search process is performed on other words. This replacement can be performed in various ways. In one example, the controller 110 can cause a specific row (storing a reference value, such as "0") to be activated to further cause the "0" to be sensed by a corresponding sense amplifier, which can then provide (e.g., input) a "0" to the corresponding logic circuit 209 of the selection circuit system. In another example, the controller 110 can cause the memory cell storing the non-zero word to be overwritten with a "0" so that when the memory cell is read again, the zero word is sensed by the corresponding sense amplifier (the sense amplifier can then provide the sensed zero word to the corresponding logic circuit 209 of the selection circuit system).

[0038] Despite Figure 2 230 and 231. For example, on one side, each of these additional transistors may have a source / drain region coupled to a respective one of the digit lines 230 and another source / drain region coupled to one of the sense amplifiers 208 coupled to the digit line. On the other side, each of these additional transistors may have a source / drain region coupled to a respective one of the digit lines 231 and another source / drain region coupled to one of the sense amplifiers 208 coupled to the digit line. The gates of these additional transistors may be coupled to signal lines through which control signals may be provided.

[0039] Figure 33 is a functional block diagram illustrating a non-zero selection circuit system 309 including a plurality of circuit blocks 340-1, 340-2, ..., 340-Z according to several embodiments of the present disclosure. The non-zero selection circuit system 309 is similar to Figure 1 In addition, Figure 2 The logic circuits 235 - n, . . . , 235 -(n+2) illustrated in are part of the non-zero selection circuitry 309 .

[0040] The non-zero selection circuit system 309 includes a plurality of circuit blocks 340-1, ..., 340-Z. Each circuit block may be coupled to a corresponding group of sense amplifiers (eg, respectively at Figure 1 and 2 The sense amplifiers 108, 208-n, ..., 208-(n+2)) described in the embodiment of the present invention can receive a word from the sense amplifier. Figure 3 As shown in FIG. 1 , the circuit block 340-1 can be connected to the input channel 342-1 ( Figure 3 ) receives the word from sixteen sense amplifiers (with Figure 3 ), the circuit block 340-2 can be connected to the input channel 342-2 ( Figure 3 The "SA input" shown in FIG. 1 receives the word from different sixteen sense amplifiers (with Figure 3 ), and the circuit block 340-Z can be connected to the input channel 342-Z ( Figure 3 The "SA input" shown in FIG. 1 receives the word from different sixteen sense amplifiers (with Figure 3 These circuit blocks 340-1, ..., 340-Z may be commonly coupled to an LIO line (e.g., Figure 2 ), but the embodiment is not limited thereto.

[0041] Each circuit block 340-1, ..., 340-Z includes a corresponding input channel (e.g., 344-1, 344-2, or 344-Z) and a corresponding output channel (e.g., 348-1, 348-2, or 348-Z) to receive and provide a signal (which may be an "inhibit" signal) respectively. For example, the circuit block 340-1 may receive a signal ( Figure 3 and provides a signal ( Figure 3 ), the circuit block 340-1 may receive a signal ( Figure 3) and provides a signal (“disable”) to the next circuit block (not shown) via output channel 348-1. Figure 3 ), and circuit block 340-Z may receive a signal ( Figure 3 and outputs the signal ( Figure 3 "Prohibit next" shown in ).

[0042] The first circuit block 340-1 may be configured to receive a ground voltage ( Figure 3 , and alternatively referred to as an "activation signal"), which may be considered a logic "0". Once a signal corresponding to a ground voltage is received at the first circuit block 340-1, a search (e.g., for a non-zero word among those words received at the circuit block 340) process may begin at the non-zero selection circuit system 309.

[0043] The signals received and / or provided via input and / or output channels 344 and 348, respectively, may indicate whether to enable or disable the LIO line 338 (e.g., Figure 2 2 or LIOF 238-2 as described in the figure. For example, a signal received via input channel 344-1 may indicate whether circuit block 340-1 is enabled to output or disabled via output channel 346-1 ( Figure 3 ) and outputs the "D[0:15]" word on LIO line 338, the signal received from circuit block 340-1 via input channel 344-2 may indicate whether circuit block 340-2 is allowed to output via output channel 346-2 ( Figure 3 31]" word on LIO line 338, and a signal received at circuit block 340-Z via input channel 344-Z may indicate whether circuit block 340-Z is enabled or disabled via output channel 346-Z ( Figure 3 ) and outputs the "D[N-16:N]" word on LIO line 338. When disabled, each circuit block 340 may be prevented from outputting the corresponding word (regardless of whether the corresponding word is a non-zero word). As used herein, a signal that disables a corresponding circuit block (e.g., circuit block 340) may be referred to as an "inhibit signal."

[0044] The output channels 346-1, 346-2, ..., 346-Z may correspond to "tri-states", which include three different logic states, such as a logic high, a logic low, and a high impedance state. For example, an output channel 346 in a high impedance state does not source or sink current and does not present a signal on the LIO line 338. For example, when one output channel 346 is actively driving a signal to output data (e.g., "D[0:15]", "D[16:31]", and / or "D[N-16:N]" words), the other output channels 346 may be in a "high impedance" state, allowing the output channels 346 to drive signals without interference.

[0045] Consider an example where word "D[16:31]" is non-zero, while other words "D[0:15]" or "D[N-16:N]" are not. In this example, circuit block 340-1 places output channel 346-1 in a high impedance state, and circuit block 340-1 provides a signal to circuit block 340-2 to allow the circuit block to output the corresponding word when the word is non-zero (alternatively referred to as a "non-tri-state" output). Since word "D[16:31]" is assumed to be non-zero in this example, circuit block 340-2 outputs (actively drives) word "D[16:31]" and sends it to subsequent circuit blocks ( Figure 3 31]” is output from the non-zero selection circuit system 309 and / or the host (e.g., controller 110). The controller 110 may further include a circuit block 340-2 that provides a signal (e.g., an inhibit signal) to ultimately cause the inhibit signal to be received at the circuit block 340-Z. Upon receiving the inhibit signal, other circuit blocks (including the circuit block 340-Z) are inhibited from at least outputting (e.g., driving) the word “D[16:31]”. In addition, the circuit block 340-Z outputs a signal on the output channel 348-Z in response to the inhibit signal propagated from the circuit block 340-2. This signal output on the output channel 348-Z may be provided to a controller (e.g., controller 110) and interpreted (e.g., by the controller 110) as a “non-zero” flag indicating that at least one circuit block of the non-zero selection circuit system 309 is driving a non-tri-state output on the corresponding output channel 346. Upon determining that the word “D[16:31]” has been output from the non-zero selection circuit system 309 and / or at a host (e.g., Figure 1 When a word is received at the host 102 as described in the figure, a controller (e.g., controller 110) can input sixteen bits with all logic "0" to the circuit block 340-2 via the input channel 342-2, and the sixteen bits cause the circuit block 340-2 to place the output channel 346-2 in a high impedance state and provide a signal to the subsequent circuit block to allow the subsequent circuit block 340 to output the corresponding word when the word received at the subsequent circuit block 340 is non-zero.

[0046] Figure 44 is a schematic diagram illustrating at least a portion of non-zero selection circuitry 409 including circuit blocks 440-1 and 440-2 according to some embodiments of the present disclosure. Non-zero selection circuitry 409 is similar to that in Figure 1 and 3 In addition, the non-zero selection circuit systems 109 and 309 described in Figure 2 The logic circuits 235 - n , . . . , 235 -(n+2) illustrated in are part of the non-zero selection circuit system 409 .

[0047] although Figure 4 Two circuit blocks (eg, circuit blocks 440-1, 440-2) are illustrated in FIG. 4 , but embodiments are not limited to a specific number of circuit blocks that non-zero selection circuit system 409 may include. Figure 4 As illustrated, circuit block 440-1 may be structurally similar to circuit block 440-2. For example, logic gates 452-1, 454-1, 456-1, and selector 458-1 of circuit block 440-1 may be similar to logic gates 452-2, 454-2, 456-2, and selector 458-2 of circuit block 440-2.

[0048] like Figure 4 As illustrated, circuit block 440-1 receives signal 441 (eg, Figure 4 and is alternatively referred to as an "activation signal"). Figure 3 As described, the ground voltage received at circuit block 440-1 may be considered an activation signal. The activation signal causes non-zero selection circuit system 409 to search for and output non-zero words (output to the circuit blocks 440-1 and 440-2) respectively received at the circuit blocks of non-zero selection circuit system 409. Figure 1 102 as described in the specification). Figure 4 As illustrated, the activation signal is received as inverted at logic gate 454 - 1 .

[0049] Logic gate 454-1 further receives an input signal from logic gate 452-1 (alternatively referred to as an "output signal" from logic gate 452-1). Although embodiments are not limited thereto, logic gate 452-1 (and / or 452-2) may be a wired OR circuit that receives more than two input signals in order to perform multiple logical OR operations and generates a single output signal as a result of the logical OR operations. For example, if at least one of the input signals corresponds to a logical "1", the generated output signal corresponds to a logical "1"; however, if all input signals correspond to a logical "0", the generated output signal corresponds to a logical "0".

[0050] Thus, the signal received from logic gate 452-1 may indicate whether word "D[0:15]" is non-zero (e.g., the signal from logic gate 452-1 is a logic "1") or not non-zero (e.g., the signal from logic gate 452-1 is a logic "0"). Logic gate 454-1 provides an output signal (alternatively referred to as an "input signal" from logic gate 454-1) to selector 458-1 to enable or disable selector 458-1. For example, when logic gate 454-1 is Figure 4 15]" is non-zero (e.g., the input signal is a logic "1"). The enabled selector 458-1 may be activated on the LIO line 438 (e.g., Figure 2 4. Alternatively, the output signal from logic gate 454-1 (e.g., a logic “0”) may cause selector 458-1 to be disabled, which prevents word “D[0:15]” from being output on LIO line 438.

[0051] The output signal of logic gate 454-1 may be further provided as an input signal to logic gate 456-1. Although the embodiment is not limited thereto, logic gate 456-1 (and / 456-2) may be an OR gate. The output signal of logic gate 456-1 (alternatively referred to as the "input signal" of circuit block 440-2) may be provided to circuit block 440-2 (e.g., logic gates 454-2 and 456-2 of circuit block 440-2), and circuit block 440-2 may be disabled (when the output signal of logic gate 456-1 corresponds to a logic "1") or circuit block 440-2 may be allowed to output word "D[16:31]" (when the output signal of logic gate 456-1 corresponds to a logic "0").

[0052] For example, in response to the signal received from logic gate 454-1 having a logic “0” (indicating that word “D[0:15]” is determined to be a zero word) and assuming that logic gate 456-1 is an OR gate, logic gate 456-1 outputs a signal having a logic “0”, which can be used to output word “D[16:31]” on LIO line 438 when word “D[16:31]” is determined to be a non-zero word. On the other hand, in response to the signal received from logic gate 454-1 having a logic “1” (indicating that word “D[0:15]” is determined to be a non-zero word), logic gate 456-1 outputs a signal having a logic “1”, which is used to disable circuit block 440-2. When circuit block 440-2 is disabled, the corresponding word (e.g., word “D[16:31]”) is prevented from being output on LIO line 438, regardless of whether word “D[16:31]” is non-zero.

[0053] When circuit block 440-1 is enabled, circuit block 440-2 operates in a similar manner to circuit block 440-1. For example, circuit block 440-3 may disable subsequent circuit blocks (e.g., coupled via logic gate 456-2) in response to word "D[16:31]" being determined to be a non-zero word, or enable subsequent circuit blocks to output the corresponding word (when the corresponding word is determined to be a non-zero word).

[0054] Figure 5 1 is a flow chart illustrating an example method 570 for programming multiple erase blocks coupled to the same string according to various embodiments of the present disclosure. The method 570 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 570 is performed by Figure 1 and 3 Non-zero selection circuitry 109, 309 and 409 to 4 and / or Figure 1 100. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0055] At block 572, the non-zero selection circuitry, e.g. Figure 1 and 3 4) checks the first word (e.g., Figure 3 and 4) to determine the word "D[0:15]" from the first group of sense amplifiers (eg, Figures 1 to 2 In some embodiments, the non-zero selection circuit system 109, 309, 409 includes a first circuit block (e.g., a first circuit block for receiving the first word) and a sense amplifier 108, 208 described in the embodiment of the present invention. Figure 3-4 340-1, 440-1) and for receiving a second word (eg, Figure 3 and 4 The word "D[16:31]" and / or Figure 3 The word "D[N-16:N]" described in FIG. Figures 3 to 4 ). In this example, the method may further include placing the first circuit block 340-1, 440-1 in a high impedance state in response to the first word being determined to not have at least one bit with the first binary value.

[0056] At block 574, the selector (eg, Figure 4 The selector 458-2 described in FIG. 4 (which is configured to sense amplifiers from the second group (eg, Figures 1 to 2 409) receives the second word from the sense amplifier 108, 208 described in the embodiment of the present invention, and outputs the second word from the non-zero selection circuit system 109, 309, 409, regardless of whether the second word has at least one bit with the first binary value. In some embodiments, in response to the first word being determined to not have at least one bit with the first binary value, if the second word is determined to have at least one bit with the first binary value, then the selector 458-2 may be allowed to output the second word from the non-zero selection circuit system 109, 309, 409. In some embodiments, the non-zero selection circuit system 109, 309, 409 may be further coupled to a local input / output (LIO) line (e.g., Figures 2 to 4 In this example, the method 570 further includes outputting the first word on the LIO line 238, 338, 438 in response to the first word being determined to have at least one bit with the first binary value.

[0057] In some embodiments, in response to the first word having been output from the non-zero selection circuitry 109, 309, 409, the first word may be replaced by a number of bits that do not have the first binary value (e.g., a "zero" word). The selector 458-2 may be allowed to output a second word from the non-zero selection circuitry 109, 309, 409 in response to the first word being replaced by the number of bits. Continuing with this example, the second word may be checked at the non-zero selection circuitry 109, 309, 409 to determine whether the second word has at least one bit with the first binary value in response to the first word being determined to not have at least one bit with the first binary value or being replaced by the number of bits. Furthermore, in response to the second word being determined to have at least one bit with the first binary value, the selector (which is configured to receive the third word from the third group of sense amplifiers) may be prevented from outputting a third word from the non-zero selection circuitry 109, 309, 409 at least when the second word is output from the non-zero selection circuitry 109, 309, 409, regardless of whether the third word has at least one bit with the first binary value.

[0058] Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It will be appreciated that the above description has been made in an illustrative and non-restrictive manner. Combinations of the above embodiments and other embodiments not explicitly described herein will be apparent to those skilled in the art after reviewing the above description. The scope of one or more embodiments of the present disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims and the full range of equivalents to which such claims are entitled.

[0059] In the foregoing detailed description, some features are grouped together in a single embodiment for the purpose of simplifying the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the disclosed embodiments of the disclosure must use more features than those explicitly recited in each claim. Rather, as the appended claims reflect, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. A method for operating a selection circuit system, comprising: In selecting a circuit system (109; 309; 409) determines from the first group of sense amplifiers (108; 208-n, 208-(n+1), 208-(n+2)) whether the first word received has at least one bit with a first binary value; and preventing the first word from being output from the selection circuitry in response to determining that the first word has the at least one bit with the first binary value, from being configured to sense amplifiers from a second group (108; A selector (458-2) receiving a second word (208-n, 208-(n+1), 208-(n+2)) outputs the second word from the selection circuit system regardless of whether the second word has at least one bit with the first binary value.

2. The method according to claim 1, further comprising: In response to determining that the first word does not have the at least one bit with the first binary value, the selector is enabled to output the second word from the selection circuitry if the second word is determined to have the at least one bit with the first binary value.

3. The method according to claim 1, further comprising: responsive to the first word having been output from the selection circuitry, replacing the first word with a number of bits that do not have the first binary value; and In response to the first word being replaced by the number of bits, the selector is enabled to output the second word from the selection circuitry.

4. The method according to claim 3, further comprising: at the selection circuitry, in response to the first word being determined to not have the at least one bit with the first binary value or to be replaced by the number of bits, determining whether the second word has at least one bit with the first binary value; and In response to the second word being determined to have the at least one bit with the first binary value, the selector configured to receive a third word from a third group of sense amplifiers is prevented from outputting the third word from the selection circuit system at least when the second word is being output from the selection circuit system, regardless of whether the third word has the at least one bit with the first binary value.

5. The method according to any one of claims 1 to 4, wherein: The selection circuitry further includes a first circuit block (340-1; 440-1) for receiving the first word and a second circuit block (340-2; 440-2) for receiving the second word; and The method further includes placing the first circuit block in a high impedance state in response to the first word being determined to not have the at least one bit with the first binary value.

6. The method according to any one of claims 1 to 4, wherein: The selection circuitry is further coupled to local input / output LIO lines (238-1, 238-2; 338; 438); and The method further includes outputting the first word on the LIO line in response to the first word being determined to have the at least one bit with the first binary value.

7. An apparatus for operating a selection circuit system, comprising: Memory array (106; 206)； A plurality of sense amplifiers (108; 208-n, 208-(n+1), 208-(n+2)), which are coupled to the memory array; and Select circuit system (109; 309; 409), which is coupled to the plurality of sense amplifiers, the selection circuit system comprising: The first circuit block (340-1; 440-1) is configured to sense amplifiers (108; 208-n, 208-(n+1), 208-(n+2)) receiving the first word; and The second circuit block (340-2; 440-2) is configured to sense amplifiers (108; 208-n, 208-(n+1), 208-(n+2)) receive the second word; and The first circuit block is further configured to: determining whether the first word has at least one bit with a first binary value; and In response to determining that the first word does not have the at least one bit with the first binary value, providing an enable signal to the second circuit block to enable the second word to be output from the second circuit block when it is determined at the second circuit block that the second word has the at least one bit with the first binary value.

8. The apparatus of claim 7, wherein the first circuit block of the selection circuitry further comprises a first logic gate (452-1) configured to: receiving the first word from the first group of sense amplifiers; and A determination is made as to whether the first word has the at least one bit with the first binary value.

9. The apparatus of claim 8, wherein the first circuit block of the selection circuitry further comprises a second logic gate (454-1) coupled to the first logic gate and a selector (458-1), the second logic gate being configured to: receiving an input signal from the first logic gate indicating that the first word has the at least one bit with the first binary value; and When the first word is determined to have the at least one bit with the first binary value, the selector is enabled to allow the first word to be output via the selector.

10. The apparatus of claim 9, wherein the first circuit block of the selection circuitry further comprises a third logic gate (456-1) configured to: receiving an input signal from the second logic gate indicating that the first word is determined to have the at least one bit having the first binary value; and The enable signal is provided to the second circuit block of the selection circuitry.

11. The apparatus of claim 7, wherein: The first circuit block and the second circuit block of the selection circuitry are further coupled to a local input / output (LIO) line (238-1, 238-2; 338; 438); and The first circuit block and the second circuit block are configured to output corresponding words on the LIO line.

12. The apparatus of claim 7, wherein the memory array comprises dynamic random access memory (DRAM) devices.

13. The apparatus of claim 7, wherein the selection circuitry is located on-chip with the memory array and the plurality of sense amplifiers.

14. An apparatus for operating a selection circuit system, comprising: A plurality of sense amplifiers (108; 208-n, 208-(n+1), 208-(n+2)); and selection circuitry (109; 309; 409) coupled to the plurality of sense amplifiers and one or more local input / output (LIO) lines; and The selection circuit system is configured to respond to receiving an activation signal (341; 441), determining whether a first word received at the selection circuitry from a first group of sense amplifiers in the plurality of sense amplifiers has at least one bit with a first binary value; Wherein when it is determined that the first word does not have at least one bit with the first binary value, the activation signal further causes the selection circuit system to determine whether a second word received at the selection circuit system from a second group of sense amplifiers among the plurality of sense amplifiers has the at least one bit with the first binary value.

15. The apparatus of claim 14, wherein the selection circuitry is configured to prevent output of the second word from the selection circuitry in response to the first word being determined to have the at least one bit with the first binary value.

16. The apparatus of claim 15, further comprising a controller (110) coupled to the selection circuitry and the plurality of sense amplifiers, wherein the controller is further configured to output the first word on a respective one of the LIO lines (238-1, 238-2; 338; 438) in response to: The first word is replaced with a number of bits that do not have the first binary value to cause the selection circuitry to output the second word upon determining that the second word has at least one bit with the first binary value.

17. The apparatus of claim 16, wherein the selection circuitry is configured to output the second word without replacing the first word with the number of bits when the first word is determined to not have the at least one bit with the first binary value.

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