Memory device with tracking word line, method of operating the same, and

Abstract

The invention relates to a memory device with tracking word lines, a method of operating the same, and a method of manufacturing the same. A memory device includes: a first array of memory cells; a second array of tracking cells, the second array configured to simulate the first array; a first word line coupled to a corresponding memory cell in a corresponding row of the first array and coupled to the tracking cell; a second word line configured to simulate the first word line; a first adjustment circuit coupled to the first word line; a second adjustment circuit coupled to the second word line; and an adjustment timing circuit coupled to the second adjustment circuit.

Description

Technical Field

[0001] The present disclosure relates to a memory device having a tracking word line with an adjustment circuit, an operation method thereof, and a manufacturing method thereof. Background Art

[0002] Static random access memory (SRAM) is a type of memory device. A one-bit SRAM cell has two storage nodes that are used to store the logic state (low or high) of the bit and the complement of the bit, i.e., bit_bar. Static noise margin (SNM) is a quality factor applied to SRAM cells. The SNM of an SRAM cell is the minimum level of noise voltage on each of the two storage nodes that is sufficient to flip the state of the bit and the bit_bar value, i.e., interfere with the data stored by the SRAM cell. An increase in SNM makes the SRAM cell less susceptible to noise interference. A decrease in SNM makes the SRAM cell more susceptible to noise interference.

[0003] As semiconductor process technology nodes develop, the operating voltage of SRAM is gradually reduced. The reduction in operating voltage usually reduces the power consumed by the SRAM cell. Conversely, the reduction in operating voltage usually reduces the SNM of the SRAM cell.

[0004] Semiconductor devices are not manufactured by ideal devices under ideal conditions, but are affected by equipment tolerances, material variations, and environmental variations, so that the manufactured devices exhibit corresponding changes in resistance, threshold voltage, etc. The performance space (PS) of the manufacturing design represents the expected range of variation. Since complementary metal oxide semiconductor (CMOS) technology includes both N-channel or negative channel MOS (NMOS) elements and P-channel or positive channel (PMOS) elements, the PS of CMOS is usually represented in two dimensions by a quadrilateral figure as an angle with extreme values ​​representing the variation of each NMOS and PMOS component, angle = (NMOS, PMOS), such as SS = (slow, slow), SF (slow, fast), FF = (fast, fast), or FS (fast, slow). For a given device design, local variations occur within a single wafer (die), while global variations occur across the entire wafer (die) population. Examples of global angles are SSG, SFG, FFG, and FSG. Summary of the invention

[0005] According to one embodiment of the present disclosure, a memory device is provided, comprising: a first array of memory cells; a second array of tracking cells, the second array being configured to simulate the first array; a first word line coupled to corresponding memory cells in a corresponding row of the first array and coupled to the tracking cells; a second word line configured to simulate the first word line; a first adjustment circuit coupled to the first word line; a second adjustment circuit coupled to the second word line; and an adjustment timing circuit coupled to the second adjustment circuit.

[0006] According to another embodiment of the present disclosure, a method of operating a memory device is provided, the method comprising: raising a first voltage on a first word line to a first reference voltage, the first word line being coupled to a first array of memory cells and further coupled to memory cells in a corresponding row of the first array; and raising a second voltage on a second word line to the first reference voltage; hindering the first voltage on the first word line from significantly reaching the first reference voltage; and hindering the second voltage on the second word line from significantly reaching the first reference voltage.

[0007] According to another embodiment of the present disclosure, a method for forming a memory device is provided, the method comprising: forming an active region in a substrate; forming a source / drain (S / D) region in the active region as a first transistor component, wherein a region of the active region between corresponding S / D regions is a channel region representing a second transistor component; forming a gate structure over a corresponding channel region in the channel region as a third transistor component; forming a metal-to-S / D (MD) contact structure over a corresponding S / D region in the S / D region as a fourth transistor component; forming a via-to-gate / MD (VGD) structure over a corresponding structure in the gate structure and the MD contact structure as a fifth transistor component; relative to an orthogonal projection of the memory device on a reference plane, the memory device is arranged into a non-overlapping region, the non-overlapping region comprising a bit cell region, a main input / output (I / O) region, a main controller region, and a word line driver region; the VGD structure electrically couples the first transistor component to a corresponding group in the fourth transistor component, the The corresponding groups include: a first group, which is a first array of memory cells in the bit cell area; a second group, which is a second array of tracking cells in the bit cell area and is configured to simulate the first array; a third group, which is a first adjustment circuit located in one of the non-overlapping areas other than the bit cell area; and a fourth group, which is an adjustment timing circuit in the main controller area and is coupled to the first adjustment circuit; and correspondingly above the first to fourth groups, metallization segments are formed in corresponding metallization layers and interconnect structures are formed in corresponding interconnect layers on a staggered layer basis; and wherein: forming the metallization segments and the interconnect structures produces: a first word line, which is located in the bit cell area and is coupled to the corresponding memory cells in a corresponding row of the first array and is coupled to the tracking cells; and a second word line, which is located in the main I / O area and is configured to simulate the first word line; forming the metallization segments and the interconnect structures electrically couple: the first adjustment circuit to the second word line; and the adjustment timing circuit to the first adjustment circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] One or more embodiments are illustrated by way of example and not limitation in the accompanying drawings, in which elements having the same reference numerals refer to similar elements throughout. Unless otherwise disclosed, the accompanying drawings are not drawn to scale.

[0009] Figure 1 is a block diagram of a memory device according to some embodiments.

[0010] Figure 2 is a schematic diagram of a memory according to some embodiments.

[0011] Figure 3is a timing diagram including waveforms according to some embodiments.

[0012] Figure 4A-4C is a plan view according to some embodiments.

[0013] Figure 4D is a layout diagram according to some embodiments.

[0014] Figure 5A-Figure 5B is a corresponding cross-section according to some embodiments.

[0015] Figure 6A-6B is a flow chart of a corresponding method of manufacturing a memory device according to some embodiments.

[0016] Figure 7 is a flow chart of a method of operating a memory device according to some embodiments.

[0017] Figure 8 is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0018] Fig. 9 is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing flow associated therewith, according to some embodiments. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples for realizing the different features of the subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. can be foreseen. For example, in the following description, forming a first feature on or on a second feature includes an embodiment in which the first feature and the second feature are formed in a direct contact manner, and may also include an additional feature that can be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat the figure marks and / or letters in various examples. This repetition is for the purpose of brevity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0020] In addition, spatially related terms (e.g., "below," "below," "lower," "above," "upper," etc.) may be used herein to easily describe the relationship of an element or feature shown in the figure relative to another (one or more) element or (one or more) feature. In addition to the orientation depicted in the figure, spatially related terms are also intended to include different orientations of the device in use or operation. The device can be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be similarly interpreted accordingly. In some embodiments, the term standard cell structure refers to a standardized building block included in a library of various standard cell structures. In some embodiments, various standard cell structures are selected from their library and used as components in a layout diagram representing a circuit.

[0021] In some embodiments, a memory device includes: a first array of memory cells (e.g., a memory array); a second array of tracking cells (e.g., a tracking array), the second array being configured to emulate the first array; a first word line (e.g., a word line WL) coupled to corresponding memory cells in corresponding rows of the memory array and coupled to the tracking cells; a second word line (e.g., a tracking word line TWL) configured to emulate word line WL; a first adjustment circuit coupled to word line WL; a second adjustment circuit coupled to tracking word line TWL; and an adjustment timing circuit coupled to the second adjustment circuit. In some embodiments, the memory device further includes a second adjustment circuit coupled to word line WL.

[0022] An SRAM memory device according to another approach represents a counterpart to an embodiment of an SRAM memory device (e.g., memory device 100) disclosed herein. An SRAM memory device according to another approach provides (1) a word line adjustment scheme and a tracking word line scheme. The word line adjustment scheme according to another approach includes an adjustment circuit coupled to the word line. The tracking word line scheme according to another approach includes tracking word lines but does not include an adjustment circuit coupled to the tracking word lines. As part of developing this embodiment, the inventors recognized that there is inaccuracy in the simulation of word lines by tracking word lines according to another approach, which reduces the SNM of the SRAM memory device according to another approach. Based at least in part on the recognition noted by the inventors, an embodiment of the present application provides a tracking scheme that includes an adjustment circuit coupled to the tracking word line. Therefore, a tracking scheme for an SRAM memory device according to an embodiment of the present application includes an adjustment circuit coupled to the tracking word line. Compared with the SRAM memory device according to another approach, advantages exhibited by such embodiments of the present application include higher accuracy of the simulation of word lines by tracking word lines, resulting in an increase in the static noise margin (SNM) of the SRAM memory device. In some embodiments, such SRAM memory device embodiments of the present application including an adjustment circuit coupled to a tracking word line exhibit an increase in read margin in the range of (≈10.2)% to (≈11.1)% for SSG process corners (and better for other global variations compared to SRAM memory devices according to other approaches).

[0023] Figure 1 is a block diagram of a memory device 100 according to some embodiments.

[0024] The memory device 100 is, for example, a semiconductor memory device. In some embodiments, the memory device is included in an integrated circuit (IC). In some embodiments, the memory device 100 adopts a static random access memory (SRAM) architecture. In some embodiments, the memory device 100 has a memory architecture other than the SRAM architecture.

[0025] The memory device 100 includes: a tracking array 102, such as a column; a bit line tracking (BLT) circuit 104; an adjustment timer 106; an adjustment circuit 108 (1); an adjustment circuit 108 (2); a word line (WL) driver 110 (1); a tracking word line TWL; a TWL driver 110 (2); a bias selector 112; a multiplexer (MUX) 114; and a memory array 116 ( Figure 2) and adjustment circuit 122. Memory array 116 is coupled to each of WL driver 110(1) and multiplexer 114. WL driver 110(1) is coupled between adjustment circuit 108(1) and each of memory array 116 and tracking array 102. Adjustment circuit 108(1) is coupled between adjustment timer 106 and WL driver 110(1). Multiplexer 114 is coupled between bias selector 112 and memory array 116. Bias selector 112 is coupled between adjustment timer 106 and multiplexer 114. Adjustment circuit 122 is coupled between tracking word line TWL and tracking array 102. Tracking word line TWL is coupled between (A) adjustment circuit 108(2) and each of TWL driver 110(2) and (B) adjustment circuit 122. Adjustment circuit 108(2) is coupled between tracking word line TWL and adjustment timer 106. Adjustment timer 106 is coupled between (A) BLT tracking circuit 104 and each of (B) adjustment circuit 108(1), bias selector 112, and adjustment circuit 108(2). BLT tracking circuit 104 is coupled between tracking array 102 and adjustment timer 106. Tracking array 102 is coupled between WL driver 110(1) and BLT tracking circuit 104.

[0026] exist Figure 1 In the embodiment, driver WL driver 110 (1) is configured to drive word line WL ( Figure 2 ). Tracking word line TWL is configured as analog word line WL, as described below. In some embodiments, TWL driver 110(2) is configured as analog word line driver WL. In some embodiments, TWL driver 110(2) is configured to exhibit an operational profile substantially the same as an operational profile exhibited by word line driver WL. TWL driver 110(2) is configured to signal pre_EMU( Figure 2-Figure 3 ) is output to the first end of the tracking word line TWL, and the signal pre_EMU is output from the second end of the tracking word line TWL as the analog signal EMU ( Figure 2-Figure 3 ) appears, and in the BL adjustment circuit 122 ( Figure 2 ) is received at the input terminal of the BL adjustment circuit 122 ( Figure 2 )Use analog signal EMU( Figure 2-3 ) will track the bit line BLT( Figure 2 ) on the signal TBLT( Figure 2-Figure 3 ) is adjusted to discharge at a rate substantially similar to that of the bit lines (eg, Figure 2 The discharge speed of the signal on the BL) of the BL adjustment circuit 122 ( Figure 2 ) is configured based on the analog signal EMU ( Figure 2-Figure 3 ) voltage v_EMU adjusts the bit line BL ( Figure 2 ), which improves the performance of the BLT tracking circuit 104.

[0027] exist Figure 1 In the example, the tracking array 102 includes tracking elements ( Figure 2 Each tracking cell is coupled to a tracking bit line BLT ( Figure 2 In some embodiments, each tracking cell of tracking array 102 has substantially the same structure and substantially the same performance parameters (e.g., representing impedance or resistance-capacitance load) as the memory cells of memory array 116. BLT tracking circuit 104 uses the voltage v_BLT ( Figure 2 ) to estimate the bit line BL of the memory array 116 ( Figure 2 ) voltage drop, thereby operating the memory device 100 faster and / or more efficiently. Figure 2 Operations associated with tracking array 102 are described in greater detail.

[0028] The BLT tracking circuit 104 has an input coupled to receive a tracking bit_bar line voltage v_BLT on a tracking bit line BLT of the tracking array 102. The BLT tracking circuit 104 is configured to sense a drop in the tracking bit_bar line voltage v_BLT and send voltage drop information to the adjustment timer 106. Based on the voltage drop information from the BLT tracking circuit 104, the adjustment timer 106 is configured to generate a timing signal TMR ( Figure 2-Figure 3 ). The timing signal TMR is provided to each of the adjustment circuit 108(1), the bias selector 112, and the adjustment circuit 108(2). In the first time period of the read cycle or the write cycle ( Figure 3 ), and in response to the timing signal TMR, each of the following is true: the adjustment circuit 108 (1) adjusts the word line WL ( Figure 2 ) is asserted by WL driver 110(1) Figure 2-Figure 3 ) voltage v_DW; and the adjustment circuit 108 (2) adjusts the signal EMU (asserted by the TWL driver 110 (2) on the tracking word line TWL; Figure 2-Figure 3 The adjustment circuit 122 is configured to track the voltage v_EMU on the word line TWL based on the signal EMU ( Figure 2-Figure 3 ) voltage v_EMU adjusts the bit line BL ( Figure 2 ) on the signal BL( Figure 2-Figure 3 ) voltage v_BL.

[0029] exist Figure 1 In the second time period of the write cycle ( Figure 3 ) period, and in response to the timing signal TMR, the bias selector 112 is configured to generate a selection signal SEL ( Figure 2-Figure 3 ), the selection signal SEL controls the write auxiliary voltage VWA ( Figure 2 ) or a reference voltage such as VDD( Figure 2 )) is applied to the power supply rail CVDD via multiplexer 114 ( Figure 2 In summary, based on the information obtained from the tracking array 102, the operating conditions of the memory array 116 are estimated to facilitate application of various read and write adjustment schemes to the memory array 116, such as reducing the asserted voltage of the signal DW on the word line WL, or reducing the voltage applied to the power rail CVDD, etc.

[0030] Figure 2 is a schematic diagram of a memory device 200 according to some embodiments.

[0031] Memory device 200 is an example of memory device 100 . Memory array 116 includes memory cells arranged in M ​​rows and N columns (M×N), where each of M and N is a positive integer. An example of a memory cell of memory array 116 is memory cell 206 . Figure 2 Assume that memory cell 206 is a six-transistor (6T) memory cell. In some embodiments, each memory cell has Figure 2 Different configurations of the 6T memory cell are shown in FIG. Figure 2 In some embodiments, tracking array 102 is arranged as a one-dimensional array (eg, arranged in columns). In some embodiments, tracking array 102 is a two-dimensional array.

[0032] The memory cell 206 includes a latch and two metal oxide field effect transistors (MOSFETs) with a negative channel (NFET), namely, NFETs N13 and N14. The NFET N13 is electrically coupled (hereinafter referred to as "coupled") between the bit line BL and the first storage node nd1 of the latch. The NFET N14 is coupled between the bit_bar line BLB and the second storage node nd2 of the latch. In a normal operating mode, the logic state of the storage node nd2 is the complement of the logic state of the storage node nd1, that is, if the logic state of the storage node nd1 is low, the logic state of the node nd2 is high, and vice versa. In some embodiments, each of the NFETs N13 and N14 is referred to as a transmission gate. The bit line BL is coupled not only to the memory cell 206, but also to other memory cells (not shown) in the corresponding column of the memory array 116. The bit_bar line BLB is coupled not only to the memory cell 206, but also to other memory cells (not shown) in the corresponding column of the memory array 116. Gate terminals of the transfer gates N13 and N14 are coupled to the word line WL.

[0033] exist Figure 2 In the embodiment of the present invention, the latch of the memory cell 206 includes a first inverter and a second inverter that are cross-coupled. The first inverter includes a MOSFET having a positive channel (PFET) P11 coupled between a power rail CVDD and a storage node nd1; an NFET N11 coupled between the storage node nd1 and a reference voltage (e.g., VSS, ground (GND), etc.). The second inverter includes: a PFET P12 coupled between the power rail CVDD and a storage node nd2; and an NFET N12 coupled between the storage node nd2 and a reference voltage VSS. The gate terminals of the PFET P11 and the NFET N11 of the first inverter are coupled to the storage node nd2 of the second inverter. The gate terminals of the PFET P12 and the NFET N12 of the second inverter are coupled to the storage node nd1 of the first inverter. Therefore, the first inverter and the second inverter are referred to as being cross-coupled with each other. In some embodiments, the PFETs P11 and P12 are referred to as pull-down transistors, and the NFETs N11 and N12 are referred to as pull-up transistors.

[0034] An example of a tracking cell in the tracking array 102 is the tracking cell 202. The tracking cells of the tracking array 102 have substantially the same structure and substantially the same performance parameters as the memory cells of the memory array 116. Therefore, the tracking cell 202 has substantially the same structure and substantially the same performance parameters as the memory cell 206. The PFETs P13-P14, NFETs N13-N16, and storage nodes nd3-nd4 of the tracking cell 202 correspond to the PFETs P11-P12, NFETs N11-N12, and storage nodes nd1-nd2 of the memory cell 206. The tracking bit line BLT of the tracking cell 202 corresponds to and is configured to emulate the bit_bar line BLB of the memory cell 206. The tracking bit_bar line BLBT of the tracking cell 202 corresponds to and is configured to emulate the bit line BL of the memory cell 206. The gate terminals of the transfer gates N15 and N16 are coupled to the word line WL. As such, gate terminals of pass gates N15 and N16 of tracking cell 202 are coupled to gate terminals of pass gates N13 and N14 of memory cell 206. In some embodiments, PFETs P13 and P14 are referred to as pull-down transistors, and NFETs N13 and N14 are referred to as pull-up transistors.

[0035] exist Figure 2In the memory array 116 of: the memory cells in the row (e.g., 206) are coupled to a corresponding word line (e.g., WL); the memory cells in the column (e.g., 206) are coupled to a corresponding bit line (e.g., BL) and a corresponding bit_bar line (e.g., BLB). In some embodiments, the voltage v_BLB on the bit_bar line BLB represents a logic state that is substantially the logical complement (or logical inverse) of the logic state represented by the voltage v_BL on the corresponding bit line BL. The voltage on the bit line BL determines the read and write margins of the SRAM cell. In some embodiments, the voltage on the bit_bar line BLB determines the read and write margins of the SRAM cell. The relationship between the voltage on the bit line BL and the read and write margins will be described in detail with reference to FIG. 5.

[0036] The WL driver 110(1) includes a "represent row select" (TRS) detector 218 and an inverter, the inverter including a PFET P1 and an NFET N1. The TRS detector 218 is configured to detect when a read address or a write address selects a corresponding row of the memory array 116. For example, such selection is for the purpose of a read operation or a write operation to one of the memory cells (e.g., 206) in the selected row. In some embodiments, the TRS detector 218 includes an address decoder. The output of the TRS detector 218 is coupled to the input of the inverter of the WL driver 110(1). The output of the inverter of the WL driver 110(1) is coupled to the word line WL. When it is detected that the corresponding row has been selected, the TRS detector 218 is configured to reduce / lower its output signal, which causes the inverter of the WL driver 110(1) to not only generate a drive signal (signal DW) on the word line, but also to increase the signal DW ( Figure 3 ) increases / rises to a level sufficient to turn on each of the transmission gates N13 and N14.

[0037] exist Figure 2 In the example, during a write operation, the bit line BL and the bit_bar line BLB are set to opposite logic states according to the new data to be written into the memory cell 206. When the memory cell 206 is selected, a logic high state is applied to WL accordingly, which turns on the transmission gates N13 and N14, thereby coupling the storage nodes nd1 and nd2 of the latch of the memory cell 206 to the bit line BL and the bit_bar line BLB, respectively. As a result, the logic values ​​on the bit line BL and the bit_bar line BLB are written (and thus transferred) into the storage nodes nd1 and nd2.

[0038] The adjustment circuit 108(1) is coupled between the word line WL and the adjustment timer 106. Figure 2In the embodiment, the adjustment circuit 108 (1) includes an NFET N3 coupled between the word line WL and the reference voltage VSS. The gate terminal of the NFET N3 is coupled to receive the timing signal TMR generated by the adjustment timer 106, which is generated during a portion of the read operation ( Figure 3 ) or as part of a write operation ( Figure 3 ), thereby adjusting the voltage v_DW of the signal DW on the word line WL. As described below, the timing signal TMR is also received by the adjustment circuit 108 (2) and the bias selector 112. In some embodiments, the NFET N3 is configured to receive a control signal (not shown) that turns on the NFET N3 for the entire duration of the read operation or the entire duration of the write operation. In some embodiments, the NFET N3 has an always-on configuration, such as where the gate terminal is coupled to, for example, a reference voltage VDD. In some embodiments, a PFET is used instead of the NFET N3, and the waveform of the timing signal TMR is inverted accordingly.

[0039] exist Figure 2 In FIG. 1 , the adjustment circuit 108 ( 2 ) is coupled between the tracking word line TWL and the reference voltage VSS. Figure 2 In the embodiment, the adjustment circuit 108 (2) includes an NFET N4 coupled between the tracking word line TWL and the reference voltage VSS. The gate terminal of the NFET N4 is coupled to receive the timing signal TMR, which is used during a portion of the read operation ( Figure 3 ) or as part of a write operation ( Figure 3 ), thereby adjusting the voltage v_EMU of the analog signal EMU on the tracking word line TWL. In some embodiments, the NFET N4 is configured to receive a control signal (not shown) that turns on the NFET N4 for the entire duration of the read operation or the entire duration of the write operation. In some embodiments, the NFET N4 has an always-on configuration, such as where the gate terminal is coupled to, for example, a reference voltage VDD. In some embodiments, a PFET is used instead of the NFET N4, and the waveform of the timing signal TMR is inverted accordingly.

[0040] In some embodiments, adjustment circuit 108(2) is configured to adjust the voltage v_EMU of analog signal EMU on tracking line TWL substantially the same as adjustment circuit 108(1) is configured to adjust the voltage v_DW of signal DW on word line WL. In some embodiments, adjustment circuit 108(2) is configured to have an operating profile substantially the same as the operating profile exhibited by adjustment circuit 108(1). In some embodiments, NFET N4 is configured to have an operating profile substantially the same as the operating profile exhibited by NFET N3, e.g., with respect to various combinations of parameters such as current conduction capability, channel length, threshold voltage, etc.

[0041] The bias selector 112 is configured to receive the timing signal TMR. In response to the timing signal TMR, the bias selector 112 is configured to generate a selection signal SEL ( Figure 3 ) and outputs it to the multiplexer 114. In response to the selection signal SEL ( Figure 3 ), the multiplexer 114 selectively couples the write auxiliary voltage VWA or the reference voltage VDD to the power rail CVDD.

[0042] exist Figure 2 , tracking word line TWL is configured to present substantially the same impedance, resistive-capacitive load, etc. as word line WL. In some embodiments, the total length of tracking word line TWL is substantially the same as the total length of word line WL, and the width of a segment including tracking word line TWL is substantially the same as the width of a segment including word line WL, where the width is measured relative to the minor axis of such segment. In such embodiments, a signal transmitted through tracking word line TWL experiences a propagation delay similar to the propagation delay experienced by a signal transmitted from word line driver 110(1) through word line WL on memory array 116 to a corresponding memory cell in a column of memory array 116. In such embodiments, a transfer function representing the effect of tracking word line TWL on a signal propagating therethrough is similar to a transfer function representing the effect of word line WL on a signal propagating therethrough.

[0043] The input terminal of the tracking word line TWL is configured to receive the signal pre-EMU from the TWL driver 110 (2). Figure 2, the tracking word line TWL includes a first line segment seg(1), a second line segment seg(2), and a third line segment seg(3) connected in series. The second line segment seg(2) is connected between the first line segment seg(1) and the third line segment seg(3). In some embodiments, the total length of the tracking word line TWL, i.e., the sum of the lengths of the first line segment seg(1), the second line segment seg(2), and the third line segment seg(3), is configured to be similar to the width of N columns in the memory array 116. In some embodiments, the sum of the lengths of the line segments seg(1)-seg(3) is substantially the same as the total length of the word line WL.

[0044] In some embodiments, Figure 2 In the tracking word line TWL, the length of the first line segment seg(1) is substantially equal to approximately half of the width of the memory array 116, that is, the width of approximately N / 2 columns of the memory array. In some embodiments, the length of the third line segment seg(3) is also substantially equal to approximately half of the width of the memory array 116. For example, if the memory array 116 has 32 columns, the length of the first line segment seg(1) (and the length of the third line segment seg(3)) is configured to be substantially equal to the width of 16 columns in the memory array 116. For example, if the memory array 116 has 128 columns, the length of the first line segment seg(1) (and the length of the third line segment seg(3)) is configured to be substantially equal to the width of 64 columns in the memory array 116. In some embodiments, the length of the first line segment seg(1) (and the length of the third line segment seg(3)) is based on the size of the memory array 116. The total length of the tracking word line TWL is similar to the total length of one of the word lines (e.g., WL) of the memory array 116.

[0045] The TWL driver 110(2) includes an "arbitrary row select" (ARS) detector 220 and an inverter, the inverter including PFET P3 and NFET N8. The ARS detector 220 is configured to detect when a read address or a write address selects any row of the memory array 116. For example, such selection is for the purpose of a read operation or a write operation to one of the memory cells (e.g., 206) in the selected row. In some embodiments, the ARS detector 220 includes an address decoder. The output of the ARS detector 220 is coupled to the input of the inverter of the TWL driver 110(2). The output of the inverter of the TWL driver 110(2) is configured to generate a signal pre_EMU and is coupled to a first end of the tracking word line TWL. When it is detected that a row has been selected, the ARS detector 220 is configured to decrease / lower its output signal, which causes the inverter of the WL driver 110(1) to increase / raise the voltage v_pre_EMU of the signal pre_EMU input to the tracking word line TWL, thereby increasing / raising the signal EMU output from the tracking word line TWL ( Figure 3 ) voltage v_EMU.

[0046] The BL adjustment circuit 122 is configured to receive an analog signal EMU from the tracking word line TWL. Based on the analog signal EMU, the BL adjustment circuit 122 is configured to adjust a voltage v_BL on the bit line BL. Figure 2 , the BL adjustment circuit 122 has a quasi-inverter configuration. The BL adjustment circuit 122 includes a PFET P2 and NFETs N5, N6, and N7. The PFET P2 is coupled between a reference voltage VDD and an output node of the BL adjustment circuit 122 at a node nd5. The output node nd5 of the BL adjustment circuit 122 is coupled to the tracking bit line BLT. A first source / drain (S / D) terminal of the NFET N5 is coupled to the node nd5, and a second S / D terminal of the NFET N5 is coupled to a first S / D terminal of the NFET N6. A second S / D terminal of the NFET N6 is coupled to a first S / D terminal of the NFET N7. A second S / D terminal of the NFET N7 is coupled to a reference voltage VSS. A gate terminal of each of the PFET P2 and the NFETs N5-N7 is coupled to an input of the BL adjustment circuit 122 and thus to an analog signal EMU. The BL adjustment circuit 122 is controlled by the analog signal EMU. The BL adjustment circuit 122 is configured to discharge the voltage level on the node nd5 according to the analog signal EMU, thereby adjusting the voltage v_TBLT of the signal TBLT on the tracking bit line BLT of the tracking unit 202. In some embodiments, an NFET is used instead of the PFET P2, and corresponding PFETs are used instead of the NFETs N5-N7, and the waveform of the signal pre-EMU and thus the analog signal EMU are inverted accordingly.

[0047] When the analog signal EMU reaches a level sufficient to turn on the NFETs N4-N6 and also turn off the PFET P2, the BL adjustment circuit 122 begins to discharge / reduce the voltage on the node nd5, which discharges / reduces the voltage v_TBLT of the signal TBLT on the tracking bit line BLT, thereby adjusting (or manipulating) the waveform of the signal TBLT. In some embodiments, the number of NFETs in the BL adjustment circuit 122 is substantially equal to the number of NFETs included in a corresponding signal path (not shown) (e.g., a corresponding discharge path) in another portion of the memory device 200. The BL adjustment circuit 122 is configured to simulate the corresponding signal path (not shown). In some embodiments, the number of NFETs in the BL adjustment circuit 122 is proportional to the number of NFETs included in the corresponding signal path (not shown). In some embodiments, the number of tracking cells (e.g., 202) coupled to the tracking bit line BLT in the tracking array 102 is substantially equal to the number of rows in the memory array 116, i.e., substantially equal to N. For example, if the memory array 116 includes 256 rows such that N=256, then the tracking bit line BLT is coupled to a total of 256 tracking cells in the tracking array 102.

[0048] exist Figure 2 In some embodiments, tracking array 102 is used to estimate (or track) changes in voltage v_SBL of signal SBL on bit lines BL of memory array 116. During a read or write operation of memory array 116, a tracking operation occurs at tracking array 102. The tracking operation is applied to one of the tracking cells (e.g., 202) of tracking array 102. In some embodiments, more specifically, the tracking operation is applied to the tracking cells of tracking array 102 for compensating for operational and process variations that affect the read or write operation performed on memory array 116. In some embodiments, an average voltage drop of voltage v_TBLT of signal TBLT on tracking bit lines BLT is used as an estimate of the voltage drop of signal SBL on bit lines BL of memory array 116.

[0049] The BLT tracking circuit 104 is configured to detect a drop in the voltage v_TBLT of the signal TBLT on the tracking bit line BLT. In some embodiments, the BLT tracking circuit 104 includes a comparator (not shown) configured to compare the voltage v_TBLT of the signal TBLT on the tracking bit line BLT with a predetermined reference voltage. When the voltage v_TBLT reaches the predetermined reference voltage, the BLT tracking circuit 104 generates a control signal and outputs the control signal to the adjustment timer 106. In some embodiments, the BLT tracking circuit 104 generates the control signal by changing the logic state of the signal output from the BLT to the adjustment timer 106.

[0050] Figure 3is a timing diagram including waveforms according to some embodiments.

[0051] In Figure 3 it shows the performance of various waveforms during a read cycle and a write cycle, where the memory cells 206 of the memory array 116 are correspondingly selected. Regarding the read cycle, at the first moment t1, when the rising edge of the read clock signal (not shown) arrives, the WL driver 110(1) drives the word line WL. Therefore, the voltage v_DW on the signal DW starts to rise from the low voltage towards the voltage VDD. In addition, when the rising edge of the read clock signal (not shown) arrives, the TWL driver 110(2) drives the tracking word line TWL. Therefore, the voltage v_TWL on the tracking word line TWL starts to rise from the low voltage towards the voltage VDD.

[0052] Basically simultaneously, that is, basically at the first moment t1, the adjustment timer 106 changes the timing signal TMR from the logic low state to the logic high state. In response to the timing signal TMR changing to the logic high state basically at the first moment t1, each of the adjustment circuits 108(1) and 108(2) conducts. More specifically, in response to the timing signal TMR changing to the logic high state basically at the first moment t1, the NFET N3 conducts and pulls the voltage v_DW of the signal DW on the word line WL towards VSS, the effect of which is to limit the voltage v_DW from reaching the lower voltage LVDD1, where LVDD1 < VDD, ΔV1 = VDD - LVDD1, and 0 < ΔV1. Conducting the NFET N3 will hinder the voltage v_DW of the signal DW on the word line WL from reaching the voltage VDD by limiting the voltage v_DW at LVDD1 (although temporarily) while the NFET N3 is conducting. As a result, temporarily when the NFET N3 conducts, the voltage v_DW of the signal DW on the word line WL rises to the voltage LVDD1 but is hindered from rising above the voltage LVDD1. Similarly in response to the timing signal TMR changing to the logic high state basically at the first moment t1, the NFET N4 conducts and pulls the voltage v_EMU of the analog signal EMU on the tracking word line TWL towards VSS, the effect of which is to limit the voltage v_EMU from reaching the lower voltage LVDD2, where LVDD2 < VDD, ΔV2 = VDD - LVDD2, 0 < ΔV2, LVDD2 ≈ LVDD1, so ΔV2 ≈ ΔV1. The value of LVDD2 achievable using the adjustment circuit 108(2) varies depending on the region where the adjustment circuit 108(2) is located ( Figure 4A-4C). Turning on NFET N4 prevents the voltage v_EMU of signal EMU from reaching voltage VDD by limiting voltage v_EMU to LVDD2 (albeit temporarily) while NFET N4 is turned on. As a result, during the read cycle and temporarily while NFET N4 is turned on, voltage v_EMU on tracking word line TWL rises to voltage LVDD2 but is prevented from rising above voltage LVDD2.

[0053] Although temporarily limited to a relatively low voltage LVDD1, the voltage v_DW of the signal DW on the word line WL is sufficient to turn on the pass gate transistors N13 and N14 of the memory cell 206. The advantage of using LVDD1 instead of VDD to turn on the pass gates N13 and N14 is that the power consumption during the read operation is reduced compared to the case where the corresponding memory device does not include the adjustment circuit 108 (1). The memory device of the other method that does not include the corresponding portion of the adjustment circuit 108 (2) will generate a signal on the corresponding tracking word line, which has a voltage VDD between the times t1 and t2 of the read cycle, that is, the voltage mismatch between the signal on the corresponding tracking word line generated and the signal on the corresponding word line is ΔV2 (mismatch ΔV2) between the times t1 and t2 of the read cycle. The voltage mismatch ΔV2 suffered by the other method between the times t1 and t2 of the read cycle reduces the accuracy of the simulation of the signal on the corresponding tracking word line by the corresponding tracking word line. An advantage of including adjustment circuit 108(2) in memory device 200 is that simulation of word line WL by tracking word line TWL is more accurate than other approaches, for example, because voltage mismatch ΔV2 is not suffered, i.e., voltage mismatch ΔV2 is avoided between times t1 and t2 of the read cycle. The simulation accuracy of signal EMU (output by tracking word line TWL) is improved because voltage v_EMU of analog signal EMU of tracking word line TWL is temporarily pulled toward VSS by adjustment circuit 108(2) in substantially the same manner as voltage v_DW of signal DW is temporarily pulled toward VSS by adjustment circuit 108(1).

[0054] exist Figure 3 In, as an example, it is assumed that the storage node nd1 of the memory cell 206 stores a logic 1 / logic high value, and the storage node nd2 of the memory cell 206 stores a logic 0 / logic low value correspondingly at the start of the read operation. Starting from the first time t1, the bit line BL starts to decrease in level because the logic low value stored at the storage node nd1 discharges the bit line BL via the turned-on transmission gate NFET N13, while the bit_bar line BLB does not decrease in level due to the logic high value stored at the node nd2. In some embodiments, the tracking unit 202 performs a read "0" operation in response to the leading edge of the read clock (not shown). Figure 3, the waveform of the signal TBLT on the tracking bit line BLT is similar to the waveform of the signal SBL on the bit line BL of the memory cell 206 because, as described above, the structure and parameters of the tracking cell 202 are substantially the same as those of the memory cells (e.g., 206) in the memory array 116.

[0055] In response to the read clock signal (not shown), the bias selector 112 ignores the timing signal TMR. Thus, the bias selector 112 does not respond to the change of the logic state timing signal TMR from the logic low state to the logic high state at substantially the first time t1. Instead, the bias selector 112 maintains the selection signal SEL at the logic low state during the read cycle.

[0056] exist Figure 3 In the embodiment, from the first time t1 to the second time t2, the voltage v_DW of the signal DW on the word line WL is limited to LVDD1. Similarly, from the first time t1 to the second time t2, the voltage v_EMU of the signal EMU on the word line TWL is limited to LVDD2.

[0057] At the second time t2, once the BLT tracking circuit 104 detects that the voltage v_TBLT of the signal TBLT on the tracking bit line BLT voltage reaches a predetermined threshold, the BLT tracking circuit 104 changes the state of the control signal output to the adjustment timer 106. In response to the change in the state of the control signal, the adjustment timer 106 changes the timing signal TMR from a logic high state to a logic low state. In response to the timing signal TMR having a logic low state, and substantially at the second time t2, the NFET N3 of the adjustment circuit 108 (1) is turned off. Once turned off, the NFET N3 no longer blocks the voltage v_DW of the signal DW on the word line WL from rising. Therefore, shortly after the second time t2, the voltage v_DW of the signal DW on the word line WL rises from LVDD1 to the voltage VDD.

[0058] Also in response to timing signal TMR having a logic low state, and substantially at second time t2, NFET N4 of adjustment circuit 108(2) is turned off. Once turned off, NFET N4 no longer blocks the rise in voltage v_EMU of analog signal EMU on tracking word line TWL. Therefore, shortly after second time t2, voltage v_EMU of signal EMU on tracking word line TWL rises from LVDD2 to voltage VDD.

[0059] like Figure 3As reflected, the advantage of including the adjustment circuit 108(2) in the memory device 200 is better avoidance of read disturbance. As shown in the waveforms representing the voltages on the storage nodes nd1 and nd2 respectively, as described above, by using the adjustment circuits 108(1) and 108(2), the read disturbance of the corresponding voltages on the storage nodes nd1 and nd2 is reduced, thereby better avoiding read disturbance.

[0060] After the read cycle and before the write cycle, each of the voltage v_BL of the signal BL on the bit line BL and the voltage v_BLB of the signal BLB on the bit line BLB is precharged to a logic high state. To expand on this example, assume that the write cycle will store / write a logic 0 / logic low value in the storage node nd1 of the memory cell 206 and correspondingly store / write a logic 1 / logic high value in the storage node nd2 of the memory cell 206.

[0061] exist Figure 3 In the embodiment, the write cycle starts at the third time t3. When the leading edge of the write clock signal (not shown) arrives, the WL driver 110 (1) drives the word line WL. Therefore, the voltage v_DW on the signal DW starts to rise from the low voltage to the voltage VDD. In addition, when the leading edge of the write clock signal (not shown) arrives, the TWL driver 110 (2) drives the tracking word line TWL. Therefore, the voltage v_TWL on the tracking word line TWL starts to rise from the low voltage to the voltage VDD.

[0062] Substantially simultaneously, i.e., essentially at the third time t3, the adjustment timer 106 changes the timing signal TMR from a logic low state to a logic high state. In response to the timing signal TMR changing to the logic high state essentially at the third time t3, each of the adjustment circuits 108(1) and 108(2) conducts. More specifically, in response to the logic high state of the timing signal TMR, the NFET N3 conducts and pulls the voltage v_DW of the signal DW on the word line WL towards VSS, the effect of which limits the rise of the voltage v_DW to a lower voltage LVDD1, where LVDD1 < VDD. Conducting the NFET N3 impedes the voltage v_DW of the signal DW from reaching the voltage VDD by limiting the voltage v_DW to LVDD1 (although temporarily) while the NFET N3 is conducting. As a result, temporarily when the NFET N3 is conducting, the voltage v_DW of the signal DW on the word line WL rises to the voltage LVDD1 but is impeded from rising above the voltage LVDD1. Also in response to the logic high state of the timing signal TMR, the NFET N4 conducts and pulls the voltage v_EMU of the analog signal EMU on the tracking word line TWL towards VSS, the effect of which limits the rise of the voltage v_EMU to a lower voltage LVDD2. Again, LVDD2 ≈ LVDD1, and the value of LVDD2 achievable using the adjustment circuit 108(2) varies depending on the region where the adjustment circuit 108(2) is located ( Figure 4A-4C ). Also in addition, LVDD2 < VDD, ΔV2 = VDD - LVDD2, 0 < ΔV2, so ΔV2 ≈ ΔV1. Conducting the NFET N4 impedes the voltage v_EMU of the signal EMU from reaching the voltage VDD by limiting the voltage v_EMU to LVDD2 (although temporarily) while the NFET N4 is conducting. As a result, during the write cycle and temporarily when the NFET N4 is conducting, the voltage v_EMU on the tracking word line TWL rises to the voltage LVDD2 but is impeded from rising above the voltage LVDD2.

[0063] In response to the WRITE clock signal (not shown), the bias selector 112 stops ignoring the timing signal TMR. In response to the timing signal TMR changing to a logic high state substantially at the third time t3, the bias selector 112 changes the selection signal SEL from a logic low state to a logic high state. In response to the change of the selection signal SEL to a logic high state, the multiplexer 114 changes the voltage coupled to the power rail CVDD, that is, stops coupling the voltage VDD to the power rail CVDD, and instead couples the write auxiliary voltage VWA to the power rail CVDD. When the write cycle is not experienced, the bias selector 112 maintains the selection signal SEL at a logic low state. Therefore, when the write cycle is not experienced, the multiplexer 114 is controlled to couple the voltage VDD instead of the voltage VWA to the power rail CVDD. The voltage VWA is less than the voltage VDD, that is, VWA<VDD. By coupling the power rail CVDD to a lower voltage during the write operation, the write operation can be performed faster and / or easier.

[0064] Although temporarily limited to a relatively low voltage LVDD1, the voltage v_DW of the signal DW on the word line WL is sufficient to turn on the transfer gate transistors N13 and N14 of the memory cell 206. The advantage of using LVDD1 instead of VDD to turn on the transfer gates N13 and N14 is that the power consumption of the write operation device is reduced compared to the case where the corresponding memory device does not include the adjustment circuit 108 (1). The memory device of the other method that does not include the corresponding part of the adjustment circuit 108 (2) will generate a signal on the corresponding tracking word line, which has a voltage VDD between the times t3 and t4 of the write cycle, that is, between the times t3 and t4 of the write cycle, the voltage mismatch between the signal on the corresponding tracking word line generated and the signal on the corresponding word line is ΔV2 (mismatch ΔV2). The voltage mismatch ΔV2 suffered by the other method between the times t3 and t4 of the write cycle reduces the accuracy of the simulation of the corresponding tracking word line of the signal on the corresponding word line. An advantage of including adjustment circuit 108(2) in memory device 200 is that simulation of word line WL by tracking word line TWL is more accurate than other approaches, for example, because voltage mismatch ΔV2 is not suffered, i.e., voltage mismatch ΔV2 is avoided between times t3 and t4 of the write cycle. The simulation accuracy of signal EMU (output by tracking word line TWL) is improved because voltage v_EMU of analog signal EMU of tracking word line TWL is temporarily pulled toward VSS by adjustment circuit 108(2) in substantially the same manner as voltage v_DW of signal DW is temporarily pulled toward VSS by adjustment circuit 108(1).

[0065] Returning to this example, to reset the logic state of memory cell 206 as part of a write cycle, the voltage v_BLB of bit_bar line BLB is set to a logic low state. In some embodiments, tracking unit 202 performs a read "0" operation in response to a leading edge of a write clock (not shown). Figure 3 In this embodiment, the voltage v_DW of the signal DW on the word line WL is maintained at LVDD1 until the fourth time t4.

[0066] Figure 3 , at a fourth time t4, once the BLT tracking circuit 104 detects that the voltage v_TBLT of the signal TBLT on the tracking bit line BLT reaches a predetermined threshold, the BLT tracking circuit 104 changes the state of the control signal output to the adjustment timer 106. In response to the change in the state of the control signal, the adjustment timer 106 changes the timing signal TMR from a logic high state to a logic low state substantially at the fourth time t4. In response to the timing signal TMR having a logic low state, and substantially at the fourth time t4, the NFET N3 of the adjustment circuit 108 (1) is turned off. Once turned off, the NFET N3 no longer blocks the voltage v_DW of the signal DW on the word line WL from rising. Therefore, shortly after the fourth time t4, the voltage v_DW of the signal DW on the word line WL rises from LVDD1 to the voltage VDD.

[0067] Also in response to timing signal TMR having a logic low state, and substantially at fourth time t4, NFET N4 of adjustment circuit 108(2) is turned off. Once turned off, NFET N4 no longer blocks the voltage v_EMU of analog signal EMU on tracking word line TWL from rising. Therefore, shortly after fourth time t4, voltage v_EMU of signal EMU on tracking word line TWL rises from LVDD2 to voltage VDD.

[0068] In addition, in a delayed response to the timing signal TMR changing from a logic high state to a logic low state, and substantially at a fifth time instant t5, the bias selector 112 changes the select signal SEL from a logic high state to a logic low state. The time elapsed between the fourth time instant t4 and the fifth time instant t5 is represented by a delay 324. In response to the change of the select signal SEL to a logic low state, the multiplexer 114 changes the voltage coupled to the power rail CVDD, i.e., stops coupling the write assist voltage VWA to the power rail CVDD, and instead couples the voltage VDD to the power rail CVDD.

[0069] The bias selector 112 is configured to generate two different versions of the selection signal SEL according to whether the write operation is a high-speed type of write operation or a low-speed type of write operation.

[0070] Figure 3Assume that the write cycle is based on a high-speed SRAM operation. More specifically, when the write operation is of a higher speed type (and therefore of a higher power consumption type), the bias selector 112 generates a relatively wider / longer version of the selection signal SEL because the state of the selection signal SEL changes to a logic high state at the fourth time t4. On the other hand, when the write operation is of a slower speed type (and therefore of a lower power consumption type), the bias selector 112 generates a relatively narrower / shorter version of the selection signal SEL by waiting to change the state of the selection signal SEL to a logic high state until the fifth time t5. This delay in changing the state of the selection signal SEL is Figure 3 Delay 326 is shown in phantom / dashed line in FIG.

[0071] Figure 4A-4C are corresponding plan views 430A-430C according to some embodiments.

[0072] More specifically, each of the layout diagrams 430A-430C represents an orthogonal projection of a corresponding memory device onto a reference plane (eg, a plane defined by an X-axis and a Y-axis). Figure 4A-4C Each of the memory devices is Figure 1 An example of a memory device 100 of the present invention, although some components of the memory device 100 are not shown in FIG. Figure 4A-4C 430A-430C. Thus, each of the layout diagrams 430A-430C represents a corresponding memory device. The structure in the memory device is represented by the pattern (also referred to as shape) in the layout diagrams 430A-430C. For simplicity of discussion, the elements in each of the layout diagrams 430A-430C will be referred to as if they are structures rather than patterns themselves. The memory devices corresponding to the layout diagrams 430A-430C are examples of the memory device 100, the memory device 200, etc.

[0073] Each of the layout diagrams 430A-430C is arranged into zones (areas) that do not overlap one another and include: a bit cell region 432; a main input / output (I / O) region 434A / B / C; a main controller region 436A / B / C; and a word line driver region 438A / B / C. Each such region is contiguous and is generally defined by the components / circuits located therein, as described below.

[0074] exist Figure 4A-4CIn each of the 400 devices: the memory array 116, the tracking array 102, and the BL adjustment circuit 122 are located in the bit cell region 432; the tracking line TWL is located in the main I / O region 434A / B / C; the TWL driver 110(2) and the adjustment timer 106 are located in the main controller region 436A / B / C; and the WL driver 110(1) and the adjustment circuit 108(1) are located in the word line driver region 438A / B / C. In contrast, the adjustment circuit 408(2) is located in the corresponding Figure 4A-4C 4(2), wherein adjustment circuit 408(2) is an example of adjustment circuit 108(2). Typically, main I / O region 434A / B / C additionally includes I / O components / circuits through which the corresponding memory device communicates with other components / devices that do not include the corresponding memory device. In some embodiments, main controller region 436A / B / C additionally includes address decoders, such as row decoders and column decoders, etc. In some embodiments, main controller region 436A / B / C additionally includes sense amplifiers, etc. In some embodiments, main controller region 436A / B / C additionally includes timing control circuits other than adjustment timer 106. In some embodiments, BL adjustment circuit 122 is located in main controller region 436A / B / C. In some embodiments, BL adjustment circuit 122 is located in a region other than bit cell region 432 or main controller region 436A / B / C.

[0075] exist Figure 4A-4B In each of the , adjustment circuit 408(2) is located in a different non-overlapping region, where adjustment circuit 408(2) is an example of adjustment circuit 108(2). The value of LVDD2 that can be achieved using adjustment circuit 408(2) varies depending on the region in which adjustment circuit 408(2) is located.

[0076] exist Figure 4A In the layout diagram 430A of FIG. 430A, in addition to the TWL driver 110 (2) and the adjustment timer 106, the adjustment circuit 408 (2) is also located in the main controller area 436A. Figure 4A In the example, the adjustment circuit 408 ( 2 ) and the adjustment circuit 408 ( 1 ) are not in the same region, that is, they are not in the same region.

[0077] exist Figure 4B In the layout diagram 430B of FIG. 430A , in addition to the tracking line TWL, the adjustment circuit 408 ( 2 ) is also located in the main I / O area 434B. Figure 4B In the example, the adjustment circuit 408 (2) and the adjustment circuit 408 (1) are not in the same region, that is, they are not in the same region. Figure 4BIn FIG. 4 , the adjustment circuit 408 ( 2 ) and the tracking line TWL are in the same area, namely, the main I / O area 434B.

[0078] exist Figure 4C In the layout diagram 430C of FIG. 430A , in addition to the WL driver 110 ( 1 ) and the adjustment circuit 408 ( 1 ), the adjustment circuit 408 ( 2 ) is also located in the word line driver region 438C. Figure 4C In FIG. 4 , the adjustment circuit 408 ( 2 ) and the adjustment circuit 408 ( 1 ) are located in the same region, namely, the word line driver region 438C.

[0079] It should be recalled that LVDD2 is the word line WL asserted by WL driver 110(1) ( Figure 2 ) on the signal DW( Figure 2-Figure 3 ) of the voltage v_DW, and generally lower LVDD2 values ​​help reduce the power consumption of the corresponding memory device. The LVDD2 ( Figure 3 ) is based in part on the region ( Figure 4A-4C ) Figure 4C The LVDD2 value (LVDD2_430C) achievable by the layout diagram 430C is lower (less than) than that achieved by using Figure 4B The layout diagram 430B can realize the value of LVDD2 (LVDD2_430B), so that LVDD2_430C < LVDD2_430B. Figure 4B The LVDD2 value achievable by layout diagram 430B is lower (less than) than that achieved by using Figure 4A The layout diagram 430A can realize the value of LVDD2 (LVDD2_430A) such that LVDD2_430B < LVDD2_430A. In general, LVDD2_430C <LVDD2_430B<LVDD2_430A。

[0080] Since LVDD2_430B<LVDD2_430A, the power consumption (pw_430B) of the memory device having the layout diagram 430B is lower (smaller) than the power consumption (pw_430A) of the memory device having the layout diagram 430A, so that pw_430B<pw_430A. Since LVDD2_430C<LVDD2_430B, the power consumption (pw_430C) of the memory device having the layout diagram 430C is lower (smaller) than the power consumption (pw_430B) of the memory device having the layout diagram 430B, so that pw_430C<pw_430B. In general, pw_430C<pw_430B<pw_430A.

[0081] Recall that ΔV2 = VDD-LVDD2, using Figure 4A The ΔV2 value (ΔV2_430A) achievable with the layout 430A is less than that achieved with Figure 4B The layout diagram 430B can realize a ΔV2 value (ΔV2_430B) such that ΔV2_430A<ΔV2_430B. Figure 4B The ΔV2 value achievable by the layout diagram 430B is less than that achieved by using Figure 4C The layout diagram 430C can realize a value of ΔV2 (ΔV2_430C) such that ΔV2_430B<ΔV2_430C. In general, ΔV2_430A<ΔV2_430B<ΔV2_430C.

[0082] Figure 4D is a layout diagram of a portion 454 of a memory device according to some embodiments.

[0083] about Figure 4D The layout diagram of FIG. 454 shows a semiconductor device (as shown by the broken line 455), which is more specifically a memory device. Examples of the memory device shown in the layout diagram of the portion 454 include Figure 1 A memory device 100, Figure 2 The memory device 200, corresponding Figure 4A-4C Memory devices 430A-430C, etc.

[0084] Typically, a layout diagram represents a semiconductor device. The shapes in the layout diagram represent corresponding components in the semiconductor device. The layout diagram itself is a top view. The shapes in the layout diagram are two-dimensional relative to, for example, the X-axis and the Y-axis, while the represented semiconductor device is three-dimensional. Typically, the semiconductor device is organized as a stack of layers relative to the Z-axis, and the corresponding structure is located in the stack of layers, that is, the corresponding structure belongs to the stack of layers. Therefore, each shape in the layout diagram more specifically represents a component in a corresponding layer of the corresponding semiconductor device. Typically, the layout diagram represents the relative depth of the shape, that is, the position along the Z-axis, and therefore represents a layer by superimposing a second shape on a first shape so that the second shape at least partially overlaps the first shape. For simplicity of discussion, that is, for ease of discussion, the layout diagram is located in the top view. Figure 4D Some elements in are referred to as if they were corresponding structures in the corresponding semiconductor device rather than the patterns / shapes themselves. For example, element 460(2) is referred to as gate structure 460(2) rather than gate pattern 460(2).

[0085] The layout diagrams vary in the amount of detail represented. In some cases, selected layers of the layout diagrams are combined / abstracted into a single layer, for example, for the purpose of simplicity. Alternatively and / or additionally, in some cases, not all layers of the corresponding semiconductor device or components therein are shown, i.e., selected layers of the layout diagrams are omitted, for example, for the purpose of simplifying the illustration. For example, Figure 4DThe vias to the M1 (V1) structure, the M2 section in the third metallization layer (M2nd layer), etc. are omitted.

[0086] exist Figure 4D In the active region (AR) layer 575(1)( Figure 5A-Figure 5B ), the illustrated portion 454 of the memory device (hereinafter referred to as "portion 454") includes ARs 456B and 458B extending along a first direction (e.g., parallel to the X-axis). AR 456B has a first type of conductivity, and AR 458B has a different second type of conductivity. Figure 4D In the embodiment, it is assumed that the first conductivity type is a positive (P-type) conductivity type suitable for a PMOS transistor; the second conductivity type is a negative (N-type) conductivity type suitable for an NMOS transistor. In some embodiments, alternatively, the first conductivity type is a negative (N-type) conductivity type and the second conductivity type is a positive (P-type) conductivity type.

[0087] exist Figure 4D In GMD layer 575(4)( Figure 5A-Figure 5B ), portion 454 of the memory device also includes gate structures 460(1)-460(4) and metal-to-drain / source (MD) structures 462(1)-462(6) extending along a second direction perpendicular to the first direction, for example, the second direction is parallel to the Y axis. In some embodiments, the first direction and the second direction are Cartesian axes rather than being parallel to the X axis and the Y axis, respectively. Gate structures 460(2) and 460(3) are substantially collinear. MD structures 462(1) and 462(2) are substantially collinear. MD structures 462(3) and 462(4) are substantially collinear. MD structures 462(5) and 462(6) are substantially collinear. Relative to the X axis, the position of gate structure 460(x) alternates with respect to MD structure 462(x). For example, with respect to the X-axis, gate structure 460(1) is located between (A) substantially collinear MD structures 462(1) and 462(2) and (B) substantially collinear MD structures 462(3) and 462(4). For example, substantially collinear MD structures 462(3) and 462(4) are located between (A) gate structure 460(1) and (B) substantially collinear gate structures 460(2) and 460(3).

[0088] exist Figure 4D In the embodiment, the VGD layer 575(5) ( Figure 5A-Figure 5B), the portion 454 of the memory device also includes a via-to-gate (VG) structure 464 and a via-to-MD (VD) structure 466 located above corresponding structures in the gate structures 460 (1)-460 (4) and the MD structures 462 (1)-462 (6). The portion 454 of the memory device is arranged according to a grid (the grid includes reference lines referred to as alpha tracks α1, α2, α3, α4, α5 and α6) and extends in a direction parallel to the X-axis. With respect to the Y-axis, the VG structure 464 and the VD structure 466 are aligned corresponding to the alpha tracks α2-α6. For example, an instance of the VG structure 464 under the M0 segment 468 (9) is aligned with the alpha track α4, an instance of the VD structure 466 under the M0 segment 468 (12) is aligned with the alpha track α5, and so on. In portion 454 of the memory device, neither the instance of VG structure 464 nor the instance of VD structure 466 is above alpha orbit α1.

[0089] exist Figure 4D In the embodiment, the first metallization layer (M*1st layer) 575(4) ( Figure 5A-Figure 5B ), portion 454 of the memory device also includes M*1st segments 468(1)-468(13), which extend parallel to the X-axis, are aligned with alpha tracks α1-α6, respectively, and are therefore located above corresponding structures in VG structure 464 and VD structure 466. With respect to the Y-axis: The distance between adjacent alpha tracks is an example of a unit of measurement called track pitch (TP).

[0090] exist Figure 4D 468(1)-468(13). In some embodiments, according to the numbering convention of the corresponding process node (whereby the portion 454 of the memory device corresponds to Figure 4C and Figure 5A-5B ), the M*1st layer is the metallization layer one (M1) and correspondingly the VIA*1st layer is the interconnect layer one (V1).

[0091] With respect to the X-axis, gate structures 460(1)-460(4) are spaced apart from each other at uniform distances. Figure 4D In this context, the uniform distance represents a contact poly pitch (CPP) corresponding to a semiconductor process technology node. Here, the term “poly” in CPP does not necessarily mean a corresponding Figure 4DThe gate structures in semiconductor devices of the present invention will be formed of polysilicon, but rather represent a historical convenience, namely because gate structures in ICs manufactured according to previous semiconductor process technology nodes are often formed of polysilicon.

[0092] exist Figure 4D , portion 454 also includes a first interconnect layer (VIA*1st) layer 575(5)( Figure 5A-Figure 5B ), which is referred to herein as V0 layer 575(5) according to an assumed naming convention, and which is located above M0 layer 575(4). In V0 layer 575(5), portion 454 also includes an instance of a via-to-M*1 (VIA*1st) structure, namely a via-to-M0 (V0) structure 470 located above a corresponding segment of M0 segments 468(9), 468(10), and 468(13). With respect to the Y-axis, V0 structure 470 is substantially aligned with the long axis of the corresponding M0 segment 468(9), 468(10), and 468(13).

[0093] Portion 454 also includes a second metallization layer (M*2nd layer) 575(6) ( Figure 5A-Figure 5B ), which is referred to herein as M1 layer 575(6) according to an assumed naming convention, and which is located above V0 layer 575(5). In M1 layer 575(6), portion 454 also includes M*2nd segments, namely M1 segments 472(1)-472(2) extending parallel to the Y axis and located above corresponding structures in V0 structure 470.

[0094] Among them, NFET N4 ( Figure 2 and Figures 4A-4C ) is shown in portion 454. NFET N4 is coupled between: M0 segment 468 (12), which is coupled to analog signal EMU ( Figure 2-Figure 3 ); M0 segment 468 (13), which is coupled to voltage VSS ( Figure 2 ). The gate terminal of NFET N4 is coupled to M1 segment 472(1), which is coupled to timing signal TMR( Figure 2-Figure 3 ).

[0095] Figure 5A-Figure 5B According to some embodiments Figure 4C Corresponding cross sections 574A and 574B of portion 454 .

[0096] Sections 574A-574B follow the Figure 4C The numbering scheme is similar to the layout diagram of section 454. Although some components correspond, there are also differences in these components. To help identify corresponding but still different components, the numbering convention uses a 5 series number for sections 574A-574B and Figure 4CUse 4 series of numbers. For example, Figure 5A-Figure 5B The MD structure 562(4) in corresponds to Figure 4C The MD structure 462(4) in , their similarity is that they are both represented by _62(4), while the difference is reflected in the corresponding leading digits (5 or 4). For the sake of brevity, the discussion will focus more on Figure 5A-Figure 5B and Figure 4C differences, not similarities.

[0097] about Figure 5A , section 574A corresponds to Figure 4C Section line 5A-5A' in. Figure 5B , section 574B corresponds to Figure 4C Section line 5B-5B' in FIG. Figure 5A-Figure 5B Each of includes layers 575(1)-575(6).

[0098] exist Figure 5A-Figure 5B In each of the AR layers 575(1) includes an AR 558. Figure 5A-Figure 5B In each of the GMD layers 575(3), the GMD layer 575(3) includes a gate structure 560(3) and MD structures 562(4) and 562(6). Figure 5A , VGD layer 575(3) includes an instance of VG structure 564 and an instance of VD structure 566. Figure 5B , VGD layer 575(3) includes an instance of VD structure 566. Figure 5A In FIG. 5 , M0 layer 574(4) includes M0 segments 568(9) and 568(10). Figure 5B In FIG. 5 , M0 layer 574 (4) includes M0 segment 568 (12). Figure 5A , V0 layer 575(5) includes an instance of V0 structure 570. Figure 5A In FIG. 5 , M1 layer 575(6) includes M1 segments 572(1) and 572(2). Figure 5B , the M1 layer 575(6) includes the M1 segment 572(2).

[0099] Fig. 6A is a flow chart 600 of a method of manufacturing a memory device according to some embodiments.

[0100] According to some embodiments, the method of flowchart (flow chart) 600 may be implemented, for example, using EDA system 800 ( Figure 8 , discussed below) and IC manufacturing system 900 ( Fig. 9 , discussed below). Examples of semiconductor devices that can be manufactured based on the method of flowchart 600 include Figure 1-2 Semiconductor devices based on Figures 4A-4CA semiconductor device based on the layout diagram disclosed in this article, a semiconductor device based on the cross-section disclosed in this article, etc.

[0101] In FIG6 , the method of flowchart 600 includes blocks 602-604. In block 602, a layout diagram is generated, which may include, among other things, one or more layout diagrams disclosed herein. According to some embodiments, block 602 may be performed using, for example, EDA system 800 ( Figure 8 , discussed below). The process proceeds from block 602 to block 604.

[0102] At block 604, based on the layout diagram, at least one of the following is performed: (A) performing one or more photolithography exposures, or (B) manufacturing one or more semiconductor masks, or (C) manufacturing one or more components in a layer of a semiconductor device. Fig. 9 Discussion of IC manufacturing system 900 in FIG.

[0103] Figure 6B is a flow chart 605 of a method of manufacturing a semiconductor device, and more particularly a memory device, according to some embodiments.

[0104] Flowchart 605 is Fig. 6A 604 of the example. Flowchart 605 includes blocks 606-622. According to some embodiments, the method of flowchart 605 may be performed using, for example, IC manufacturing system 900 ( Fig. 9 , discussed below). Examples of semiconductor devices that can be manufactured according to the method of flowchart 600 include Figure 1-Figure 2 Semiconductor devices based on Figures 4A-4C A semiconductor device based on the layout diagram disclosed in this article, a semiconductor device based on the cross-section disclosed in this article, etc.

[0105] exist Figure 6B In block 606, an active region (AR) is formed in the substrate including corresponding doped regions of the substrate. Examples of active regions include Figure 4D AR 456 and 458, Figure 5A-Figure 5B AR 558, etc. Flow proceeds from box 606 to box 608.

[0106] At block 608, source / drain (S / D) regions representing a first transistor component (TC) are formed in the AR including corresponding first corresponding doped regions of the active region, wherein a second region of the AR between the corresponding S / D regions is a channel region representing a second TC. Examples of S / D regions include correspondingly located Figure 5A-Figure 5BThe portion of AR 558 below the MD structures 562 ( 4 ), 562 ( 6 ), etc. Examples of channel regions include the portion of AR 558 between the example S / D regions mentioned, etc. Flow proceeds from block 608 to block 610 .

[0107] At block 610, a gate structure representing a third TC is formed in a gate and MD (GMD) layer over a corresponding active region, and more specifically over a corresponding channel region. An example of a GMD layer is Figure 5A-Figure 5B The GMD layer 575(2) of the gate structure includes Figure 4D The gate structures 460(1)-460(4) Figure 5A-Figure 5B The gate structure 560 (3), etc. From block 610, the process proceeds to block 612.

[0108] At block 612, a metal-to-S / D (MD) contact structure representing a fourth TC is formed in the GMD layer over the corresponding S / D region. Examples of MD structures include Figure 4D MD structure 462(1)-462(6), Figure 5A-Figure 5B MD structures 562(4) and 562(6), etc. Flow proceeds from block 612 to block 614.

[0109] At block 614, a via-to-gate / MD (VGD) structure is formed over corresponding structures in the gate structure and the MD contact structure. The VGD structure includes two types, namely, a via-to-gate (VG) structure and a via-to-MD (VD) structure. Examples of VG structure types of VGD structures include Figure 4D VG structure 464, Figure 5A Examples of VG structures 564, etc. in FIG. 5A and 5B are examples of VGD structures of the VD structure type. Figure 4D VD structure 466, Figure 5A-Figure 5B Flow proceeds from block 614 to block 616.

[0110] With respect to an orthogonal projection of the memory device (formed by the method of flowchart 605) onto a reference plane, the memory device is arranged into non-overlapping regions, which include: a bit cell region (e.g., Figure 4A-4C 432); main input / output (I / O) area (e.g., corresponding Figure 4A-4C 434A / B / C); main controller area (for example, corresponding Figure 4A-4C 436A / B / C); and word line driver regions (eg, corresponding Figure 4A-4C 438A / B / C).

[0111] about Figure 6BIn some embodiments, the active region of block 606, the S / D region and corresponding channel region of block 608, the gate structure of block 610, the MD contact structure of block 612, and the VGD structure of block 614 are formed so that the VGD structure electrically couples the first transistor to the corresponding group in the fourth transistor assembly as shown below: The first group, as a bit cell region (e.g., Figure 4A-4C 432) of a first array (e.g., 116) of memory cells (e.g., 206); a second group, as a bit cell region (e.g., Figure 4A-4C a second array (e.g., 102) of tracking cells (e.g., 202) in a bit cell region (e.g., 432) and configured to emulate the first array (e.g., 116); a third group as a first adjustment circuit (e.g., 108(1)) in a word line driver region (e.g., 438x); a fourth group as a second adjustment circuit (e.g., 108(2)) located in one of the non-overlapping regions other than the bit cell region (e.g., 432); and a fifth group as an adjustment timing circuit (e.g., 106) in a master controller region (e.g., 436x) and coupled to each of the first adjustment circuit (e.g., 108(1)) and the second adjustment circuit (e.g., 108(2)).

[0112] At block 616, metallization segments in corresponding metallization layers and interconnect structures in corresponding interconnect layers are formed based on the staggered layers. Examples of metallization layers are discussed below. Examples of interconnect layers are discussed below. Within block 616, the flow proceeds to block 618.

[0113] At block 618, M*1st metallization segments in a first metallization layer are formed over corresponding instances of the VGD structure. An example of a first metallization layer is Figure 5A-Figure 5B M0 layer 575(4), etc. Examples of M*1st metallization segments include Figure 4C M0 segment 468(1)-468(13), Figure 5A M0 segments 568(9) and 568(10), Figure 5B M0 segment 568 (12), etc. Flow proceeds from block 618 to block 620.

[0114] At block 620, a V*1st interconnect structure is formed in the first interconnect layer and over corresponding ones of the M*1st metallization segments. An example of a first interconnect layer is Figure 5A-Figure 5B V0 layer 575(5), etc. Examples of V*1st interconnect structures include Figure 4C V0 structure 470, Figure 5B , etc. Flow proceeds from block 620 to block 622.

[0115] At block 622, M*2nd metallization segments are formed in a second metallization layer over corresponding instances of the VGD structure. An example of a second metallization layer is Figure 5A-Figure 5B M1 layer 575 (6), etc. Examples of M*2nd metallization segments include Figure 4C M1 section 472(1)-472(2), Figure 5A-Figure 5B M1 segments 572(1) and 572(2), etc.

[0116] In some embodiments, forming the metallization segments and interconnect structures of block 616 results in the following: a first word line (eg, word line WL) located in a bit cell region (eg, Figure 4A-4C 432 of the first array (e.g., 116), and coupled to the memory cells (e.g., 206) and the tracking cells (e.g., 202) in a corresponding row of the first array (e.g., 116); a bit line (e.g., bit line BL) coupled to the memory cells in the memory cells (e.g., 206) in a corresponding column of the first array (e.g., 116); and a second word line (e.g., tracking word line TWL) located in the main I / O region (e.g., 434A / B / C or corresponding Figure 4A-4C ), and is configured to emulate a first word line (e.g., word line WL). In some embodiments, a fourth group representing the second adjustment circuit (108(2)) is located in the main controller region (436A). In some embodiments, a fourth group representing the second adjustment circuit (108(2)) is located in the main I / O region (434B). In some embodiments, a fourth group representing the second adjustment circuit (108(2)) is located in the word line driver region (438C).

[0117] In some embodiments, metallization segments and interconnect structures are formed to electrically couple the following items, including: coupling a first adjustment circuit (e.g., 108(1)) between a second word line (e.g., TWL) and a bit line (e.g., BL); coupling a second adjustment circuit (e.g., 108(2)) to the second word line (e.g., TWL); coupling an adjustment timing circuit (e.g., 106) to each of the second adjustment circuits (e.g., 108(2)).

[0118] Figure 7 is a flowchart 700 of a method of operating a memory device according to some embodiments.

[0119] Examples of memory devices operating according to flowchart 700 include Figure 1 , Figure 2 , Figure 4A-4C etc. memory devices.

[0120] Flowchart 700 includes blocks 702-718. At block 702, an active edge of an enable signal is received at a word line driver and an adjustment timer. Examples of enable signals include Figure 3 The flow proceeds from block 702 to block 704 .

[0121] At block 704, a first voltage on a first word line is raised to a first reference voltage. An example of a first word line is Figure 1-Figure 2 The word line WL, etc. An example of the first voltage is Figure 3 The voltage v_DW of the signal DW on the word line WL mentioned in the discussion of etc. An example of the first reference voltage is Figure 3 The flow proceeds from block 704 to block 706 .

[0122] At block 706, a second voltage on the second word line is raised to a first reference voltage. An example of a second word line is Figure 1-Figure 2 The tracking word line TWL, etc. An example of the second voltage is Figure 3 The flow proceeds from block 706 to block 708 .

[0123] At block 708, the first voltage is prevented from substantially reaching the first reference voltage. Block 708 includes block 710. An example of the first voltage is Figure 1-Figure 2 , Figure 4A-4C The voltage v_DW of the signal DW on the word line WL is, for example, v_DW. In block 710, an example of preventing the first voltage from reaching the first reference voltage is turning on the first adjustment circuit. An example of the first adjustment circuit is Figure 1-Figure 2 , Figure 4A-4C The adjustment circuit 108 (1) of FIG. 1 includes a pull-down transistor NFET N3. When turned on, NFET N3 pulls the voltage v_DW of the signal DW on the word line WL toward the reference voltage VSS, which is a more detailed example of preventing the first voltage from substantially reaching the first reference voltage. The process exits block 708 from block 710 and proceeds to block 712.

[0124] At block 712, the second voltage is prevented from substantially reaching the first reference voltage. An example of the second voltage is Figure 1-Figure 2 , Figure 4A-4C The voltage v_EMU of the signal EMU on the word line TWL is 0. Block 712 includes block 714. At block 714, the second adjustment circuit is turned on. An example of preventing the second voltage from reaching the second reference voltage is turning on the second adjustment circuit. An example of the second adjustment circuit is Figure 1-Figure 2 , Figure 4A-4C The adjustment circuit 108 (2) of FIG. 1 includes a pull-down transistor NFET N4. When turned on, NFET N4 pulls the voltage v_EMU of the signal EMU on the tracking word line TWL toward the reference voltage VSS, which is a more detailed example of preventing the second voltage from substantially reaching the first reference voltage. The process exits block 712 from block 714 and proceeds to block 716.

[0125] At block 716, a detection condition is that a third voltage on a first bit line has reached a predetermined value. Examples of the third voltage are Figure 2 the voltage v_TLBT of the signal TBLT on the tracking bit line TBL such as Figure 1-Figure 2 the operation of the BLT tracking circuit 104 such as

[0126] At block 718, each of the first adjustment circuit and the second adjustment circuit is turned off. Examples of the first adjustment circuit and the second adjustment circuit include Figure 1-Figure 2 and Figure 4A-4C the corresponding adjustment circuits 108(1) and 108(2) such as Figure 3 the discussion about the second time t2 and the fourth time t4 such as

[0127] In some embodiments, blocks 702 - 718 are performed as part of a read operation. For example, in Figure 3 the context of the discussion about the first time t1 and the second time t2 such as Figure 3 the examples of the read operation. In some embodiments, blocks 702 - 718 are performed as part of a write operation. For example, in

[0128] In some embodiments where blocks 702 - 718 are performed as part of a write operation, the method further includes: after the active edge of the received write operation start signal, applying a write adjustment voltage VWA (e.g., Figure 2-Figure 3 the voltage VWA such as

[0129] Figure 1-Figure 2 as the positive power supply voltage CVDD of a first array (e.g., 116), such that CVDD = VWA. In such embodiments, for a larger system including the first array (e.g., 116), the write adjustment voltage VWA is less than the reference power supply voltage VDD; where VWA < VDD; and where CVDD < VDD. In such embodiments where blocks 702 - 718 are performed as part of a write operation, the method further includes applying the reference power supply voltage VDD as the positive power supply voltage CVDD such that CVDD = VDD at a predetermined time after applying the write adjustment voltage VWA. 、 Figure 4A-4C114) to select the write adjustment voltage VWA instead of the reference power supply voltage VDD as the positive power supply voltage CVDD.

[0130] Figure 8 is a block diagram of an electronic design automation (EDA) system 800 according to some embodiments.

[0131] In some embodiments, the EDA system 800 includes an automatic placement and routing (APR) system. In some embodiments, the EDA system 800 is a general purpose computing device that includes a hardware processor 802 and a non-transitory computer-readable storage medium 804. The storage medium 804 is encoded with (i.e., stores) computer program code 806 (i.e., a set of executable instructions). The execution of the instructions 806 by the hardware processor 802 (at least in part) represents an EDA tool that implements part or all of the following methods according to one or more embodiments (hereinafter, referred to as the indicated processes and / or methods): for example, the method of FIG. 5 (block 502), generating such as Figure 2 Method for generating a layout diagram corresponding to Figure 1 The storage medium 804 particularly stores a layout diagram 811, such as the layout diagram disclosed herein.

[0132] The processor 802 is electrically coupled to the computer-readable storage medium 804 via a bus 808. The processor 802 is also electrically coupled to an I / O interface 810 via the bus 808. A network interface 812 is also electrically connected to the processor 802 via the bus 808. The network interface 812 is connected to a network 814 so that the processor 802 and the computer-readable storage medium 804 can be connected to external elements via the network 814. The processor 802 is configured to execute a computer program code 806 encoded in the computer-readable storage medium 804 so that the system 800 can be used to perform part or all of the processes and / or methods mentioned. In one or more embodiments, the processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0133] In one or more embodiments, the computer-readable storage medium 804 is an electrical, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 804 includes a semiconductor or solid-state memory, a magnetic tape, a removable computer floppy disk, a random access memory (RAM), a read-only memory (ROM), a hard disk, and / or an optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 804 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0134] In one or more embodiments, the storage medium 804 stores computer program code 806, which is configured to enable the system 800 (where such execution represents (at least in part) an EDA tool) to be used to perform some or all of the processes and / or methods mentioned. In one or more embodiments, the storage medium 804 also stores information that facilitates the execution of some or all of the processes and / or methods mentioned. In one or more embodiments, the storage medium 804 stores a standard cell library 807 including such standard cells disclosed herein. In some embodiments, the storage medium 804 stores one or more layout diagrams 811.

[0135] The EDA system 800 includes an I / O interface 810. The I / O interface 810 is coupled to an external circuit. In one or more embodiments, the I / O interface 810 includes a keyboard, a key, a mouse, a trackball, a trackpad, a touch screen, and / or a cursor direction key for transmitting information and commands to the processor 802.

[0136] The EDA system 800 also includes a network interface 812 coupled to the processor 802. The network interface 812 allows the system 800 to communicate with a network 814 to which one or more other computer systems are connected. The network interface 812 includes a wireless network interface, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and / or methods mentioned are implemented in two or more systems 800.

[0137] The system 800 is configured to receive information through the I / O interface 810. The information received through the I / O interface 810 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 802. The information is transmitted to the processor 802 via the bus 808. The EDA system 800 is configured to receive information related to a user interface (UI) through the I / O interface 810. The information is stored in the computer readable medium 804 as the UI 842.

[0138] In some embodiments, some or all of the processes and / or methods mentioned are implemented as a standalone software application for execution by a processor. In some embodiments, some or all of the processes and / or methods mentioned are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the processes and / or methods mentioned are implemented as a plug-in for a software application. In some embodiments, at least one of the processes and / or methods mentioned is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the processes and / or methods mentioned are implemented as a software application used by the EDA system 800. In some embodiments, the system 800 is implemented using a software application such as the one from CADENCE DESIGN SYSTEMS, Inc. or other suitable layout generation tools to generate a layout including standard cells.

[0139] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more of the following: optical disks (e.g., DVD, DVD); magnetic disks, such as hard disks; semiconductor memories, such as ROM, RAM, memory cards, etc.

[0140] Fig. 9 is a block diagram of an integrated circuit (IC) manufacturing system 900 and an IC manufacturing flow associated therewith, according to some embodiments.

[0141] Based on the layout diagram generated by block 502 of FIG. 5 , IC manufacturing system 900 implements block 504 of FIG. 5 , wherein manufacturing system 900 is used to manufacture at least one of: (A) one or more semiconductor masks or (B) at least one component in an early semiconductor integrated circuit layer.

[0142] exist Fig. 9In the present invention, the IC manufacturing system 900 includes entities that interact with each other in the design, development and manufacturing cycle, such as a design room 920, a mask room 930 and an IC manufacturer / fab ("fab") 950 and / or services related to manufacturing IC devices 960. The entities in the system 900 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more other entities. In some embodiments, two or more of the design room 920, the mask room 930 and the IC fabrication plant 950 are owned by a single larger company. In some embodiments, two or more of the design room 920, the mask room 930 and the IC fabrication plant 950 coexist in a common facility and use common resources.

[0143] The design office (or design team) 920 generates an IC design layout 922. The IC design layout 922 includes various geometric patterns designed for the IC device 960. The geometric pattern corresponds to the pattern of the metal, oxide or semiconductor layer of the various components constituting the IC device 960 to be manufactured. The various layers are combined to form various IC functions. For example, a part of the IC design layout 922 includes various IC features to be formed in a semiconductor substrate (e.g., a silicon wafer), such as an active region, a gate electrode, a source and a drain, a metal line or a via for interconnecting layers, and an opening for bonding pads, and various material layers arranged on the semiconductor substrate. (One or more) source / drain regions may refer to a source or drain individually or collectively, depending on the context. The design office 920 implements an appropriate design process to form the IC design layout 922. The design process includes one or more of a logical design, a physical design, or a layout and routing. The IC design layout 922 is presented in one or more data files with geometric pattern information. For example, the IC design layout 922 is expressed in a GDSII file format or a DFII file format.

[0144] The mask chamber 930 includes data preparation 932 and mask manufacturing 934. The mask chamber 930 uses the IC design layout 922 to manufacture one or more masks 935 for manufacturing various layers of the IC device 960 according to the IC design layout 922. The mask chamber 930 performs mask data preparation 932, wherein the IC design layout 922 is converted into a representative data file ("RDF"). The mask data preparation 932 provides the RDF to the mask manufacturing 934. The mask manufacturing 934 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) or a semiconductor wafer. The design layout is manipulated by the mask data preparation 932 to conform to the specific characteristics of the mask writer and / or the requirements of the IC manufacturing plant 950. In Fig. 9 , mask data preparation 932, mask manufacturing 934, and mask 935 are shown as separate elements. In some embodiments, mask data preparation 932 and mask manufacturing 934 are collectively referred to as mask data preparation.

[0145] In some embodiments, mask data preparation 932 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 922. In some embodiments, mask data preparation 932 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution adjustment features, phase shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography techniques (ILT) are also used, which treat OPC as an inverse imaging problem.

[0146] In some embodiments, mask data preparation 932 includes a mask rule checker (MRC) that checks an IC design layout that has undergone processing in OPC using a set of mask creation rules that contain certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for the constraints during mask fabrication 934, which can undo some of the modifications performed by OPC to satisfy the mask creation rules.

[0147] In some embodiments, mask data preparation 932 includes a lithography process check (LPC), which simulates a process to be performed by the IC manufacturing plant 950 to manufacture an IC device 960. The LPC simulates the process based on the IC design layout 922 to manufacture a simulated manufactured device, such as the IC device 960. The processing parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as spatial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc. or combinations thereof. In some embodiments, after the simulated manufactured device is manufactured by LPC, if the shape of the simulated device is not close enough to meet the design rules, the OPC and / or MRC are repeated to further optimize the IC design layout 922.

[0148] For the sake of clarity, the above description of mask data preparation 932 has been simplified. In some embodiments, mask data preparation 932 includes additional features such as logic operations (LOP) to modify the IC design layout according to manufacturing rules. In addition, the processes applied to IC design layout 922 during data preparation 932 can be performed in a variety of different orders.

[0149] After mask data preparation 932 and during mask manufacturing 934, a mask 935 or a set of masks 935 are manufactured based on the modified IC design layout. In some embodiments, an electron beam (e-beam) or a plurality of electron beam mechanisms are used to form a pattern on a mask (photomask or reticle) based on the modified IC design layout. The mask is formed with various techniques. In some embodiments, the mask is formed using binary technology. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) for exposing an image sensitive material layer (e.g., a photoresist) coated on a wafer is blocked by the opaque area and passes through the transparent area. In one example, the binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque area of ​​the mask. In another example, a mask is formed using a phase shifting technique. In a phase shift mask (PSM), various features in the pattern formed on the mask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase shift mask is an attenuated PSM or an alternating PSM. The mask(s) generated by mask manufacturing 934 are used in various processes. For example, such mask(s) are used in an ion implantation process to form various doped regions in a semiconductor wafer, in an etching process to form various etched regions in a semiconductor wafer, and / or in other suitable processes.

[0150] IC fab 950 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC fab 950 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end of line (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility may provide back-end manufacturing (back-end of line (BEOL) manufacturing) for interconnecting and packaging IC products, and a third manufacturing facility may provide other services for the foundry business.

[0151] IC manufacturing plant 950 uses mask (or multiple masks) 935 manufactured by mask chamber 930 to use manufacturing tool 952 to manufacture IC device 960. Therefore, IC manufacturing plant 950 uses IC design layout 922 at least indirectly to manufacture IC device 960. In some embodiments, semiconductor wafer 953 is manufactured by IC factory 950 using mask (or multiple masks) 935 to form IC device 960. Semiconductor wafer 953 includes a silicon substrate or other suitable substrate with material layers formed thereon. The semiconductor wafer also includes one or more of various doped regions, dielectric features, multi-layer interconnects, etc. (formed in subsequent manufacturing steps).

[0152] In some embodiments, a memory device includes: a first array of memory cells; a second array of tracking cells, the second array being configured to simulate the first array; a first word line coupled to corresponding memory cells in a corresponding row of the first array and coupled to the tracking cells; a second word line configured to simulate the first word line; a first adjustment circuit coupled to the first word line; a second adjustment circuit coupled to the second word line; and an adjustment timing circuit coupled to the second adjustment circuit.

[0153] In some embodiments, the second adjustment circuit is configured to selectively lower a voltage level of the second word line based on a signal from the adjustment timing circuit.

[0154] In some embodiments, the second adjustment circuit includes a metal oxide field effect transistor (MOSFET) having a negative channel (NFET) coupled between the second word line and a low reference voltage node of the memory device.

[0155] In some embodiments, the memory device is arranged into different regions relative to an orthogonal projection of the memory device on a reference plane, the regions including an array region, a main input / output (IO) region, a main controller region, and a word line driver region; the first array of memory cells, most of the first word lines, and each of the second arrays are located in the array region; most of the second word lines are located in the main IO region; and the first adjustment circuit is located in the word line driver region.

[0156] In some embodiments, the second adjustment circuit is located in the main controller area.

[0157] In some embodiments, the second adjustment circuit is located in the main IO area.

[0158] In some embodiments, the second adjustment circuit is located in the word line driving region.

[0159] In some embodiments, the first adjustment circuit is configured to selectively reduce a voltage level of the first word line based on a signal from the adjustment timing circuit; and the adjustment timing circuit is also coupled to the first adjustment circuit.

[0160] In some embodiments, the second adjustment circuit is further configured to exhibit an operating profile that is substantially the same as an operating profile exhibited by the first adjustment circuit.

[0161] In some embodiments, the memory devices are arranged in corresponding non-overlapping regions relative to an orthogonal projection of the memory devices on a reference plane; and the first adjustment circuit and the second adjustment circuit are located in a same region of the regions.

[0162] In some embodiments, the first adjustment circuit includes a metal oxide field effect transistor (MOSFET) having a negative channel (NFET) coupled between the first word line and a low reference voltage node of the memory device.

[0163] In some embodiments, the memory device further includes a third adjustment circuit coupled to the first sub-line.

[0164] In some embodiments, the third adjustment circuit is configured to adjust a voltage on the tracking bit line based on a voltage on the second word line.

[0165] In some embodiments, a method (of operating a memory device), the method comprising: in some embodiments, raising a first voltage on a first word line to a first reference voltage, the first word line being coupled to a first array of memory cells and further coupled to memory cells in a corresponding row of the first array; and raising a second voltage on a second word line to the first reference voltage; hindering the first voltage on the first word line from significantly reaching the first reference voltage; and hindering the second voltage on the second word line from significantly reaching the first reference voltage.

[0166] In some embodiments, the method is performed as part of a read operation or a write operation of the memory cell.

[0167] In some embodiments, impeding the second voltage and impeding the first voltage start significantly simultaneously; the method further includes: (1) stopping impeding the first voltage after impeding the first voltage but before terminating the raising of the first voltage; and (2) stopping impeding the second voltage after impeding the second voltage but before terminating the raising of the second voltage; and stopping impeding the second voltage and stopping impeding the first voltage start significantly simultaneously.

[0168] In some embodiments, the method further includes: receiving an active edge of a start signal at a word line driver and an adjustment timer, the start signal being a signal that starts a read operation or a write operation; and wherein: after receiving the active edge of the start signal, impeding the first voltage includes turning on a first adjustment circuit coupled to the first word line; and after receiving the active edge of the start signal, impeding the second voltage includes turning on a second adjustment circuit coupled to the second word line.

[0169] In some embodiments, the method further includes: detecting that a third voltage on a tracking bit line reaches a predetermined value, the tracking bit line being coupled to a tracking unit of a second array; and wherein: in response to the third voltage reaching the predetermined value, impeding the first voltage includes turning off the first adjustment circuit; and in response to the third voltage reaching the predetermined value, impeding the second voltage includes turning off the second adjustment circuit.

[0170] In some embodiments, turning on the first adjustment circuit includes: using a metal oxide field effect transistor (MOSFET) having a negative channel (NFET) coupled between the first word line and a low reference voltage node of the memory device to impede the first voltage on the first word line from significantly reaching a first reference voltage.

[0171] In some embodiments, turning on the second adjustment circuit includes: using a metal oxide field effect transistor (MOSFET) having a negative channel (NFET) coupled between the second word line and a low reference voltage node of the memory device to impede the second voltage on the second word line from significantly reaching a first reference voltage.

[0172] In some embodiments, the method is performed as part of a write operation of a memory cell, and the method further includes, after receiving an active edge of a write operation start signal, applying a write adjustment voltage VWA as a positive supply voltage CVDD of a first array, such that CVDD = VWA; for a larger system including the first array, the write adjustment voltage VWA is less than a reference supply voltage VDD; VWA < VDD; and CVDD < VDD.

[0173] In some embodiments, the method further includes: applying the reference power supply voltage VDD as the positive power supply voltage CVDD at a predetermined time after applying the write adjustment voltage VWA, such that CVDD=VDD.

[0174] In some embodiments, applying the write adjustment voltage (VWA) as the positive power supply voltage (CVDD) includes controlling a multiplexer to select the write adjustment voltage VWA instead of the reference power supply voltage VDD as the positive power supply voltage (CVDD) after receiving an active edge of a write operation start signal.

[0175] In some embodiments, applying the write adjustment voltage (VWA) as the positive power supply voltage (CVDD) includes controlling the multiplexer to select the reference power supply voltage VDD instead of the write adjustment voltage VWA as the positive power supply voltage CVDD a predetermined time after controlling the multiplexer to select the write adjustment voltage VWA.

[0176] In some embodiments, a method (of forming a memory device) includes: forming an active region in a substrate; forming a source / drain (S / D) region in the active region as a first transistor component, wherein a region of the active region between corresponding S / D regions is a channel region representing a second transistor component; forming a gate structure over a corresponding channel region in the channel region as a third transistor component; forming a metal-to-S / D (MD) contact structure over a corresponding S / D region in the S / D region as a fourth transistor component; forming a via-to-gate / MD (VGD) structure over a corresponding structure in the gate structure and the MD contact structure as a fifth transistor component; relative to an orthogonal projection of the memory device on a reference plane, the memory device is arranged into non-overlapping regions, the non-overlapping regions including a bit cell region, a main input / output (I / O) region, a main controller region, and a word line driver region; the VGD structure electrically couples the first transistor component to a corresponding group in the fourth transistor component, the corresponding group including : a first group, as a first array of memory cells in the bit cell area; a second group, as a second array of tracking cells in the bit cell area and configured to simulate the first array; a third group, as a first adjustment circuit located in one of the non-overlapping areas other than the bit cell area; and a fourth group, as an adjustment timing circuit in the main controller area and coupled to the first adjustment circuit; and correspondingly forming metallization segments in corresponding metallization layers and forming interconnect structures in corresponding interconnect layers on a staggered layer basis above the first to fourth groups; and wherein: forming the metallization segments and the interconnect structures produces: a first word line, located in the bit cell area, and coupled to the corresponding memory cells in a corresponding row of the first array and coupled to the tracking cells; and a second word line, located in the main I / O area and configured to simulate the first word line; forming the metallization segments and the interconnect structures to electrically couple: the first adjustment circuit to the second word line; and the adjustment timing circuit to the first adjustment circuit.

[0177] In some embodiments, the third group representing the first regulation circuit is located in the main controller region.

[0178] In some embodiments, the third group representing the first adjustment circuit is located in the main I / O region.

[0179] In some embodiments, the third group representing the first adjustment circuit is located in the word line driver region.

[0180] It will be readily apparent to one of ordinary skill in the art that one or more of the disclosed embodiments achieve one or more of the above advantages. After reading the foregoing description, one of ordinary skill will be able to effect various changes, substitutions of equivalents, and various other embodiments broadly disclosed herein. Therefore, the protection intended to be granted hereby is limited only by the definitions contained in the attached claims and their equivalents.

[0181] Example 1 is a memory device comprising: a first array of memory cells; a second array of tracking cells, the second array being configured to simulate the first array; a first word line coupled to corresponding memory cells in a corresponding row of the first array and coupled to the tracking cells; a second word line configured to simulate the first word line; a first adjustment circuit coupled to the first word line; a second adjustment circuit coupled to the second word line; and an adjustment timing circuit coupled to the second adjustment circuit.

[0182] Example 2 is the memory device of Example 1, wherein: the second adjustment circuit is configured to selectively reduce a voltage level of the second word line based on a signal from the adjustment timing circuit.

[0183] Example 3 is the memory device described in Example 1, wherein: relative to an orthogonal projection of the memory device on a reference plane, the memory device is arranged into different areas, the areas including an array area, a main input / output (IO) area, a main controller area, and a word line driver area; the first array of memory cells, most of the first word lines, and each of the second arrays are located in the array area; most of the second word lines are located in the main IO area; and the first adjustment circuit is located in the word line driver area.

[0184] Example 4 is the memory device of Example 3, wherein: the second adjustment circuit is located in the main controller area.

[0185] Example 5 is the memory device of Example 3, wherein: the second adjustment circuit is located in the main IO region.

[0186] Example 6 is the memory device of Example 3, wherein: the second adjustment circuit is located in the word line driving region.

[0187] Example 7 is the memory device of Example 1, wherein: the first adjustment circuit is configured to selectively reduce the voltage level of the first word line based on a signal from the adjustment timing circuit; and the adjustment timing circuit is also coupled to the first adjustment circuit.

[0188] Example 8 is the memory device of Example 1, wherein: the second adjustment circuit is further configured to exhibit an operating profile that is substantially the same as an operating profile exhibited by the first adjustment circuit.

[0189] Example 9 is the memory device described in Example 1, wherein: relative to an orthogonal projection of the memory device on a reference plane, the memory device is arranged in corresponding non-overlapping areas; and the first adjustment circuit and the second adjustment circuit are located in the same area of ​​the areas.

[0190] Example 10 is the memory device described in Example 1, wherein: relative to an orthogonal projection of the memory device on a reference plane, the memory device is arranged in non-overlapping corresponding areas; and the first adjustment circuit and the second adjustment circuit are not located in the same area of ​​the areas.

[0191] Example 11 is the memory device of Example 1, further comprising: a third adjustment circuit coupled between the second word line and a tracking bit line coupled to a tracking cell in the second array of tracking cells.

[0192] Example 12 is the memory device of Example 11, wherein: a third adjustment circuit is configured to adjust the voltage on the tracking bit line based on the voltage on the second word line.

[0193] Example 13 is a method of operating a memory device, the method comprising: raising a first voltage on a first word line to a first reference voltage, the first word line being coupled to a first array of memory cells and further coupled to memory cells in a corresponding row of the first array; and raising a second voltage on a second word line to the first reference voltage; hindering the first voltage on the first word line from significantly reaching the first reference voltage; and hindering the second voltage on the second word line from significantly reaching the first reference voltage.

[0194] Example 14 is the method described in Example 13, wherein: blocking the second voltage starts significantly at the same time as blocking the first voltage; the method also includes: stopping blocking the first voltage after blocking the first voltage but before terminating the increase of the first voltage; and stopping blocking the second voltage after blocking the second voltage but before terminating the increase of the second voltage; and stopping blocking the second voltage starts significantly at the same time as stopping blocking the first voltage.

[0195] Example 15 is the method described in Example 13, wherein the method further includes: receiving an effective edge of a start signal at a word line driver and an adjustment timer, the start signal being a signal that starts a read operation or a write operation; and wherein: after receiving the effective edge of the start signal, blocking the first voltage includes: turning on a first adjustment circuit coupled to the first word line; and after receiving the effective edge of the start signal, blocking the second voltage includes: turning on a second adjustment circuit coupled to the second word line.

[0196] Example 16 is the method described in Example 15, further comprising: detecting that a third voltage on a tracking bit line reaches a predetermined value, the tracking bit line being coupled to a tracking unit of a second array; and wherein: in response to the third voltage reaching the predetermined value, blocking the first voltage comprises: turning off the first adjustment circuit; and in response to the third voltage reaching the predetermined value, blocking the second voltage comprises: turning off the second adjustment circuit.

[0197] Example 17 is a method for forming a memory device, the method comprising: forming an active region in a substrate; forming a source / drain (S / D) region in the active region as a first transistor component, wherein a region of the active region between corresponding S / D regions is a channel region representing a second transistor component; forming a gate structure over a corresponding channel region in the channel region as a third transistor component; forming a metal to S / D (MD) contact structure over a corresponding S / D region in the S / D region as a fourth transistor component; forming a via to gate / MD (VGD) structure over a corresponding structure in the gate structure and the MD contact structure as a fifth transistor component; relative to an orthogonal projection of the memory device on a reference plane, the memory device is arranged into a non-overlapping region, the non-overlapping region including a bit cell region, a main input / output (I / O) region, a main controller region, and a word line driver region; the VGD structure electrically couples the first transistor component to a corresponding group in the fourth transistor component, the corresponding group including : a first group, as a first array of memory cells in the bit cell area; a second group, as a second array of tracking cells in the bit cell area and configured to simulate the first array; a third group, as a first adjustment circuit located in one of the non-overlapping areas other than the bit cell area; and a fourth group, as an adjustment timing circuit in the main controller area and coupled to the first adjustment circuit; and correspondingly forming metallization segments in corresponding metallization layers and forming interconnect structures in corresponding interconnect layers on a staggered layer basis above the first to fourth groups; and wherein: forming the metallization segments and the interconnect structures produces: a first word line, located in the bit cell area, and coupled to the corresponding memory cells in a corresponding row of the first array and coupled to the tracking cells; and a second word line, located in the main I / O area and configured to simulate the first word line; forming the metallization segments and the interconnect structures to electrically couple: the first adjustment circuit to the second word line; and the adjustment timing circuit to the first adjustment circuit.

[0198] Example 18 is the method of Example 17, wherein: the third group representing the first adjustment circuit is located in the main controller area.

[0199] Example 19 is the method of Example 17, wherein: the third group representing the first adjustment circuit is located in the main I / O region.

[0200] Example 20 is the method of Example 17, wherein: the third group representing the first adjustment circuit is located in the word line driver region.

Claims

1. A memory device, comprising: a first array of memory cells; a second array of tracking elements, the second array configured to emulate the first array; a first word line coupled to a corresponding memory cell in a corresponding row of the first array and to the tracking cell; a second word line configured to emulate the first word line; a first adjustment circuit coupled to the first word line; a second adjustment circuit coupled to the second word line; as well as An adjustment timing circuit is coupled to the second adjustment circuit.

2. The memory device according to claim 1, wherein: The second adjustment circuit is configured to selectively lower a voltage level of the second word line based on a signal from the adjustment timing circuit.

3. The memory device according to claim 1, wherein: With respect to an orthogonal projection of the memory device on a reference plane, the memory device is arranged into different regions, including an array region, a main input / output IO region, a main controller region, and a word line driver region; the first array of memory cells, a majority of the first word lines, and each of the second arrays are located in the array region; Most of the second word line is located in the main IO region; and The first adjustment circuit is located in the word line driver region.

4. The memory device according to claim 3, wherein: The second adjustment circuit is located in the main controller area.

5. The memory device according to claim 3, wherein: The second adjustment circuit is located in the main IO area.

6. The memory device according to claim 3, wherein: The second adjustment circuit is located in the word line driving region.

7. The memory device according to claim 1, wherein: The first adjustment circuit is configured to selectively reduce a voltage level of the first word line based on a signal from the adjustment timing circuit; and The adjustment timing circuit is also coupled to the first adjustment circuit.

8. The memory device of claim 1, wherein: The second regulation circuit is also configured to exhibit an operating profile that is substantially the same as an operating profile exhibited by the first regulation circuit.

9. A method of operating a memory device, the method comprising: raising a first voltage on a first word line to a first reference voltage, the first word line being coupled to a first array of memory cells and further coupled to memory cells in a corresponding row of the memory cells in the first array; and increasing a second voltage on a second word line to the first reference voltage; preventing a first voltage on the first word line from significantly reaching the first reference voltage; as well as A second voltage on the second word line is prevented from significantly reaching the first reference voltage.

10. A method of forming a memory device, the method comprising: forming an active region in a substrate; forming source / drain S / D regions in the active region as a first transistor component, wherein a region of the active region between corresponding S / D regions is a channel region representing a second transistor component; forming a gate structure as a third transistor component over a corresponding one of the channel regions; forming a metal-to-S / D MD contact structure over corresponding ones of the S / D regions as a fourth transistor component; forming a via-to-gate / MD VGD structure as a fifth transistor component over the gate structure and corresponding ones of the MD contact structures; The memory device is arranged into non-overlapping regions relative to an orthogonal projection of the memory device on a reference plane, the non-overlapping regions including a bit cell region, a main input / output I / O region, a main controller region, and a word line driver region; The VGD structure electrically couples the first transistor component to a corresponding group of fourth transistor components, the corresponding group comprising: a first group, being a first array of memory cells in the bit cell region; a second set, being a second array of tracking cells in the bit cell region and configured to emulate the first array; a third group, as a first trimming circuit located in one of the non-overlapping regions other than the bit cell region; and a fourth group, being an adjustment timing circuit in the main controller region and coupled to the first adjustment circuit; and Correspondingly forming metallization sections in corresponding metallization layers and interconnect structures in corresponding interconnect layers on a staggered layer basis over the first to fourth groups; and in: Formation of metallization segments and interconnect structures produces: a first word line located in the bit cell region and coupled to a corresponding memory cell in a corresponding row of the first array and to the tracking cell; and a second word line located in the primary I / O region and configured to emulate the first word line; Forming metallization segments and interconnect structures to electrically couple: the first adjustment circuit to the second word line; and The adjustment timing circuit is to the first adjustment circuit.

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