Fuse circuit and chip control method

Abstract

The invention relates to a fuse circuit and a chip control method. The fuse circuit comprises: a control signal generation module configured to receive a clock signal and a data signal, and sample and decode the data signal according to the clock signal to generate a control signal; the control module is connected with the control signal generation module and is configured to perform corresponding operation on a fuse unit according to the control signal; and the fuse array is connected with the control module and comprises a plurality of fuse units arranged in an array, and each fuse unit comprises a selection transistor and a breakdown capacitor. According to the invention, controllable fuse writing, reading and broadcasting processes can be realized, and normal starting of a chip is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a fuse circuit and a chip control method. Background Art

[0002] A fuse circuit is provided in the chip. The fuse circuit includes a plurality of fuse cells arranged in an array, each of which includes a selection transistor and a breakdown capacitor. The breakdown of the dielectric layer in the capacitor is irreversible, and the solidified storage data can be obtained by reading the breakdown state of the capacitor. Moreover, the fuse cell can only be programmed once and cannot be electrically erased. The fuse circuit can play a role in memory chip identification, as a memory cell repair area, and storage function test parameters.

[0003] The operations on the fuse unit include programming, reading and broadcasting (English: broadcast). Programming is to apply a high voltage to the capacitor to make it break down when the selection transistor is turned on. Reading is to determine the breakdown state of the capacitor by reading the current flowing through the capacitor when the selection transistor is turned on. If the current is large, it means that the dielectric layer in the capacitor is broken down and is in a low-resistance state, that is, the fuse unit stores data "1". If the current is small, it means that the dielectric layer in the capacitor is not broken down and is in a high-resistance state, that is, the fuse unit stores data "0". Broadcasting is to transmit the data in the fuse unit to each required functional module in the chip.

[0004] The data in the fuse unit is read and latched in the latch, and is automatically transmitted to the corresponding functional module when the chip is powered on / reset. The process is uncontrollable. If the data in the fuse unit is written incorrectly, the data transmitted to the corresponding functional module will also be incorrect, which will cause the chip function to fail to function normally. Summary of the invention

[0005] Based on this, it is necessary to provide a controllable fuse circuit and a chip control method.

[0006] In a first aspect, a fuse circuit is provided, the fuse circuit comprising:

[0007] A control signal generating module is configured to receive a clock signal and a data signal, and to sample and decode the data signal according to the clock signal to generate a control signal;

[0008] A control module, connected to the control signal generating module, and configured to perform corresponding operations on the fuse unit according to the control signal;

[0009] The fuse array is connected to the control module and includes a plurality of fuse units arranged in an array, each of the fuse units including a selection transistor and a breakdown capacitor.

[0010] The above-mentioned fuse circuit includes a control signal generating module, a control module and a fuse array. The control signal generating module is configured to receive a clock signal and a data signal, and to sample and decode the data signal according to the clock signal to generate a control signal. The control module is connected to the control signal generating module and the fuse array respectively, and is configured to perform corresponding operations on the fuse units arranged in the fuse array according to the control signal, so as to realize a controllable fuse writing, reading and broadcasting process and ensure the normal startup of the chip.

[0011] In one embodiment, the control signal generating module includes:

[0012] A serial-to-parallel unit is configured to receive the clock signal from the clock interface, receive the data signal from the data interface, the data signal includes N bits of serial data, sample the data signal according to the clock signal, and output N coded signals in parallel, where N is a positive integer;

[0013] The decoding unit is connected to the serial-to-parallel unit and is configured to generate the control signal based on decoding of the encoded signal.

[0014] In one embodiment, the serial-to-parallel unit includes:

[0015] N shift registers, the clock end of each shift register is connected to the clock interface, the input end of the first shift register is connected to the data interface, the input end of the i-th shift register is connected to the output end of the i-1-th shift register, 2≤i≤N and i is an integer, the output end of each shift register is connected to the input end of the decoding unit, and the N shift registers output the N-bit encoded signals in parallel.

[0016] In one embodiment, the decoding unit comprises:

[0017] A first-stage decoding subunit, connected to the output terminals of the j shift registers, configured to receive the j coded signals and generate a mode signal based on the j coded signals, where 1≤j<N and j is an integer;

[0018] The second-stage decoding subunit is connected to the output end of the (Nj) shift registers, and is configured to receive the (Nj) coded signals and generate a parameter signal based on the (Nj) coded signals, wherein the control signal includes the mode signal and the parameter signal.

[0019] In one embodiment, the decoding unit further includes:

[0020] A counter, wherein an input end of the counter is connected to an output end of the first-stage decoding subunit; the counter is configured to receive the mode signal and count to obtain a digital signal;

[0021] The second-stage decoding subunit is further configured to receive the digital signal and generate a parameter signal based on the digital signal and the encoded signal.

[0022] In one embodiment, the decoding unit further includes:

[0023] a comparator, wherein an enable terminal of the comparator is connected to an output terminal of the first-stage decoding subunit, and an input terminal of the comparator is connected to output terminals of (Nj) of the shift registers; the comparator is configured to receive (Nj) of the coded signals and compare them with a preset value when the mode signal is valid, and output an enable signal;

[0024] The fuse circuit is configured to be turned on or off based on the enable signal.

[0025] In one embodiment, the control module includes:

[0026] a power supply unit connected to the second-stage decoding subunit, configured to receive the parameter signal and generate corresponding operating power based on the parameter signal and transmit it to the fuse array;

[0027] The address unit is connected to the second-stage decoding subunit and is configured to receive the parameter signal and operate a target fuse unit of the fuse array based on the parameter signal.

[0028] In one of the embodiments, the control module is further configured to receive the parameter signal and enable or disable based on the parameter signal.

[0029] In a second aspect, a chip control method is provided, the chip control method comprising:

[0030] Receive a clock signal and a data signal, and sample and decode the data signal according to the clock signal to generate a control signal;

[0031] The fuse unit is operated accordingly according to the control signal, the fuse array comprises a plurality of the fuse units arranged in an array, and each of the fuse units comprises a selection transistor and a breakdown capacitor.

[0032] The above chip control method receives a clock signal and a data signal, samples and decodes the data signal according to the clock signal to generate a control signal, and performs corresponding operations on the fuse units arranged in the fuse array according to the control signal, thereby realizing a controllable fuse writing, reading and broadcasting process to ensure the normal startup of the chip.

[0033] In one embodiment, the step of sampling and decoding the data signal according to the clock signal to generate a control signal includes:

[0034] Receive the clock signal from the clock interface, receive the data signal from the data interface, the data signal includes N bits of serial data, N is a positive integer;

[0035] Sampling the data signal according to the clock signal, and outputting N coded signals in parallel;

[0036] The control signal is generated based on decoding of the encoded signal.

[0037] In one embodiment, the step of generating the control signal based on the decoding of the coded signal comprises:

[0038] Decoding and generating a mode signal based on j of the coded signals, 1≤j<N and j is an integer;

[0039] A parameter signal is generated based on the (Nj) coded signals, and the control signal includes the mode signal and the parameter signal.

[0040] In one embodiment, the decoding and generating of the parameter signal based on the (Nj) coded signals comprises:

[0041] When the mode signal is valid, the (Nj) coded signals are compared with a preset value, an enable signal is output, and the fuse circuit is turned on or off based on the enable signal;

[0042] When the mode signal is a setting mode, a parameter signal is generated by decoding the (Nj) coded signals.

[0043] In one embodiment, comparing the (Nj) coded signals with a preset value and outputting an enable signal comprises:

[0044] When (Nj) of the coded signals are identical to the first preset data, generating an enable signal at a valid level;

[0045] When (Nj) of the coded signals are identical to the second preset data, an enable signal at an inactive level is generated.

[0046] In one embodiment, the decoding and generating of the parameter signal based on the (Nj) coded signals comprises:

[0047] When the mode signal is the first command mode and the digital signal is the first value, the parameter signal includes an operation command signal, and the operation command signal is one of a read command, a write command, and a broadcast command;

[0048] When the mode signal is the second command mode, the parameter signal includes a target read data signal;

[0049] When the mode signal is the third command mode, the parameter signal includes a target write data signal;

[0050] When the mode signal is in the first command mode and the digital signal is in the second value, the parameter signal includes an address signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0052] Figure 1 is a structural block diagram of a fuse circuit according to an embodiment;

[0053] Figure 2 is a structural block diagram of a control signal generating module according to an embodiment;

[0054] Figure 3 A timing diagram of a clock signal and a data signal according to an embodiment;

[0055] Figure 4 A structural block diagram of a serial-to-parallel unit according to an embodiment;

[0056] Figure 5 is a structural block diagram of a decoding unit according to an embodiment;

[0057] Figure 6 is a structural block diagram of a decoding unit according to another embodiment;

[0058] Figure 7 is a structural block diagram of a decoding unit according to another embodiment;

[0059] Figure 8 is a structural block diagram of a control module of an embodiment;

[0060] Fig. 9 is a flow chart of a chip control method according to an embodiment;

[0061] Fig.10 is a flow chart of step S901 of an embodiment;

[0062] Fig.11 FIG. 1 is a flow chart of step S1003 of an embodiment.

[0063] Description of reference numerals:

[0064] 10. Control signal generating module, 11. Serial-to-parallel unit, 111. Shift register, 12. Decoding unit, 121. First-level decoding subunit, 122. Second-level decoding subunit, 123. Counter, 124. Comparator, 20. Control module, 21. Power supply unit, 22. Address unit, 30. Fuse array. DETAILED DESCRIPTION

[0065] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0067] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0068] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0069] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0070] Please refer to Figure 1In one embodiment of the present application, a fuse circuit is provided, which includes a control signal generating module 10, a control module 20 and a fuse array 30. The control signal generating module 10 is configured to receive a clock signal and a data signal, and to sample and decode the data signal according to the clock signal to generate a control signal. The control module 20 is connected to the control signal generating module 10, and is configured to perform corresponding operations on the fuse unit according to the control signal. The fuse array 30 is connected to the control module 20, and the fuse array 30 includes a plurality of fuse units arranged in an array, and each fuse unit includes a selection transistor and a breakdown capacitor.

[0071] Specifically, the breakdown capacitor can be a transistor capacitor composed of a metal-oxide-semiconductor (English: Metal-Oxide-Semiconductor, abbreviated as MOS) structure (also called a MOS capacitor), or a capacitor capacitor composed of a metal-insulator-metal (English: Metal-Oxide-Metal, abbreviated as MIM) structure (also called a MIM capacitor), etc., without limitation here.

[0072] Among them, the control signal generating module 10 of the fuse circuit is configured with an input / output (I / O) interface for interacting with the outside world. It can receive signals transmitted from a controller or a test machine, such as clock signals, data signals, etc., and can also output signals to the controller or the test machine, such as data signals stored inside the chip.

[0073] The clock signal (English: Clock, abbreviated as: CLK) generally refers to the external clock signal sent from the controller or test machine received from the clock interface of the chip, which can be used as the clock signal for the chip to work. For a double data rate (English: Double Date Rate, abbreviated as: DDR) chip, the chip will sample once at the rising edge and falling edge of the clock signal when working, so as to transmit data twice in one clock cycle.

[0074] Data signal (DQ for short) is a signal that carries data information. It generally refers to a data signal sent from a controller or test machine and received from the chip's data interface, or a data signal stored inside the chip and output from the chip's data interface to a controller or test machine. A data signal generally includes N bits of serial data, and the serially transmitted N-bit data signal can be sampled by a clock signal.

[0075] The control signal is a signal for controlling the operation of the fuse unit. The operation on the fuse unit can be to read data, that is, to read the data stored in the fuse unit; to write data, that is, to program the fuse unit; or to transmit data, that is, to broadcast the data latched in the latch corresponding to the fuse unit.

[0076] Taking the anti-fuse unit as an example, the anti-fuse unit includes a pass transistor (English: pass transistor) and a programming transistor (English: program transistor). When writing data, the pass transistor is turned on, and a high voltage is applied to the programming transistor to break down the gate dielectric layer of the programming transistor, corresponding to the programming written data. When reading data, the pass transistor is turned on, and a reference voltage is applied to the programming transistor, corresponding to the data reading. When broadcasting, the data programmed into the anti-fuse unit will be stored in the latch after reading. When the chip is powered on, the latch is enabled, corresponding to the broadcast data.

[0077] For chips, the data stored in the one-shot breakdown capacitor in the fuse circuit will be automatically propagated to the corresponding functional module when the chip is powered on or reset, and the process is uncontrollable. If the data written in the fuse unit is misplaced, the corresponding function of the chip cannot be started normally. Or during the chip manufacturing process, the internal power supply drifts due to unstable process technology. At this time, the chip cannot be powered on normally, and the corresponding function cannot be started normally. The fuse circuit provided in the present application includes a control signal generating module 10, a control module 20 and a fuse array 30. The control signal generating module 10 is configured to receive a clock signal and a data signal, and to sample and decode the data signal according to the clock signal to generate a control signal. The control module 20 is connected to the control signal generating module 10, and is configured to perform corresponding operations on the fuse unit according to the control signal. The fuse array 30 includes a plurality of fuse units arranged in an array, and each fuse unit includes a selection transistor and a breakdown capacitor. In this way, the fuse circuit can be used to receive the clock signal and the data signal through the clock interface / data interface when the chip cannot start normally, sample and decode to generate corresponding control signals to operate the fuse units in the fuse array, and enter a special mode when the chip cannot start normally. By adjusting the data stored in the fuse unit, the internal power supply module and the functional modules corresponding to the core parameters are further adjusted to achieve normal startup of the chip.

[0078] Please refer to Figure 2In one embodiment, the control signal generation module 10 includes a serial-to-parallel unit 11 and a decoding unit 12. The serial-to-parallel unit 11 is configured to receive a clock signal from a clock interface, receive a data signal from a data interface, the data signal includes N-bit serial data, sample the data signal according to the clock signal, and output N coded signals in parallel, where N is a positive integer. The decoding unit 12 is connected to the serial-to-parallel unit 11, and is configured to generate a control signal based on the decoding of the coded signal.

[0079] Specifically, Figure 2 As shown, the serial-to-parallel unit 11 receives a clock signal from a clock interface, which is located on the chip and is connected to a controller or a test machine with a clock signal line SCL for transmitting the clock signal. The serial-to-parallel unit 11 receives a data signal from a data interface, which is located on the chip and is connected to a controller or a test machine with a data signal line SDA for transmitting the data signal. When the chip cannot be started normally, the fuse circuit can receive the clock signal and the data signal respectively through the clock interface and the data interface, thereby controlling the data storage state of the fuse unit, and adjusting the corresponding functional module so that the chip can be started normally.

[0080] The clock signal is a signal quantity with a fixed period and is independent of the operation. By using the rising edge or falling edge of the clock signal that appears once every fixed period as the sampling moment of the data signal, the serially transmitted data signal can be sampled once every fixed period. For example, Figure 3 As shown, the clock signal has a rising edge every fixed period, at which time the data signal is sampled once. Then the multiple sampled data signals are output simultaneously, thus realizing the function of serial to parallel conversion.

[0081] The decoding unit 12 decodes the N coded signals according to a preset decoding rule to obtain a control signal.

[0082] In this embodiment, the control signal generating module 10 includes a serial-to-parallel unit 11 and a decoding unit 12. The serial-to-parallel unit 11 first receives a clock signal and a data signal including N-bit serial data from a clock interface and a data interface respectively, samples the data signal according to the clock signal, and outputs N coded signals in parallel. Then, the decoding unit 12 generates a control signal based on the decoding of the coded signal. When the chip cannot start normally, the clock signal and the data signal transmitted by the external controller or the test machine are received from the clock interface and the data interface, and the corresponding control signal is obtained by sampling and decoding. Then, the control signal can be used to realize the writing, reading and broadcasting process of the controllable fuse unit, thereby controlling the data storage state of the fuse unit, and then adjusting the corresponding functional module so that the chip can start normally.

[0083] See also Figure 4Optionally, the serial-to-parallel unit 11 includes N shift registers 111, the clock end of each shift register 111 is connected to the clock interface, the input end of the first shift register 111 is connected to the data interface, the input end of the i-th shift register 111 is connected to the output end of the i-1-th shift register 111, 2≤i≤N and i is an integer, the output end of each shift register 111 is connected to the input end of the decoding unit 12, and the N shift registers 111 output N encoded signals in parallel.

[0084] In this embodiment, the serial-to-parallel unit 11 includes N shift registers 111, the clock end of each shift register 111 receives a clock signal, the input end of the first shift register 111 receives a data signal, the input end of the i-th shift register 111 is connected to the output end of the i-1-th shift register 111, 2≤i≤N and i is an integer, the output end of each shift register 111 is connected to the input end of the decoding unit 12, and the N shift registers 111 output N coded signals in parallel. In this way, under the control of the clock signal, the data signal is sequentially input to the input end of the first shift register 111 in a serial manner, at the first rising edge of the clock signal, the first bit of the data signal is sampled by the first shift register 111 to output the intermediate signal Q1, at the second rising edge of the clock signal, the second bit of the data signal is sampled by the first shift register 111 to output the intermediate signal Q1, and the first bit of the data signal is sampled by the second shift register 111 to output the intermediate signal Q2. By analogy, under the control of the clock signal, the serial data signal is shifted right bit by bit in sequence, and the output end of each shift register 111 outputs the intermediate signal Q1-Qn correspondingly. At the Nth rising edge of the clock signal, the intermediate signal Q1 outputted from the output end of the first shift register 111 corresponds to the Nth bit in the data signal, the intermediate signal Q2 outputted from the output end of the second shift register 111 corresponds to the N-1th bit in the data signal, and by analogy, the intermediate signal Qn outputted from the output end of the Nth shift register 111 corresponds to the 1st bit in the data signal. Among them, the output end of each shift register 111 is connected to the input end of the decoding unit 12, and the N intermediate signals Q1-Qn are outputted in parallel to the input end of the decoding unit 12, that is, the serial data signal is converted into the output of the parallel coded signal.

[0085] See also Figure 5Optionally, the decoding unit 12 includes a first-level decoding subunit 121 and a second-level decoding subunit 122. The first-level decoding subunit 121 is connected to the output ends of the j shift registers 111, and is configured to receive j coded signals and generate corresponding mode signals based on the j coded signals, 1≤j<N and j is an integer. The second-level decoding subunit 122 is connected to the output ends of the (Nj) shift registers 111, and is configured to receive (Nj) coded signals and generate parameter signals based on the (Nj) coded signals, and the control signal includes a mode signal and a parameter signal.

[0086] In this embodiment, the first-level decoding subunit 121 performs first-level decoding on j coded signals to generate a mode signal, and then the second-level decoding subunit performs second-level decoding on (Nj) coded signals to generate a parameter signal. The parameter signal and the mode signal constitute a control signal. In this way, two-level decoding can reduce the complexity of the decoding unit, simplify the encoding, and improve the decoding efficiency.

[0087] For example, when N=10, the data signal is a serial 10-bit data signal. At the rising edge of the tenth clock cycle of the clock signal, the 10 intermediate signals Q1-Q10 output from the output ends of the 10 shift registers 111 are 10 parallel coded signals, among which the 2-bit coded signals Code1 and Code2 are first-level decoded to generate the mode signal, and the other 8-bit coded signals Code3-Code10 are second-level decoded to generate the parameter signal.

[0088] When Code1 and Code2 are 00, the mode signal is determined to be the first command mode, and the first command mode corresponds to the activation of the fuse circuit. At this time, Code3-Code10 is decoded at the second level, and the generated parameter signal may include address signals RA0-RA16, operation signals cmd and control start / end signals CTRL. Among them, the address signal is used to indicate the operation of the fuse unit of the target address. The operation signal is used to indicate which operation is performed on the fuse unit, such as writing, reading, etc. The control start / end signal is used to indicate the start and end of the control module.

[0089] When Code1 and Code2 are 01, the command mode is determined to be the second command mode, and the second command mode corresponds to the reading of the fuse circuit. At this time, Code3-Code10 are second-level decoded, and the generated parameter signal may include the read data D0-D14.

[0090] When Code1 and Code2 are 11, the command mode is determined to be the third command mode, which corresponds to writing of the fuse circuit. At this time, Code3-Code10 are second-level decoded, and the generated parameter signal may include write data D0-D14.

[0091] When Code1 and Code2 are 10, the command mode is determined to be the fourth command mode, and the fourth command mode corresponds to the enable / disable of the fuse circuit. At this time, Code3-Code10 is decoded at the second level, and the generated parameter signal may include enable data. If the enable data is 10101011, the fuse circuit is enabled. If the enable data is 00000001, the fuse circuit is not enabled, that is, the fuse circuit is not used to enter the special mode to realize the normal startup of the chip.

[0092]

[0093] See also Figure 6 Optionally, the decoding unit 12 further includes a counter 123, and an input end of the counter 123 is connected to an output end of the first-level decoding subunit 121. The counter 123 is configured to receive the mode signal and count to obtain a digital signal. The second-level decoding subunit 122 is also connected to the output end of the counter 123, configured to receive the digital signal, and generate a parameter signal based on the digital signal and the coded signal.

[0094] In actual applications, the number of bits of the parameter signal will be greater than the number of parallel bits of the coded signal, so a parameter signal will be composed of coded signals transmitted in parallel multiple times. For example, only 8 bits of the coded signal transmitted in parallel once are used to generate the parameter signal, and the parameter signal generated corresponding to the first command mode has 22 bits, which needs to be composed of coded signals transmitted in parallel three times. For another example, the parameter signal generated corresponding to the second command mode and the third command mode has 15 bits, which needs to be composed of coded signals transmitted in parallel twice. In the above embodiment, by adding the counter 123, the mode signal can be counted to obtain a digital signal, so that the second-level decoding subunit 122 can determine the content of the coded signal based on the digital signal to generate a parameter signal.

[0095] For example, when Code1 and Code2 are 00, if the digital signal is 0, the parameter signal generated by Code3-Code10 decoding includes the operation signal cmd, the control start / end signal CTRL and the address signal RA0-RA2; if the digital signal is 1, the parameter signal generated by Code3-Code10 decoding includes the address signal RA3-RA10; if the digital signal is 2, the parameter signal generated by Code3-Code10 decoding includes the address signal RA11-RA16.

[0096] For another example, when Code1 and Code2 are 01 or 11, if the digital signal is 0, the parameter signal generated by decoding Code3-Code10 includes data D0-D7; if the digital signal is 1, the parameter signal generated by decoding Code3-Code10 includes data D8-D14.

[0097] In a first implementation manner, when the mode signal is the first command mode and the digital signal is the first value, the parameter signal includes an operation command signal, and the operation command signal is one of a read command, a write command, and a broadcast command.

[0098] The read command is configured to control the read operation of the fuse array, the write command is configured to control the write operation of the fuse array, and the broadcast command is configured to control the broadcast operation of the fuse array.

[0099] In this embodiment, the corresponding operation on the fuse array according to the control signal may be a read operation, a write operation, or a broadcast operation. The operation range covers all basic operations of the fuse array and has a wide application range.

[0100] In a second implementation manner, when the mode signal is the second command mode, the parameter signal includes a target read data signal.

[0101] In a third implementation manner, when the mode signal is the third command mode, the parameter signal includes a target write data signal.

[0102] The target write data signal carries the data to be written into the fuse array.

[0103] In this embodiment, the parameter signal includes a target write data signal, which carries the data to be written in the fuse array and can rewrite the data to be written into the fuse array 30 , thereby correcting errors in the stored data of the fuse array 30 .

[0104] In a fourth implementation manner, when the mode signal is the first command mode and the digital signal is the second value, the parameter signal includes an address signal.

[0105] The address signal carries the address of the fuse unit to be operated in the fuse array 30. By way of example, the fuse unit address may include a row address and / or a column address.

[0106] In this embodiment, the parameter signal includes an address signal, and the address signal carries the address of the fuse unit to be operated in the fuse array 30 , so that the corresponding fuse unit in the fuse array 30 can be accurately determined for operation.

[0107] See also Figure 7Optionally, the decoding unit 12 further includes a comparator 124, an enable terminal of the comparator 124 is connected to the output terminal of the first-stage decoding subunit 121, and an input terminal of the comparator 124 is connected to the output terminal of the (Nj) shift registers 111. The comparator 124 is configured to receive the (Nj) coded signals and compare them with a preset value when the mode signal is valid, and output an enable signal. The fuse circuit is configured to be turned on or off based on the enable signal.

[0108] Exemplarily, when the (Nj) coded signals are identical to the first preset data, an enable signal at a valid level is generated; when the (Nj) coded signals are identical to the second preset data, an enable signal at an invalid level is generated.

[0109] In the above embodiment, by setting the comparator 124, when the mode signal is valid, the (Nj) coded signals are compared with the preset value, and an enable signal is output, and then turned on or off based on the enable signal, thereby avoiding erroneous operation of the fuse array 30.

[0110] For example, when the mode signal is 10, the mode signal is valid, and the comparator 124 compares the (Nj) coded signals with the preset value. If the (Nj) coded signals are the same as the first preset data, the fuse circuit is enabled, the fuse circuit is turned on, and this special mode is entered, and the normal startup of the chip can be achieved through the background.

[0111] See also Figure 8 In one embodiment, the control module 20 includes a power supply unit 21 and an address unit 22. The power supply unit 21 is connected to the second-level decoding subunit 122, and is configured to receive a parameter signal, and generate a corresponding operating power supply based on the parameter signal and transmit it to the fuse array 30. The address unit 22 is connected to the second-level decoding subunit 122, and is configured to receive a parameter signal, and operate a target fuse unit of the fuse array 30 based on the parameter signal.

[0112] Optionally, the control module 20 is further configured to receive a parameter signal, and enable or disable based on the parameter signal.

[0113] In this embodiment, the control module 20 includes a power supply unit 21 and an address unit 22. The power supply unit 21 is connected to the second-level decoding sub-unit 122 and generates a corresponding operating power supply based on a parameter signal and transmits it to the fuse array 30. The address unit 22 is connected to the second-level decoding sub-unit 122 and operates the target fuse unit of the fuse array based on the parameter signal, and can control the target fuse unit in the fuse array 30 to perform corresponding operations.

[0114] Exemplarily, the operating power corresponding to the write command is different from the operating power corresponding to the read command, and the operating power corresponding to different data is also different. For example, the operating power corresponding to writing data "1" is greater than the operating power corresponding to the read command, and the operating power corresponding to the read command is greater than the operating power corresponding to writing data "0".

[0115] Still taking the anti-fuse unit as an example, when the operation command signal is a write command, the power supply unit 21 provides a conduction voltage to the transmission transistor corresponding to the target fuse unit to turn on the transmission transistor; at the same time, it provides a data voltage to the programming transistor based on the target data signal to write data into the programming transistor. When the operation command signal is a read command, the power supply unit 21 provides a conduction voltage to the transmission transistor corresponding to the target fuse unit to turn on the transmission transistor; at the same time, it provides a reference voltage to the programming transistor to read data from the programming transistor. When the operation command signal is a broadcast command, the power supply unit 21 enables the latch based on the parameter signal for broadcasting.

[0116] Exemplarily, the core control parameters inside the chip include, but are not limited to, power startup frequency, design for testability (DFT) parameters, power reference level, and working speed.

[0117] Based on the same inventive concept, in one embodiment of the present application, a chip control method is also provided. Fig. 9 , the chip control method comprises the following steps:

[0118] S901, receiving a clock signal and a data signal, and sampling and decoding the data signal according to the clock signal to generate a control signal.

[0119] S902, performing corresponding operations on the fuse array according to the control signal.

[0120] The fuse array includes a plurality of fuse units arranged in an array, and each fuse unit includes a selection transistor and a breakdown capacitor.

[0121] In this embodiment, a clock signal and a data signal are received, the data signal is sampled and decoded according to the clock signal to generate a control signal, and the fuse array is operated accordingly according to the control signal, so that a controllable fuse writing, reading and broadcasting process can be realized to ensure the normal startup of the chip.

[0122] In one embodiment, please refer to Fig.10 , S901 includes the following steps:

[0123] S1001, receiving a clock signal from a clock interface, and receiving a data signal from a data interface, wherein the data signal includes N bits of serial data, where N is a positive integer.

[0124] S1002, sampling the data signal according to the clock signal, and outputting N coded signals in parallel.

[0125] S1003, generating a control signal based on decoding of the coded signal.

[0126] In this embodiment, a clock signal and a data signal including N-bit serial data are first received simultaneously from the outside, the data signal is sampled according to the clock signal, N coded signals are output in parallel, and then a control signal is generated based on the coded signal. The control signal can be obtained from the clock signal and data signal transmitted externally, and then the control signal can be used to realize controllable fuse writing, reading and broadcasting processes to ensure normal startup of the chip.

[0127] Optionally, refer to Fig.11 , S1003 includes the following steps:

[0128] S1101, generate a mode signal based on decoding of j coded signals, where 1≤j<N and j is an integer.

[0129] S1102, generating a parameter signal based on (Nj) coded signals, where the control signal includes a mode signal and a parameter signal.

[0130] Exemplarily, S1102 includes the following steps: when the mode signal is valid, (Nj) coded signals are compared with preset values, an enable signal is output, and the fuse circuit is turned on or off based on the enable signal; when the mode signal is a set mode, a parameter signal is generated based on the (Nj) coded signals decoding.

[0131] For example, when the first two coded signals are 10, the mode signal is valid, the last eight coded signals are compared with the preset value, and an enable signal is output; when the first two coded signals are one of 00, 01 and 11, the mode signal is the set mode, and a parameter signal is generated based on the decoding of the last eight coded signals.

[0132] Optionally, (Nj) coded signals are compared with preset values ​​and an enable signal is output, comprising the following steps: when the (Nj) coded signals are the same as the first preset data, an enable signal at a valid level is generated; when the (Nj) coded signals are the same as the second preset data, an enable signal at an invalid level is generated.

[0133] Optionally, generating a parameter signal based on decoding (Nj) encoded signals includes the following steps: when the mode signal is a first command mode and the digital signal is a first value, the parameter signal includes an operation command signal, and the operation command signal is one of a read command, a write command and a broadcast command; when the mode signal is a second command mode, the parameter signal includes a target read data signal; when the mode signal is a third command mode, the parameter signal includes a target write data signal; when the mode signal is a first command mode and the digital signal is a second value, the parameter signal includes an address signal.

[0134] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0135] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0136] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A fuse circuit, characterized in that: The fuse circuit comprises: A control signal generating module is configured to receive a clock signal and a data signal, and to sample and decode the data signal according to the clock signal to generate a control signal; A control module, connected to the control signal generating module, and configured to perform corresponding operations on the fuse unit according to the control signal; The fuse array is connected to the control module and includes a plurality of fuse units arranged in an array, each of the fuse units including a selection transistor and a breakdown capacitor.

2. The fuse circuit according to claim 1, characterized in that: The control signal generating module comprises: A serial-to-parallel unit is configured to receive the clock signal from the clock interface, receive the data signal from the data interface, the data signal includes N bits of serial data, sample the data signal according to the clock signal, and output N coded signals in parallel, where N is a positive integer; The decoding unit is connected to the serial-to-parallel unit and is configured to generate the control signal based on decoding of the encoded signal.

3. The fuse circuit according to claim 2, characterized in that: The serial-to-parallel unit comprises: N shift registers, the clock end of each shift register is connected to the clock interface, the input end of the first shift register is connected to the data interface, the input end of the i-th shift register is connected to the output end of the i-1-th shift register, 2≤i≤N and i is an integer, the output end of each shift register is connected to the input end of the decoding unit, and the N shift registers output the N encoded signals in parallel.

4. The fuse circuit according to claim 3, characterized in that: The decoding unit comprises: A first-stage decoding subunit, connected to the output terminals of the j shift registers, configured to receive the j coded signals and generate a mode signal based on the j coded signals, where 1≤j<N and j is an integer; The second-stage decoding subunit is connected to the output end of the (Nj) shift registers, and is configured to receive the (Nj) coded signals and generate a parameter signal based on the (Nj) coded signals, wherein the control signal includes the mode signal and the parameter signal.

5. The fuse circuit according to claim 4, characterized in that: The decoding unit also includes: A counter, wherein an input end of the counter is connected to an output end of the first-stage decoding subunit; the counter is configured to receive the mode signal and count to obtain a digital signal; The second-stage decoding subunit is also connected to the output terminal of the counter, and is configured to receive the digital signal and generate a parameter signal based on the digital signal and the encoded signal.

6. The fuse circuit according to claim 4, characterized in that: The decoding unit also includes: a comparator, wherein an enable terminal of the comparator is connected to an output terminal of the first-stage decoding subunit, and an input terminal of the comparator is connected to output terminals of (Nj) of the shift registers; the comparator is configured to receive (Nj) of the coded signals and compare them with a preset value when the mode signal is valid, and output an enable signal; The fuse circuit is configured to be turned on or off based on the enable signal.

7. The fuse circuit according to any one of claims 4 to 6, characterized in that: The control module comprises: a power supply unit connected to the second-stage decoding subunit, configured to receive the parameter signal and generate corresponding operating power based on the parameter signal and transmit it to the fuse array; The address unit is connected to the second-stage decoding subunit and is configured to receive the parameter signal and operate a target fuse unit of the fuse array based on the parameter signal.

8. The fuse circuit according to claim 7, characterized in that: The control module is further configured to receive the parameter signal and enable or disable based on the parameter signal.

9. A chip control method, characterized in that: The chip control method comprises: Receive a clock signal and a data signal, and sample and decode the data signal according to the clock signal to generate a control signal; The fuse unit is operated accordingly according to the control signal, the fuse array comprises a plurality of the fuse units arranged in an array, and each of the fuse units comprises a selection transistor and a breakdown capacitor.

10. The chip control method according to claim 9, characterized in that: The step of sampling and decoding the data signal according to the clock signal to generate a control signal comprises: Receive the clock signal from the clock interface, receive the data signal from the data interface, the data signal includes N bits of serial data, N is a positive integer; Sampling the data signal according to the clock signal, and outputting N coded signals in parallel; The control signal is generated based on decoding of the encoded signal.

11. The chip control method according to claim 10, characterized in that: The step of generating the control signal based on decoding the coded signal comprises: Decoding and generating a mode signal based on j of the coded signals, 1≤j<N and j is an integer; A parameter signal is generated based on the (Nj) coded signals, and the control signal includes the mode signal and the parameter signal.

12. The chip control method according to claim 11, characterized in that: The step of generating a parameter signal based on decoding of (Nj) coded signals comprises: When the mode signal is valid, the (Nj) coded signals are compared with a preset value, an enable signal is output, and the fuse circuit is turned on or off based on the enable signal; When the mode signal is a setting mode, a parameter signal is generated by decoding the (Nj) coded signals.

13. The chip control method according to claim 12, characterized in that: The step of comparing (Nj) coded signals with a preset value and outputting an enable signal comprises: When (Nj) of the coded signals are identical to the first preset data, generating an enable signal at a valid level; When (Nj) of the coded signals are identical to the second preset data, an enable signal at an inactive level is generated.

14. The chip control method according to claim 12, characterized in that: The step of generating a parameter signal based on decoding of (Nj) coded signals comprises: When the mode signal is the first command mode and the digital signal is the first value, the parameter signal includes an operation command signal, and the operation command signal is one of a read command, a write command, and a broadcast command; When the mode signal is the second command mode, the parameter signal includes a target read data signal; When the mode signal is the third command mode, the parameter signal includes a target write data signal; When the mode signal is in the first command mode and the digital signal is in the second value, the parameter signal includes an address signal.

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