Shift register, gate drive circuit, drive method and display device

Abstract

The invention provides a shift register, a gate driving circuit, a driving method and a display device. The shift register comprises a denoising sub-circuit; the de-noising sub-circuit comprises a pull-down control sub-circuit, a pull-down de-noising sub-circuit and a reset de-noising sub-circuit; the pull-down controller writes a first power supply voltage signal into a second node; the pull-down denoising sub-circuit discharges the first node and the output signal end through a second power supply voltage signal end under the control of the potential of the second node; and the reset denoising sub-circuit discharges the pull-up node and the output signal end through a second power supply voltage signal end under the control of a second reset signal. According to the invention, the number of elements of the de-noising sub-circuit can be reduced, and performance drift caused by the fact that circuit elements in the de-noising sub-circuit are in a bias state for a long time can be avoided, so that the reliability of the shift register is improved.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims application number filed on January 2, 2024 P The entire contents of the PCT application No. CT / CN2024 / 070169 are incorporated herein by reference. Technical Field

[0003] The present invention relates to the field of display technology, and in particular to a shift register, a gate drive circuit, a drive method and a display device. Background Art

[0004] As a typical field of new generation information technology integration and innovation, the key technologies of virtual reality (VR) are becoming more mature, the market is developing rapidly, and it is in a rapid upward trend. In recent years, the global VR commercialization scenarios have become increasingly diversified. In addition to the application scenarios that are well known to the public, such as games and entertainment, VR has gradually entered new fields such as medical care, education, and manufacturing, and the industry penetration rate is also increasing. With the rapid development of display technology, traditional LCD (Liquid Crystal Display) technology has matured; with the rise of VR products, the application of LCD products in VR has brought new technical layout and vitality to the LCD field. The current pixel circuit of LCD is a 1T or 2T design, where T stands for Thin Film Transistor (TFT), which is relatively simple and can achieve ultra-high pixel density (Pixels Per Inch, PPI). Compared with the organic light-emitting diode (OLED) display technology, it has advantages, and the LCD process technology is mature, and it also has advantages in cost control. Today, VR display technology in the LCD field has completed mass production of 1200PPI-level products and has reserved 1500PPI technology; with the increase in VR market demand, the speed of technology iteration is accelerating, and there is an urgent need for the implementation of PPI technology above 2000, including corresponding Real RGB pixel design, optical innovation and more sophisticated process technology. Summary of the invention

[0005] In one aspect, an embodiment of the present invention provides a shift register, comprising a denoising subcircuit;

[0006] The denoising subcircuit includes a pull-down control subcircuit, a pull-down denoising subcircuit and a reset denoising subcircuit;

[0007] The pull-down control subcircuit is electrically connected to the first power supply voltage signal terminal and the second node respectively, and is used to write the first power supply voltage signal provided by the first power supply voltage signal terminal into the second node;

[0008] The pull-down denoising subcircuit is electrically connected to the second node, the first node, the second power supply voltage signal terminal and the output signal terminal respectively, and is used to discharge the first node and the output signal terminal through the second power supply voltage signal terminal under the control of the potential of the second node;

[0009] The reset denoising sub-circuit is electrically connected to the second reset signal terminal, the first node, the second power supply voltage signal terminal and the output signal terminal, respectively, and is used to discharge the pull-up node and the output signal terminal through the second power supply voltage signal terminal under the control of the second reset signal provided by the second reset signal terminal.

[0010] Optionally, the pull-down control subcircuit is also electrically connected to a third power supply voltage signal terminal, and is configured to write the first power supply voltage signal into the second node under the control of a third power supply voltage signal provided by the third power supply voltage signal terminal.

[0011] Optionally, the denoising subcircuit further includes a second node denoising subcircuit;

[0012] The second node denoising subcircuit is electrically connected to the denoising control terminal, the second node and the second power supply voltage signal terminal respectively, and is used to control the second node to be connected to the second power supply voltage signal terminal under the control of the denoising control signal provided by the denoising control terminal;

[0013] The de-noising control terminal is the second reset signal terminal or the fourth power supply voltage signal terminal.

[0014] Optionally, the reset denoising subcircuit includes a first transistor and a second transistor;

[0015] The control electrode of the first transistor is electrically connected to the second reset signal terminal, the first electrode of the first transistor is electrically connected to the output signal terminal, and the second electrode of the first transistor is electrically connected to the second power supply voltage signal terminal;

[0016] The control electrode of the second transistor is electrically connected to the second reset signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second power supply voltage signal terminal.

[0017] Optionally, the pull-down control subcircuit includes a third transistor;

[0018] The control electrode of the third transistor is electrically connected to the third power supply voltage signal terminal, the first electrode of the third transistor is electrically connected to the first power supply voltage signal terminal, and the second electrode of the third transistor is electrically connected to the second node.

[0019] Optionally, the pull-down control subcircuit includes a third transistor;

[0020] The control electrode of the third transistor and the first electrode of the third transistor are both electrically connected to the first power supply voltage signal terminal, and the second electrode of the third transistor is electrically connected to the second node.

[0021] Optionally, the second node denoising subcircuit includes a fourth transistor;

[0022] The control electrode of the fourth transistor is electrically connected to the de-noising control terminal, the first electrode of the fourth transistor is electrically connected to the second node, and the second electrode of the fourth transistor is electrically connected to the second power supply voltage signal terminal.

[0023] Optionally, the pull-down denoising subcircuit includes a fifth transistor and a sixth transistor;

[0024] The control electrode of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the second power supply voltage signal terminal;

[0025] The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the output signal terminal, and the second electrode of the sixth transistor is electrically connected to the second power supply voltage signal terminal;

[0026] The denoising sub-circuit also includes a seventh transistor and an eighth transistor;

[0027] The control electrode of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second node, and the second electrode of the seventh transistor is electrically connected to the second power supply voltage signal terminal;

[0028] The control electrode of the eighth transistor is electrically connected to the input signal terminal, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the second power supply voltage signal terminal.

[0029] The shift register described in at least one embodiment of the present invention further includes an input subcircuit, an output subcircuit and a reset subcircuit;

[0030] The input subcircuit is electrically connected to the input signal terminal and the first node respectively, and is used to write an input signal to the first node under the control of the input signal provided by the input signal terminal;

[0031] The output subcircuit is electrically connected to the clock signal terminal, the first node and the output signal terminal respectively, and is used to output the clock signal provided by the clock signal terminal to the output signal terminal under the control of the potential of the first node;

[0032] The reset subcircuit is electrically connected to the first reset signal terminal, the first node and the second power supply voltage signal terminal respectively, and is used to reset the first node through the second power supply voltage signal provided by the second power supply voltage signal terminal under the control of the first reset signal provided by the first reset signal terminal.

[0033] Optionally, the input subcircuit includes a ninth transistor; the reset subcircuit includes a tenth transistor; and the output subcircuit includes an eleventh transistor and a capacitor;

[0034] The control electrode of the ninth transistor and the first electrode of the ninth transistor are both electrically connected to the input signal terminal, and the second electrode of the ninth transistor is electrically connected to the first node;

[0035] The gate of the tenth transistor is electrically connected to the first reset signal terminal, the first electrode of the tenth transistor is electrically connected to the first node, and the second electrode of the tenth transistor is electrically connected to the second power supply voltage signal terminal;

[0036] The gate of the eleventh transistor is electrically connected to the first node, the first electrode of the eleventh transistor is electrically connected to the clock signal terminal, and the second electrode of the eleventh transistor is electrically connected to the output signal terminal;

[0037] The first end of the capacitor is electrically connected to the first node, and the second end of the capacitor is electrically connected to the output signal end.

[0038] Optionally, the control electrode of the eleventh transistor includes a first control electrode and a second control electrode, and the first control electrode and the second control electrode are both electrically connected to the first node.

[0039] In a second aspect, an embodiment of the present invention provides a gate driving circuit, comprising a plurality of cascaded shift registers as described above.

[0040] Optionally, the shift register includes a first reset signal terminal; the multiple cascaded shift registers are divided into M driving partitions, M>1 and is an integer; in the same driving partition, the output signal terminal of the i-th shift register is electrically connected to the input signal terminal of the i+1-th shift register and the first reset signal terminal of the i-1-th shift register, respectively, i is an integer, i is greater than or equal to 2 and less than or equal to N-1, N≥3 and is an integer;

[0041] The gate drive circuit also includes M first power supply voltage signal lines and M reset signal lines, and one of the drive partitions corresponds to one of the first power supply voltage signal lines and one of the reset signal lines; the second reset signal end of each shift register in the same drive partition is electrically connected to the reset signal line corresponding to the drive partition, and the first power supply voltage signal end of each shift register in the same drive partition is electrically connected to the first power supply voltage signal line corresponding to the drive partition.

[0042] Optionally, the denoising subcircuit further includes a second node denoising subcircuit; the denoising control terminal is a fourth power supply voltage signal terminal;

[0043] The gate driving circuit further includes M fourth power supply voltage signal lines; one of the driving partitions corresponds to one of the fourth power supply voltage signal lines;

[0044] The fourth power supply voltage signal terminal of each shift register in the same driving subarea is electrically connected to the fourth power supply voltage signal line corresponding to the driving subarea.

[0045] Optionally, M is equal to 2; the first fourth power supply voltage signal line and the second first power supply voltage signal line are the same signal line, and the second fourth power supply voltage signal line and the first first power supply voltage signal line are the same signal line;

[0046] The first power supply voltage signal terminal of each shift register in the first driving subarea is electrically connected to the first first power supply voltage signal line, and the fourth power supply voltage signal terminal of each shift register in the first driving subarea is electrically connected to the second first power supply voltage signal line;

[0047] The first power supply voltage signal terminal of each shift register in the second driving partition is electrically connected to the second first power supply voltage signal line, and the fourth power supply voltage signal terminal of each shift register in the second driving partition is electrically connected to the first first power supply voltage signal line.

[0048] In a third aspect, an embodiment of the present invention provides a driving method of a gate driving circuit, which is applied to the above-mentioned gate driving circuit, and the driving method includes:

[0049] The first power supply voltage signal terminal is controlled to input the first power supply voltage signal, so that the pull-down control subcircuit writes the first power supply voltage signal into the second node, and the pull-down denoising subcircuit discharges the first node and the output signal terminal through the second power supply voltage signal terminal; or, the second reset signal terminal is controlled to input the second reset signal, so that the reset denoising subcircuit discharges the first node and the output signal terminal through the second power supply voltage signal terminal under the control of the second reset signal.

[0050] Optionally, the shift register further includes an input subcircuit, an output subcircuit and a reset subcircuit; and the driving method further includes:

[0051] Controlling the input signal terminal to input an input signal so that the input subcircuit writes the input signal at the first node;

[0052] Controlling the clock signal terminal to input a clock signal, so that the output sub-circuit outputs the clock signal to the output signal terminal under the control of the potential of the first node;

[0053] The first reset signal terminal is controlled to input the first reset signal, so that the reset subcircuit resets the first node through the second power supply voltage signal provided by the second power supply voltage signal terminal.

[0054] Optionally, the multiple cascaded shift registers are divided into M driving partitions, the gate driving circuit further includes M first power supply voltage signal lines and M reset signal lines, one driving partition corresponds to one first power supply voltage signal line and one reset signal line; the second reset signal end of each shift register of the same driving partition is connected to the reset signal line corresponding to the driving partition, and the first power supply voltage signal end of each shift register of the same driving partition is connected to the first power supply voltage signal line corresponding to the driving partition;

[0055] The driving method comprises: when scanning the shift register in the j-th driving partition,

[0056] The first power supply voltage signal line corresponding to the j-th driving partition is controlled to input a valid first power supply voltage signal; and the reset signal lines corresponding to the remaining driving partitions except the j-th driving partition are controlled to input a valid second reset signal.

[0057] The driving method according to at least one embodiment of the present invention further comprises: when scanning the shift register in the j-th driving subarea,

[0058] The reset signal line corresponding to the j-th driving subarea is controlled to input an invalid second reset signal, and the first power supply voltage signal lines corresponding to the remaining driving subareas except the j-th driving subarea are controlled to input an invalid first power supply voltage signal.

[0059] Optionally, the denoising subcircuit further includes a second node denoising subcircuit; the denoising control terminal is a fourth power supply voltage signal terminal; the gate drive circuit further includes M fourth power supply voltage signal lines; one drive partition corresponds to one fourth power supply voltage signal line; the fourth power supply voltage signal terminal of each shift register in the same drive partition is electrically connected to the fourth power supply voltage signal line corresponding to the drive partition; the driving method further includes:

[0060] When scanning the shift register in the j-th drive partition,

[0061] The fourth power supply voltage signal line corresponding to the jth driving subarea is controlled to input an invalid first power supply voltage signal, and the first power supply voltage signal lines corresponding to the remaining driving subareas except the jth driving subarea are controlled to input a valid fourth power supply voltage signal.

[0062] In a fourth aspect, an embodiment of the present invention provides an array substrate, including:

[0063] A base substrate, the base substrate comprising a display area and a peripheral area;

[0064] A plurality of cascaded shift registers according to any one of claims 1 to 11 are arranged in the peripheral area.

[0065] Optionally, no more than two columns of the shift registers are arranged in a peripheral area located on the same side of the display area, the area where each column of shift registers is located includes a first sub-area and a second sub-area, the input sub-circuit, the reset sub-circuit and the denoising sub-circuit are located in the first sub-area, the output sub-circuit is located in the second sub-area, and the second sub-area is closer to the display area than the first sub-area;

[0066] The denoising subcircuit includes a first transistor, a second transistor, a third transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, the input subcircuit includes a ninth transistor, and the reset subcircuit includes a tenth transistor;

[0067] The array substrate further comprises a first power supply voltage signal line, a second power supply voltage signal line, a clock signal line and a reset signal line, wherein the second power supply voltage signal line comprises a first low level signal line and a second low level signal line;

[0068] In the direction from the first sub-region to the second sub-region, the first power supply voltage signal line, the reset signal line, the first low-level signal line, the clock signal line and the second low-level signal line are arranged in sequence; the third transistor is arranged on the side of the first power supply voltage signal line away from the second sub-region, the second transistor and the fifth transistor are arranged on the side of the reset signal line close to the second sub-region, the eighth transistor and the seventh transistor are arranged on the side of the first low-level signal line away from the second sub-region, the ninth transistor and the tenth transistor are arranged on the side of the first low-level signal line close to the second sub-region, and the first transistor and the sixth transistor are arranged on the side of the second low-level signal line close to the second sub-region.

[0069] Optionally, the output subcircuit includes an eleventh transistor and a capacitor, and in a column direction of a column of the shift registers, the eleventh transistor and the capacitor are alternately arranged in sequence.

[0070] Optionally, a channel width-to-length ratio of the eleventh transistor is greater than or equal to 120:5 and less than or equal to 300:5.

[0071] Optionally, the channel of the eleventh transistor includes a plurality of sub-channels connected in series, and a channel width-to-length ratio of each of the sub-channels is 20:5.

[0072] In a fifth aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] Figure 1A It is a schematic diagram of the vertical layout of a shift register;

[0074] Figure 1B It is a schematic diagram of an 18T1C shift register;

[0075] Figure 1C yes Figure 1B Schematic diagram of timing control corresponding to the shift register;

[0076] Figure 2 is a structural diagram of a shift register according to at least one embodiment of the present invention;

[0077] Figure 3 is a structural diagram of a shift register according to at least one embodiment of the present invention;

[0078] Figure 4 is a structural diagram of a shift register according to at least one embodiment of the present invention;

[0079] Figure 5 is a structural diagram of a shift register according to at least one embodiment of the present invention;

[0080] Figure 6 is a circuit diagram of a shift register according to at least one embodiment of the present invention;

[0081] Figure 7 is a circuit diagram of a shift register according to at least one embodiment of the present invention;

[0082] Figure 8 is a circuit diagram of a shift register according to at least one embodiment of the present invention;

[0083] Fig. 9A is a circuit diagram of a shift register according to at least one embodiment of the present invention;

[0084] Fig. 9BWhen the gate drive circuit includes multiple stages of the present invention Fig. 9A In at least one embodiment of the shift register shown, a simulation timing diagram of a final stage driving signal provided by a first stage first node PU1, a first stage second node PD1, a final stage first node PUL, a final stage second node PDL and a final stage output signal terminal GTL;

[0085] Fig. 10A is a circuit diagram of a shift register according to at least one embodiment of the present invention;

[0086] Fig. 10B When the gate drive circuit includes multiple stages of the present invention Fig. 10A In at least one embodiment of the shift register shown, a simulation timing diagram of a final stage driving signal provided by a first stage first node PU1, a first stage second node PD1, a final stage first node PUL, a final stage second node PDL and a final stage output signal terminal GTL;

[0087] Fig.11A is a circuit diagram of a shift register according to at least one embodiment of the present invention;

[0088] Fig. 11B is a circuit diagram of a shift register according to at least one embodiment of the present invention;

[0089] Fig. 12A is a circuit diagram of a shift register according to at least one embodiment of the present invention;

[0090] Fig. 12B is a simulation timing diagram of a final-stage driving signal provided by a first-stage first node PU1, a first-stage second node PD1, a final-stage first node PUL, a final-stage second node PDL and a final-stage output signal terminal GTL when the gate driving circuit includes at least one embodiment of a multi-stage shift register shown in FIG. 12 of the present invention;

[0091] Fig.13 is a schematic diagram of the cascade relationship and corresponding timing control of gate driving circuits of two driving partitions provided according to at least one embodiment of the present invention;

[0092] Fig.14A is a schematic diagram of a timing control simulation of a gate driving circuit provided according to at least one embodiment of the present invention;

[0093] Fig. 14B is the simulation result of the intermediate stage shift register;

[0094] Fig.15 It is the simulation result of the final shift register; the simulation result is the simulation result of one frame time;

[0095] Fig.16 is a schematic diagram of the layout of a shift register in a peripheral area according to at least one embodiment of the present invention;

[0096] Fig.17 is a schematic diagram of the layout of a sub-circuit module in a shift register provided according to at least one embodiment of the present invention;

[0097] Fig.18 3. A circuit layout of an input subcircuit, a reset subcircuit and a denoising subcircuit provided according to at least one embodiment of the present invention;

[0098] Fig.19 is a circuit layout of an output sub-circuit provided according to at least one embodiment of the present invention;

[0099] Fig. 20 is a schematic structural diagram of an eleventh transistor with a dual-gate structure provided according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0100] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0101] The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, in order to distinguish the two electrodes of the transistor except the control electrode, one electrode is called the first electrode and the other electrode is called the second electrode.

[0102] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0103] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0104] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0105] Unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, "one", "one" or "the" and similar words do not indicate quantity restrictions, but indicate that there is at least one. "Include" or "include" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0106] At present, in the pixel design of 1000PPI (Pixels Per Inch) and 1500PPI, the LTPS (low temperature polycrystalline silicon) or LTPO (low temperature polycrystalline oxide) process is often used. When the driving part of GOA (Gate On Array, the gate driving circuit set on the array substrate) adopts the LTPS process, the GOA unit in the LTPS GOA circuit, that is, the shift register can adopt the 8T2C (including 8 transistors and 2 capacitors) structure, and adopt single-sided alternating drive to achieve a border width of ≤1.2mm. However, for the oxide process, the GOA unit often adopts the 18T1C structure, and the oxide GOA unit with high mobility requirements has reached the 23T2C structure; compared with the 8T2C commonly used in LTPS GOA, the 18T1C structure commonly used in oxide GOA currently doubles the number of TFTs (thin film transistors), and the border width naturally increases significantly.

[0107] In addition to the limitations of the GOA circuit, the GOA circuit design of ultra-high PPI VR (virtual reality) products is also affected by pitch. Table 1 lists the pixel pitch and GOA pitch of 1200PPI display products, 1500PPI display products, and 2117PPI display products. It can be seen that the higher the PPI, the smaller the pixel pitch; if the GOA circuit adopts unilateral alternating drive, the pitch of the GOA circuit is twice the pixel pitch. Therefore, the higher the PPI, the smaller the pitch of the GOA circuit, and the smaller the vertical space of the GOA layout in the border area. Layout can only be performed by stretching the horizontal space, which leads to an increase in the border of the product. Among them, the vertical direction can be the column direction of the pixel array on the display substrate or display panel, and the horizontal direction can be the row direction of the pixel array.

[0108] Table 1: Pixel pitch and GOA pitch corresponding to different PPI display products:

[0109]

[0110] For example, for the 2117PPI product in Table 1, the design pixel arrangement of its real RGB is 4×12; the vertical pixel pitch is 12μm (micrometers), and the GOA pitch is 24μm; in some embodiments, a Delta RGB arrangement can also be used, with a pixel arrangement of 6×8 to improve transmittance from the perspective of pixel design; when this design is adopted, the pixel pitch width is only 8μm, and the corresponding GOA pitch, i.e., the vertical space is only 16μm, which will cause a serious problem of insufficient vertical space.

[0111] For details, please refer to Figure 1A , at least one thin film transistor T0, one pull-up line PUL and one pull-down line PDL need to be set in the vertical space of the GOA layout, and it is necessary to ensure that there is no short circuit between the lines. For example, for the current design of the channel length L of the thin film transistor T0 of 5μm to 6μm, the vertical spacing (pitch) required to set a group of GOA units is at least the total spacing d, d is equal to 23μm, where the first spacing d1 occupied by the thin film transistor T0 is about 15.5μm, and the second spacing d2 occupied by PUL and PDL is about 7.5μm; and the GOA pitch of the current 2117PPIDelta RGB design is only 16μm, which cannot place a group of GOA units. This is a GOA layout and border problem caused by the PPI increase.

[0112] Figure 1BA circuit diagram of a stable and effective oxide GOA unit is provided. The GOA unit is an 18T1C structure, that is, it uses 18 oxide thin film transistors and 1 capacitor C. Its main architecture is to use a pull-up node PU to control the output, and the first pull-down node PD1 and the second pull-down node PD2 are discharged alternately. Figure 1B As shown, at least one embodiment of the GOA unit includes:

[0113] A first first transistor M1A is connected to the first control voltage terminal VDDO and the first pull-down node PD1 respectively;

[0114] The second first transistor M1B is connected to the second control voltage terminal VDDE and the second pull-down node PD2 respectively;

[0115] The first second transistor M2A is respectively connected to the pull-up node PU, the first pull-down node PD1 and the first low level signal terminal LVGL;

[0116] The second second transistor M2B is respectively connected to the pull-up node PU, the second pull-down node PD2 and the first low level signal terminal LVGL;

[0117] The first third transistor M3A is respectively connected to the output signal terminal Gt(n), the first pull-down node PD1 and the second low level signal terminal VGL;

[0118] The second third transistor M3B is respectively connected to the output signal terminal Gt(n), the second pull-down node PD2 and the second low level signal terminal VGL;

[0119] The fourth transistor M4 is connected to the pull-up node PU, the second reset signal terminal TRST and the first low level signal terminal LVGL respectively, and the potential of the first low level signal provided by LVGL is lower than the potential of the second low level signal provided by VGL;

[0120] The first sixth transistor M6A is connected to the first pull-down node PD1, the pull-up node PU and the first low level signal terminal LVGL respectively;

[0121] The second sixth transistor M6B is respectively connected to the second pull-down node PD2, the pull-up node PU and the first low level signal terminal LVGL;

[0122] The first seventh transistor M7A is connected to the first pull-down node PD1, the input signal terminal STV and the first low level signal terminal LVGL respectively;

[0123] The second seventh transistor M7B is respectively connected to the second pull-down node PD2, the input signal terminal STV and the first low level signal terminal LVGL;

[0124] an eighth transistor M8, connected to the input signal terminal INT and the pull-up node PU respectively;

[0125] The ninth transistor M9 is connected to the pull-up node PU, the first reset signal terminal RST and the first low level signal terminal LVGL respectively, wherein the first reset signal terminal RST may be an output signal terminal of the adjacent next level GOA unit;

[0126] a tenth transistor M10 connected to the clock signal terminal CLK, the pull-up node PU and the output signal terminal Gt(n);

[0127] an eleventh transistor M11, connected to the clock signal terminal CLK, the pull-up node PU and the cascade output signal terminal OC(n);

[0128] The first twelfth transistor M12A is respectively connected to the cascade output signal terminal OC(n), the first pull-down node PD1 and the first low level signal terminal LVGL;

[0129] The second twelfth transistor M12B is respectively connected to the cascade output signal terminal OC(n), the second pull-down node PD2 and the first low level signal terminal LVGL;

[0130] The thirteenth transistor M13 is respectively connected to the output signal terminal Gt(n), the n+1th output signal terminal Gt(n+1) and the second low level signal terminal VGL; n is a positive integer;

[0131] The capacitor C is connected to the pull-up node PU and the output signal terminal Gt(n) respectively.

[0132] The output signal terminal Gt(n) is used to output a light emitting control signal, and OC(n) is used to provide an input signal to the next-stage GOA unit, and is used to provide a first reset signal to the previous-stage GOA unit.

[0133] Figure 1C for Figure 1B A timing control diagram of at least one embodiment of a GOA unit is shown.

[0134] like Figure 1C As shown, the driving cycle includes an input phase t1, an output phase t2, a reset phase t3 and a denoising phase t4 which are arranged successively;

[0135] In the input stage t1, the input signal terminal INT provides a high voltage. Since the gate of M8 and the drain of M8 are connected to form a diode structure, M8 is turned on and the potential of the pull-up node PU is pulled high.

[0136] In the output stage t2, the potential of the pull-up node PU is bootstrapped by the capacitor C, so that M10 is turned on and the high voltage signal provided by the clock signal terminal is provided to the output signal terminal Gt(n);

[0137] In the reset phase t3, the first reset signal terminal RST provides a high voltage signal, T0 is turned on, and the pull-up node PU is reset;

[0138] In the denoising stage t4, VDDO provides a high voltage signal, the gate of M1A and the drain of M1A are electrically connected to form a diode structure, the potential of PD1 is a high voltage, and the pull-up node PU and the output signal terminal Gt(n) are discharged through PD1 for denoising.

[0139] Specifically, during a certain frame display time, VDDO inputs a high voltage signal, transistor M1A is turned on, VDDO directly charges the pull-down node PD1, and keeps the potential of the pull-down node PD1 at a high voltage during operation, thereby using M2A to discharge the pull-up node PU, keeping the pull-up node PU at a low potential state, and reducing the noise of the GOA unit; and during the next frame display time, VDDE switches to a high level state, VDDO switches to a low level state, and the second pull-down node PD2 is switched to work, and the first pull-down node PD1 is resting. The first pull-down node PD1 and the second pull-down node PD2 work alternately.

[0140] In the related art, PD1 and PD2 are used to work alternately to reduce the bias time of the transistor related to the pull-down node, thereby solving the problem of threshold voltage offset of the oxide transistor under bias. However, when this GOA unit is applied to display products with high PPI and small pitch, it will bring the problem of excessive border.

[0141] In order to solve the above problem, in an optional embodiment, as Figure 2 As shown, the shift register described in at least one embodiment of the present invention may include a denoising subcircuit;

[0142] The denoising subcircuit includes a pull-down control subcircuit 41, a pull-down denoising subcircuit 42 and a reset denoising subcircuit 43;

[0143] The pull-down control subcircuit 41 is electrically connected to the first power supply voltage signal terminal VDD and the second node PD respectively, and is used to write the first power supply voltage signal provided by the first power supply voltage signal terminal VDD into the second node PD;

[0144] The pull-down denoising sub-circuit 42 is electrically connected to the second node PD, the first node PU, the second power supply voltage signal terminal VG and the output signal terminal GT respectively, and is used to discharge the first node PU and the output signal terminal GT through the second power supply voltage signal terminal VG under the control of the potential of the second node PD;

[0145] The reset denoising sub-circuit 43 is electrically connected to the second reset signal terminal TRST, the first node PU, the second power supply voltage signal terminal VG and the output signal terminal GT, respectively, and is used to discharge the pull-up node PU and the output signal terminal GT through the second power supply voltage signal terminal VG under the control of the second reset signal provided by the second reset signal terminal TRST.

[0146] The present invention Figure 2 At least one embodiment of the shift register shown may include a denoising subcircuit, and the denoising subcircuit may include a pull-down control subcircuit 41, a pull-down denoising subcircuit 42 and a reset denoising subcircuit 43; the reset denoising subcircuit 43 may discharge the pull-up node PU and the output signal terminal GT under the control of a second reset signal, thereby improving the denoising capability of the shift register for the pull-up node and the output signal terminal, so that only one set of pull-down nodes and corresponding denoising subcircuits are needed to achieve alternate discharge denoising of the pull-up node PU and the output signal terminal GT. Compared with a solution that uses two sets of pull-down nodes and corresponding denoising subcircuits to alternately discharge denoising, it can reduce the number of components of the denoising subcircuit and reduce the border size of display products with high PPI requirements, and avoid performance drift of circuit components in the denoising subcircuit due to being in a bias state for a long time, thereby improving the reliability of the shift register.

[0147] like Figure 3 As shown, in Figure 2 Based on at least one embodiment of the shift register shown, the shift register described in at least one embodiment of the present invention further includes an input subcircuit 10, an output subcircuit 20 and a reset subcircuit 30;

[0148] The input sub-circuit 10 is electrically connected to the input signal terminal INT and the first node PU respectively, and is used to write an input signal to the first node PU under the control of the input signal provided by the input signal terminal INT;

[0149] The output sub-circuit 20 is electrically connected to the clock signal terminal CLK, the first node PU and the output signal terminal GT respectively, and is used to output the clock signal provided by the clock signal terminal CLK to the output signal terminal GT under the control of the potential of the first node PU;

[0150] The reset sub-circuit 30 is electrically connected to the first reset signal terminal RST, the first node PU and the second power supply voltage signal terminal VG, respectively, and is used to reset the first node PU through the second power supply voltage signal provided by the second power supply voltage signal terminal VG under the control of the first reset signal provided by the first reset signal terminal RST.

[0151] In the GOA technology, multiple shift registers are cascaded to form a GOA circuit. Therefore, the input signal terminal INT of the shift register of the current stage can be connected to the output signal terminal or the cascade output terminal of the shift register of the previous stage. Correspondingly, the input signal can be the output signal of the shift register of the previous stage, or the cascade output signal of the shift register of the previous stage. Therefore, in addition to being used to drive the pixels of this row, the output signal of the output signal terminal GT can also be used as a reset signal for the previous row and an input signal for the next row. In some embodiments, the first reset signal terminal RST connected to the reset subcircuit 30 can be connected to the output signal terminal of the shift register of the next stage, and the second reset signal terminal TRST connected to the reset denoising subcircuit 43 can be connected to an independently set reset signal line, and the second reset signal in the reset signal line is output from the timing controller.

[0152] The first power supply voltage signal terminal VDD and the second power supply voltage signal terminal VG are working voltage signals output by a power management integrated circuit (PowerManagement IC, PMIC). For the GOA circuit, unless otherwise specified, the embodiment of the present invention is described by taking the first power supply voltage signal as a high-level working voltage signal and the second power supply voltage signal as a low-level gate-off voltage as an example.

[0153] The timing control process of the shift register can be as follows:

[0154] 1) In the input stage, a valid input signal is input to the input signal terminal INT, so that the input sub-circuit 10 starts to work and writes the input signal into the pull-up node PU;

[0155] 2) In the output stage, under the control of the input signal of the pull-up node PU, the output sub-circuit 20 starts to work and outputs the clock signal provided by the clock signal terminal CLK as a valid output signal to the output signal terminal GT;

[0156] 3) In the reset phase, the first reset signal terminal RST inputs a valid first reset signal to enable the reset sub-circuit 30 to operate, and the pull-up node PU is reset through the second power supply voltage signal terminal VG; and

[0157] 4) In the denoising stage, the voltage signal of the pull-down node PD or the effective second reset signal provided by the second reset signal terminal TRST can be selectively used to operate one of the pull-down denoising sub-circuit 42 or the reset denoising sub-circuit 43 to discharge and denoise the pull-up node PU and the output signal terminal GT.

[0158] The pull-down denoising sub-circuit 42 is a circuit for discharging and denoising the pull-up node PU and the output signal terminal GT under the control of the pull-down node PD, and the reset denoising sub-circuit 43 is a circuit for discharging and denoising the pull-up node PU and the output signal terminal GT under the control of the second reset signal terminal TRST. Therefore, alternate discharge denoising can be selectively achieved through the pull-down denoising sub-circuit 42 or the reset denoising sub-circuit 43. When a valid signal is written to the pull-down node PD, such as a high-potential first power supply voltage signal, the pull-down denoising sub-circuit 42 can be operated, and the low-potential state of the second power supply voltage signal terminal VG can be used to discharge and denoise the pull-up node PU and the output signal terminal GT. Alternatively, when a valid signal is input to the second reset signal terminal TRST, the reset denoising sub-circuit 43 can be operated, and the second power supply voltage signal terminal VG can be used to discharge and denoise the pull-up node PU and the output signal terminal GT.

[0159] Therefore, the shift register of some embodiments of the present invention only needs to use a set of pull-down nodes PD and corresponding denoising sub-circuits to achieve alternating discharge denoising of the pull-up node PU and the output signal terminal GT. Compared with the solution of using two sets of pull-down nodes PD and corresponding denoising circuits for alternating discharge denoising, it can not only reduce the number of components of the denoising sub-circuit and reduce the border size of display products with high PPI requirements, but also avoid the performance drift of the circuit elements in the denoising sub-circuit due to being in a bias state for a long time, thereby improving the reliability performance of the shift register.

[0160] In some embodiments, the second power supply voltage signal terminal VG may include a first low level signal terminal LVGL and a second low level signal terminal VGL; the second power supply voltage signal includes a first low level signal provided by the first low level signal terminal LVGL and a second low level signal provided by the second low level signal terminal VGL, and the voltage value of the first low level signal is lower than the voltage value of the second low level signal; the reset sub-circuit 30 is connected to the first low level signal terminal LVGL, and is used to reset the pull-up node PU through the first low level signal terminal LVGL under the control of the first reset signal provided by the first reset signal terminal RST; the pull-down denoising sub-circuit 42 The first low level signal terminal LVGL and the second low level signal terminal VGL are connected, and are used to discharge the pull-up node PU through the first low level signal terminal LVGL and discharge the output signal terminal GT through the second low level signal terminal VGL under the control of the potential of the pull-down node PD; the reset denoising sub-circuit 43 is connected to the first low level signal terminal LVGL and the second low level signal terminal VGL, and is used to discharge the pull-up node PU through the first low level signal terminal LVGL and discharge the output signal terminal GT through the second low level signal terminal VGL under the control of the second reset signal provided by the second reset signal terminal TRST.

[0161] In some embodiments, the voltage value of the first low level signal may be -10 V, and the voltage value of the second low level signal may be -8 V. By using the first low level signal terminal LVGL with a lower potential to discharge the pull-up node PU, the discharge denoising effect may be improved.

[0162] Optionally, the second power supply voltage signal terminal VG may also only include the second low level signal terminal VGL.

[0163] In at least one embodiment of the present invention, the pull-down control subcircuit is also electrically connected to a third power supply voltage signal terminal, and is used to write the first power supply voltage signal into the second node under the control of a third power supply voltage signal provided by the third power supply voltage signal terminal.

[0164] In a specific implementation, the pull-down control circuit can also be electrically connected to the third power supply voltage signal terminal. Under the control of the third power supply voltage signal, the first power supply voltage signal is written into the second node. The third power supply voltage signal can continuously output a high voltage signal, so that the transistor included in the pull-down control subcircuit is always turned on. When the first power supply voltage terminal provides a low voltage signal, the pull-down control subcircuit can directly lower the potential of the pull-down node.

[0165] like Figure 4 As shown, in Figure 3 Based on at least one embodiment of the shift register shown, the pull-down control subcircuit 41 is also electrically connected to the third power supply voltage signal terminal VGH, and is used to write the first power supply voltage signal into the second node PD under the control of the third power supply voltage signal provided by the third power supply voltage signal terminal VGH.

[0166] In at least one embodiment of the present invention, the denoising subcircuit further includes a second node denoising subcircuit;

[0167] The second node denoising subcircuit is electrically connected to the denoising control terminal, the second node and the second power supply voltage signal terminal respectively, and is used to control the second node to be connected to the second power supply voltage signal terminal under the control of the denoising control signal provided by the denoising control terminal;

[0168] The de-noising control terminal is the second reset signal terminal or the fourth power supply voltage signal terminal.

[0169] In a specific implementation, the denoising sub-circuit may further include a second node denoising sub-circuit, which, under the control of a denoising control signal provided by the denoising control terminal, controls the connection between the second node and the second power supply voltage signal terminal to reset the potential of the second node.

[0170] like Figure 5 As shown, in Figure 3 Based on at least one embodiment of the shift register shown, the shift register described in at least one embodiment of the present invention includes a second node denoising subcircuit 51;

[0171] The second node denoising sub-circuit 51 is electrically connected to the denoising control terminal ST, the second node PD and the second power supply voltage signal terminal VG, respectively, and is used to control the connection between the second node PD and the second power supply voltage signal terminal VG under the control of the denoising control signal provided by the denoising control terminal ST.

[0172] exist Figure 5 In at least one embodiment shown, when the second reset signal terminal is a first frame reset terminal, the denoising control terminal may be a first frame reset terminal;

[0173] When the second reset signal terminal is a second frame reset terminal, the denoising control terminal may be a second frame reset terminal.

[0174] exist Figure 5 In at least one embodiment shown, when the second reset signal terminal is the first frame reset terminal and the first power supply voltage signal terminal is the first control voltage terminal, the denoising control terminal may be the second control voltage terminal;

[0175] When the second reset signal terminal is a second frame reset terminal and the first power supply voltage signal terminal is a second control voltage terminal, the denoising control terminal may be a first control voltage terminal.

[0176] Optionally, the reset denoising subcircuit includes a first transistor and a second transistor;

[0177] The control electrode of the first transistor is electrically connected to the second reset signal terminal, the first electrode of the first transistor is electrically connected to the output signal terminal, and the second electrode of the first transistor is electrically connected to the second power supply voltage signal terminal;

[0178] The control electrode of the second transistor is electrically connected to the second reset signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second power supply voltage signal terminal.

[0179] Optionally, the pull-down control subcircuit includes a third transistor;

[0180] The control electrode of the third transistor is electrically connected to the third power supply voltage signal terminal, the first electrode of the third transistor is electrically connected to the first power supply voltage signal terminal, and the second electrode of the third transistor is electrically connected to the second node.

[0181] Optionally, the pull-down control subcircuit includes a third transistor;

[0182] The control electrode of the third transistor and the first electrode of the third transistor are both electrically connected to the first power supply voltage signal terminal, and the second electrode of the third transistor is electrically connected to the second node.

[0183] Optionally, the second node denoising subcircuit includes a fourth transistor;

[0184] The control electrode of the fourth transistor is electrically connected to the de-noising control terminal, the first electrode of the fourth transistor is electrically connected to the second node, and the second electrode of the fourth transistor is electrically connected to the second power supply voltage signal terminal.

[0185] Optionally, the pull-down denoising subcircuit includes a fifth transistor and a sixth transistor;

[0186] The control electrode of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the second power supply voltage signal terminal;

[0187] The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the output signal terminal, and the second electrode of the sixth transistor is electrically connected to the second power supply voltage signal terminal;

[0188] The denoising sub-circuit also includes a seventh transistor and an eighth transistor;

[0189] The control electrode of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second node, and the second electrode of the seventh transistor is electrically connected to the second power supply voltage signal terminal;

[0190] The control electrode of the eighth transistor is electrically connected to the input signal terminal, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the second power supply voltage signal terminal.

[0191] Optionally, the input subcircuit includes a ninth transistor; the reset subcircuit includes a tenth transistor; and the output subcircuit includes an eleventh transistor and a capacitor;

[0192] The control electrode of the ninth transistor and the first electrode of the ninth transistor are both electrically connected to the input signal terminal, and the second electrode of the ninth transistor is electrically connected to the first node;

[0193] The gate of the tenth transistor is electrically connected to the first reset signal terminal, the first electrode of the tenth transistor is electrically connected to the first node, and the second electrode of the tenth transistor is electrically connected to the second power supply voltage signal terminal;

[0194] The gate of the eleventh transistor is electrically connected to the first node, the first pole of the eleventh transistor is electrically connected to the clock signal terminal, and the second pole of the eleventh transistor is electrically connected to the second power supply voltage signal terminal;

[0195] The first end of the capacitor is electrically connected to the first node, and the second end of the capacitor is electrically connected to the output signal terminal.

[0196] In at least one embodiment of the present invention, the control pole of the eleventh transistor includes a first control pole and a second control pole, and both the first control pole and the second control pole are electrically connected to the first node.

[0197] It should be noted that each transistor used in the shift register can be a thin film transistor (TFT) with an oxide as the active layer. The control pole of each transistor is the gate of the transistor, the first pole is one of the source and drain of the transistor, and the second pole is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetric in structure and can be considered indistinguishable in structure, that is to say, the first pole and the second pole of the transistor in the embodiment of the present invention can be indistinguishable in structure.

[0198] For example, for a P-type transistor, the first pole of the transistor is the source, the second pole is the drain, and the control pole is the gate; according to the conduction condition of the P-type transistor: Vg < Vs, Vgs - Vth < 0, where Vg is the gate voltage, Vs is the source voltage, Vgs is the voltage between the gate and the source, and Vth is the threshold voltage; applying a low-level signal to the gate can turn on the transistor. Another example is that when the transistor is an N-type transistor, the first pole of the transistor is the drain, the second pole is the source, and the control pole is the gate; according to the conduction condition of the N-type transistor: Vg > Vs, Vgs - Vth > 0, it can be seen that applying a high-level signal to the gate can turn on the transistor. Unless otherwise specified, the embodiments of the present invention are described by taking an N-type transistor as an example.

[0199] After connecting the control pole of the third transistor to the first pole, the third transistor can be converted into a diode connection and turned on when a high-voltage signal is input at the first power supply voltage signal terminal VDD, so that the potential of the second node PD is a high voltage. When the second node PD is in a high-level state, the fifth transistor M5 and the sixth transistor M6 whose control poles are connected to the second node PD are turned on, thereby controlling the connection between the first node PU and the first low-level signal terminal LVGL, and controlling the connection between the output signal terminal GT and the second low-level signal terminal VGL, so that the first node PU and the output signal terminal GT are maintained at a low potential state to achieve discharge and noise reduction.

[0200] The reset denoising sub-circuit discharges and denoises the first node PU and the output signal terminal GT under the control of the second reset signal terminal TRST.

[0201] Therefore, the shift register of some embodiments of the present invention can selectively perform discharge denoising on the first node PU and the output signal terminal GT through a pull-down denoising sub-circuit, or perform discharge denoising on the first node PU and the output signal terminal GT through a reset denoising sub-circuit, which can avoid some transistors in the pull-down denoising sub-circuit or the reset denoising sub-circuit working in a biased state for a long time, thereby avoiding the threshold voltage drift of the oxide transistor, which is beneficial to improving control accuracy and reducing control failures.

[0202] like Figure 6 As shown, in Figure 3 Based on at least one embodiment of the shift register shown,

[0203] The reset denoising subcircuit includes a first transistor M1 and a second transistor M2;

[0204] The gate of the first transistor M1 is electrically connected to the second reset signal terminal TRST, the drain of the first transistor M1 is electrically connected to the output signal terminal GT, and the source of the first transistor M1 is electrically connected to the second low level signal terminal VGL;

[0205] The gate of the second transistor M2 is electrically connected to the second reset signal terminal TRST, the drain of the second transistor M2 is electrically connected to the first node PU, and the source of the second transistor M2 is electrically connected to the first low level signal terminal LVGL;

[0206] The pull-down control subcircuit includes a third transistor M3;

[0207] The gate of the third transistor M3 and the drain of the third transistor M3 are both electrically connected to the first power supply voltage signal terminal VDD, and the source of the third transistor M3 is electrically connected to the second node PD;

[0208] The pull-down denoising subcircuit includes a fifth transistor M5 and a sixth transistor M6;

[0209] The gate of the fifth transistor M5 is electrically connected to the second node PD, the drain of the fifth transistor M5 is electrically connected to the first node PU, and the source of the fifth transistor M5 is electrically connected to the first low level signal terminal LVGL;

[0210] The gate of the sixth transistor M6 is electrically connected to the second node PD, the drain of the sixth transistor M6 is electrically connected to the output signal terminal GT, and the source of the sixth transistor M6 is electrically connected to the second low level signal terminal VGL;

[0211] The denoising sub-circuit also includes a seventh transistor M7 and an eighth transistor M8;

[0212] The gate of the seventh transistor M7 is electrically connected to the first node PU, the drain of the seventh transistor M7 is electrically connected to the second node PD, and the source of the seventh transistor M7 is electrically connected to the first low level signal terminal LVGL;

[0213] The gate of the eighth transistor M8 is electrically connected to the input signal terminal INT, the drain of the eighth transistor M8 is electrically connected to the second node PD, and the source of the eighth transistor M8 is electrically connected to the first low level signal terminal LVGL;

[0214] The input subcircuit includes a ninth transistor M9; the reset subcircuit includes a tenth transistor M10; the output subcircuit includes an eleventh transistor M11 and a capacitor C;

[0215] The gate of the ninth transistor M9 and the drain of the ninth transistor M9 are both electrically connected to the input signal terminal INT, and the source of the ninth transistor M9 is electrically connected to the first node PU;

[0216] The gate of the tenth transistor M10 is electrically connected to the first reset signal terminal RST, the drain of the tenth transistor M10 is electrically connected to the first node PU, and the source of the tenth transistor M10 is electrically connected to the first low level signal terminal LVGL;

[0217] The gate of the eleventh transistor M11 is electrically connected to the first node PU, the drain of the eleventh transistor M11 is electrically connected to the clock signal terminal CLK, and the source of the eleventh transistor M11 is electrically connected to the second low level signal terminal VGL;

[0218] A first end of the capacitor C is electrically connected to the first node PU, and a second end of the capacitor C is electrically connected to the output signal terminal GT.

[0219] exist Figure 6 In at least one embodiment of the shift register shown, all transistors are n-type transistors and all transistors are oxide transistors.

[0220] In at least one embodiment of the present invention, the denoising sub-circuit further includes a seventh transistor M7 and an eighth transistor M8;

[0221] The seventh transistor M7 is used to be turned on under the control of the potential of the first node PU, and discharge the second node PD through LVGL; the eighth transistor M8 is used to be turned on under the control of the input signal terminal INT, and discharge the second node PD through LVGL. Therefore, the seventh transistor M7 and the eighth transistor M8 can form a pull-up denoising sub-circuit for discharging and denoising the second node PD under the control of the first node PU.

[0222] In at least one embodiment of the present invention, the input sub-circuit includes a ninth transistor M9; the gate of the ninth transistor M9 and the drain of the ninth transistor M9 are electrically connected to the input signal terminal INT; the ninth transistor M9 is a diode structure, which can be turned on when INT provides a high voltage signal and turned off when INT provides a low voltage signal.

[0223] In at least one embodiment of the present invention, the reset subcircuit includes a tenth transistor M10; when the first reset signal terminal RST outputs a valid first reset signal, M10 is turned on to reset the first node PU through the first low level signal terminal LVGL.

[0224] In at least one embodiment of the present invention, the output subcircuit includes an eleventh transistor M11 and a capacitor C; when the first node PU is in a high level state, M11 is turned on, and the high level clock signal of the clock signal terminal CLK is output as an output signal to the output signal terminal GT. The capacitor C can further increase the voltage of the first node PU in the output stage through bootstrapping or coupling, thereby improving the stability of the signal output.

[0225] At least one embodiment of the present invention provides a shift register with a 10T1C architecture and oxide transistors. Compared with the discharge denoising of the double second nodes of 18T1C, the 10T1C shift register provided by the embodiment of the present invention is a single second node discharge, and 8 thin film transistors are reduced compared with the 18T1C shift register; at the same time, the 10T1C shift register omits the cascade output terminal, and adds a first transistor M1 to form a reset denoising subcircuit, the drain of the first transistor M1 is connected to the output signal terminal GT, the source of the first transistor M1 is connected to the second low-level signal terminal VGL, and the gate is connected to the second reset signal terminal TRST, and the discharge denoising of the output signal terminal GT can be achieved through the second reset signal terminal TRST.

[0226] Compared with the related 18T1C shift register, the 10T1C shift register achieves a reduction in the number of transistors mainly by reducing a set of second nodes and corresponding denoising transistors, and denoising is achieved through a single second node. However, if a single second node is always used for discharge denoising, the related third transistor M3, fifth transistor M5 and sixth transistor M6 will have the problem of threshold voltage drift under long-term bias, significantly reducing the reliability of the shift base heater. Therefore, this problem can be improved by performing discharge denoising through the pull-down denoising subcircuit controlled by the second node PD for part of the time during the display cycle of a frame, and performing discharge denoising through the reset denoising subcircuit controlled by the second reset signal terminal TRST for the remaining time.

[0227] Figure 7 At least one embodiment of the shift register shown is Figure 6 At least one embodiment of the shift register shown differs as follows:

[0228] The source of the second transistor M2 is electrically connected to the second low level signal terminal VGL;

[0229] The source of the fifth transistor M5 is electrically connected to the second low level signal terminal VGL;

[0230] The source of the seventh transistor M7 is electrically connected to the second low level signal terminal VGL;

[0231] The source of the eighth transistor M8 is electrically connected to the second low level signal terminal VGL;

[0232] A source of the tenth transistor M10 is electrically connected to the second low level signal terminal VGL.

[0233] Figure 8 At least one embodiment of the shift register shown is Figure 7 The difference of at least one embodiment of the shift register shown is as follows: it also includes a second node denoising subcircuit;

[0234] The second node denoising subcircuit includes a fourth transistor M4;

[0235] A gate of the fourth transistor M4 is electrically connected to the de-noising control terminal ST, a drain of the fourth transistor M4 is electrically connected to the second node PD, and a source of the fourth transistor M4 is electrically connected to the second low level signal terminal VGL.

[0236] exist Figure 8 In at least one embodiment shown, M4 is an n-type transistor and M4 is an oxide transistor.

[0237] In the present invention Figure 8In at least one embodiment of the shift register shown, a fourth transistor M4 is added, and the gate of M4 is electrically connected to the de-noising control terminal ST. The de-noising control signal provided by the de-noising control terminal ST can be used to de-noise the second node PD, thereby preventing the potential of the second node PD from being affected by leakage current due to the second node PD being in a floating state when the potential of the first node PU is a low voltage and VDD provides a low voltage signal.

[0238] like Fig. 9A As shown, in Figure 8 Based on at least one embodiment of the shift register shown, the denoising control terminal is a second reset signal terminal TRST.

[0239] When the display panel includes Fig. 9A In at least one embodiment of the shift register unit shown,

[0240] In the first driving module for driving the pixel circuit of the upper half screen, the second reset signal terminal is electrically connected to the first reset signal line, and the first power supply voltage signal terminal is electrically connected to the first first power supply voltage signal line;

[0241] In the second driving module for driving the pixel circuit of the lower half screen, the second reset signal terminal is electrically connected to the second reset signal line, and the first power supply voltage signal terminal is electrically connected to the second first power supply voltage signal line;

[0242] When the first driving module scans the pixel circuit of the upper half screen, the first first power supply voltage signal line provides a high voltage signal, the second reset signal line provides a high voltage signal, the second first power supply voltage signal line provides a low voltage signal, and the first reset signal line provides a low voltage signal. At this time, the output signals of the shift registers at all levels in the first driving module are normally transmitted downward, and discharge and noise reduction are performed by the first node PD; the first reset signal line turns off M1, M2 and M4; at this time, the second driving module for driving the pixel circuit of the lower half screen controls M1, M2 and M4 by the second reset signal line to discharge and noise reduction;

[0243] When the first driving module finishes scanning the pixel circuit of the upper half screen, the first first power supply voltage signal line is switched to provide a low voltage signal, the second reset signal line is switched to provide a low voltage signal, the second first power supply voltage signal line is switched to provide a high voltage signal, and the first reset signal line is switched to provide a high voltage signal. At this time, in the first driving module, the first reset signal line is switched to discharge and denoise; the shift register in the second driving module is switched to discharge and denoise by the second node, so that the output signals of the shift registers at each level in the second driving module are transmitted downward normally, thereby completing the function of shift registration.

[0244] In the present invention Fig. 9AIn at least one embodiment of the shift register shown, a fourth transistor M4 is added to discharge the second node PD, so that in the upper half screen scanning time of a frame time, the potential of the second node in the second driving module is a low voltage, and in the lower half screen scanning time of a frame time, the potential of the second node in the first driving module is a low voltage, so as to balance the bias stress of the TFT related to the second node.

[0245] Fig. 9B When the gate drive circuit includes multiple stages of the present invention Fig. 9A In at least one embodiment of the shift register shown, a simulation timing diagram of a final-stage driving signal provided by a first-stage first node PU1, a first-stage second node PD1, a final-stage first node PUL, a final-stage second node PDL and a final-stage output signal terminal GTL.

[0246] like Fig. 10A As shown, in Figure 8 Based on at least one embodiment of the shift register shown, the de-noising control terminal may be a fourth power supply voltage signal terminal VD;

[0247] When the first power supply electrical signal terminal is electrically connected to the first first power supply voltage signal line, the fourth power supply voltage signal terminal may be electrically connected to the second first power supply voltage signal line;

[0248] When the first power supply electrical signal terminal is electrically connected to the second first power supply voltage signal line, the fourth power supply voltage signal terminal may be electrically connected to the first first power supply voltage signal line.

[0249] Fig. 10B When the gate drive circuit includes multiple stages of the present invention Fig. 10A In at least one embodiment of the shift register shown, a simulation timing diagram of a final-stage driving signal provided by a first-stage first node PU1, a first-stage second node PD1, a final-stage first node PUL, a final-stage second node PDL and a final-stage output signal terminal GTL.

[0250] like Fig.11A As shown, in Figure 8 Based on at least one embodiment of the shift register shown, the first power supply voltage signal terminal is electrically connected to the first first power supply voltage signal line VDD1, and the de-noising control terminal is electrically connected to the second first power supply voltage signal line VDD2.

[0251] The present invention Fig.11A When at least one embodiment of the shift register shown is in operation, when VDD1 provides a high voltage signal and VDD2 provides a low voltage signal, the shift register scans normally;

[0252] When VDD1 provides a low voltage signal and VDD2 provides a high voltage signal, M4 is turned on to discharge noise at the second node PD.

[0253] like Fig. 11B As shown, in Figure 8 Based on at least one embodiment of the shift register shown, the first power supply voltage signal terminal is electrically connected to the second first power supply voltage signal line VDD2, and the de-noising control terminal is electrically connected to the first first power supply voltage signal line VDD1.

[0254] The present invention Fig. 11B When at least one embodiment of the shift register shown is in operation, when VDD2 provides a high voltage signal and VDD1 provides a low voltage signal, the shift register scans normally;

[0255] When VDD2 provides a low voltage signal and VDD1 provides a high voltage signal, M4 is turned on to discharge noise from the second node PD.

[0256] The present invention Fig. 12A At least one embodiment of the shift register shown is Figure 7 The difference of at least one embodiment of the shift register shown is as follows: the gate of M3 is electrically connected to the third power supply voltage signal terminal VGH.

[0257] The present invention Fig. 12A When at least one embodiment of the shift register shown is in operation, the gate of M3 is electrically connected to VGH, VGH always provides a high voltage signal, M3 always remains in an open state, and when VDD provides a high voltage signal, the potential of PD is pulled up; when VDD provides a low voltage signal, VDD can directly pull down the potential of PD, and M4 does not need to pull down the potential of PD.

[0258] The present invention Fig. 12A At least one embodiment of the shift register shown requires an increase in VGH, which requires a stronger bias capability for M3.

[0259] Fig. 12B It is a simulation timing diagram of the final stage driving signal provided by the first node PU1 of the first stage, the second node PD1 of the first stage, the first node PUL of the final stage, the second node PDL of the final stage and the output signal terminal GTL of the final stage when the gate driving circuit includes at least one embodiment of the multi-stage shift register shown in Figure 12 of the present invention.

[0260] The gate driving circuit described in the embodiment of the present invention includes a plurality of cascaded shift registers as described above.

[0261] In at least one embodiment of the present invention, the shift register includes a first reset signal terminal; the multiple cascaded shift registers are divided into M driving partitions, M>1 and is an integer; in the same driving partition, the output signal terminal of the i-th shift register is electrically connected to the input signal terminal of the i+1-th shift register and the first reset signal terminal of the i-1-th shift register, respectively, i is an integer, i is greater than or equal to 2 and less than or equal to N-1, N≥3 and is an integer;

[0262] The gate drive circuit also includes M first power supply voltage signal lines and M reset signal lines, and one of the drive partitions corresponds to one of the first power supply voltage signal lines and one of the reset signal lines; the second reset signal end of each shift register in the same drive partition is electrically connected to the reset signal line corresponding to the drive partition, and the first power supply voltage signal end of each shift register in the same drive partition is electrically connected to the first power supply voltage signal line corresponding to the drive partition.

[0263] In the second aspect, based on the same inventive concept, in another optional embodiment, a gate drive circuit is provided, comprising a plurality of cascaded shift registers provided by the first aspect embodiment. The cascading method can be that the shift registers in adjacent rows are cascaded in sequence, or that the shift registers separated by a certain number of rows are cascaded, which is not limited here. When cascading, the output signal end of the shift register of the current stage is connected to the input signal end of the shift register of the next stage and the first reset signal end of the shift register of the previous stage.

[0264] Accordingly, in some embodiments, the timing control method of the gate driving circuit includes:

[0265] 1) In the input stage, the input signal terminal is controlled to provide an input signal so that the input subcircuit writes the input signal at the first node;

[0266] 2) In the output stage, the clock signal terminal CLK is controlled to input a clock signal, so that the output sub-circuit outputs the clock signal to the output signal terminal under the control of the potential of the first node;

[0267] 3) in the reset phase, controlling the first reset signal terminal to input the first reset signal, so that the reset subcircuit resets the first node through the second power supply voltage signal terminal; and,

[0268] 4) In the denoising stage: control the first power supply voltage signal terminal to input the first power supply voltage signal, so that the pull-down control sub-circuit writes the first power supply voltage signal to the second node, and the pull-down denoising sub-circuit discharges the first node and the output signal terminal through the second power supply voltage signal terminal; or, control the second reset signal terminal TRST to input the second reset signal, so that the reset denoising sub-circuit discharges the first node and the output signal terminal through the second power supply voltage signal terminal under the control of the second reset signal.

[0269] It should be noted that the input signal, clock signal, first reset signal, second reset signal, and first power supply voltage signal in the above timing control process are effective signals for controlling the conduction of different types of transistors. For a shift register using N-type transistors, the above effective signals are high-level signals, and for a shift register using P-type transistors, the above effective signals are low-level signals.

[0270] In order to better improve the reliability performance of the shift register, the cascade relationship and timing control can be improved. In some embodiments, multiple cascaded shift registers are divided into M driving partitions, M>1 and is an integer; in the same driving partition, the output signal end of the i-th shift register is respectively connected to the input signal end of the i+1-th shift register and the first reset signal end of the i-1-th shift register, i is an integer between 2 and N-1, N≥3 and is an integer; the gate drive circuit also includes M first power supply voltage signal lines and M reset signal lines, one driving partition corresponds to a first power supply voltage signal line and a reset signal line; the second reset signal end of each shift register in the same driving partition is connected to the reset signal line corresponding to the driving partition, and the first power supply voltage signal end of each shift register in the same driving partition is connected to the first power supply voltage signal line corresponding to the driving partition.

[0271] After the multiple shift registers are divided into multiple driving partitions, the timing of the effective signals of the first power supply voltage signal line and the reset signal line corresponding to the different driving partitions can be controlled to adjust whether each driving partition performs discharge denoising through a pull-down denoising sub-circuit or a reset denoising sub-circuit, so as to reduce the problem of threshold voltage drift caused by long-term bias of transistors related to the denoising sub-circuit.

[0272] In at least one embodiment of the present invention, in the time period of [(j-1)T / M, jT / M], the first power supply voltage signal line corresponding to the jth driving partition is controlled to input the first power supply voltage signal, and the reset signal lines corresponding to the remaining driving partitions are controlled to input the second reset signal; wherein T is the display period or display time of a frame, and j is an integer ranging from 1 to M in sequence.

[0273] Specifically, in the display cycle T of each frame, the display cycle T is divided into corresponding sub-cycles according to the number of driving partitions. In the jth sub-cycle, the first power supply voltage signal line of the jth driving partition is controlled to input a valid first power supply voltage signal, so that the pull-down denoising sub-circuit works, and the pull-up node and the output signal terminal are discharged and denoised through the second node, while the reset signal line corresponding to the jth driving partition does not output a valid signal, so that the reset denoising sub-circuit is in a resting state. For other driving partitions, the corresponding reset signal line is controlled to output a valid second reset signal, and the first power supply voltage signal line does not output a valid signal, so that the reset denoising sub-circuit works, and the pull-down denoising sub-circuit is in a resting state, so as to avoid the problem of threshold voltage drift of the oxide TFT due to long-term bias.

[0274] For the sake of intuition, in an optional embodiment, M=2 is used as an example for illustration. For a certain model of display product, please refer to Fig.13 In the left part, 2880 shift registers are cascaded to form a gate drive circuit, which is divided into two drive partitions. The first drive partition DA1 corresponds to the first drive module for driving the pixel circuit of the upper half screen, including the shift registers of the 1st to 1440th levels, and the second drive partition DA2 corresponds to the second drive module for driving the pixel circuit of the lower half screen, including the shift registers of the 1441st to 2880th levels. The shift register adopts the following structure: Figure 6 The architecture of 10T1C is shown.

[0275] exist Fig.13 , the line labeled TRST1 is the first reset signal line, the line labeled TRST2 is the second reset signal line, the line labeled VDD1 is the first first power supply voltage signal line, and the line labeled VDD2 is the second first power supply voltage signal line.

[0276] exist Fig.13 Among them, the one labeled Y1 is the first-level shift register, the one labeled Y2 is the second-level shift register, the one labeled Y1439 is the 1439th-level shift register, the one labeled Y1440 is the 1440th-level shift register, the one labeled Y1441 is the 1441st-level shift register, the one labeled Y1442 is the 1442nd-level shift register, the one labeled Y2879 is the 2879th-level shift register, and the one labeled Y2880 is the 2880th-level shift register.

[0277] Corresponding to the two driving partitions, two first power supply voltage signal lines and reset signal lines for controlling the denoising sub-circuit are also set accordingly, wherein one first power supply voltage signal line is connected to the control electrodes of the third transistors of all shift registers in one driving partition, and the other first power supply voltage signal line is connected to the control electrodes of the first transistors of all shift registers in another driving partition; the reset signal line is similarly connected to the control electrodes of the corresponding first transistor and second transistor.

[0278] Fig.13 The right part provides the timing control process of the gate drive circuit, dividing a display cycle into two half-frame sub-cycles: an upper half-frame sub-cycle and a lower half-frame sub-cycle. Each half-frame sub-cycle includes an input stage t1, an output stage t2, a reset stage t3 and a denoising stage t4.

[0279] Corresponding to the first driving partition DA1 of the upper half frame sub-period, the corresponding first first power supply voltage signal line VDD1 continuously inputs the first power supply voltage signal of high level, and the first reset signal line TRST1 remains in the low level state. The timing control process includes:

[0280] In the input stage t1, the input signal terminal INT inputs a high-level input signal, turns on the ninth transistor, and writes the high-level input signal into the first node PU; at the same time, the first node PU in the high-level state turns on the seventh transistor, writes the first low-level signal provided by the first low-level signal terminal LVGL into the second node PD, and keeps the second node PD in the low-level state;

[0281] In the output stage t2, the input signal terminal INT changes to a low level state, and the potential of the first node PU is further pulled up under the coupling effect of the capacitor, so that the eleventh transistor is turned on, and the high level clock signal provided by the clock signal terminal is output to the output signal terminal GT;

[0282] In the reset phase t3, the first reset signal terminal RST inputs the high level output signal of the next stage shift register as the first reset signal, so that the tenth transistor is turned on, and the potential of the first node PU is pulled down by the first low level signal terminal; and

[0283] In the denoising stage t4, after the potential of the first node PU is pulled low, the seventh transistor is turned off, and the first power supply voltage signal provided by the first power supply voltage signal terminal is written into the second node PD through the third transistor, so that the second node PD becomes a high potential state, thereby turning on the fifth transistor and the sixth transistor, and discharging and denoising the first node PU through the first low-level signal terminal, and discharging and denoising the output signal terminal GT through the second low-level signal terminal.

[0284] Therefore, the first driving partition DA1 works at the second node PD in the upper half frame sub-period, and discharges and de-noises the pull-up node PU and the output signal terminal GT. The signal transmission from level 1 to level 1440 is realized through the high-level clock signal of the output signal terminal GT, and the first reset signal line TRST1 corresponding to the first driving partition DA1 is in a low-level output state.

[0285] Corresponding to the second driving partition DA2 of the lower half frame sub-period, the corresponding second first power supply voltage signal line VDD2 remains in a low level state, so that the second node PD remains in a low level state, and the second reset signal line TRST2 continues to output a high-level second reset signal, so the first transistor and the second transistor remain in the on state, and all shift registers in the second driving partition DA2 denoise the first node PU and the output signal terminal GT through the reset denoising sub-circuit.

[0286] When the display cycle comes to the second half frame, the first first power supply voltage signal line VDD1 corresponding to the first driving partition DA1 remains in a low level state, so that the second node PD remains in a low level state, and the first reset signal line TRST1 continues to output a high level second reset signal, and all shift registers in the first driving partition DA1 continue to denoise the first node PU and the output signal terminal GT through the reset denoising sub-circuit.

[0287] In the second driving partition DA2 corresponding to the lower half frame sub-period, the corresponding second first power supply voltage signal line VDD2 continuously inputs the high-level first power supply voltage signal, and the second reset signal line TRST2 is kept in the low-level state. The timing control process is the same as that of the first driving partition DA1 in the upper half frame, that is, the second driving partition DA2 is in the state of working at the second node PD and performing discharge denoising on the first node PU and the output signal terminal GT in the lower half frame to period. The signal transmission from level 1441 to level 2880 is realized by the high-level clock signal of the output signal terminal GT, and the second reset signal line TRST2 corresponding to the second driving partition DA2 is in the low-level output state.

[0288] In general, in the upper half frame sub-period, when the first driving module performs shift register work, the first set of first power supply voltage signal line VDD1 and the second reset signal line TRST2 are in a high level state, and the second first power supply voltage signal line VDD2 and the first reset signal line TRST1 are in a low level state. At this time, the output signal end of the shift register from the 1st level to the 1440th level is normally transmitted downward, and discharge and noise reduction are performed by the second node PD, and the first reset signal line TRST1 turns off the corresponding first transistor and the second transistor. For the second driving partition DA2 of the lower half screen, that is, the shift register from the 1441st level to the 2880th level relies on the second reset signal line TRST2 to control the corresponding first transistor and the second transistor for discharge and noise reduction, and at this stage, there is no output signal transmission action from the 1441st level to the 2880th level, and the second reset signal line TRST2 can be used to achieve discharge and noise reduction.

[0289] When the output signal is transmitted to the 1441th level, it enters the lower half frame sub-cycle, the first first power supply voltage signal line VDD1 switches to a low level state, and the first reset signal line TRST1 switches to a high level state. At this time, the discharge of the 1st level shift register to the 1440th level shift register is controlled by the second node PD and switched to the discharge denoising controlled by the second reset signal terminal TRST; at the same time, the second first power supply voltage signal line VDD2 switches to a high level state, and the second reset signal line TRST2 switches to a low level state, and the 1441th level shift register to the 2880th level shift register is transformed into the discharge denoising controlled by the second node PD to cope with the output signal being transmitted from the 1441th level to the 2880th level, thereby completing the function of the GOA shift register.

[0290] Therefore, the gate drive circuit provided by at least one embodiment of the present invention performs denoising by discharging and denoising the upper half screen and the lower half screen in different time periods, and uses the second node PD and the second reset signal terminal TRST to discharge and denoise the first node PU and the output signal terminal GT of the shift register within the display cycle or display time of a frame. Compared with the discharge circuit with a single second node without the second transistor, such as the 9T1C structure, the positive bias time PB and the negative bias time NB of the third transistor, the fifth transistor, and the sixth transistor related to the second node PD, and the first transistor and the second transistor related to the second reset signal terminal TRST in the shift register described in at least one embodiment of the present invention are both 50%. By adjusting the timing of the positive and negative bias voltages, the bias working state of the key oxide TFT is balanced, the stability of the oxide TFT is significantly improved, and the yield and reliability of the shift register and the gate drive circuit are improved. Table 2 provides the bias time and nominal size (size) of each oxide TFT in the 9T1C shift register during operation, as well as the bias time and nominal size (size) of each oxide TFT in the 10T1C shift register during operation. In Table 2, W / L is the ratio of the channel width W to the channel length L of each transistor, PBT represents the positive bias time ratio, and NBT represents the negative bias time ratio; in order to reduce the border. By optimizing the channel width W of each TFT, the minimum W that satisfies the normal operation of the gate drive circuit is achieved.

[0291] Table 2

[0292]

[0293] In the above embodiment, the gate drive circuit based on the 10T1C shift register is divided into zones and time-divided for discharge denoising, mainly by dividing the gate drive circuit in the display product or screen into two drive zones, and adding the first reset signal line TRSR1 and the second reset signal line TRST2 to achieve discharge denoising, wherein one drive zone discharges through the second node PD, and the other drive zone can discharge through the first reset signal line TRST1 or the second reset signal line TRST2, and the time-divided zone discharge is achieved by this switching method. It should be noted that the above two drive zones are exemplary descriptions. On this basis, in some embodiments, the gate drive circuit can also be divided into multiple more drive zones for time-divided discharge denoising, and more first power supply voltage signal lines and reset signal lines are added to achieve this. In this design, the gate drive circuit can realize signal transmission when discharging through the second node PD, but the gate drive circuit cannot transmit signals when discharging through the reset signal terminal TRST, so it is necessary to allocate whether the discharge denoising is performed by the second node PD or the reset signal line according to the drive signal transmission.

[0294] Fig.14A This is a schematic diagram of the timing control simulation of the gate drive circuit. Fig.14A PU1 in the figure represents the first node in the first-level shift register, GT1 represents the output signal end of the first-level shift register, PU1441 represents the first node of the 1441st-level shift register, and GT1441 represents the output signal end of the 1441st-level shift register; PD1 represents the second node in the 1440th-level shift register, and PD2 represents the second node in the 1441st-level shift register to the 2880th-level shift register. The first reset signal line TRST1 switches earlier than PD1 to ensure the discharge and denoising of the 1st-level shift register to the 1440th-level shift register; the second reset signal line TRST2 must switch to a low level before the 1441st-level shift register starts working to ensure that the drive signal is transmitted to the 1441st-level shift register. PD2 officially starts discharging after the output of the 1441st-level shift register ends. Fig.14A The simulation results verify that the 10T1C shift register can meet the normal operation of the gate drive circuit.

[0295] In at least one embodiment of the present invention, the denoising subcircuit further includes a second node denoising subcircuit; the denoising control terminal is a fourth power supply voltage signal terminal;

[0296] The gate driving circuit further includes M fourth power supply voltage signal lines; one of the driving partitions corresponds to one of the fourth power supply voltage signal lines;

[0297] The fourth power supply voltage signal terminal of each shift register in the same driving subarea is electrically connected to the fourth power supply voltage signal line corresponding to the driving subarea.

[0298] In at least one embodiment of the present invention, M is equal to 2; the first fourth power supply voltage signal line and the second first power supply voltage signal line are the same signal line, and the second fourth power supply voltage signal line and the first first power supply voltage signal line are the same signal line;

[0299] The first power supply voltage signal terminal of each shift register in the first driving subarea is electrically connected to the first first power supply voltage signal line, and the fourth power supply voltage signal terminal of each shift register in the first driving subarea is electrically connected to the second first power supply voltage signal line;

[0300] The first power supply voltage signal terminal of each shift register in the second driving partition is electrically connected to the second first power supply voltage signal line, and the fourth power supply voltage signal terminal of each shift register in the second driving partition is electrically connected to the first first power supply voltage signal line.

[0301] In at least one embodiment of the present invention, Fig.13The structure of the shift register in can also be as follows Figure 7 , 8 , 9, 10, 12, Fig.13 The shift register in can be an 11T1C shift register.

[0302] In the related 18T1C shift register, the channel width-to-length ratio of M8 is 20 / 5, the positive bias time of M8 accounts for less than 1%, and the negative bias time of M8 accounts for more than 99%; the channel width-to-length ratio of M9 is 6 / 5, the positive bias time of M9 accounts for less than 1%, and the negative bias time of M9 accounts for more than 99%; the channel width-to-length ratio of M10 is 600 / 5, the positive bias time of M10 accounts for less than 1%, and the negative bias time of M10 accounts for more than 99%; M1A's The channel width-to-length ratio is 6 / 5, the positive bias time of M1A is 50%, and the negative bias time of M1A is 50%; the channel width-to-length ratio of M1B is 6 / 5, the positive bias time of M1B is 50%, and the negative bias time of M1B is 50%; the channel width-to-length ratio of M6A is 30 / 5, the positive bias time of M6A is less than 1%, and the negative bias time of M6A is greater than 99%; the channel width-to-length ratio of M6B is 30 / 5, the positive bias time of M6B is less than 1%, and the negative bias time of M6B is greater than 99%. The bias time is greater than 99%; the channel width-to-length ratio of M7A is 30 / 5, the positive bias time of M7A is less than 1%, and the negative bias time of M7A is greater than 99%; the channel width-to-length ratio of M7B is 30 / 5, the positive bias time of M7B is less than 1%, and the negative bias time of M7B is greater than 99%; the channel width-to-length ratio of M2A is 15 / 5, the positive bias time of M2A is 50%, and the negative bias time of M2A is 50%; the channel width-to-length ratio of M2B is 15 / 5, and the M2 The positive bias time of M2B is 50%, and the negative bias time of M2B is 50%; the channel width-to-length ratio of M3A is 20 / 5, the positive bias time of M3A is 50%, and the negative bias time of M3A is 50%; the channel width-to-length ratio of M3B is 20 / 5, the positive bias time of M3B is 50%, and the negative bias time of M3B is 50%; the channel width-to-length ratio of M4 is 600 / 5, the negative bias time of M15 accounts for less than 1%, and the positive bias time of M4 accounts for more than 99%;

[0303] In the relevant 9T1C pixel circuit, the channel width-to-length ratio of M9 is 20 / 5, the positive bias time of M9 accounts for less than 1%, and the negative bias time of M9 accounts for more than 99%; the channel width-to-length ratio of M10 is 6 / 5, the positive bias time of M10 accounts for less than 1%, and the negative bias time of M10 accounts for more than 99%; the channel width-to-length ratio of M11 is 600 / 5, the positive bias time of M11 accounts for less than 1%, and the negative bias time of M11 accounts for more than 99%; the channel width-to-length ratio of M3 is 6 / 5, and the positive bias time of M3 accounts for 100%; the channel width-to-length ratio of M7 is 30 / 5, and the positive bias time of M7 accounts for less than 1%. The time proportion of M7 is less than 1%, and the negative bias time proportion of M7 is greater than 99%; the channel width-to-length ratio of M8 is 30 / 5, the positive bias time proportion of M8 is less than 1%, and the negative bias time proportion of M8 is greater than 99%; the channel width-to-length ratio of M5 is 15 / 5, the positive bias time proportion of M5 is greater than 99%, and the negative bias time proportion of M5 is less than 1%; the channel width-to-length ratio of M6 is 20 / 5, the positive bias time proportion of M6 is greater than 99%, and the negative bias time proportion of M6 is less than 1%; the channel width-to-length ratio of M2 is 20 / 5, the positive bias time proportion of M2 is less than 1%, and the negative bias time proportion of M2 is greater than 99%.

[0304] In the 11T1C shift register of at least one embodiment of the present invention, the channel width-to-length ratio of M9 is 20 / 5, the positive bias time of M9 accounts for less than 1%, and the negative bias time of M9 accounts for more than 99%; the channel width-to-length ratio of M10 is 6 / 5, the positive bias time of M10 accounts for less than 1%, and the negative bias time of M10 accounts for more than 99%; the channel width-to-length ratio of M11 is 600 / 5, the positive bias time of M11 accounts for less than 1%, and the negative bias time of M11 accounts for more than 99%; the channel width-to-length ratio of M3 is 6 / 5, the positive bias time of M3 accounts for 50%, and the negative bias time of M3 accounts for 50%; the channel width-to-length ratio of M7 is 30 / 5, the positive bias time of M7 accounts for less than 1%, and the negative bias time of M7 accounts for more than 99%; the channel width-to-length ratio of M8 is 600 / 5, the positive bias time of M11 accounts for less than 1%, and the negative bias time of M11 accounts for more than 99%; The channel width-to-length ratio of M5 is 15 / 5, the positive bias time of M5 is 50%, and the negative bias time of M5 is 50%; the channel width-to-length ratio of M4 is 15 / 5, the positive bias time of M4 is 50%, and the negative bias time of M4 is 50%; the channel width-to-length ratio of M1 is 20 / 5, the positive bias time of M1 is 50%, and the negative bias time of M1 is 50%; the channel width-to-length ratio of M6 is 20 / 5, the positive bias time of M6 is 50%, and the negative bias time of M6 is 50%; the channel width-to-length ratio of M2 is 20 / 5, the positive bias time of M2 is 50%, and the negative bias time of M2 is 50%.

[0305] From the above comparison, it can be seen that the shift register described in at least one embodiment of the present invention can achieve a state of positive and negative bias balance, and the effect of the double second node in the 18T1C shift register is achieved by using the 11T1C shift register.

[0306] In at least one embodiment of the present invention, it is assumed that the gate driving circuit includes a 2N-stage shift register (the structure of the shift register is the 11T1C structure in at least one embodiment of the present invention), N is a positive integer; the intermediate stages are the Nth stage and the N+1th stage, wherein the Nth stage is the last stage in the first driving module, and the N+1th stage is the first stage in the second driving module, Fig. 14B is the simulation result of the intermediate stage shift register;

[0307] like Fig. 14B As shown, the N-th level first node PUN and the N-th level second node PDN work normally, and the N-th level output signal terminal GTN included in the N-th level shift register outputs the N-th level drive signal normally. At the same time, the N+1-th level first node PUN+1, the N+1-th level second node PDN+1 and the N+1-th level output signal terminal GTN+1 work normally, indicating that when the second reset signal and the first power supply voltage signal of the upper and lower half screens are switched, the drive signal is successfully transmitted from the upper half screen to the lower half screen; the timing of the signal provided by VDD1, the signal provided by TRST1, the signal provided by VDD2 and the signal provided by TRST2 is as shown in Fig. 14B As shown;

[0308] After GTN provides a high voltage signal, TRST1 starts to provide a high voltage signal; before the potential of PUN+1 becomes a high voltage, VDD2 starts to provide a high voltage signal. After VDD2 provides a high voltage, after 1H (a row of scanning time), TRST2 starts to provide a high voltage signal to ensure signal transmission between the Nth stage shift register and the N+1th stage shift register;

[0309] Fig.15 is the simulation result of the final shift register; the simulation result is the simulation result of one frame time, wherein the signal provided by VDD1, the signal provided by VDD2, the signal provided by TRST1 and the signal provided by TRST2 are switched in the middle row;

[0310] like Fig.15 As shown, the first node PUL of the last-stage shift register and the second node PDL of the last-stage shift register can both work normally, and the timing of the drive signal output by the output signal terminal GTL of the last-stage shift register is also consistent with expectations, proving that the drive signal can be transmitted to the last row normally, the gate drive circuit works normally, and there is no noise, multiple output, insufficient output, and other problems. The 11T1C shift register is very stable.

[0311] exist Fig.15 Among them, the one labeled STV is the starting voltage terminal.

[0312] In a third aspect, an embodiment of the present invention provides a driving method of a gate driving circuit, which is applied to the above-mentioned gate driving circuit, and the driving method includes:

[0313] The first power supply voltage signal terminal is controlled to input the first power supply voltage signal, so that the pull-down control subcircuit writes the first power supply voltage signal into the second node, and the pull-down denoising subcircuit discharges the first node and the output signal terminal through the second power supply voltage signal terminal; or, the second reset signal terminal is controlled to input the second reset signal, so that the reset denoising subcircuit discharges the first node and the output signal terminal through the second power supply voltage signal terminal under the control of the second reset signal.

[0314] In at least one embodiment of the present invention, the shift register further includes an input subcircuit, an output subcircuit and a reset subcircuit; and the driving method further includes:

[0315] Controlling the input signal terminal to input an input signal so that the input subcircuit writes the input signal at the first node;

[0316] Controlling the clock signal terminal to input a clock signal, so that the output sub-circuit outputs the clock signal to the output signal terminal under the control of the potential of the first node;

[0317] The first reset signal terminal is controlled to input the first reset signal, so that the reset subcircuit resets the first node through the second power supply voltage signal provided by the second power supply voltage signal terminal.

[0318] In at least one embodiment of the present invention, the plurality of cascaded shift registers are divided into M driving partitions, the gate driving circuit further comprises M first power supply voltage signal lines and M reset signal lines, one driving partition corresponds to one first power supply voltage signal line and one reset signal line; the second reset signal end of each shift register of the same driving partition is connected to the reset signal line corresponding to the driving partition, and the first power supply voltage signal end of each shift register of the same driving partition is connected to the first power supply voltage signal line corresponding to the driving partition;

[0319] The driving method comprises: when scanning the shift register in the j-th driving partition,

[0320] The first power supply voltage signal line corresponding to the j-th driving partition is controlled to input a valid first power supply voltage signal; and the reset signal lines corresponding to the remaining driving partitions except the j-th driving partition are controlled to input a valid second reset signal.

[0321] The driving method according to at least one embodiment of the present invention further comprises: when scanning the shift register in the j-th driving subarea,

[0322] The reset signal line corresponding to the j-th driving subarea is controlled to input an invalid second reset signal, and the first power supply voltage signal lines corresponding to the remaining driving subareas except the j-th driving subarea are controlled to input an invalid first power supply voltage signal.

[0323] In at least one embodiment of the present invention, the denoising subcircuit further includes a second node denoising subcircuit; the denoising control terminal is a fourth power supply voltage signal terminal; the gate drive circuit further includes M fourth power supply voltage signal lines; one of the drive partitions corresponds to one of the fourth power supply voltage signal lines; the fourth power supply voltage signal terminals of each shift register in the same drive partition are electrically connected to the fourth power supply voltage signal line corresponding to the drive partition; the driving method further includes:

[0324] When scanning the shift register in the j-th drive partition,

[0325] The fourth power supply voltage signal line corresponding to the jth driving subarea is controlled to input an invalid first power supply voltage signal, and the first power supply voltage signal lines corresponding to the remaining driving subareas except the jth driving subarea are controlled to input a valid fourth power supply voltage signal.

[0326] In a fourth aspect, an embodiment of the present invention provides an array substrate, the array substrate comprising:

[0327] A base substrate, the base substrate comprising a display area and a peripheral area;

[0328] A plurality of cascaded shift registers are provided in the peripheral area.

[0329] In at least one embodiment of the present invention, no more than two columns of the shift registers are arranged in a peripheral area located on the same side of the display area, and the area where each column of shift registers is located includes a first sub-area and a second sub-area, the input sub-circuit, the reset sub-circuit and the denoising sub-circuit are located in the first sub-area, and the output sub-circuit is located in the second sub-area, and the second sub-area is closer to the display area than the first sub-area;

[0330] The denoising subcircuit includes a first transistor, a second transistor, a third transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, the input subcircuit includes a ninth transistor, and the reset subcircuit includes a tenth transistor;

[0331] The array substrate further comprises a first power supply voltage signal line, a second power supply voltage signal line, a clock signal line and a reset signal line, wherein the second power supply voltage signal line comprises a first low level signal line and a second low level signal line;

[0332] In the direction from the first sub-region to the second sub-region, the first power supply voltage signal line, the reset signal line, the first low-level signal line, the clock signal line and the second low-level signal line are arranged in sequence; the third transistor is arranged on the side of the first power supply voltage signal line away from the second sub-region, the second transistor and the fifth transistor are arranged on the side of the reset signal line close to the second sub-region, the eighth transistor and the seventh transistor are arranged on the side of the first low-level signal line away from the second sub-region, the ninth transistor and the tenth transistor are arranged on the side of the first low-level signal line close to the second sub-region, and the first transistor and the sixth transistor are arranged on the side of the second low-level signal line close to the second sub-region.

[0333] In at least one embodiment of the present invention, the output subcircuit includes an eleventh transistor and a capacitor, and in a column direction of a column of the shift registers, the eleventh transistor and the capacitor are alternately arranged in sequence.

[0334] In at least one embodiment of the present invention, a channel width-to-length ratio of the eleventh transistor is greater than or equal to 120:5 and less than or equal to 300:5.

[0335] In at least one embodiment of the present invention, the channel of the eleventh transistor includes a plurality of sub-channels connected in series, and a channel width-to-length ratio of each of the sub-channels is 20:5.

[0336] An array substrate according to at least one embodiment of the present invention comprises:

[0337] A base substrate, the base substrate comprising a display area and a peripheral area; and a plurality of cascaded shift registers provided by the first aspect embodiment arranged in the peripheral area.

[0338] In some embodiments, by combining the cascade mode of the shift register provided by the first aspect embodiment and the shift register provided by the second aspect embodiment, the width of the peripheral area can be effectively reduced, thereby broadening the application of oxide technology in display products, especially VR (virtual reality) display products.

[0339] For some display products designed with high PPI (pixel density), the GOA (Gate On Array, a gate drive circuit arranged in an array substrate) pitch is insufficient. For example, the GOA pitch of the aforementioned 2117PPI display product is only 16μm, which cannot accommodate a set of shift registers. To solve this problem, in some embodiments, no more than two columns of shift registers are arranged in the peripheral area on the same side of the display area. For high PPI display products, arranging the shift registers in two columns can effectively solve the problem of insufficient GOA pitch.

[0340] Fig.16 A schematic diagram of the layout of a shift register is provided. From left to right, the peripheral area includes: a cutting area CT, i.e., a cutting area of ​​a display panel; a signal wiring area Sig, an area for arranging various signal wirings; a first shift register column LG1 and a second shift register column LG2, which are arranged adjacent to each other. Fig.16 In the embodiment, the first shift register column LG1 is provided with the second-stage shift register Y2 and the fourth-stage shift register Y4, and the second shift register column LG2 is provided with the first-stage shift register Y1 and the third-stage shift register Y3; the common voltage area and the redundant area Com. The side of Com away from the second sub-area ZA2 is the display area.

[0341] In some embodiments, please combine Fig.17 A schematic diagram of a modular layout of the circuit of the first column of shift registers LG1 is provided, wherein the area where each column of shift registers is located includes a first sub-area ZA1 and a second sub-area ZA2, the input sub-circuit 10, the reset sub-circuit 30 and the denoising sub-circuit 40 are located in the first sub-area ZA1, the output sub-circuit 20 is located in the second sub-area ZA2, and the second sub-area ZA2 is closer to the display area than the first sub-area ZA1.

[0342] Taking the 10T1C shift register provided by the embodiment of the first aspect as an example, in some embodiments, the denoising subcircuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and an eighth transistor M8, the input subcircuit 10 includes a ninth transistor M9, and the reset subcircuit 30 includes a tenth transistor M10; the array substrate also includes a first power supply voltage signal line, a second power supply voltage signal line, a clock signal line and a reset signal line, and the second power supply voltage signal line includes a first low-level signal line and a second low-level signal line; in the direction from the first sub-region ZA1 to the second sub-region ZA2, the first power supply voltage signal line, the reset signal line, the first low-level signal line, the clock signal line and the second low-level signal line are arranged in sequence;

[0343] The third transistor M3 is arranged on a side of the first power supply voltage signal line away from the second sub-region ZA2, the second transistor 2 and the fifth transistor M5 are arranged on a side of the reset signal line close to the second sub-region ZA2, the eighth transistor M8 and the seventh transistor M7 are arranged on a side of the first low-level signal line away from the second sub-region ZA2, the ninth transistor M9 and the tenth transistor M10 are arranged on a side of the first low-level signal line close to the second sub-region ZA2, and the first transistor M1 and the sixth transistor M6 are arranged on a side of the second low-level signal line close to the second sub-region ZA2.

[0344] See also Fig.18 The circuit layout diagram of the input subcircuit 10, the reset subcircuit 30 and the denoising subcircuit 40 in the first driving partition DA1 of the upper half screen is provided, and is arranged in order from left to right, that is, in the direction from the edge of the peripheral area to the edge of the display area (horizontally), as follows: the third transistor M3, the first first power supply voltage signal line VDD1, the first reset signal line TRST1, the second transistor M2, the fifth transistor M5, the eighth transistor M7, the seventh transistor M7, the first low-level signal line LVGL, the ninth transistor M9, the tenth transistor M10, the first clock signal line CLK1, the second clock signal line CLK2, the second reset signal line TRST2, the second low-level signal line VGL, the first transistor M1 and the sixth transistor M6. The arrangement order of the above-mentioned transistors and signal lines is currently a better Layout design, which can further reduce the border of the display product.

[0345] In some embodiments, the output sub-circuit 20 includes an eleventh transistor M11 and a capacitor C. In a column direction of a column of shift registers, the eleventh transistor M11 and the capacitor C are alternately arranged in sequence.

[0346] Fig.19 A layout design of the output sub-circuit 20 is provided, in which the eleventh transistor M11 is arranged on the top and the capacitor C is arranged on the bottom in the column direction, that is, the vertical direction of the peripheral area or the column direction of the pixel array. It should be noted that the "top" and "bottom" here are not the up-and-down position relationship in the thickness direction of the array substrate, but the up-and-down relationship in the plane direction of the array substrate. By arranging the capacitor C below the eleventh transistor M11, the capacitor C can be prevented from increasing the border width.

[0347] After the shift register adopts the 10T1C architecture provided by the first embodiment, combined with the above-mentioned peripheral area layout design, the border can be compressed to 1.74mm, specifically: the width L1 of the cutting area CT is about 0.2mm, the width L2 of the signal wiring area Sig is about 0.1mm, the width L3 of the first shift register column LG1 is about 0.67mm, the width L4 of the second shift register column LG2 is about 0.67mm, the width L5 of the common voltage area and the redundant area Com is about 0.1mm, and the total width L1+L2+L3+L4+L5=1.74mm. At present, the minimum border width required for the gate drive circuit of the 18T1C shift register based on Oxide TFT technology is 2.2mm. The 10T1C shift register and the corresponding gate drive circuit provided by at least one embodiment of the present invention can narrow the border to 1.74mm, thereby achieving the effect of reducing the border width by 0.46mm, and well meeting the needs of VR display products.

[0348] In some embodiments, the channel width-to-length ratio of the eleventh transistor M11 is 120: 5 to 300: 5. The channel width of the eleventh transistor M11 affects the frame width, so the channel parameters of the eleventh transistor M11 can be determined according to actual requirements and PPI design.

[0349] according to Figure 17 to Figure 19 From the layout design diagram of FIG. 1 , it can be seen that about 40% of the frame is occupied by the eleventh transistor M11. Currently, the channel width W of the eleventh transistor M11 is about 300 μm, so further narrowing the frame can be started from reducing the channel width W of the eleventh transistor M11.

[0350] In some embodiments, the control electrode of the eleventh transistor M11 includes a first gate and a second gate, and the first gate and the second gate are connected to the first node PU. Fig. 20 As shown, the eleventh transistor M11 can adopt a dual-gate design, including a top gate TG and a bottom gate BG, and the two sides of the channel CL are source-drain metal layers SD, one side is the source, and the other side is the drain. By adding the bottom gate BG and applying a pull-up signal to the top gate TG and the bottom gate BG at the same time, that is, connecting to the pull-up node PU, the on-state current (Ion) of the eleventh transistor M11 can be increased, thereby supporting the reduction of the channel width W of the eleventh transistor M11, and achieving the purpose of reducing the border.

[0351] In some embodiments, see Fig.19, the channel of the eleventh transistor M11 includes a plurality of sub-channels connected in series, and the channel width-to-length ratio of each sub-channel is 20:5. That is, the channel structure adopts a unit cell segmentation design, and the channel width corresponding to a unit cell, that is, a sub-channel, is 20μm, and a plurality of sub-channels are connected in series to form a complete channel structure of the eleventh transistor M11. The unit segmentation design in the channel width direction can better cope with the heat dissipation problem of the oxide TFT caused by the increase of the on-state current Ion.

[0352] Table 3 provides the channel width-to-length ratio W / L and the frame width of the eleventh transistor M11 corresponding to different on-state currents Ion. With the current dual-gate design, the on-state current Ion can reach 5.5 mA (milliamperes), an increase of 60%, thereby narrowing the frame to 1.38 mm.

[0353] Table 3

[0354]

[0355] In summary, the shift register provided by at least one embodiment of the present invention, whose denoising subcircuit includes a pull-down control subcircuit 41, a pull-down denoising subcircuit 42 and a reset denoising subcircuit 43, can selectively use the second power supply voltage signal terminal VG to discharge denoise the first node PU and the output signal terminal GT under the control of the potential of the second node PD, or use the second power supply voltage signal terminal VG to discharge denoise the first node PU and the output signal terminal GT under the control of the second reset signal terminal TRST. Therefore, the shift register provided by the present invention only needs to use a set of second nodes PD and corresponding denoising subcircuits to achieve discharge denoising of the first node PU and the output signal terminal GT. Compared with the scheme of using two sets of second nodes and corresponding denoising circuits to alternately perform discharge denoising, it can not only reduce the number of components of the denoising subcircuit, thereby reducing the frame size of the display product with high PPI requirements, but also avoid the performance drift of the circuit elements in the denoising subcircuit due to being in a bias state for a long time, thereby improving the reliability of the shift register.

[0356] On this basis, the gate driving circuit and array substrate obtained by using the above shift register 100 have the following characteristics:

[0357] 1) For high PPI applications such as VR display, the oxide process route of LCD (liquid crystal display) is adopted, based on a PPI of more than 2000. In order to cope with the problem of increased border caused by a significant reduction in GOA Pitch due to ultra-high PPI, the noise reduction sub-circuit and corresponding timing control of the shift register 100 using oxide TFT are adjusted to reduce the number of oxide TFTs in the shift register, thereby reducing the border width, solving the problem of increased border width of ultra-high PPI display products, and providing core technical support for high-end VR display products.

[0358] 2) In order to reduce the left and right borders of the display product, the results of the denoising subcircuit of the shift register, as well as the cascade and timing control of the gate drive circuit are improved. Specifically, within a frame display time or a display cycle, the second node PD and the second reset signal terminal TRST are used to perform partitioned and time-divided discharge denoising on the shift register, thereby reducing the bias time of the transistor associated with the second node PD or the second reset signal terminal TRST; reducing the threshold voltage drift of the oxide TFT, while simplifying the gate drive circuit and reducing the border width, while improving the reliability of the gate drive circuit and increasing the service life of the display product.

[0359] 3) Based on the circuit architecture of 10T1C, a dual-gate device design is added to the output transistor, i.e., the eleventh transistor M11, to increase the on-state current Ion, reduce the size of the transistor, and further reduce the border; at the same time, the layout of the shift register in the peripheral area is optimized, and the layout of the oxide TFT and signal routing is optimized as much as possible to achieve the purpose of minimizing the border.

[0360] In the fifth aspect, based on the same inventive concept, in another optional embodiment, a display device is provided, including the array substrate provided in the fourth aspect embodiment. The display device may be a display panel, a display module, or a display device. The type of the display panel may be a liquid crystal display panel, a display module is a module after various chips and circuit boards are bound or installed on the display panel, and the display device may be a VR display product, or may be a display, a flat-panel TV, a tablet computer, a mobile phone, a car display, or other electronic device with a display screen.

[0361] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0362] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A shift register, characterized in that: Including denoising sub-circuit; The denoising subcircuit includes a pull-down control subcircuit, a pull-down denoising subcircuit and a reset denoising subcircuit; The pull-down control subcircuit is electrically connected to the first power supply voltage signal terminal and the second node respectively, and is used to write the first power supply voltage signal provided by the first power supply voltage signal terminal into the second node; The pull-down denoising subcircuit is electrically connected to the second node, the first node, the second power supply voltage signal terminal and the output signal terminal respectively, and is used to discharge the first node and the output signal terminal through the second power supply voltage signal terminal under the control of the potential of the second node; The reset denoising sub-circuit is electrically connected to the second reset signal terminal, the first node, the second power supply voltage signal terminal and the output signal terminal, respectively, and is used to discharge the pull-up node and the output signal terminal through the second power supply voltage signal terminal under the control of the second reset signal provided by the second reset signal terminal.

2. The shift register according to claim 1, wherein: The pull-down control subcircuit is also electrically connected to the third power supply voltage signal terminal, and is used to write the first power supply voltage signal into the second node under the control of a third power supply voltage signal provided by the third power supply voltage signal terminal.

3. The shift register according to claim 1, wherein: The denoising subcircuit also includes a second node denoising subcircuit; The second node denoising subcircuit is electrically connected to the denoising control terminal, the second node and the second power supply voltage signal terminal respectively, and is used to control the second node to be connected to the second power supply voltage signal terminal under the control of the denoising control signal provided by the denoising control terminal; The de-noising control terminal is the second reset signal terminal or the fourth power supply voltage signal terminal.

4. The shift register according to claim 1, wherein: The reset denoising subcircuit includes a first transistor and a second transistor; The control electrode of the first transistor is electrically connected to the second reset signal terminal, the first electrode of the first transistor is electrically connected to the output signal terminal, and the second electrode of the first transistor is electrically connected to the second power supply voltage signal terminal; The control electrode of the second transistor is electrically connected to the second reset signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second power supply voltage signal terminal.

5. The shift register according to claim 2, wherein: The pull-down control subcircuit includes a third transistor; The control electrode of the third transistor is electrically connected to the third power supply voltage signal terminal, the first electrode of the third transistor is electrically connected to the first power supply voltage signal terminal, and the second electrode of the third transistor is electrically connected to the second node.

6. The shift register according to claim 1, wherein: The pull-down control subcircuit includes a third transistor; The control electrode of the third transistor and the first electrode of the third transistor are both electrically connected to the first power supply voltage signal terminal, and the second electrode of the third transistor is electrically connected to the second node.

7. The shift register according to claim 3, wherein: The second node denoising subcircuit includes a fourth transistor; The control electrode of the fourth transistor is electrically connected to the de-noising control terminal, the first electrode of the fourth transistor is electrically connected to the second node, and the second electrode of the fourth transistor is electrically connected to the second power supply voltage signal terminal.

8. The shift register according to claim 1, wherein: The pull-down denoising subcircuit includes a fifth transistor and a sixth transistor; The control electrode of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the second power supply voltage signal terminal; The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the output signal terminal, and the second electrode of the sixth transistor is electrically connected to the second power supply voltage signal terminal; The denoising sub-circuit also includes a seventh transistor and an eighth transistor; The control electrode of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second node, and the second electrode of the seventh transistor is electrically connected to the second power supply voltage signal terminal; The control electrode of the eighth transistor is electrically connected to the input signal terminal, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the second power supply voltage signal terminal.

9. The shift register according to any one of claims 1 to 8, characterized in that: Also includes an input subcircuit, an output subcircuit and a reset subcircuit; The input subcircuit is electrically connected to the input signal terminal and the first node respectively, and is used to write an input signal to the first node under the control of the input signal provided by the input signal terminal; The output subcircuit is electrically connected to the clock signal terminal, the first node and the output signal terminal respectively, and is used to output the clock signal provided by the clock signal terminal to the output signal terminal under the control of the potential of the first node; The reset subcircuit is electrically connected to the first reset signal terminal, the first node and the second power supply voltage signal terminal respectively, and is used to reset the first node through the second power supply voltage signal provided by the second power supply voltage signal terminal under the control of the first reset signal provided by the first reset signal terminal.

10. The shift register according to claim 9, wherein: The input subcircuit includes a ninth transistor; the reset subcircuit includes a tenth transistor; and the output subcircuit includes an eleventh transistor and a capacitor; The control electrode of the ninth transistor and the first electrode of the ninth transistor are both electrically connected to the input signal terminal, and the second electrode of the ninth transistor is electrically connected to the first node; The gate of the tenth transistor is electrically connected to the first reset signal terminal, the first electrode of the tenth transistor is electrically connected to the first node, and the second electrode of the tenth transistor is electrically connected to the second power supply voltage signal terminal; The gate of the eleventh transistor is electrically connected to the first node, the first electrode of the eleventh transistor is electrically connected to the clock signal terminal, and the second electrode of the eleventh transistor is electrically connected to the output signal terminal; The first end of the capacitor is electrically connected to the first node, and the second end of the capacitor is electrically connected to the output signal end.

11. The shift register according to claim 10, wherein: The control electrode of the eleventh transistor includes a first control electrode and a second control electrode, and the first control electrode and the second control electrode are both electrically connected to the first node.

12. A gate driving circuit comprising a plurality of cascaded shift registers according to any one of claims 1 to 11.

13. The gate driving circuit according to claim 12, wherein: The shift register includes a first reset signal terminal; the multiple cascaded shift registers are divided into M driving partitions, M>1 and is an integer; in the same driving partition, the output signal terminal of the i-th shift register is electrically connected to the input signal terminal of the i+1-th shift register and the first reset signal terminal of the i-1-th shift register, respectively, i is an integer, i is greater than or equal to 2 and less than or equal to N-1, N≥3 and is an integer; The gate drive circuit also includes M first power supply voltage signal lines and M reset signal lines, and one of the drive partitions corresponds to one of the first power supply voltage signal lines and one of the reset signal lines; the second reset signal end of each shift register in the same drive partition is electrically connected to the reset signal line corresponding to the drive partition, and the first power supply voltage signal end of each shift register in the same drive partition is electrically connected to the first power supply voltage signal line corresponding to the drive partition.

14. The gate driving circuit according to claim 12, wherein: The denoising subcircuit also includes a second node denoising subcircuit; the denoising control terminal is a fourth power supply voltage signal terminal; The gate driving circuit further includes M fourth power supply voltage signal lines; one of the driving partitions corresponds to one of the fourth power supply voltage signal lines; The fourth power supply voltage signal terminal of each shift register in the same driving subarea is electrically connected to the fourth power supply voltage signal line corresponding to the driving subarea.

15. The gate driving circuit according to claim 14, characterized in that: M is equal to 2; the first fourth power supply voltage signal line and the second first power supply voltage signal line are the same signal line, and the second fourth power supply voltage signal line and the first first power supply voltage signal line are the same signal line; The first power supply voltage signal terminal of each shift register in the first driving subarea is electrically connected to the first first power supply voltage signal line, and the fourth power supply voltage signal terminal of each shift register in the first driving subarea is electrically connected to the second first power supply voltage signal line; The first power supply voltage signal terminal of each shift register in the second driving partition is electrically connected to the second first power supply voltage signal line, and the fourth power supply voltage signal terminal of each shift register in the second driving partition is electrically connected to the first first power supply voltage signal line.

16. A driving method of a gate driving circuit, applied to the gate driving circuit according to any one of claims 12 to 15, characterized in that: The driving method comprises: The first power supply voltage signal terminal is controlled to input the first power supply voltage signal, so that the pull-down control subcircuit writes the first power supply voltage signal into the second node, and the pull-down denoising subcircuit discharges the first node and the output signal terminal through the second power supply voltage signal terminal; or, the second reset signal terminal is controlled to input the second reset signal, so that the reset denoising subcircuit discharges the first node and the output signal terminal through the second power supply voltage signal terminal under the control of the second reset signal.

17. The driving method according to claim 16, characterized in that: The shift register further includes an input subcircuit, an output subcircuit and a reset subcircuit; the driving method further includes: Controlling the input signal terminal to input an input signal so that the input subcircuit writes the input signal at the first node; Controlling the clock signal terminal to input a clock signal, so that the output sub-circuit outputs the clock signal to the output signal terminal under the control of the potential of the first node; The first reset signal terminal is controlled to input the first reset signal, so that the reset subcircuit resets the first node through the second power supply voltage signal provided by the second power supply voltage signal terminal.

18. The driving method according to claim 17, characterized in that: The multiple cascaded shift registers are divided into M driving partitions, and the gate driving circuit further includes M first power supply voltage signal lines and M reset signal lines, and one of the driving partitions corresponds to one of the first power supply voltage signal lines and one of the reset signal lines; the second reset signal end of each shift register of the same driving partition is connected to the reset signal line corresponding to the driving partition, and the first power supply voltage signal end of each shift register of the same driving partition is connected to the first power supply voltage signal line corresponding to the driving partition; The driving method comprises: when scanning the shift register in the j-th driving partition, The first power supply voltage signal line corresponding to the j-th driving partition is controlled to input a valid first power supply voltage signal; and the reset signal lines corresponding to the remaining driving partitions except the j-th driving partition are controlled to input a valid second reset signal.

19. The driving method according to claim 18, characterized in that: Also includes: When scanning the shift register in the j-th drive partition, The reset signal line corresponding to the j-th driving subarea is controlled to input an invalid second reset signal, and the first power supply voltage signal lines corresponding to the remaining driving subareas except the j-th driving subarea are controlled to input an invalid first power supply voltage signal.

20. The driving method according to claim 19, characterized in that: The denoising subcircuit further includes a second node denoising subcircuit; the denoising control terminal is a fourth power supply voltage signal terminal; the gate driving circuit further includes M fourth power supply voltage signal lines; one driving partition corresponds to one fourth power supply voltage signal line; the fourth power supply voltage signal terminal of each shift register in the same driving partition is electrically connected to the fourth power supply voltage signal line corresponding to the driving partition; the driving method further includes: When scanning the shift register in the j-th drive partition, The fourth power supply voltage signal line corresponding to the jth driving subarea is controlled to input an invalid first power supply voltage signal, and the first power supply voltage signal lines corresponding to the remaining driving subareas except the jth driving subarea are controlled to input a valid fourth power supply voltage signal.

21. An array substrate, characterized in that: include: A base substrate, the base substrate comprising a display area and a peripheral area; A plurality of cascaded shift registers according to any one of claims 1 to 11 are arranged in the peripheral area.

22. The array substrate according to claim 21, wherein: No more than two columns of the shift registers are arranged in a peripheral area on the same side of the display area, the area where each column of shift registers is located includes a first sub-area and a second sub-area, the input sub-circuit, the reset sub-circuit and the denoising sub-circuit are located in the first sub-area, the output sub-circuit is located in the second sub-area, and the second sub-area is closer to the display area than the first sub-area; The denoising subcircuit includes a first transistor, a second transistor, a third transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, the input subcircuit includes a ninth transistor, and the reset subcircuit includes a tenth transistor; The array substrate further comprises a first power supply voltage signal line, a second power supply voltage signal line, a clock signal line and a reset signal line, wherein the second power supply voltage signal line comprises a first low level signal line and a second low level signal line; In the direction from the first sub-region to the second sub-region, the first power supply voltage signal line, the reset signal line, the first low-level signal line, the clock signal line and the second low-level signal line are arranged in sequence; the third transistor is arranged on the side of the first power supply voltage signal line away from the second sub-region, the second transistor and the fifth transistor are arranged on the side of the reset signal line close to the second sub-region, the eighth transistor and the seventh transistor are arranged on the side of the first low-level signal line away from the second sub-region, the ninth transistor and the tenth transistor are arranged on the side of the first low-level signal line close to the second sub-region, and the first transistor and the sixth transistor are arranged on the side of the second low-level signal line close to the second sub-region.

23. The array substrate according to claim 22, characterized in that: The output subcircuit comprises an eleventh transistor and a capacitor. In a column direction of a column of the shift registers, the eleventh transistor and the capacitor are alternately arranged in sequence.

24. The array substrate according to claim 23, characterized in that: A channel width-to-length ratio of the eleventh transistor is greater than or equal to 120:5 and less than or equal to 300:

5.

25. The array substrate according to claim 24, characterized in that: The channel of the eleventh transistor includes a plurality of sub-channels connected in series, and a channel width-to-length ratio of each of the sub-channels is 20:

5.

26. A display device comprising the array substrate according to any one of claims 21 to 25.

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