Double data rate synchronous dynamic random access memory test method and computing device

Abstract

The invention provides a double-data-rate synchronous dynamic random access memory testing method and computing equipment, the method is used for performance testing of a multi-path double-data-rate synchronous dynamic random access memory subsystem in a system-on-chip product board, and the method comprises the following steps: setting a plurality of testing frequency points; performing traversal training on the plurality of test frequency points to obtain a first configuration combination set; and carrying out a pressure read-write test on the design target frequency point, carrying out a pressure test on the test frequency point, carrying out a frequency reduction pressure test on the double data rate synchronous dynamic random access memory subsystem which is unqualified in the pressure test, and finding out the frequency point which can pass the pressure test and a corresponding third configuration combination set. According to the technical scheme, comprehensive testing of the double-data-rate synchronous dynamic random access memory subsystem can be comprehensively and stably achieved.

Description

Technical Field

[0001] The present invention relates to the field of development and testing technology, and in particular to a double data rate synchronous dynamic random access memory testing method and computing equipment. Background Art

[0002] In a data flow architecture system-on-chip (SoC) chip, there are usually multiple independent double data rate synchronous dynamic random access memory (DDR) subsystems, which are used to cache data for the CPU, acceleration engine, codec, etc. Errors in cached data can lead to errors in calculation results or even system crashes, so the stability of DDR is crucial.

[0003] The SoC main chip and devices such as double data rate synchronous dynamic random access memory (DDR SDRAM) are all attached to the printed circuit board (PCB) and connected through printed circuit data lines. The signal quality of the data line is closely related to the control logic configuration in the main chip, the configuration of DDR SDRAM, on-board wiring, PCB circuit board production process, device patch process, etc. Any problem in any of these links will cause the DDR subsystem to be unstable or even not work.

[0004] Due to the large number of parallel signal lines between the DDR SDRAM and the SoC main chip, it is necessary to adjust the delay of each signal line (1D training) or adjust the delay and reference voltage of the signal line at the same time (2D training) through the training program in the SoC main chip. During the training process, the delay configuration and reference voltage configuration of each signal line will be traversed, and at the same time, it will be determined whether the size of the digital eye diagram of the signal meets the passing condition. If the signal digital eye diagram is large enough, it will be marked as training passed.

[0005] In addition to signal line delay and reference voltage, there are also configurations such as the signal driving capability and signal terminal value of the SoC main chip port, the signal driving capability and signal terminal value of the DDR SDRAM port, which may affect the opening degree of the digital eye diagram. By traversing and configuring these parameters, the corresponding configuration parameter combination when the eye diagram is maximum can be obtained.

[0006] In addition, the largest parameter configuration set for the eye diagram can be obtained through system simulation, but the accuracy of the simulation is heavily dependent on the accuracy of the simulation models of each component, including the main chip model, PCB circuit board model, DDR SDRAM model, etc. If any of these models has errors, misleading simulation results will be produced.

[0007] The methods described above are all based on training eye diagrams, trying to find the optimal configuration parameter combination of the eye diagram. However, in actual system product testing, the test method of the digital eye diagram is that the number of read and write times during training is relatively small and incomplete; second, the read and write pressure during training is relatively small, and the actual test requires higher driving capabilities for each signal line; third, the training cannot traverse the entire space of SDRAM and cannot scan out defects at a certain address. Therefore, even if the digital eye diagram effect is very good, it may not necessarily run comprehensively and stably, especially in various rigorous stress test procedures and wide temperature environments, defective products may still be leaked to the delivery end. Therefore, relying solely on the eye diagram during training cannot fully test the stability of the system product.

[0008] Therefore, a technical solution is needed to comprehensively and stably implement a comprehensive test of the DDR subsystem. Summary of the invention

[0009] The present invention aims to provide a DDR testing method and computing equipment, which can comprehensively and stably implement a comprehensive test of a DDR subsystem.

[0010] According to one aspect of the present invention, a DDR test method is provided, the method being used for performance testing of a multi-channel DDR subsystem in a system-on-chip product board, the method comprising:

[0011] Obtain multiple test frequency points set according to the design target frequency;

[0012] At the plurality of test frequency points, different configuration combinations of the system-on-chip product board are applied to perform traversal training to obtain a first configuration combination set corresponding to the plurality of test frequency points;

[0013] At the design target frequency point, the first configuration combination set is applied to configure the system-on-chip product board, and a stress read-write test is performed based on a central processing unit bare metal program to obtain a second configuration combination set;

[0014] At the test frequency point, applying the second configuration combination set to configure the system-on-chip product board, performing a stress test based on an operating system stress test program, obtaining a stress test result and locating a DDR subsystem that fails the stress test;

[0015] A frequency reduction stress test is performed on the DDR subsystem that fails the stress test until a frequency point at which the DDR subsystem can pass the stress test and a corresponding third configuration combination set are found.

[0016] According to some embodiments, the method further comprises:

[0017] At other frequency points except the design target frequency point, the first configuration combination set is applied to configure the system-on-chip product board, and a stress read-write test is performed through a central processing unit bare metal program to obtain a fourth configuration combination set.

[0018] According to some embodiments, applying different configuration combinations of the system-on-chip product board to perform traversal training includes:

[0019] At the multiple test frequency points, different configuration combinations of the system-on-chip product board are applied to perform traversal training on the multi-channel double data rate synchronous dynamic random access memory subsystem to obtain training results of different configuration combinations, and record the size of each training eye diagram.

[0020] According to some embodiments, the method further comprises:

[0021] The stress test result set is analyzed to obtain an optimal configuration combination set for the DDR subsystem performance test.

[0022] According to some embodiments, analyzing the stress test result set to obtain an optimal configuration combination set for the DDR subsystem performance test includes:

[0023] The stress test result set is analyzed to obtain a parameter combination set with the largest number of DDR subsystem test passes, which is used as an optimal configuration combination set for the DDR subsystem performance test.

[0024] According to some embodiments, analyzing the stress test result set to obtain an optimal configuration combination set for the DDR subsystem performance test includes:

[0025] If there are configuration combinations with the same number of test passes, refer to the corresponding training eye diagram analysis in the test results and select the configuration parameter combination with the largest eye diagram as the final configuration parameter combination to obtain the optimal configuration combination set for the DDR subsystem performance test.

[0026] According to some embodiments, before applying different configuration combinations of the system-on-chip product board to perform traversal training, the method further includes:

[0027] A certain number of the system-on-chip product boards are randomly selected, and adjustable signal driving capabilities and terminal resistance configuration parameter ranges of the main chip end and the double data rate synchronous dynamic random access memory end of the system-on-chip product board are determined to obtain different configuration combinations of the system-on-chip product board.

[0028] According to some embodiments, the method further comprises:

[0029] The system-on-chip product board is classified according to the configuration combination set and the stress test result set, and the categories include: all DDRs meet the design target frequency, some DDRs need to be operated at a reduced frequency, some DDRs are faulty, and all DDRs are faulty.

[0030] According to another aspect of the present invention, a computer program product is provided, comprising: a computer program, wherein when the computer program is executed by a processor, the computer program performs any of the above methods.

[0031] According to another aspect of the present invention, there is provided a computing device, comprising:

[0032] Processor; and

[0033] A memory storing a computer program, which, when executed by the processor, enables the processor to execute any of the methods described above.

[0034] According to another aspect of the present invention, there is provided a non-transitory computer-readable storage medium having computer-readable instructions stored thereon, and when the instructions are executed by a processor, the processor is caused to execute any of the above methods.

[0035] According to the embodiment of the present invention, multiple test frequency points are set according to the design target frequency, and the optimal DDR configuration parameter combination is selected by automatically training and testing different configuration combinations under different test frequencies and analyzing the test results. Furthermore, read and write and actual stress tests are added, as well as frequency reduction tests after stress tests fail. Compared with the traditional technology that only analyzes the training eye diagram, the test results are more comprehensive, complete and reliable.

[0036] According to some embodiments, the present invention improves test efficiency by combining a bare metal test program with a test program within an operating system, making the test more complete and the results more reliable.

[0037] It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for describing the embodiments are briefly introduced below.

[0039] Figure 1 A flow chart of a DDR test method according to an example embodiment is shown.

[0040] Figure 2 A block diagram of a computing device is shown according to an exemplary embodiment. DETAILED DESCRIPTION

[0041] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0042] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present invention. However, those skilled in the art will appreciate that the technical solution of the present invention can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring various aspects of the present invention.

[0043] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0044] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0045] It should be understood that although the terms first, second, third, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. Therefore, the first component discussed below can be referred to as the second component without departing from the teachings of the present inventive concept. As used herein, the term "and / or" includes any one of the associated listed items and all combinations of one or more.

[0046] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the present invention are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0047] Those skilled in the art will appreciate that the drawings are merely schematic diagrams of example embodiments, and the modules or processes in the drawings are not necessarily necessary for implementing the present invention, and therefore cannot be used to limit the protection scope of the present invention.

[0048] DDR (Double Data Rate) test technology is a test method and technology for DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory). DDR SDRAM is a high-speed memory technology widely used in computer systems, servers, mobile devices and other electronic devices. With the development of DDR technology, the versions of DDR SDRAM are constantly updated, from DDR1, DDR2, DDR3, DDR4 to DDR5, and each new version brings higher data transfer rates and lower power consumption.

[0049] As DDR technology continues to develop, test techniques and tools are also constantly improving to meet the needs of higher performance. In the process of designing and manufacturing DDR SDRAM, the use of advanced test techniques and tools is the key to ensuring product quality and performance. The importance of DDR test technology lies in ensuring that DDR SDRAM can operate stably and reliably under various working conditions.

[0050] To this end, the present invention proposes a DDR testing method and apparatus and computing equipment, which can comprehensively and stably implement comprehensive testing of the DDR subsystem. According to the embodiment, the scheme of the present invention selects the optimal DDR configuration parameter combination by automatically training and testing different configuration combinations at different test frequencies and analyzing the test results, and further adds read-write and actual stress testing. Compared with the traditional technology of analyzing the training eye diagram, the test results are more comprehensive, complete and reliable. The scheme of the present invention improves the test efficiency by combining the bare metal test program with the test program in the operating system, making the test more complete and the results more reliable.

[0051] Exemplary embodiments of the present invention are described below with reference to the accompanying drawings.

[0052] Figure 1 A flow chart of a DDR test method according to an example embodiment is shown.

[0053] See also Figure 1 According to an exemplary embodiment, a DDR test method is provided, the method being used for performance testing of a multi-channel DDR subsystem in a Soc system product board, the method comprising:

[0054] In S101, a plurality of test frequency points set according to a design target frequency are obtained.

[0055] According to some embodiments, according to the design target frequency, a plurality of test frequency points are set, and these test frequency points are less than or equal to the target frequency. Specifically, according to the design target frequency of the DDR subsystem, such as 4266Mbps, a plurality of test frequency points are set, such as 4266Mbps, 3733Mbps, 3200Mbps, 2666Mbps, 2400Mbps, etc. from high to low, the range of the frequency points can be larger or smaller, and the frequency intervals can be set more densely or more sparsely.

[0056] According to some embodiments, the test frequency points are set to define the target operating frequency of the DDR subsystem according to the product specifications and performance requirements. The design target frequency is usually determined based on the highest performance requirements of the SoC and the maximum rated speed of the DDR memory. After the target frequency is determined, a series of test frequency points are set around this frequency. These test frequency points should cover a range from lower frequencies to higher frequencies so that the performance boundaries of the DDR subsystem can be fully evaluated.

[0057] According to some embodiments, under normal circumstances, the test frequency points will include but are not limited to: Minimum stable frequency: This should be the minimum frequency at which the DDR subsystem can ensure stable operation. Target frequency: That is, the normal operating frequency expected during design. In some special scenarios, the test frequency points may also include: Overclocking frequency: One or more points higher than the target frequency, used to test the extreme performance of the DDR subsystem. By setting such test frequency points, the performance of the DDR subsystem can be comprehensively evaluated, and it can be ensured that it can operate stably under various conditions. Next, further tests are performed based on these frequency points.

[0058] In S103, at the multiple test frequency points, different configuration combinations of the system-on-chip product board are applied to perform traversal training to obtain a first configuration combination set corresponding to the multiple test frequency points.

[0059] According to some embodiments, test modes for training are prepared, and these modes should be able to cover all key data transmission rates. Afterwards, a certain number of product boards are randomly selected as test samples, and different configuration combinations of the system-level chip product board are applied to perform traversal training at the multiple test frequency points. The different configuration combinations mainly include the signal drive strength, terminal resistance and level reference voltage at the control chip end, and the signal drive strength, terminal resistance and level reference voltage at the memory end, etc. The traversal training is to perform training tests on all configuration combinations in turn through the control software, retain the parameter combinations that pass the training according to the test results, and obtain the first configuration combination set corresponding to the multiple test frequency points.

[0060] According to some embodiments, at each test frequency point, the training data of the DDR subsystem of each configuration combination is recorded, and these data may include but are not limited to clock cycle, data bit width, bit error rate (BER), eye diagram quality, etc., and the size of the eye diagram is recorded. Among them, the size of the eye diagram is an important indicator for measuring signal quality, which reflects the clarity and stability of the signal.

[0061] According to some embodiments, in general, the training software adjusts the delay of the signal line from the minimum delay to the maximum delay value. A certain delay range in the middle can be correctly read and written, and the remaining delays are beyond the correct reading and writing range. The delay corresponding points that can be correctly read and written are recorded as 0, otherwise they are recorded as 1, and the following one-dimensional eye diagram can be obtained: ...11111111111110000000000000000000000011111111111...

[0063] During one-dimensional training, set the delay value to the position corresponding to 0 in the middle above, so that the signal line has the strongest anti-interference ability.

[0064] For each signal line, you can also set a different reference voltage and perform the above 1D training at each reference voltage value, which is the so-called 2D training. You can get the following 2D training eye diagram (just as a simple example): ...11111111111111111111111111111111111111111111111.. ...1111111111111111111100000000111111111111111111... ...11111111111111110000000000000000111111111111111... ...111111111111110000000000000000000001111111111111... ...11111111111110000000000000000000000011111111111... ...11111111111111110000000000000000001111111111111... ...11111111111111111100000000000011111111111111111... ...11111111111111111111111111111111111111111111111..

[0073] The horizontal axis above is the delay, and the vertical axis is the reference voltage value. The size of the eye diagram can be defined as the widest and highest of the 0 set in the figure above. Of course, in practice, a weight coefficient may be multiplied respectively, so that the delay margin or the reference voltage margin is more emphasized.

[0074] According to some embodiments, at each test frequency point, the relevant signal driving capability configuration and terminal resistance configuration of the SoC main chip end, and the relevant signal driving capability configuration and terminal resistance configuration of the DDR SDRAM end are traversed and trained. If the training passes, the corresponding parameter combination is saved. After multiple traversals, several configuration combination sets that have passed the training corresponding to each frequency point are obtained, ensuring that DDR can perform basic reading and writing at different frequency points.

[0075] According to some embodiments, multiple previously set test frequency points are traversed, and test result sets of all DDR subsystems at these different test frequency points are collected until test results of all test frequency points are obtained, and the test results at all test frequency points are aggregated together to form a complete test result set.

[0076] According to some embodiments, the collected test result sets are screened to determine which configuration combinations of DDR subsystems at different test frequency points are qualified. The qualified test criteria are clarified, and a pass rate threshold is usually set to measure whether the test is suitable.

[0077] According to some embodiments, a first pass threshold is defined according to the specifications and design requirements of the DDR subsystem. The first pass threshold may be a minimum value of the number of training passes, such as 4 successes out of 5 successful trainings. For each DDR subsystem, check whether its number of training passes is greater than or equal to the first pass threshold. If the number of training passes of a certain DDR subsystem is less than the first pass threshold, the DDR subsystem is considered to be faulty, and the test results of the DDR subsystem are discarded. All qualified DDR subsystems and their corresponding test results are aggregated together to form a qualified test result set, namely the first configuration combination set, and the first configuration combination set includes the performance of all qualified DDR subsystems and their configuration combinations at different test frequency points.

[0078] In S105, at the design target frequency point, the first configuration combination set is applied to configure the system-on-chip product board to perform a stress read-write test based on a central processing unit bare metal program to obtain a second configuration combination set.

[0079] According to some embodiments, at the design target frequency point, the first configuration combination set is applied to configure the system-on-chip product board, and read and write tests are performed on the qualified DDR subsystems to screen out qualified read and write configuration combinations, namely the second configuration combinations.

[0080] According to some embodiments, at the design target frequency point, basic stress read and write tests are performed through a CPU bare metal program. The program directly interacts with the CPU and other hardware components (such as memory, I / O devices, etc.) without an operating system as an intermediary. The test content includes traversal read and write, random read and write, etc., and the configuration combination sets that fail the read and write are screened out to obtain the second configuration combination set, so that subsequent operating system-based tests can be performed.

[0081] According to some embodiments, the read / write test should simulate actual application scenarios, such as continuously reading and writing a large amount of data. Alternatively, a dedicated test tool or software is used to perform read / write operations and record the test results. Based on the results of the read / write test, select configuration combinations that can stably read and write with no or very few errors.

[0082] According to some embodiments, all qualified read and write configuration combinations are aggregated to form a qualified read and write configuration combination set, namely, the second configuration combination set, which includes all configuration combinations that can stably read and write at the design target frequency.

[0083] In S107, at the design target frequency point, the second configuration combination set is applied to configure the system-on-chip product board, a stress test is performed based on an operating system stress test program, a stress test result set is obtained, and a DDR subsystem that fails the stress test is located.

[0084] According to some embodiments, at the design target frequency point, the second configuration combination set is applied to configure the system-on-chip product board, the DDR subsystem is stress tested for a certain period of time, and the stress test result sets of all DDR subsystems under these configuration combinations are collected.

[0085] According to some embodiments, for each qualified read and write configuration combination, a stress test is performed at the design target frequency point. The stress test should simulate the high-intensity load in actual applications, use a dedicated test tool or software to perform the stress test, for example, a CPU bare metal program, and record the test results, which include the performance of all qualified read and write DDR subsystems and their configuration combinations under long-term high-intensity loads. By performing stress testing, it is identified which configuration combinations can enable the DDR subsystem to operate stably under long-term high-intensity loads. The stress test result set is analyzed to determine the final set of configuration combinations that pass the performance test, wherein the content recorded in the stress test result set includes the results of whether each system-level chip product board has passed the stress test for different parameter combinations at each test frequency point.

[0086] According to some embodiments, at the design target frequency point, the second configuration combination set is applied to configure the system-level chip product board, the operating system is started, and all multi-channel DDR space is allocated to the operating system. A more complete stress test is performed through the stress testing program in the operating system (such as memtester, stressapptest, etc.). If these stress tests fail, the error address can be used to locate which DDR subsystem the error is in.

[0087] According to some embodiments, the second configuration combination set (i.e., all configuration combinations that are qualified for reading and writing) is applied to configure the Soc system product board, and the stress test results at the design target frequency point are summarized together to form a stress test result set. Such a method can determine which configuration combinations can enable the DDR subsystem to operate stably under long-term high-intensity loads. For DDR subsystems that cannot pass the target frequency point test, their test results at lower frequencies can also be obtained.

[0088] In S109, a frequency reduction stress test is performed on the DDR subsystem that fails the stress test until a frequency point at which the DDR subsystem can pass the stress test and a corresponding third configuration combination set are found.

[0089] According to some embodiments, if it is found that some DDR subsystems cannot pass all configurations corresponding to the target frequency, they need to be processed by rate reduction until a configuration that can pass is found or the configuration combination set of all frequency points is traversed, that is, a third configuration combination set is obtained. Specifically, when a certain DDR subsystem cannot pass all configurations corresponding to the target frequency, it is processed by rate reduction. Starting from the design target frequency, the frequency points are reduced in sequence, for example, 3733Mbps, 3200Mbps, 2666Mbps, 2400Mbps, etc. are tested for frequency reduction in sequence until the test is passed at a certain frequency point, or the configuration combination set of all frequency points is traversed.

[0090] According to some embodiments, the method further includes: applying the first configuration combination set to configure the system-on-chip product board at other frequency points except the design target frequency point, performing stress read and write tests through a central processing unit bare metal program, and obtaining a fourth configuration combination set.

[0091] According to some embodiments, in addition to the design target frequency point, the same read and write test can also be performed on other frequency points. After multiple tests, the optimal configuration combination at each frequency point is obtained, that is, the fourth configuration combination set, and the system product is classified according to the test results. According to the test results and product strategy, corresponding processing is performed. For example: at a frequency of 4266Mbps, the number of DDR paths passed by the test of configuration combination 1 is 1000, the number of paths passed by configuration combination 2 is 900, and the number of paths passed by the remaining combinations is less than 1000, then combination 1 is used as the optimal combination at this frequency. At a frequency of 3733Mbps, the number of DDR paths passed by the test of configuration combination 4 is 1200, the number of paths passed by configuration combination 5 is 800, and the number of paths passed by the remaining combinations is less than 1200, then combination 4 is used as the optimal combination at this frequency. Similarly, the configuration combination with the most test passing paths at other frequency points is obtained. There is an optimal combination corresponding to each frequency.

[0092] According to some embodiments, different configuration combinations of the system-level chip product board are applied to perform traversal training, including: at the multiple test frequency points, different configuration combinations of the system-level chip product board are applied to perform traversal training on the multi-channel DDR subsystem, the different configuration combinations mainly include controlling the signal drive strength, terminal resistance and level reference voltage at the chip end, and the signal drive strength, terminal resistance and level reference voltage at the memory end, etc. The traversal training is to perform training tests on all configuration combinations in turn through control software, retain the parameter combinations that pass the training according to the test results, obtain training results of different configuration combinations, and record the size of each training eye diagram.

[0093] According to some embodiments, according to the different configuration combinations, for each configuration combination, modify the relevant signal driving capability configuration and terminal resistance configuration of the SoC main chip end, the relevant signal driving capability configuration and terminal resistance configuration of the DDR SDRAM end, continue training, obtain training data of different configuration combinations, that is, the first configuration combination set corresponding to the multiple test frequency points, and record the size of each training eye diagram. Until all configuration combinations are traversed. At each test frequency point, perform traversal training on the DDR subsystem under each configuration combination, and use an oscilloscope to monitor the eye diagram on the DDR signal line to ensure signal integrity.

[0094] According to some embodiments, the method further comprises: analyzing the stress test result set to obtain an optimal configuration combination set for the DDR subsystem performance test.

[0095] According to some embodiments, the stress test result set is analyzed to obtain the optimal configuration combination set for the DDR subsystem performance test, including: analyzing the stress test result set to obtain the parameter combination set with the largest number of passed DDR subsystem tests as the optimal configuration combination set for the DDR subsystem performance test.

[0096] According to some embodiments, the stress test result set is analyzed to obtain the optimal configuration combination set for the DDR subsystem performance test, including: if there are configuration combinations with the same number of test passes, referring to the corresponding training eye diagram analysis in the test results, selecting the configuration parameter combination with the largest eye diagram as the final configuration parameter combination, to obtain the optimal configuration combination set for the DDR subsystem performance test.

[0097] According to some embodiments, the stress test result set is analyzed to obtain the configuration combination with the largest number of passes in the most DDR subsystem tests. If there are configuration combinations with the same number of passes, the configuration parameter combination with the largest eye diagram is selected as the final configuration parameter combination based on the recorded training eye diagram size. This configuration parameter combination is a general configuration that meets the requirements of most products. Similarly, for the test result data that passed the frequency reduction test, the configuration combination with the most passes in the frequency reduction test is obtained. Finally, a group of optimal configuration combinations at different frequencies is obtained.

[0098] According to some embodiments, a certain number of the system-level chip product boards are randomly selected, and the adjustable signal driving capabilities and terminal resistance configuration parameter ranges of the main chip end and the double data rate synchronous dynamic random access memory end of the system-level chip product board are determined to obtain different configuration combinations of the system-level chip product board.

[0099] According to some embodiments, a certain number of product boards are randomly selected as test samples to measure the signal driving capability of the SoC end, which includes parameters such as output voltage swing and drive current, and measure the signal driving capability of the DDR SDRAM end, including input impedance, receiving sensitivity, etc. The function of the terminal resistor is to reduce signal reflection and improve signal integrity. Generally, the terminal resistance value needs to match the characteristic impedance of the trace. A reasonable terminal resistance configuration range can also be determined based on the recommended values ​​of the SoC and DDR SDRAM. For example, if the recommended terminal resistance values ​​of the SoC and DDR SDRAM are 40Ω to 60Ω, different resistance values ​​can be set within this range for testing.

[0100] According to some embodiments, a series of different configuration combinations are generated by combining the above signal driving capability and the terminal resistance configuration parameter range. Each configuration combination represents a specific set of signal driving parameters and terminal resistance values. Afterwards, these configuration combinations are tested to evaluate the performance of the DDR subsystem.

[0101] According to some embodiments, the method also includes: classifying the Soc system product board according to the configuration combination set and the stress test result set, and the specific categories include: all DDRs meet the design target frequency, some DDRs need to run at a reduced frequency, some DDRs are faulty, and all DDRs are faulty.

[0102] According to some embodiments, the solution of the present invention can be applied to the design of test software for Soc system product boards. When the test software is running, the method described above is executed, so that the test software can achieve comprehensive, stable and multi-faceted testing of the DDR subsystem, and screen out the most efficient and reliable configuration combination corresponding to the DDR subsystem.

[0103] According to some embodiments, the solution of the present invention can not only select the optimal DDR configuration parameter combination, but also classify the product performance through multiple automated tests and test result analysis. Through comprehensive training, reading and writing, and actual stress testing, the test results are more comprehensive, complete, and reliable than the traditional technology of analyzing the training eye diagram.

[0104] According to some embodiments, the solution of the present invention traverses multiple groups of parameters of multiple board products for testing, and retains the trained parameters and corresponding eye diagrams as configurations for further stress testing, and provides a reference for subsequent test result analysis, so that the analysis of the test results is more comprehensive and accurate.

[0105] According to some embodiments, the present invention combines the bare metal test program with the test program in the operating system, the former removes invalid parameters, improves the test efficiency, makes the test more complete, and the results more reliable. By automatically reducing the frequency individually during the test process, the highest frequency that each DDR can run is found.

[0106] Figure 2 A block diagram of a computing device according to an example embodiment of the invention is shown.

[0107] like Figure 2 As shown, computing device 30 includes processor 12 and memory 14. Computing device 30 may also include bus 22, network interface 16, and I / O interface 18. Processor 12, memory 14, network interface 16, and I / O interface 18 may communicate with each other via bus 22.

[0108] The processor 12 may include one or more general-purpose CPUs (Central Processing Units, processors), microprocessors, or application-specific integrated circuits, etc., for executing relevant program instructions. According to some embodiments, the computing device 30 may also include a high-performance graphics card (GPU) 20 for accelerating the processor 12.

[0109] The memory 14 may include a machine system readable medium in the form of a volatile memory, such as a random access memory (RAM), a read-only memory (ROM) and / or a cache memory. The memory 14 is used to store one or more programs including instructions and data. The processor 12 can read the instructions stored in the memory 14 to execute the above-mentioned method according to the embodiment of the present invention.

[0110] The computing device 30 may also communicate with one or more networks via the network interface 16. The network interface 16 may be a wireless network interface.

[0111] The bus 22 may include an address bus, a data bus, a control bus, etc. The bus 22 provides a path for exchanging information between components.

[0112] It should be noted that, in the specific implementation process, the computing device 30 may also include other components necessary for normal operation. In addition, those skilled in the art may understand that the above device may only include components necessary for implementing the embodiments of this specification, and need not include all components shown in the figure.

[0113] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above method when executed by a processor. The computer-readable storage medium may include, but is not limited to, any type of disk, including a floppy disk, an optical disk, a DVD, a CD-ROM, a microdrive, and a magneto-optical disk, a ROM, a RAM, an EPROM, an EEPROM, a DRAM, a VRAM, a flash memory device, a magnetic card or an optical card, a nanosystem (including a molecular memory IC), a network storage device, a cloud storage device, or any type of medium or device suitable for storing instructions and / or data.

[0114] An embodiment of the present invention also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute part or all of the steps of any method recorded in the above method embodiments.

[0115] Those skilled in the art can clearly understand that the technical solution of the present invention can be implemented with the help of software and / or hardware. "Unit" and "module" in this specification refer to software and / or hardware that can independently complete or cooperate with other components to complete specific functions, where the hardware can be, for example, a field programmable gate array, an integrated circuit, etc.

[0116] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0117] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0118] In the several embodiments provided by the present invention, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0119] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0120] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0121] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the whole or part of the technical solution can be embodied in the form of a software product, which is stored in a memory and includes several instructions for a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the methods of various embodiments of the present invention.

[0122] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0123] The exemplary embodiments of the present invention are specifically shown and described above. It should be understood that the present invention is not limited to the detailed structures, configurations or implementations described herein; on the contrary, the present invention is intended to cover various modifications and equivalent configurations included in the spirit and scope of the appended clauses.

Claims

1. A method for testing a double data rate synchronous dynamic random access memory, characterized in that: The method is used for performance testing of a multi-channel double data rate synchronous dynamic random access memory subsystem in a system-on-chip product board, and the method comprises: Obtain multiple test frequency points set according to the design target frequency; At the plurality of test frequency points, different configuration combinations of the system-on-chip product board are applied to perform traversal training to obtain a first configuration combination set corresponding to the plurality of test frequency points; At the design target frequency point, the first configuration combination set is applied to configure the system-on-chip product board, and a stress read-write test is performed based on a central processing unit bare metal program to obtain a second configuration combination set; At the design target frequency point, applying the second configuration combination set to configure the system-on-chip product board, performing a stress test based on an operating system stress test program, obtaining a stress test result set and locating a double data rate synchronous dynamic random access memory subsystem that failed the stress test; A frequency reduction stress test is performed on the DDR SDRAM subsystem that fails the stress test until a frequency point at which the DDR SDRAM subsystem can pass the stress test and a corresponding third configuration combination set are found.

2. The method according to claim 1, characterized in that Also includes: At other frequency points except the design target frequency point, the first configuration combination set is applied to configure the system-on-chip product board, and a stress read-write test is performed through a central processing unit bare metal program to obtain a fourth configuration combination set.

3. The method according to claim 1, characterized in that Also includes: Different configuration combinations of the system-on-chip product board are applied for traversal training, including: At the multiple test frequency points, different configuration combinations of the system-on-chip product board are applied to perform traversal training on the multi-channel double data rate synchronous dynamic random access memory subsystem to obtain training results of different configuration combinations, and record the size of each training eye diagram.

4. The method according to claim 2, characterized in that: Also includes: The stress test result set is analyzed to obtain an optimal configuration combination set for the double data rate synchronous dynamic random access memory subsystem performance test.

5. The method according to claim 4, characterized in that Analyzing the stress test result set to obtain an optimal configuration combination set for the double data rate synchronous dynamic random access memory subsystem performance test, including: The stress test result set is analyzed to obtain a parameter combination set with the largest number of passed DDR SDRAM subsystem tests, which is used as the DDR SDRAM case number: The optimal configuration combination set for storage subsystem performance testing.

6. The method according to claim 4, characterized in that Analyzing the stress test result set to obtain an optimal configuration combination set for the double data rate synchronous dynamic random access memory subsystem performance test, including: If there are configuration combinations with the same number of test passes, refer to the corresponding training eye diagram analysis in the test results and select the configuration parameter combination with the largest eye diagram as the final configuration parameter combination to obtain the optimal configuration combination set for the double data rate synchronous dynamic random access memory subsystem performance test.

7. The method according to claim 1, characterized in that Before applying different configuration combinations of the system-level chip product board to perform traversal training, it also includes: A certain number of the system-on-chip product boards are randomly selected, and adjustable signal driving capabilities and terminal resistance configuration parameter ranges of the main chip end and the double data rate synchronous dynamic random access memory end of the system-on-chip product board are determined to obtain different configuration combinations of the system-on-chip product board.

8. The method according to claim 2, characterized in that: Also includes: The system-on-chip product board is classified according to the configuration combination set and the stress test result set, and the categories include: all double data rate synchronous dynamic random access memories meet the design target frequency, some double data rate synchronous dynamic random access memories need to be operated at a reduced frequency, some double data rate synchronous dynamic random access memories are faulty, and all double data rate synchronous dynamic random access memories are faulty.

9. A computer program product, characterized in that include: A computer program, wherein when the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

10. A computing device, characterized in that: include: processor; as well as A memory storing a computer program, which, when executed by the processor, enables the processor to perform the method according to any one of claims 1 to 8.

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