Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof.The method includes the steps that a photoresist layer is exposed and developed based on a halftone mask plate so that the photoresist layer can be patterned, then a semiconductor layer is etched based on the patterned photoresist layer, the halftone mask plate comprises a shading area, a semi-light-transmitting area and a light-transmitting area which are divided according to preset rules, and the semi-light-transmitting area and the light-transmitting area are divided according to the preset rules; the patterned photoresist layer comprises a first photoresist part which covers the capacitor region and has a first thickness, a second photoresist part which covers the conductive region and has a second thickness, and a photoresist layer opening which exposes the conductive region, the first thickness is greater than the second thickness, and in the etching process, the patterning of the lower electrode plate metal layer and the formation of the MIM capacitor are completed at the same time, so that the etching efficiency is improved. Meanwhile, the upper pole plate metal layer of the capacitor area is still covered with the first light resistance part, so that patterns are etched on the MIM capacitor and the lower pole plate metal layer at the same time through one-step photoetching and one-time etching, the productivity can be saved, defects and overlay alignment abnormity in a long manufacturing process are avoided, and meanwhile, the yield is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] The BCD process simultaneously manufactures bipolar devices, CMOS devices, and DMOS power devices on the same chip, integrating the high transconductance and strong load driving capability of bipolar devices with the high integration and low power consumption of CMOS, allowing them to complement each other and give full play to their respective advantages. At the same time, DMOS can work in switching mode with extremely low power consumption.

[0003] Typical devices of BCD process include low-voltage CMOS, high-voltage MOS tubes, LDMOS with various breakdown voltages, vertical NPN / PNP and Schottky diodes, etc. Some processes also integrate devices such as JFET and EEPROM.

[0004] BCD technology is widely used in power management (power and battery control), display drive, automotive electronics, industrial control, etc. Among them, power management chip (PMIC) is one of the important types of analog chips. The combination of BCD technology and SOI technology is also a major feature of the development of BCD technology.

[0005] MIM capacitors are needed in some BCD semiconductor devices. MIM (metal-insulator-metal) capacitors are short for metal-insulator-metal capacitors. Their structure includes two metal electrodes and an insulating layer between the metal electrodes. They have the advantages of high Q value, small loss, high withstand voltage and low ESR, which can improve the efficiency of the system.

[0006] In the current manufacturing process of semiconductor devices including MIM capacitors, the formation of the MIM capacitor and the patterning of the bottom plate metal layer are performed separately by photolithography, resulting in a long process loop and a waste of production capacity.

[0007] Therefore, how to improve the manufacturing process of semiconductor devices including MIM capacitors to save production capacity and improve yield has become an important technical problem that needs to be solved urgently by those skilled in the art.

[0008] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0009] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor device and a manufacturing method thereof, so as to solve the problem of low production capacity of the manufacturing process of the existing semiconductor device including MIM capacitors.

[0010] To achieve the above object and other related objects, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0011] Forming a photoresist layer on a semiconductor layer, wherein the semiconductor layer includes a lower plate metal layer, an insulating layer and an upper plate metal layer arranged in sequence from bottom to top, and the semiconductor layer is divided into a capacitor region, an isolation region and a conductive region outside the capacitor region and defined by the isolation region according to a preset rule;

[0012] Exposing and developing the photoresist layer based on a half-tone mask to pattern the photoresist layer, the half-tone mask comprising a light-shielding area, a semi-transparent area and a light-transparent area divided according to a preset rule, the patterned photoresist layer comprising a first photoresist portion covering the capacitor area and having a first thickness, a second photoresist portion covering the conductive area and having a second thickness, and a photoresist layer opening exposing the conductive area, wherein the first thickness is greater than the second thickness;

[0013] The semiconductor layer is etched based on the patterned photoresist layer until the lower electrode metal layer in the isolation area is etched through, and at the same time the insulating layer in the conductive area is etched through to expose the upper surface of the lower electrode metal layer, and the upper electrode metal layer in the capacitor area is still covered with the first photoresist portion.

[0014] Optionally, the method for forming the halftone mask comprises the following steps:

[0015] Providing a light-transmitting substrate, and forming a light-impermeable layer on the light-transmitting substrate;

[0016] Patterning the opaque layer to obtain a light-shielding pattern layer;

[0017] forming a semi-transparent layer covering the light-shielding pattern layer on the light-transparent substrate;

[0018] Patterning the semi-transparent layer to obtain a semi-transparent layer opening, wherein the bottom of the semi-transparent layer opening exposes the transparent substrate;

[0019] The area where the shading pattern layer is located corresponds to the shading area, the area where the semi-transparent layer opening is located corresponds to the transparent area, and the area of ​​the semi-transparent layer other than the shading pattern layer and the semi-transparent layer opening corresponds to the semi-transparent area.

[0020] Optionally, the opaque layer includes a Cr layer, and the semi-transmissive layer includes a Ni layer.

[0021] Optionally, the transmittance of the semi-transparent area ranges from 40% to 70%.

[0022] Optionally, the photoresist layer adopts positive photoresist, the light-shielding area corresponds to the capacitor area, the light-transmitting area corresponds to the isolation area, and the semi-light-transmitting area corresponds to the conductive area.

[0023] Optionally, the photoresist layer adopts negative photoresist, the light-transmitting area corresponds to the capacitor area, the light-shielding area corresponds to the isolation area, and the semi-light-transmitting area corresponds to the conductive area.

[0024] Optionally, the lower plate metal layer includes one or more of an AlCu alloy layer, a TiN layer, a Ti layer and an Au layer, the insulating layer includes a silicon nitride layer, and the upper plate metal layer includes one or more of an AlCu alloy layer, a TiN layer, a Ti layer and an Au layer.

[0025] Optionally, the semiconductor layer further includes an anti-reflection layer located on the upper electrode metal layer, and the photoresist layer is formed on the surface of the anti-reflection layer.

[0026] Optionally, the semiconductor layer also includes a through-hole layer located below the lower electrode metal layer and a metal interconnection layer located below the through-hole layer, the through-hole layer includes a dielectric layer and a plurality of conductive through-holes distributed in the dielectric layer, and the lower electrode metal layer and the metal interconnection layer are electrically connected through the conductive through-holes.

[0027] The present invention further provides a semiconductor device, including a MIM capacitor, wherein the semiconductor device is manufactured using any of the semiconductor device manufacturing methods described above.

[0028] As described above, the method for manufacturing a semiconductor device of the present invention first exposes and develops the photoresist layer based on a half-tone mask to pattern the photoresist layer, and then etches the semiconductor layer based on the patterned photoresist layer, wherein the half-tone mask includes a light-shielding area, a semi-transparent area, and a light-transparent area divided according to a preset rule, and the patterned photoresist layer includes a first photoresist portion covering the capacitor area and having a first thickness, a second photoresist portion covering the conductive area and having a second thickness, and a photoresist layer opening exposing the conductive area, the first thickness is greater than the second thickness, and during the etching process, the pattern of the lower plate metal layer The formation of the MIM capacitor is completed at the same time, that is, when the lower plate metal layer of the isolation area is etched through, the insulating layer of the conductive area (the area around the capacitor area except the isolation area) is also etched through to expose the upper surface of the lower plate metal layer, and at this time, the upper plate metal layer of the capacitor area is still covered with the first photoresist portion, so that the MIM capacitor and the lower plate metal layer are etched out of the pattern at the same time through one-step photolithography and one-time etching, which can save process steps, save production capacity, avoid introducing defects and overlay alignment (OVL) abnormalities in a long process, and reduce steps to improve the yield to a certain extent. The semiconductor device with MIM capacitor manufactured by the method of the present invention has better quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 The schematic diagram shows a method for manufacturing a semiconductor device including a MIM capacitor, in which a first patterned photoresist layer is formed on a semiconductor layer through a first photolithography process to cover the MIM capacitor region.

[0030] Figure 2 The schematic diagram shows a structure obtained after a first anti-reflection layer is formed in a method for manufacturing a semiconductor device including a MIM capacitor, in which a semiconductor layer is etched using a first patterned photoresist layer as a mask until an insulating layer is etched through.

[0031] Figure 3 The schematic diagram shows a structure obtained after a second patterned photoresist layer is formed on a semiconductor layer through a second photolithography process in a method for manufacturing a semiconductor device including a MIM capacitor.

[0032] Figure 4 It is a schematic diagram showing a structure obtained after the bottom plate metal layer 102 is patterned by etching the semiconductor layer using the second patterned photoresist layer as a mask in a method for manufacturing a semiconductor device including a MIM capacitor.

[0033] Figure 5 The process flow chart of the method for manufacturing a semiconductor device of the present invention is shown.

[0034] Figure 6 It is a schematic diagram showing the structure obtained after a photoresist layer is formed on a semiconductor layer according to the method for manufacturing a semiconductor device of the present invention.

[0035] Figure 7 It is a schematic structural diagram showing the method for manufacturing a semiconductor device of the present invention when exposing a photoresist layer based on a half-tone mask.

[0036] Figure 8 It is a schematic diagram showing the structure obtained after the photoresist layer is patterned by development in the method for manufacturing a semiconductor device of the present invention.

[0037] Fig. 9 Shown is a schematic structural diagram of a light-transmitting substrate provided in a manufacturing process of a half-tone mask.

[0038] Fig.10 The diagram shows a structure obtained after forming an opaque layer on a transparent substrate during a manufacturing process of a half-tone mask.

[0039] Fig.11 Shown is a schematic diagram of the structure obtained after patterning an opaque layer to obtain a light-shielding pattern layer during a manufacturing process of a half-tone mask.

[0040] Fig.12 The diagram shows a structure obtained after a semi-transparent layer covering a light-shielding pattern layer is formed on a transparent substrate during a manufacturing process of a half-tone mask.

[0041] Fig.13 Shown is a schematic diagram of a structure obtained after patterning a semi-transparent layer to obtain openings in the semi-transparent layer during a manufacturing process of a half-tone mask.

[0042] Fig.14 It is a schematic structural diagram of an intermediate process of etching a semiconductor layer based on a patterned photoresist layer in the method for manufacturing a semiconductor device of the present invention.

[0043] Fig.15 It is a schematic diagram showing a structure obtained after the lower plate metal layer of the isolation area and the insulating layer of the conductive area are simultaneously etched through in the method for manufacturing a semiconductor device of the present invention.

[0044] Description of Reference Numerals

[0045] 101 Via Layer

[0046] 102 Lower plate metal layer

[0047] 103 Insulation layer

[0048] 104 upper plate metal layer

[0049] 105 first anti-reflection layer

[0050] 106 first patterned photoresist layer

[0051] 107 Second anti-reflection layer

[0052] 108 second patterned photoresist layer

[0053] Steps S1 to S3

[0054] 201 Photoresist layer

[0055] 201a First photoresist portion

[0056] 201b Second photoresist portion

[0057] 201c Photoresist layer opening

[0058] 202 Lower plate metal layer

[0059] 203 Insulation layer

[0060] 204 upper plate metal layer

[0061] 205 Anti-reflective layer

[0062] 206 dielectric layer

[0063] 207 Conductive vias

[0064] 3 Halftone Mask

[0065] 301 Transparent substrate

[0066] 302 opaque layer

[0067] 303 Shading Graphic Layer

[0068] 304 Semi-translucent layer

[0069] 305 Semi-translucent layer opening

[0070] A Capacitor area

[0071] B. Isolation Area

[0072] C Conductive area DETAILED DESCRIPTION

[0073] See also Figures 1 to 4 , which is a structural schematic diagram showing the various steps of a method for manufacturing a semiconductor device including a MIM capacitor, wherein two photolithography steps and two etching steps are used to obtain a MIM capacitor and a patterned lower plate metal layer.

[0074] Specifically, Figure 1As shown, a semiconductor layer is provided, which includes a through-hole layer 101, a lower plate metal layer 102, an insulating layer 103, an upper plate metal layer 104 and a first anti-reflection layer 105 arranged in sequence from bottom to top, and then a first patterned photoresist layer 106 is formed on the semiconductor layer through a first photolithography process to cover the MIM capacitor area.

[0075] like Figure 2 As shown, the semiconductor layer is etched using the first patterned photoresist layer 106 as a mask until the insulating layer 103 is etched through to expose the upper electrode metal layer 104, and then a second anti-reflection layer 107 is formed.

[0076] like Figure 3 As shown, a second patterned photoresist layer 108 is formed on the semiconductor layer through a second photolithography process.

[0077] like Figure 4 As shown, the semiconductor layer is etched using the second patterned photoresist layer 108 as a mask until the lower electrode metal layer 102 is etched through, so that the lower electrode metal layer 102 is patterned to obtain a metal connection.

[0078] In the above method, the formation of the MIM capacitor and the patterning of the lower plate metal layer are photolithographically processed separately, which results in a relatively long manufacturing process and wastes production capacity.

[0079] The inventors of this application have improved the method for manufacturing semiconductor devices of MIM capacitors through extensive research and experiments. It is possible to simultaneously etch the patterns of the MIM capacitor and the lower plate metal layer through one-step photolithography and one-time etching, which can save process steps, save production capacity, avoid the introduction of defects and overlay alignment (OVL) anomalies in a long process, and reducing the steps can improve the yield to a certain extent.

[0080] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0081] See also Figures 1 to 15 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0082] The present invention provides a method for manufacturing a semiconductor device. Figure 5 , shown as a process flow chart of the method, comprising the following steps:

[0083] S1: forming a photoresist layer on a semiconductor layer, wherein the semiconductor layer comprises a lower plate metal layer, an insulating layer and an upper plate metal layer arranged in sequence from bottom to top, and the semiconductor layer is divided into a capacitor region, an isolation region and a conductive region outside the capacitor region and defined by the isolation region according to a preset rule;

[0084] S2: exposing and developing the photoresist layer based on a half-tone mask to pattern the photoresist layer, wherein the half-tone mask includes a light-shielding area, a semi-transparent area, and a light-transparent area divided according to a preset rule, and the patterned photoresist layer includes a first photoresist portion covering the capacitor area and having a first thickness, a second photoresist portion covering the conductive area and having a second thickness, and a photoresist layer opening exposing the conductive area, wherein the first thickness is greater than the second thickness;

[0085] S3: etching the semiconductor layer based on the patterned photoresist layer until the lower electrode metal layer of the isolation area is etched through, and at the same time the insulating layer of the conductive area is etched through to expose the upper surface of the lower electrode metal layer, and the upper electrode metal layer of the capacitor area is still covered with the first photoresist portion.

[0086] The above steps are described in detail below with reference to the structure diagram.

[0087] First see Figure 6 , perform the step S1: form a photoresist layer 201 on the semiconductor layer, the semiconductor layer includes a lower plate metal layer 202, an insulating layer 203 and an upper plate metal layer 204 arranged in sequence from bottom to top, and the semiconductor layer is divided into a capacitor area A, an isolation area B and a conductive area C outside the capacitor area A and limited by the isolation area B according to a preset rule.

[0088] As an example, an anti-reflection layer 205 is pre-formed on the semiconductor layer to reduce the reflection of light on the interface. The anti-reflection layer 205 covers the upper plate metal layer 204 , and the photoresist layer 201 is formed on the surface of the anti-reflection layer 205 .

[0089] In some embodiments, the anti-reflection layer 205 may be a SiON layer.

[0090] As an example, according to the required MIM capacitor performance, the lower plate metal layer 202 can be selected to include one or more of an AlCu alloy layer, a TiN layer, a Ti layer and an Au layer, and / or other suitable metal layers, the insulating layer 203 can be selected to include a silicon nitride layer, and / or other suitable insulating materials, and the upper plate metal layer 204 can be selected to include one or more of an AlCu alloy layer, a TiN layer, a Ti layer and an Au layer, and / or other suitable metal layers.

[0091] In some embodiments, for example Figure 6 As shown in the figure, the lower plate metal layer 202 includes a Ti layer, a TiN layer, an AlCu alloy layer, a Ti layer and a TiN layer stacked in sequence from bottom to top, the insulating layer 203 includes a silicon nitride layer, and the upper plate metal layer 204 includes an AlCu alloy layer and a TiN layer stacked in sequence from bottom to top, and the thickness of each layer can be set according to actual needs.

[0092] In some embodiments, the semiconductor layer also includes a through-hole layer located below the lower electrode metal layer 202 and a metal interconnection layer (not shown) located below the through-hole layer, the through-hole layer includes a dielectric layer 206 and a plurality of conductive vias 207 distributed in the dielectric layer, and the lower electrode metal layer 202 and the metal interconnection layer are electrically connected through the conductive vias 207.

[0093] Please see again Figure 7 and Figure 8 , execute the step S2: expose the photoresist layer 201 based on the half-tone mask 3 (such as Figure 7 As shown), developing to pattern the photoresist layer 201 (as shown in 8), wherein the halftone mask 3 includes a shading area, a semi-transparent area and a transparent area divided according to a preset rule, and the patterned photoresist layer 201 includes a first photoresist portion 201a covering the capacitor area and having a first thickness, a second photoresist portion 201b covering the conductive area and having a second thickness, and a photoresist layer opening 201c exposing the conductive area, and the first thickness is greater than the second thickness.

[0094] Specifically, a half-tone mask (HT mask for short) is a semi-transparent light-shielding film attached to a photomask so that the propagation speed of light is reduced when passing through a substance, and the phase changes accordingly, thereby partially changing the phase of the pattern part, and the interference phenomenon between the light whose phase changes through the semi-transparent light-shielding film and the light whose phase does not change without passing through the semi-transparent light-shielding film improves the resolution. In the present invention, the half-tone mask 3 with different transmittances in different regions is used to make the exposure light intensity of different regions different, and the exposure degree of the photoresist is different when the light intensity is different under the exposure action. After development, the residual thickness of the photoresist layer 201 in different regions is different, so that the MIM capacitor and the lower plate metal layer pattern are superimposed on the photoresist layer 201, that is, after development, the MIM capacitor pattern and the lower plate metal layer pattern can be obtained at the same time, and the patterned photoresist layer 201 is used as an etching barrier layer, and the MIM capacitor and the lower plate metal layer can be etched out of the pattern at the same time through one etching.

[0095] As an example, post-baking may be performed after development, which can better complete the curing of the photoresist layer after development and increase the etching blocking ability of the photoresist layer.

[0096] Specifically, in the photoresist layer 201, the MIM capacitor pattern is the thickest (the first photoresist portion 201a having the first thickness), the thickness of the lower electrode metal layer pattern is zero (the photoresist layer opening 201c that exposes the conductive area), and the thickness of the middle area (the second photoresist portion 201b having the second thickness) is adjusted according to the etching rate to ensure that after the MIM capacitor is etched, the lower electrode metal layer is also etched.

[0097] In the present invention, the photoresist layer 201 can be made of positive photoresist or negative photoresist as required, and only needs to use the opposite half-tone mask pattern.

[0098] Specifically, the photolithography process includes two basic processes: negative photolithography and positive photolithography. Positive photolithography is to replicate the same pattern as the pattern on the mask onto the surface of the semiconductor layer, wherein the area exposed to ultraviolet light undergoes a chemical reaction, softens in the developer and can be dissolved in the developer, and the exposed positive photoresist area can be removed by development, while the unexposed photoresist under the opaque mask remains on the surface of the semiconductor layer. Negative photolithography is to replicate the opposite pattern to the pattern on the mask onto the surface of the semiconductor layer, wherein the area exposed to ultraviolet light becomes insoluble and hardens due to cross-linking. Once hardened, the cross-linked photoresist cannot be washed off in the solvent, while the photoresist under the opaque mask is not exposed and therefore does not change, and the photoresist remains soft, and the unexposed negative photoresist area can be removed by development, while the exposed negative photoresist will not dissolve in the developer and remains on the semiconductor surface.

[0099] Specifically, in Figure 7 and Figure 8 In the presented embodiment, the photoresist layer 201 adopts positive photoresist, the light-shielding area corresponds to the capacitor area A, the light-transmitting area corresponds to the isolation area B, and the semi-light-transmitting area corresponds to the conductive area C.

[0100] In other embodiments, when the photoresist layer 201 is made of negative photoresist, the light-transmitting area corresponds to the capacitor area A, the light-shielding area corresponds to the isolation area B, and the semi-light-transmitting area corresponds to the conductive area C.

[0101] The following is an example of a half-tone mask corresponding to a positive photoresist to illustrate a manufacturing process of the half-tone mask 3. Figures 9 to 13 The formation of the half-tone mask 3 includes the following steps:

[0102] (1) Fig. 9 As shown, a light-transmitting substrate 301 is provided;

[0103] (2) Fig.10 As shown, a light-impermeable layer 302 is formed on the light-transmitting substrate 301 by deposition, and the light-impermeable layer 302 may be, for example, a chromium (Cr) layer;

[0104] (3) Fig.11 As shown, the opaque layer 302 is patterned to obtain a light-shielding pattern layer 303, and the area where the light-shielding pattern layer 303 is located is the light-shielding area, which corresponds to the capacitor area A and is used to ensure the MIM pattern;

[0105] (4) Fig.12 As shown, a semi-transparent layer 304 covering the shading graphic layer 303 is formed on the translucent substrate 301. The semi-translucent layer 304 can be, for example, a nickel (Ni) layer or other suitable material layer. The specific selection of the translucent material can be adjusted according to the thickness of the MIM capacitor and the lower electrode metal layer to ensure that the etching of the lower electrode metal layer and the etching of the insulating layer of the MIM capacitor are completed at the same time.

[0106] (5) Fig.13 As shown, the semi-transparent layer 304 is patterned to obtain a semi-transparent layer opening 305, the bottom of the semi-transparent layer opening 305 reveals the transparent substrate 301, the area where the semi-transparent layer opening 305 is located, namely the transparent area, corresponds to the isolation area B, and the area of ​​the semi-transparent layer 304 other than the shading graphic layer 303 and the semi-transparent layer opening 305, namely the semi-transparent area, corresponds to the conductive area C.

[0107] As an example, the light-shielding area can be considered to be 100% opaque, the light-transmitting area can be considered to be 100% transparent, and the light transmittance range of the semi-transmitting area can be, for example, 40% to 70%.

[0108] Please see again Fig.14 and Fig.15 , execute the step S3: based on the patterned photoresist layer 201, the semiconductor layer is etched until the lower electrode metal layer 202 of the isolation area B is etched through, and at the same time, the insulating layer 203 of the conductive area C is etched through to expose the upper surface of the lower electrode metal layer 202, and the upper electrode metal layer 204 of the capacitor area A is still covered with the first photoresist portion 201a.

[0109] As an example, the etching may be dry etching or other suitable etching methods.

[0110] Specifically, etching is mainly divided into two stages:

[0111] ① The second photoresist portion 201b with a relatively thin thickness in the conductive region C is completely etched, revealing the upper surface of the upper plate metal layer 204, while the first photoresist portion 201a located on the upper surface of the upper plate metal layer 204 in the capacitor region A still has a certain thickness due to its relatively thick thickness. That is, at this time, only the MIM capacitor pattern remains in the photoresist layer, and at the same time, the semiconductor layer in the isolation region B is etched to a certain depth because there is no photoresist layer to block it.

[0112] ② The semiconductor layers of the conductive region C and the isolation region B are etched simultaneously, and the remaining etching time is the same, so the etching can be completed simultaneously.

[0113] Specifically, Fig.14 What is presented is a structural schematic diagram of an intermediate process in which the semiconductor layers of the conductive area C and the isolation area B are simultaneously etched. At this time, the semiconductor layer of the capacitor area A is not etched because it is blocked by the remaining first photoresistance portion 201a, and the semiconductor layer of the conductive area C is etched to a certain depth because the second photoresistance portion 201b is consumed, so that a portion of the upper electrode metal layer 204 of the conductive area C is etched away, and the semiconductor layer of the isolation area B is further etched on the basis of having been etched to a certain depth before, and the etched depth is greater than the etched depth of the semiconductor layer of the conductive area C, reaching the lower electrode metal layer 202.

[0114] Specifically, Fig.15What is presented is a schematic diagram of the structure when etching is completed. At this time, a certain thickness of photoresist layer still remains on the semiconductor layer of the capacitor area A to protect the upper electrode metal layer 204 from being etched. The semiconductor layer of the conductive area C is etched to expose the upper surface of the lower electrode metal layer 202, and the semiconductor layer of the isolation area B is etched to the bottom surface of the lower electrode metal layer 202.

[0115] It should be pointed out that in actual implementation, the graphic morphology of the photoresist layer after development can be inferred based on the MIM capacitor of the actual device and the thickness of the lower plate metal layer, and then the light-transmitting material for preparing the HTmask can be selected based on the desired graphic morphology of the photoresist layer after development. In addition, during the etching process, the etching signals of the insulating layer (such as the silicon nitride layer) of the MIM capacitor and the lower plate metal layer can be used to adjust the light transmittance of different areas.

[0116] At this point, the MIM capacitor and the lower plate metal layer are simultaneously etched into patterns through one-step photolithography and one-time etching, which can save process steps, save production capacity, avoid introducing defects and overlay alignment (OVL) anomalies in the long process, and reduce the number of steps to improve the yield to a certain extent.

[0117] The present invention also provides a semiconductor device, including a MIM capacitor, wherein the semiconductor device is manufactured using the semiconductor device manufacturing method as described above, and has better quality. The semiconductor device may be, for example, a BCD semiconductor device or other types of devices.

[0118] In summary, the method for manufacturing a semiconductor device of the present invention first exposes and develops a photoresist layer based on a half-tone mask to pattern the photoresist layer, and then etches a semiconductor layer based on the patterned photoresist layer, wherein the half-tone mask includes a light-shielding area, a semi-transparent area, and a light-transparent area divided according to a preset rule, and the patterned photoresist layer includes a first photoresist portion covering the capacitor area and having a first thickness, a second photoresist portion covering the conductive area and having a second thickness, and a photoresist layer opening exposing the conductive area, the first thickness is greater than the second thickness, and during the etching process, the pattern of the lower plate metal layer is The formation of the MIM capacitor is completed at the same time, that is, when the lower plate metal layer of the isolation area is etched through, the insulating layer of the conductive area (the area around the capacitor area except the isolation area) is also etched through to expose the upper surface of the lower plate metal layer, and at this time, the upper plate metal layer of the capacitor area is still covered with the first photoresist portion, so that the MIM capacitor and the lower plate metal layer are etched out of the pattern at the same time through one-step photolithography and one-time etching, which can save process steps, save production capacity, avoid introducing defects and overlay alignment (OVL) abnormalities in a long process, and reduce steps to improve the yield to a certain extent. The semiconductor device with MIM capacitor manufactured by the method of the present invention has better quality. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0119] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: Forming a photoresist layer on a semiconductor layer, wherein the semiconductor layer includes a lower plate metal layer, an insulating layer and an upper plate metal layer arranged in sequence from bottom to top, and the semiconductor layer is divided into a capacitor region, an isolation region and a conductive region outside the capacitor region and defined by the isolation region according to a preset rule; Exposing and developing the photoresist layer based on a half-tone mask to pattern the photoresist layer, the half-tone mask comprising a light-shielding area, a semi-transparent area and a light-transparent area divided according to a preset rule, the patterned photoresist layer comprising a first photoresist portion covering the capacitor area and having a first thickness, a second photoresist portion covering the conductive area and having a second thickness, and a photoresist layer opening exposing the conductive area, wherein the first thickness is greater than the second thickness; The semiconductor layer is etched based on the patterned photoresist layer until the lower electrode metal layer in the isolation area is etched through, and at the same time the insulating layer in the conductive area is etched through to expose the upper surface of the lower electrode metal layer, and the upper electrode metal layer in the capacitor area is still covered with the first photoresist portion.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The method for forming the halftone mask comprises the following steps: Providing a light-transmitting substrate, and forming a light-impermeable layer on the light-transmitting substrate; Patterning the opaque layer to obtain a light-shielding pattern layer; forming a semi-transparent layer covering the light-shielding pattern layer on the light-transparent substrate; Patterning the semi-transparent layer to obtain a semi-transparent layer opening, wherein the bottom of the semi-transparent layer opening exposes the transparent substrate; The area where the shading pattern layer is located corresponds to the shading area, the area where the semi-transparent layer opening is located corresponds to the transparent area, and the area of ​​the semi-transparent layer other than the shading pattern layer and the semi-transparent layer opening corresponds to the semi-transparent area.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The light-impermeable layer includes a Cr layer, and the semi-light-transmitting layer includes a Ni layer.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The light transmittance of the semi-transparent area ranges from 40% to 70%.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The photoresist layer adopts positive photoresist, the light-shielding area corresponds to the capacitor area, the light-transmitting area corresponds to the isolation area, and the semi-light-transmitting area corresponds to the conductive area.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The photoresist layer adopts negative photoresist, the light-transmitting area corresponds to the capacitor area, the light-shielding area corresponds to the isolation area, and the semi-light-transmitting area corresponds to the conductive area.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The lower plate metal layer includes one or more of an AlCu alloy layer, a TiN layer, a Ti layer and an Au layer, the insulating layer includes a silicon nitride layer, and the upper plate metal layer includes one or more of an AlCu alloy layer, a TiN layer, a Ti layer and an Au layer.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The semiconductor layer further includes an anti-reflection layer located on the upper electrode metal layer, and the photoresist layer is formed on the surface of the anti-reflection layer.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: The semiconductor layer also includes a through-hole layer located below the lower electrode metal layer and a metal interconnection layer below the through-hole layer. The through-hole layer includes a dielectric layer and a plurality of conductive through-holes distributed in the dielectric layer. The lower electrode metal layer and the metal interconnection layer below the through-hole layer are electrically connected through the conductive through-holes.

10. A semiconductor device comprising a MIM capacitor, characterized in that: The semiconductor device is manufactured by using the method for manufacturing a semiconductor device as described in any one of claims 1-9.

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