Semiconductor structure and manufacturing method thereof
By forming through holes and through holes in the semiconductor structure, the interconnection structures are in an air state, which solves the problem in the existing technology that the k value of the dielectric layer in the interconnection structure and the RC delay of the integrated circuit cannot be further reduced, and achieves a better High signal transmission speed and integration.
Patent Information
- Application Number
- CN202411435816.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-14
- Publication Date
- 2025-01-24
AI Technical Summary
The prior art cannot further reduce the k value of the dielectric layer in the interconnect structure and the RC delay of the integrated circuit, and it is difficult to reduce the metal line width.
By forming multiple interconnect structures at intervals in the semiconductor structure, and forming through-holes and through-holes between adjacent interconnect structures, the interconnect structures are left in an air state, thereby reducing capacitance and resistance-capacitance delay.
Effectively reduce the capacitance and RC delay of the interconnected structure, improve the signal transmission speed, achieve higher line width ratio and integration, and reduce string disturbances, and improve the anti -interference capacity of the circuit.
Smart Images
Figure CN119361537A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art
[0002] In recent years, the RC (resistance-capacitance) delay of copper interconnects has become one of the important components of the RC delay of the entire integrated circuit chip. Entering the technology generation below 28nm, the industry needs to consider using ULK (UltraLow-k) media with a dielectric constant of 2.0-2.2.
[0003] With the development of integrated circuit technology and the reduction of key dimensions, people have been committed to exploring and further optimizing the reduction of RC delay of integrated circuits, preventing mutual interference between circuits of each layer, and improving the stability and operating frequency of chips in recent years. At present, the industry generally uses lower dielectric constant (Low-k) media to reduce the RC delay of copper interconnects. This is because porous low-k materials can achieve a dielectric constant of about 2.5 (the dielectric constant of air is 1, so porous materials can obtain a very low k value), which can effectively reduce the RC delay of integrated circuits. However, the ultra-low dielectric constant media of the prior art have reduced the k value to around 2.0, which still cannot meet the technical requirements for further reduction of metal line width. Therefore, how to use air with a dielectric constant of 1 to reduce the dielectric constant of the interconnect medium is particularly important.
[0004] In view of this, there is an urgent need for a method for manufacturing a semiconductor structure that can effectively reduce the k value of a dielectric layer in an interconnect structure and the RC delay of an integrated circuit and further reduce the metal line width. Summary of the invention
[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a semiconductor structure and a manufacturing method thereof, which are used to solve the problem that the prior art cannot further reduce the k value of the dielectric layer in the interconnect structure and the RC delay of the integrated circuit, and further reduce the metal line width.
[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a semiconductor structure, comprising the following steps:
[0007] A substrate is provided, and a stacked structure is formed on the substrate, wherein the stacked structure includes a first barrier layer, a first dielectric layer, a second barrier layer, and a third barrier layer stacked in sequence, and a plurality of interconnect structures arranged at intervals are formed in the stacked structure, wherein the interconnect structures penetrate the stacked structure and are electrically connected to the semiconductor device in the substrate;
[0008] A through hole is formed in the third barrier layer between two adjacent interconnect structures, wherein the second barrier layer is exposed at the bottom of the through hole and the inner wall of the through hole is spaced a preset distance from the interconnect structure;
[0009] forming a sacrificial layer filling the through hole and a fourth barrier layer covering the sacrificial layer, the third barrier layer, and the upper surface of the interconnect structure, and forming a through hole in the fourth barrier layer with the bottom exposing the sacrificial layer;
[0010] The sacrificial layer in the through hole is removed based on the through hole, and a second dielectric layer is formed on the upper surface of the fourth barrier layer to block the through hole opening.
[0011] Optionally, the method for forming the first barrier layer comprises chemical vapor deposition; the method for forming the first dielectric layer comprises chemical vapor deposition; the method for forming the second barrier layer comprises chemical vapor deposition; and the method for forming the third barrier layer comprises chemical vapor deposition.
[0012] Optionally, forming the interconnection structure includes the following steps: forming a first connection hole passing through the stacked structure and a second connection hole passing through the third barrier layer, and the top of the first connection hole is connected to the bottom of the second connection hole; and sequentially forming an isolation layer and a conductive layer filling the first connection hole and the second connection hole to obtain the interconnection structure.
[0013] Optionally, the material of the isolation layer includes at least one of tantalum and tantalum nitride; and the material of the conductive layer includes copper.
[0014] Optionally, a diameter of the first connection hole is smaller than a diameter of the second connection hole.
[0015] Optionally, the method of forming the first connection hole includes dry etching; the method of forming the second connection hole includes dry etching.
[0016] Optionally, after the through hole is formed, the distance between the side wall of the through hole and the side wall of the interconnection structure is in the range of
[0017] Optionally, the method of forming the through hole includes dry etching; and the method of removing the sacrificial layer in the through hole includes wet etching.
[0018] Optionally, the material of the first dielectric layer includes a low dielectric constant material; and the material of the second dielectric layer includes a low dielectric constant material.
[0019] The present invention further provides a semiconductor structure, wherein the semiconductor structure is manufactured by using any one of the above-mentioned methods for manufacturing a semiconductor structure.
[0020] As described above, the semiconductor structure and the manufacturing method thereof of the present invention have the following beneficial effects: by forming the interconnected through holes and the through holes between the interconnected structures, the interconnected structures are in an air state, which effectively reduces the capacitance and resistance-capacitance delay of the interconnected structures, thereby improving the signal transmission speed, and helping to achieve a higher line width ratio and a higher integration. In addition, making the interconnected structures in an air state can also reduce the crosstalk between adjacent interconnected structures, and improve the anti-interference ability of the circuit; and by arranging the through holes and the first barrier layer, the first dielectric layer, and the second barrier layer stacked in sequence below the through holes, the stability and Young's modulus of the semiconductor structure are effectively improved, and while ensuring the strength of the semiconductor structure, the volume of the through holes and the through holes can be as large as possible, effectively reducing the effective k value of the through holes and the through holes; in addition, by arranging the third barrier layer between the inner wall of the through hole and the interconnected structure, water vapor in the air is prevented from entering the conductive layer, thereby avoiding failure of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 It is a schematic diagram of the manufacturing process of the semiconductor structure of the present invention.
[0022] Figure 2 It is a schematic diagram of the structure after forming the second barrier layer of the present invention.
[0023] Figure 3 It is a schematic diagram of the structure after forming the third barrier layer of the present invention.
[0024] Figure 4 It is a schematic diagram of the structure after forming the interconnection structure of the present invention.
[0025] Figure 5 It is a schematic diagram of the structure after forming the through hole of the present invention.
[0026] Figure 6 It is a schematic diagram of the structure after forming a sacrificial layer of the present invention.
[0027] Figure 7 It is a schematic diagram showing the structure after the sacrificial layer located on the upper surface of the interconnection structure is removed in the present invention.
[0028] Figure 8 It is a schematic diagram of the structure after forming the fourth barrier layer of the present invention.
[0029] Fig. 9 It is a schematic diagram of the structure after forming the through hole of the present invention.
[0030] Fig.10It is a schematic diagram of the structure after removing the sacrificial layer in the through hole of the present invention.
[0031] Fig.11 It is a schematic diagram of the structure after forming the second dielectric layer of the present invention.
[0032] Component number description
[0033] 1 Substrate
[0034] 2. Laminated structure
[0035] 21 First barrier layer
[0036] 22. First dielectric layer
[0037] 23 Second barrier layer
[0038] 24 Third barrier layer
[0039] 3 Interconnection Structure
[0040] 31 First connection hole
[0041] 32 Second connection hole
[0042] 33 Isolation layer
[0043] 34 Conductive layer
[0044] 4 Through holes
[0045] 5 Sacrificial layer
[0046] 6 Fourth barrier layer
[0047] 61 Through Holes
[0048] 7 Second dielectric layer DETAILED DESCRIPTION
[0049] The following is a description of the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.
[0050] See also Figures 1 to 11. It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings in this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.
[0051] Embodiment 1
[0052] The present invention provides a method for manufacturing a semiconductor structure. Figure 1 FIG. 1 is a schematic diagram of a semiconductor structure manufacturing process, which includes the following steps:
[0053] S1: providing a substrate, forming a stacked structure on the substrate, the stacked structure comprising a first barrier layer, a first dielectric layer, a second barrier layer and a third barrier layer stacked in sequence, forming a plurality of spaced interconnect structures in the stacked structure, the interconnect structures penetrating the stacked structure and being electrically connected to the semiconductor device in the substrate;
[0054] S2: forming a through hole in the third barrier layer between two adjacent interconnect structures, wherein the second barrier layer is exposed at the bottom of the through hole and the inner wall of the through hole is spaced a preset distance from the interconnect structure;
[0055] S3: forming a sacrificial layer filling the through hole and a fourth barrier layer covering the sacrificial layer, the third barrier layer, and the upper surface of the interconnect structure, and forming a through hole in the fourth barrier layer with the bottom exposing the sacrificial layer;
[0056] S4: removing the sacrificial layer in the through hole based on the through hole, and forming a second dielectric layer on the upper surface of the fourth barrier layer to block the through hole opening.
[0057] For details, please refer to Figure 2-Figure 4 , perform step S1, provide a substrate 1, form a stacked structure 2 on the substrate 1, the stacked structure 2 includes a first barrier layer 21, a first dielectric layer 22, a second barrier layer 23 and a third barrier layer 24 stacked in sequence, and form a plurality of spaced interconnect structures 3 in the stacked structure 2, the interconnect structures 3 penetrate the stacked structure 2 and are electrically connected to the semiconductor device in the substrate 1.
[0058] Specifically, a semiconductor device is disposed in the substrate 1 , and the type of the semiconductor device can be selected according to actual conditions while satisfying the performance of the semiconductor structure, and is not limited here.
[0059] As an example, a method of forming the first barrier layer 21 includes chemical vapor deposition or other suitable methods.
[0060] Specifically, when the first barrier layer 21 is formed by chemical vapor deposition, the reaction gases used include tetramethylsilane and ammonia, the deposition temperature ranges from 330° C. to 380° C., and the thickness of the deposited first barrier layer 21 ranges from The gas flow rate of tetramethylsilane is in the range of 800 sccm to 1000 sccm, and the gas flow rate of ammonia is in the range of 4000 sccm to 5000 sccm. In this embodiment, the deposition temperature is 350°C.
[0061] As an example, a method of forming the first dielectric layer 22 includes chemical vapor deposition or other suitable methods.
[0062] Specifically, when the first dielectric layer 22 is formed by chemical vapor deposition, the reaction gases used include octamethylcyclotetrasiloxane and oxygen, the deposition temperature ranges from 330° C. to 380° C., and the thickness of the deposited first dielectric layer 22 ranges from In this embodiment, the deposition temperature is 350°C.
[0063] As an example, the first dielectric layer 22 includes a low dielectric constant material or other suitable materials.
[0064] As an example, Figure 2 , which is a schematic diagram of the structure after the second barrier layer 23 is formed. The method for forming the second barrier layer 23 includes chemical vapor deposition or other suitable methods.
[0065] Specifically, when the second barrier layer 23 is formed by chemical vapor deposition, the reaction gases used include tetramethylsilane and ammonia, the deposition temperature ranges from 330° C. to 380° C., and the thickness of the deposited second barrier layer 23 ranges from The gas flow rate of tetramethylsilane is in the range of 800 sccm to 1000 sccm, and the gas flow rate of ammonia is in the range of 4000 sccm to 5000 sccm. In this embodiment, the deposition temperature is 350°C.
[0066] Specifically, by forming the first barrier layer 21, the first dielectric layer 22 and the second barrier layer 23 stacked in sequence on the substrate 1, the substrate 1 is effectively protected and the stability of the semiconductor structure is improved.
[0067] As an example, Figure 3, which is a schematic diagram of the structure after the third barrier layer 24 is formed. The method for forming the third barrier layer 24 includes chemical vapor deposition or other suitable methods.
[0068] Specifically, when the third barrier layer 24 is formed by chemical vapor deposition, the reaction gases used include tetramethylsilane and ammonia, the deposition temperature ranges from 330° C. to 380° C., and the thickness of the deposited third barrier layer 24 ranges from The gas flow rate of tetramethylsilane is in the range of 1500 sccm to 1800 sccm, and the gas flow rate of ammonia is in the range of 4000 sccm to 5000 sccm.
[0069] Specifically, by increasing the gas flow rate of tetramethylsilane used when forming the third barrier layer 24 by chemical vapor deposition, more silicon content is provided to the third barrier layer 24 , thereby increasing the compactness of the third barrier layer 24 .
[0070] As an example, Figure 4 As shown, it is a schematic diagram of the structure after the interconnection structure 3 is formed. The formation of the interconnection structure 3 includes the following steps: forming a first connection hole 31 penetrating the stacked structure 2 and a second connection hole 32 penetrating the third barrier layer 24, respectively, and the top of the first connection hole 31 is connected to the bottom of the second connection hole 32; sequentially forming an isolation layer 33 and a conductive layer 34 filling the first connection hole 31 and the second connection hole 32 to obtain the interconnection structure 3.
[0071] As an example, a method of forming the first connection hole 31 includes dry etching or other suitable methods; a method of forming the second connection hole 32 includes dry etching or other suitable methods.
[0072] As an example, the hole diameter of the first connection hole 31 is smaller than the hole diameter of the second connection hole 32 .
[0073] Specifically, the method of forming the isolation layer 33 includes physical vapor deposition or other suitable methods; the method of forming the conductive layer 34 includes physical vapor deposition or other suitable methods.
[0074] As an example, the material of the isolation layer 33 includes at least one of tantalum nitride and tantalum, or other suitable materials; the material of the conductive layer 34 includes copper or other suitable materials.
[0075] Specifically, the isolation layer 33 is used to provide better adhesion and barrier properties for the conductive layer, and helps to reduce the diffusion of the conductive layer 34 and improve the reliability of the interconnect structure 3; the conductive layer 34 is used to provide an excellent signal transmission channel for the semiconductor structure.
[0076] For details, please refer to Figure 5, executing step S2, forming a through hole 4 in the third barrier layer 24 between two adjacent interconnect structures 3, wherein the second barrier layer 23 is exposed at the bottom of the through hole 4 and the inner wall thereof is spaced a preset distance from the interconnect structure 3.
[0077] Specifically, Figure 5 , which is a schematic diagram of the structure after the through hole 4 is formed. The method of forming the through hole 4 includes dry etching, wet etching or other suitable methods.
[0078] Specifically, under the condition that the performance of the semiconductor structure is met, the aspect ratio of the through hole 4 can be selected according to actual conditions, and is not limited here.
[0079] As an example, after the through hole 4 is formed, the distance between the inner wall of the through hole 4 and the interconnection structure 3 is in the range of That is, after forming the through hole 4, the width of the remaining third barrier layer 24 is in the range of
[0080] Specifically, by forming a through hole 4 in the third barrier layer 24 between two adjacent interconnect structures 3, and making the second barrier layer 23 exposed at the bottom of the through hole 4 while the inner wall of the through hole 4 is spaced a preset distance from the interconnect structure 3, water vapor in the air is prevented from entering the conductive layer 34, thereby avoiding device failure.
[0081] For details, please refer to Figure 6-Figure 9 , perform step S3 to form a sacrificial layer 5 filling the through hole 4 and a fourth barrier layer 6 covering the sacrificial layer 5 , the third barrier layer 24 , and the upper surface of the interconnect structure 2 , and form a through hole 61 in the fourth barrier layer 6 with the bottom exposing the sacrificial layer 5 .
[0082] Specifically, Figure 6-Figure 7 As shown, they are schematic diagrams of the structure after forming the sacrificial layer 5 and the schematic diagram of the structure after removing the sacrificial layer 5 located on the upper surface of the interconnect structure 3, respectively. The formation of the sacrificial layer 5 includes the following steps: forming a sacrificial layer 5 that fills the through hole 4 and covers the upper surface of the interconnect structure 3; removing the sacrificial layer 5 located on the upper surface of the interconnect structure 3 so that the upper surface of the sacrificial layer 5 is flush with the upper surface of the interconnect structure 3.
[0083] Specifically, the method for forming the sacrificial layer 5 includes chemical vapor deposition, and when the sacrificial layer 5 is formed by chemical vapor deposition, the reaction gas used includes octamethylcyclotetrasiloxane and oxygen, the deposition temperature ranges from 330° C. to 380° C., and the thickness of the deposited sacrificial layer 5 ranges from
[0084] Specifically, the method of removing the sacrificial layer 5 located on the upper surface of the interconnect structure 3 includes chemical mechanical polishing or other suitable methods.
[0085] Specifically, Figure 8 , which is a schematic diagram of the structure after forming the fourth barrier layer 6, wherein the method for forming the fourth barrier layer 6 includes chemical vapor deposition, and when the fourth barrier layer 6 is formed by chemical vapor deposition, the reaction gas used includes tetramethylsilane and ammonia, the deposition temperature ranges from 330° C. to 380° C., and the thickness of the deposited fourth barrier layer 6 ranges from The gas flow rate of tetramethylsilane is in the range of 800 sccm to 1000 sccm, and the gas flow rate of ammonia is in the range of 4000 sccm to 5000 sccm. In this embodiment, the deposition temperature is 350°C.
[0086] Specifically, Fig. 9 , which is a schematic diagram of the structure after the through hole 61 is formed. The method of forming the through hole 61 includes dry etching or other suitable methods.
[0087] Specifically, under the condition that the performance of the semiconductor structure is satisfied, the aspect ratio of the formed through hole 61 can be selected according to actual conditions, and is not limited here.
[0088] For details, please refer to Figure 10-11 , executing step S4 , removing the sacrificial layer 5 in the through hole 4 based on the through hole 61 , and forming a second dielectric layer 7 on the upper surface of the fourth barrier layer 6 to block the opening of the through hole 61 .
[0089] Specifically, Fig.10 , which is a schematic diagram of the structure after the sacrificial layer 5 in the through hole 4 is removed, and the method of removing the sacrificial layer 5 in the through hole 4 includes wet etching or other suitable methods.
[0090] Specifically, Fig.11 , which is a schematic diagram of the structure after forming the second dielectric layer 7. The method for forming the second dielectric layer 7 includes chemical vapor deposition or other suitable methods. When the second dielectric layer 7 is formed by chemical vapor deposition, the reaction gas used includes octamethylcyclotetrasiloxane and oxygen.
[0091] Specifically, by adjusting the parameters when forming the second dielectric layer 7 by chemical vapor deposition, the formed second dielectric layer 7 blocks the opening of the through hole 61 without filling the through hole 61, thereby ensuring that the volume between the interconnect structures 3 is in an air state.
[0092] As an example, the material of the second dielectric layer 7 includes a low dielectric constant material or other suitable materials.
[0093] Specifically, under the condition that the performance of the semiconductor structure is satisfied, the thickness of the formed second dielectric layer 7 can be selected according to the actual situation, and is not limited here. Specifically, the interconnection structures 3 are in an air state through the through holes 61 and the through holes 4 connected between the interconnection structures 3, which effectively reduces the capacitance and resistance-capacitance delay of the interconnection structures 3, thereby improving the transmission speed of the signal, and helping to achieve a higher line width ratio and a higher integration. In addition, making the interconnection structures 3 in an air state can also reduce the crosstalk between adjacent interconnection structures and improve the anti-interference ability of the circuit.
[0094] Specifically, by arranging the first barrier layer 21, the first dielectric layer 22, and the second barrier layer 23 stacked in sequence below the through hole 61 and the through hole 4, the stability and Young's modulus of the semiconductor structure are effectively improved, and while ensuring the strength of the device structure, the volume of the through hole 61 and the through hole 4 can be as large as possible, thereby effectively reducing the effective k value of the through hole 41 and the through hole 4.
[0095] The manufacturing method of the semiconductor structure of the present embodiment forms a through hole 61 and a through hole 4 that are connected between the interconnection structures 3, so that the interconnection structures 3 are in an air state, which effectively reduces the capacitance and resistance-capacitance delay of the interconnection structures 3, thereby improving the transmission speed of the signal, and helping to achieve a higher line width ratio and a higher integration. In addition, making the interconnection structures 3 in an air state can also reduce the crosstalk between adjacent interconnection structures 3 and improve the anti-interference ability of the circuit; and by arranging a first barrier layer 21, a first dielectric layer 22, and a second barrier layer 23 stacked in sequence below the through hole 61 and the through hole 4, the stability and Young's modulus of the semiconductor structure are effectively improved, and while ensuring the strength of the device structure, the volume of the through hole 61 and the through hole 4 can be as large as possible, and the effective k value of the through hole 61 and the through hole 4 is effectively reduced; in addition, by arranging a third barrier layer 24 between the inner wall of the through hole 4 and the interconnection structure 3, water vapor in the air is prevented from entering the conductive layer 43, thereby avoiding failure of the semiconductor structure.
[0096] Embodiment 2
[0097] The present embodiment provides a semiconductor structure, which is manufactured by the manufacturing method of the semiconductor structure described in the first embodiment, and includes: a substrate 1, a stacked structure 2, an interconnection structure 3, a fourth barrier layer, a through hole, a through hole and a second dielectric layer, wherein the stacked structure 2 is located on the substrate 1, the stacked structure 2 includes a first barrier layer 21, a first dielectric layer 22, a second barrier layer 23 and a third barrier layer 24 stacked in sequence, a plurality of interconnection structures 3 are arranged at intervals in the stacked structure 2, and the interconnection structures 3 penetrate the stacked structure 2 and are electrically connected to the semiconductor device in the substrate 1; the through hole 4 is located in the third barrier layer 24 between two adjacent interconnection structures 3, the second barrier layer 23 is exposed at the bottom of the through hole 4, and the inner wall of the through hole 4 is spaced from the interconnection structure 3 by a preset distance; the fourth barrier layer 6 covers the upper surface of the interconnection structure 3 and the third barrier layer 24, the through hole 61 is located in the fourth barrier layer 6 and the bottom is connected to the through hole 4, and the second dielectric layer 7 is located on the upper surface of the fourth barrier layer 6 and blocks the opening of the through hole 61.
[0098] Specifically, the interconnection structure 3 includes a first connection hole 31 passing through the stacked structure 2, a second connection hole 32 passing through the third barrier layer 24, an isolation layer 33 and a conductive layer 34 stacked in sequence and filling the first connection hole 31 and the second connection hole 32, and the top of the first connection hole 31 is connected to the bottom of the second connection hole 32.
[0099] A connected through hole 61 and a through hole 4 are formed between two adjacent interconnect structures 3 of the semiconductor structure of this embodiment, so that the interconnect structures 3 are in an air state, which effectively reduces the capacitance and resistance-capacitance delay of the interconnect structure 3, thereby improving the signal transmission speed and helping to achieve a higher line width ratio and a higher integration.
[0100] In summary, the semiconductor structure and its manufacturing method of the present invention, by forming interconnected through holes and through holes between interconnected structures, so that the interconnected structures are in an air state, effectively reducing the capacitance and resistance-capacitance delay of the interconnected structures, thereby improving the transmission speed of the signal, and helping to achieve a higher line width ratio and a higher integration. In addition, making the interconnected structures in an air state can also reduce the crosstalk between adjacent interconnected structures and improve the anti-interference ability of the circuit; and by setting the stacked structure below the through holes and through holes, including the first barrier layer, the first dielectric layer, and the second barrier layer stacked in sequence, the stability and Young's modulus of the semiconductor structure are effectively improved, and the volume of the through holes and through holes can be obtained as large as possible while ensuring the strength of the device structure, effectively reducing the effective k value of the through holes and through holes; in addition, by setting the third barrier layer between the inner wall of the through hole and the interconnected structure, water vapor in the air is prevented from entering the conductive layer, thereby avoiding the failure of the semiconductor structure. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0101] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: The following steps are involved: A substrate is provided, and a stacked structure is formed on the substrate, wherein the stacked structure includes a first barrier layer, a first dielectric layer, a second barrier layer, and a third barrier layer stacked in sequence, and a plurality of interconnect structures arranged at intervals are formed in the stacked structure, wherein the interconnect structures penetrate the stacked structure and are electrically connected to the semiconductor device in the substrate; A through hole is formed in the third barrier layer between two adjacent interconnect structures, wherein the second barrier layer is exposed at the bottom of the through hole and the inner wall of the through hole is spaced a preset distance from the interconnect structure; forming a sacrificial layer filling the through hole and a fourth barrier layer covering the sacrificial layer, the third barrier layer, and the upper surface of the interconnect structure, and forming a through hole in the fourth barrier layer with the bottom exposing the sacrificial layer; The sacrificial layer in the through hole is removed based on the through hole, and a second dielectric layer is formed on the upper surface of the fourth barrier layer to block the through hole opening.
2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The method for forming the first barrier layer includes chemical vapor deposition; the method for forming the first dielectric layer includes chemical vapor deposition; the method for forming the second barrier layer includes chemical vapor deposition; and the method for forming the third barrier layer includes chemical vapor deposition.
3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Forming the interconnection structure includes the following steps: forming a first connection hole penetrating the stacked structure and a second connection hole penetrating the third barrier layer, respectively, and the top of the first connection hole is connected to the bottom of the second connection hole; sequentially forming an isolation layer and a conductive layer filling the first connection hole and the second connection hole to obtain the interconnection structure.
4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that: The material of the isolation layer includes at least one of tantalum and tantalum nitride; the material of the conductive layer includes copper.
5. The method for manufacturing a semiconductor structure according to claim 3, wherein: The diameter of the first connection hole is smaller than the diameter of the second connection hole.
6. The method for manufacturing a semiconductor structure according to claim 3, characterized in that: The method of forming the first connection hole includes dry etching; the method of forming the second connection hole includes dry etching.
7. The method for manufacturing a semiconductor structure according to claim 1, wherein: After the through hole is formed, the distance between the side wall of the through hole and the side wall of the interconnection structure is in the range of 8. The method for manufacturing a semiconductor structure according to claim 1, wherein: The method of forming the through hole includes dry etching; the method of removing the sacrificial layer in the through hole includes wet etching.
9. The method for manufacturing a semiconductor structure according to claim 1, wherein: The material of the first dielectric layer includes a low dielectric constant material; the material of the second dielectric layer includes a low dielectric constant material.
10. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by using the method for manufacturing a semiconductor structure according to any one of claims 1 to 9.