Method for manufacturing display device

Abstract

A manufacturing method of a display device includes: preparing a substrate including a metal pattern; forming a first active pattern disposed on the substrate and including first and second regions and a first channel region between the first and second regions; forming a first gate electrode pattern on the first active pattern; forming a second active pattern on the first gate electrode pattern; forming an etch stop pattern overlapping the first region and the second region; forming an interlayer insulating layer covering the etching stop pattern; defining a first hole exposing the etch stop pattern and a second hole penetrating the interlayer insulating layer; defining a third hole exposing the top surface of the substrate; defining a fourth hole penetrating the etch stop pattern and a fifth hole exposing the metal pattern; forming a metal pattern connection electrode on the metal pattern; and forming a light emitting device on the metal pattern connection electrode.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a display device. More specifically, the present disclosure relates to a method for manufacturing a spliced ​​display device. Background Art

[0002] Generally, a spliced ​​display device includes multiple display devices to realize a large screen. Multiple display devices can be connected to each other to form a spliced ​​display device structure.

[0003] Each of the plurality of display devices may include a display area and a non-display area adjacent to the display area. An image may be displayed in the display area, and a driving circuit module (e.g., a driver integrated chip or a printed circuit board, etc.) for displaying the image may be disposed in the non-display area. That is, the non-display area may refer to a frame having a predetermined width on which the driving circuit module for displaying the image is disposed. Summary of the invention

[0004] The embodiment provides a manufacturing method of a display device with improved manufacturing process efficiency.

[0005] The embodiment provides a display device manufactured by the display device manufacturing method.

[0006] The manufacturing method of the display device in the embodiment includes: preparing a substrate including a metal pattern and defining a display area and a non-display area therein; forming a first active pattern that is arranged on the substrate and includes a first area, a second area and a first channel area arranged between the first area and the second area; forming a first gate electrode pattern overlapping the first channel area on the first active pattern; forming a second active pattern on the first gate electrode pattern; forming an etch stop pattern in the same layer as the second active pattern and overlapping the first area and the second area of ​​the first active pattern; forming an interlayer insulating layer covering the etch stop pattern; defining a first hole that exposes the etch stop pattern and a second hole that penetrates the interlayer insulating layer; defining a third hole that extends from the second hole and exposes the top surface of the substrate; defining a fourth hole that extends from the first hole and penetrates the etch stop pattern and a fifth hole that extends from the third hole and exposes the metal pattern; forming a metal pattern connecting electrode that is arranged on the metal pattern and connected to the metal pattern through the fifth hole; and forming a light-emitting device on the metal pattern connecting electrode.

[0007] In an embodiment, the preparing of the substrate may include: forming a first base substrate on a carrier substrate; forming a metal pattern on the first base substrate; and forming a second base substrate on the first base substrate and the metal pattern.

[0008] In an embodiment, the third hole may expose the top surface of the second base substrate.

[0009] In an embodiment, the first base substrate and the second base substrate may include plastic having flexible properties.

[0010] In an embodiment, the first base substrate and the second base substrate may include polyimide.

[0011] In an embodiment, the method may further include removing the carrier substrate after forming the light emitting device.

[0012] In an embodiment, the method may further include: after forming the first active pattern, forming a first insulating layer covering the first active pattern; and after forming the first gate electrode pattern, forming a second insulating layer covering the first gate electrode pattern.

[0013] In an embodiment, an etch rate of the first insulating layer, an etch rate of the second insulating layer, and an etch rate of the interlayer insulating layer may be greater than an etch rate of the etch stop pattern.

[0014] In an embodiment, when each of the first insulating layer, the second insulating layer and the interlayer insulating layer includes an inorganic material, an etching selectivity ratio between at least one of the first insulating layer, the second insulating layer and the interlayer insulating layer including the inorganic material and the etching stop pattern can be about 15:1 or greater.

[0015] In an embodiment, when each of the first insulating layer, the second insulating layer and the interlayer insulating layer includes an organic material, an etching selectivity ratio between at least one of the first insulating layer, the second insulating layer and the interlayer insulating layer including the organic material and the etching stop pattern may be approximately 1000:1 or greater.

[0016] In an embodiment, the first active pattern and the second active pattern may include different materials from each other.

[0017] In an embodiment, the first active pattern may include a silicon semiconductor.

[0018] In an embodiment, the etch stop pattern and the second active pattern may be formed simultaneously.

[0019] In an embodiment, the etch stop pattern and the second active pattern may include or consist of the same oxide semiconductor.

[0020] In an embodiment, the etch stop pattern and the second active pattern may include or consist of indium gallium zinc oxide (“IGZO”).

[0021] In an embodiment, a fifth hole may be defined in the display area.

[0022] In an embodiment, the fifth hole may be defined in the non-display area.

[0023] The manufacturing method of the display device in the embodiment may include: preparing a substrate including a metal pattern and defining a display area and a non-display area therein; forming a first active pattern disposed on the substrate and including a first area, a second area, and a first channel area disposed between the first area and the second area; forming a first gate electrode pattern overlapping the first channel area on the first active pattern; forming a second active pattern on the first gate electrode pattern; forming an etch stop pattern in the same layer as the second active pattern and overlapping the first area and the second area of ​​the first active pattern; forming an interlayer insulating layer covering the etch stop pattern; defining a first hole exposing the etch stop pattern and a second hole penetrating the interlayer insulating layer; defining a third hole extending from the second hole and exposing the top surface of the substrate; defining a fourth hole extending from the first hole and penetrating the etch stop pattern and a fifth hole extending from the third hole and exposing the metal pattern; forming a metal pattern connection electrode disposed on the metal pattern and connected to the metal pattern through the fifth hole; and forming a light emitting device on the metal pattern connection electrode. Accordingly, a photo process may be omitted. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Illustrative and non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0025] Figure 1 is a perspective view illustrating an embodiment of a spliced ​​display device according to the present disclosure.

[0026] Figure 2 yes Figure 1 Front view of a video wall device.

[0027] Figure 3 is included in Figure 1 A perspective view of a display device in a spliced ​​display device.

[0028] Figure 4 is along Figure 3 A cross-sectional view taken along line II'.

[0029] Figure 5 is along Figure 3 A cross-sectional view taken along line II-II'.

[0030] Figures 6 to 21 It is a graphic Figure 3 A cross-sectional view of a method for manufacturing a display device. DETAILED DESCRIPTION

[0031] Embodiments of the present disclosure will now be more fully described below with reference to the accompanying drawings in which various embodiments are shown. However, the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure thorough and complete, and to fully convey the scope of the present invention to those skilled in the art. The same reference numerals always refer to the same elements.

[0032] It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0033] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below may be referred to as a second element, component, region, layer or part without departing from the teachings herein.

[0034] The terms used herein are only used for the purpose of describing specific embodiments, and are not intended to be limiting. As used herein, the singular "one" and "the (described)" are intended to include plural forms, including "at least one", unless the context clearly indicates otherwise. "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the listed associated items. It will be further understood that when used in this specification, the term "includes" and / or its variations or "comprising" and / or its variations indicate the existence of stated features, regions, wholes, steps, operations, elements and / or parts, but does not exclude the existence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or its groups.

[0035] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as illustrated in the figure. It will be understood that relative terms are intended to cover different orientations of the device in addition to the orientation depicted in the figure. For example, if the device in one of the figures is turned over, the element described as being on the "lower" side of the other elements will then be oriented to be on the "upper" side of the other elements. Therefore, the exemplary term "lower" may include both "lower" and "upper" orientations, depending on the specific orientation of the figure. Similarly, if the device in one of the figures is turned over, the element described as being "below" or "below" the other elements will then be oriented to be "above" the other elements. Therefore, the exemplary term "below" or "below" may cover both upper and lower orientations.

[0036] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for that particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, a term such as "about" may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0038] Figure 1 is a perspective view illustrating a spliced ​​display device according to the present disclosure. Figure 2 yes Figure 1 Front view of a video wall device.

[0039] In an embodiment, for example, Figure 2 The front view of FIG. 1 shows the front surface of the spliced ​​display device TDD. The front surface may be defined by a first direction DR1 and a second direction DR2. The second direction DR2 may intersect the first direction DR1. The front surface is also referred to as a "display surface".

[0040] refer to Figure 1 and Figure 2 The spliced ​​display device TDD may include a housing HS and a plurality of display devices DD. The plurality of display devices DD may be arranged in a matrix form. The spliced ​​display device TDD is also referred to as a "multi-screen display".

[0041] The splicing display device TDD may have various planar shapes. In an embodiment, for example, the splicing display device TDD may have a quadrilateral shape (e.g., a rectangular shape) in a plan view. However, the present disclosure is not limited thereto. In an embodiment, for example, the splicing display device TDD may have various shapes such as a circle or an ellipse in a plan view. In addition, the edge of the splicing display device TDD may have a sharp angle shape or a curved shape.

[0042] In an embodiment, the splicing display device TDD may be a rigid display device. In another embodiment, for example, the splicing display device TDD may be a flexible display device. In an embodiment, for example, the splicing display device TDD may be deformable. Specifically, the splicing display device TDD may be folded, bent, or curled. However, the present disclosure is not limited thereto.

[0043] The plurality of display devices DD may include a first display device DD1, a second display device DD2, a third display device DD3, and a fourth display device DD4. Figure 2 As shown in , for example, a plurality of display devices DD can display one image in a divided manner. In another embodiment, each of the plurality of display devices DD can display an image separately.

[0044] The housing HS may physically combine a plurality of display devices DD to form a spliced ​​display device TDD. To this end, a fastening member or the like may be further included between the housing HS and the plurality of display devices DD. In an embodiment, for example, the housing HS may be disposed on a rear surface of the spliced ​​display device TDD. The rear surface may face away from the front surface in a third direction DR3. The third direction DR3 may intersect with the first direction DR1. In addition, the third direction DR3 may also intersect with the second direction DR2.

[0045] Figure 1 and Figure 2 A plurality of display devices DD arranged in two rows and two columns are shown, but the present disclosure is not limited thereto. In an embodiment, for example, L display devices DD may be provided (where L is a natural number of 2, 3, 5 or more). In addition, a plurality of display devices DD may be arranged in n rows and m columns (each of n and m is a natural number of 3 or more).

[0046] In addition, Figure 1 and Figure 2 In the embodiment, the spliced ​​display device TDD is described as including multiple display devices DD having the same size as each other, but the present disclosure is not limited thereto. In an embodiment, for example, the spliced ​​display device TDD may include multiple display devices DD of various types, structures, sizes and / or shapes.

[0047] Figure 3is included in Figure 1 A perspective view of a display device in a spliced ​​display device.

[0048] In an embodiment, for example, one of the plurality of display devices DD may be included in Figure 1 The first display device DD1 in the spliced ​​display device TDD.

[0049] refer to Figure 1 , Figure 2 and Figure 3 , each of the plurality of display devices DD may have various planar shapes. In an embodiment, each of the plurality of display devices DD may have a quadrilateral shape (e.g., a rectangular shape) in a plan view. However, the present disclosure is not limited thereto. In an embodiment, each of the plurality of display devices DD may have various shapes such as a circle or an ellipse in a plan view. In addition, the edge of each of the plurality of display devices DD may have a sharp angle shape or a curved shape.

[0050] In an embodiment, for example, each of the plurality of display devices DD may be a rigid display device. In another embodiment, each of the plurality of display devices DD may be a flexible display device. In an embodiment, for example, at least one region of each of the plurality of display devices DD may be deformable. Specifically, each of the plurality of display devices DD may be folded, bent, or curled. However, the present disclosure is not limited thereto.

[0051] Each of the plurality of display devices DD may include a display area DA and a non-display area NA.

[0052] Each of the plurality of display devices DD may be a region for displaying an image. To this end, pixels may be arranged in the display region DA. In an embodiment, for example, each of the plurality of display devices DD may be an organic light-emitting display device including an organic light-emitting diode. However, the present disclosure is not limited thereto. In an embodiment, for example, each of the plurality of display devices DD may be a liquid crystal display device including a liquid crystal capacitor.

[0053] The display area DA may have various planar shapes. In an embodiment, the display area DA may have various planar shapes such as a quadrangle (eg, a rectangle), a circle, or an ellipse. However, the present disclosure is not limited thereto.

[0054] The pixels may be arranged in the display area DA according to various arrangement structures. In an embodiment, for example, the pixels may be arranged to be spaced apart from each other along the first direction DR1. In an alternative embodiment, the pixels may be arranged to be spaced apart from each other along the second direction DR2. However, the present disclosure is not limited thereto.

[0055] The display area DA may be defined on at least one surface of each of the plurality of display devices DD. In an embodiment, for example, the display area DA may be defined on the front surface of each of the plurality of display devices DD. In an alternative embodiment, the display area DA may be defined on the rear surface or the side surface of each of the plurality of display devices DD. The side surface may intersect with the front surface (or the rear surface). The side surface may be defined by a first direction DR1 and a third direction DR3. In an alternative embodiment, the side surface may be defined by a second direction DR2 and a third direction DR3. However, the present disclosure is not limited thereto.

[0056] The non-display area NA may be an area where no image is displayed. That is, pixels may not be set in the non-display area NA. A circuit structure (e.g., a line, a pad, or a driving circuit, etc.) for driving pixels may be set in the non-display area NA. The non-display area NA may include a black ink layer so that the circuit structure is not visible from the outside of each of the multiple display devices DD. For this reason, the non-display area NA is also referred to as a border area. However, the present disclosure is not limited thereto. In an embodiment, for example, the ink layer may be omitted and the circuit structure may be set at a different position.

[0057] The non-display area NA may be adjacent to the display area DA. In an embodiment, for example, the non-display area NA may surround the display area DA. However, the present disclosure is not limited thereto. In an embodiment, for example, the non-display area NA may be disposed only on one side of the display area DA.

[0058] Without increasing the size of each of the plurality of display devices DD (or the area of ​​each of the plurality of display devices DD), when the area of ​​the non-display area NA becomes smaller, the size of the display area DA can be increased. By this, the area of ​​the display surface on which the image is displayed can be increased.

[0059] In addition, when the area of ​​the non-display area NA becomes smaller, when a spliced ​​display device is implemented using multiple display devices DD, the visibility of the boundaries (or seams) between the multiple display devices DD can be reduced. By this, the sense of disconnection in the image is reduced, and the image can be viewed more naturally.

[0060] Figure 4 is along Figure 3 A cross-sectional view taken along line II'. Figure 5 is along Figure 3 A cross-sectional view taken along line II-II'.

[0061] refer to Figure 3 , Figure 4 and Figure 5 , each of the plurality of display devices DD may include a substrate SUB, a device wiring layer DRL including at least one transistor, and a light emitting device layer EDL.

[0062] In an embodiment, the device wiring layer DRL may be disposed on the substrate SUB. The light emitting device layer EDL may, for example, be included in and disposed on the device wiring layer DRL. Figure 4 , but when the light emitting device layer EDL includes an organic material, the display device DD may further include an encapsulation layer to prevent oxidation of the organic material.

[0063] The substrate SUB may have a flexible property. In an embodiment, for example, the substrate SUB may include a polymer organic material (eg, plastic, etc.).

[0064] The circuit structure connected to the pixel may be disposed in the device wiring layer DRL. In an embodiment, for example, the device wiring layer DRL may include various lines such as gate lines, data lines, or power lines, etc. In an alternative embodiment, the device wiring layer DRL may further include control lines, etc.

[0065] The light emitting device layer EDL may include light emitting devices constituting pixels. There is no limitation on the type, structure, shape, size, etc. of the light emitting devices included in the light emitting device layer EDL.

[0066] In embodiments, the substrate SUB may have a metal embedded polyimide (“MEP”) structure including at least one metal pattern. In embodiments, for example, the substrate SUB may include a first base substrate BS1 , a metal pattern MP, and a second base substrate BS2 .

[0067] Each of the first base substrate BS1 and the second base substrate BS2 may include a plastic having a flexible property. In an embodiment, for example, each of the first base substrate BS1 and the second base substrate BS2 may include polyethersulfone ("PES"), polyacrylate ("PA"), polyetherimide ("PEI"), polyethylene naphthalate ("PEN"), polyethylene terephthalate ("PET"), polyphenylene sulfide ("PPS"), polyarylate ("PAR"), polyimide ("PI"), polycarbonate ("PC"), cellulose triacetate ("TAC"), or cellulose acetate propionate ("CAP"), etc. These materials may be used alone or in any combination with each other. However, the present disclosure is not limited thereto.

[0068] In an embodiment, each of the first base substrate BS1 and the second base substrate BS2 may include polyimide. However, the present disclosure is not limited thereto. In an embodiment, for example, each of the first base substrate BS1 and the second base substrate BS2 may include another polymer material, and each of the first base substrate BS1 and the second base substrate BS2 may include polymer materials different from each other.

[0069] In an embodiment, the metal pattern MP may be disposed between the first base substrate BS1 and the second base substrate BS2. In an embodiment, for example, the metal pattern MP may be disposed on the first base substrate BS1, and the second base substrate BS2 may be disposed on the first base substrate BS1 and the metal pattern MP.

[0070] In an embodiment, the metal pattern MP may include a first metal pattern MP1, a second metal pattern MP2, and a third metal pattern MP3. In an embodiment, for example, the metal pattern MP may be formed in a display area and / or a non-display area. In an embodiment, as shown in FIG. Figure 4 As shown in , for example, the first metal pattern MP1 and the second metal pattern MP2 may be formed in the display area. Figure 5 As shown in , the third metal pattern MP3 may be formed in the non-display area.

[0071] In an embodiment, for example, a constant voltage may be provided to the metal pattern MP. In an embodiment, for example, the metal pattern MP may be connected to a voltage electrode pattern ( Figure 5 A voltage electrode pattern EVS is provided, and a power supply voltage may be provided to the metal pattern MP. However, the present disclosure is not limited thereto. In an embodiment, for example, an AC voltage may be provided to the metal pattern MP.

[0072] In an embodiment, the metal pattern MP may include a conductive metal or an alloy of a metal. In an embodiment, for example, the metal pattern MP may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), or copper (Cu). These materials may be used alone or in any combination with each other. However, the present disclosure is not limited thereto. The metal pattern MP may be formed as a single layer or multiple layers.

[0073] The substrate SUB may further include at least one buffer layer. In an embodiment, for example, a first buffer layer 120 may be disposed on the first base substrate BS1. The metal pattern MP may be disposed on the first buffer layer 120. The second buffer layer 140 may be disposed on the first buffer layer 120 and the metal pattern MP. In addition, the second base substrate BS2 may be disposed on the second buffer layer 140.

[0074] In an embodiment, for example, each of the first buffer layer 120 and the second buffer layer 140 may include an inorganic material. In an embodiment, for example, each of the first buffer layer 120 and the second buffer layer 140 may include silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiOx N y ) etc. These materials can be used alone or in any combination with each other. However, the present disclosure is not limited thereto.

[0075] exist Figure 4 , the substrate SUB is described as including the first base substrate BS1 and the second base substrate BS2, however the present disclosure is not limited thereto. In an embodiment, for example, one of the first base substrate BS1 and the second base substrate BS2 may be omitted.

[0076] In an embodiment, a device wiring layer DRL may be disposed on a substrate SUB. The device wiring layer DRL may include a first transistor, a second transistor, a first capacitor, and an etching stop pattern residue ESR. In an embodiment, for example, the first transistor may include a first active pattern ACT1 and a first gate electrode pattern GA1. The first capacitor may include a first capacitor electrode pattern CEP1 overlapping the first gate electrode pattern GA1. The second transistor may include a second gate electrode pattern GA2 and a second active pattern ACT2.

[0077] The third buffer layer 200 may be disposed on the substrate SUB. In an embodiment, for example, the third buffer layer 200 may be disposed on the second base substrate BS2.

[0078] The third buffer layer 200 may prevent impurities from penetrating into transistors (eg, the first transistor and / or the second transistor). In addition, the third buffer layer 200 may control a rate at which heat is provided during a crystallization process of forming the first active pattern ACT1. Accordingly, the first active pattern ACT1 may be uniformly formed.

[0079] In an embodiment, for example, the third buffer layer 200 may include an inorganic insulating material. In an embodiment, for example, the inorganic insulating material may include silicon nitride, silicon oxide, or silicon oxynitride, etc. These materials may be used alone or in any combination with each other. However, the present disclosure is not limited thereto. In an embodiment, for example, the third buffer layer 200 may include an organic material. In an alternative embodiment, the third buffer layer 200 may be omitted.

[0080] In an embodiment, the first active pattern ACT1 may be disposed on the substrate SUB. In an embodiment, for example, the first active pattern ACT1 may be disposed on the third buffer layer 200 .

[0081] In an embodiment, the first active pattern ACT1 may include a first region A1, a first channel region CH1, and a second region A2. For example, the first region A1 and the second region A2 may be spaced apart from each other in the second direction DR2. The first channel region CH1 may be disposed between the first region A1 and the second region A2.

[0082] In an embodiment, the first active pattern ACT1 may include a silicon semiconductor. In an embodiment, for example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon, etc. In an embodiment, for example, the first active pattern ACT1 may include polycrystalline silicon formed by crystallizing amorphous silicon. Crystallization may be performed at a relatively low temperature.

[0083] The first active pattern ACT1 may be doped (eg, ions implanted). In an embodiment, for example, when the first active pattern ACT1 constitutes a P-channel metal oxide semiconductor (“PMOS”) transistor, ions such as boron (B) may be implanted into the first active pattern ACT1.

[0084] The first insulating layer IN1 may be disposed on the first active pattern ACT1. The first insulating layer IN1 may be disposed under the first gate electrode pattern GA1, and is also referred to as a 'first gate insulating layer'.

[0085] In an embodiment, for example, the first insulating layer IN1 may include an inorganic insulating material. In an embodiment, for example, the inorganic insulating material may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, or hafnium oxide, etc. These materials may be used alone or in any combination with each other. The first insulating layer IN1 may have a single-layer or multi-layer structure. However, the present disclosure is not limited thereto. In an embodiment, for example, the first insulating layer IN1 may include an organic material.

[0086] In an embodiment, the first gate electrode pattern GA1 may be disposed on the first active pattern ACT1 overlapping the first channel region CH1 .

[0087] In an embodiment, for example, the first gate electrode pattern GA1 may include a conductive material. In an embodiment, for example, the first gate electrode pattern GA1 may include aluminum (Al), molybdenum (Mo), copper (Cu), or titanium (Ti), etc. These materials may be used alone or in any combination with each other. However, the present disclosure is not limited thereto.

[0088] The second insulating layer IN2 may be disposed on the first gate electrode pattern GA1. The second insulating layer IN2 may be disposed under the second gate electrode pattern GA2, and is also referred to as a 'second gate insulating layer'.

[0089] In an embodiment, for example, the second insulating layer IN2 may include an inorganic insulating material. In an embodiment, for example, the inorganic insulating material may include silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) or aluminum oxide (AlO x) etc. These materials may be used alone or in any combination with each other. The second insulating layer IN2 may have a single layer or a multi-layer structure. However, the present disclosure is not limited thereto. In an embodiment, for example, the second insulating layer IN2 may include an organic material.

[0090] In an embodiment, the first capacitor electrode pattern CEP1 may be disposed on the first gate electrode pattern GA1. The first capacitor electrode pattern CEP1 may form a storage capacitor together with the first gate electrode pattern GA1. The first transistor (eg, a driving transistor) may control a driving current flowing through the light emitting device ED based on the value of the stored voltage.

[0091] In an embodiment, for example, the first capacitor electrode pattern CEP1 may include a conductive material. However, the present disclosure is not limited thereto.

[0092] In embodiments, the first capacitor electrode pattern CEP1 may be disposed in the same layer as the second gate electrode pattern GA2 .

[0093] In an embodiment, for example, the second gate electrode pattern GA2 may include a conductive material. However, the present disclosure is not limited thereto. In an embodiment, the first capacitor electrode pattern CEP1 and the second gate electrode pattern GA2 may include the same material as each other. In an embodiment, for example, the first capacitor electrode pattern CEP1 and the second gate electrode pattern GA2 may be formed simultaneously. However, the present disclosure is not limited thereto.

[0094] The third insulating layer IN3 may be disposed on the first capacitor electrode pattern CEP1 and the second gate electrode pattern GA2. The third insulating layer IN3 is also referred to as a "first interlayer insulating layer". The third insulating layer IN3 may be disposed under the second active pattern ACT2 described later, and is also referred to as an "oxide buffer layer". That is, the third insulating layer IN3 may prevent impurities from penetrating into the second active pattern ACT2.

[0095] In an embodiment, for example, the third insulating layer IN3 may include an inorganic insulating material. In an embodiment, for example, the inorganic insulating material may include silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) or aluminum oxide (AlO x ) etc. These materials may be used alone or in any combination with each other. The third insulating layer IN3 may have a single layer or a multi-layer structure. However, the present disclosure is not limited thereto. In an embodiment, for example, the third insulating layer IN3 may include an organic material.

[0096] In an embodiment, the second active pattern ACT2 may be disposed on the second gate electrode pattern GA2. In an embodiment, for example, the second active pattern ACT2 may be disposed on the third insulating layer IN3. Specifically, the second active pattern ACT2 may be disposed to be spaced apart from the first active pattern ACT1. In an embodiment, for example, the second active pattern ACT2 may be disposed on the third insulating layer IN3 at a position spaced apart from the first active pattern ACT1 in the second direction DR2.

[0097] In an embodiment, for example, the second active pattern ACT2 may include a third region A3, a second channel region CH2, and a fourth region A4. The third region A3 and the fourth region A4 may be spaced apart from each other in the second direction DR2. The second channel region CH2 may be disposed between the third region A3 and the fourth region A4.

[0098] In an embodiment, the first active pattern ACT1 and the second active pattern ACT2 may include materials different from each other. In an embodiment, for example, the second active pattern ACT2 may include an oxide semiconductor. In an embodiment, for example, the oxide semiconductor may include indium gallium zinc oxide ("IGZO"). However, the present disclosure is not limited thereto. In an embodiment, for example, the second active pattern ACT2 may include another semiconductor material or an oxide semiconductor other than IGZO.

[0099] In an embodiment, the etch stop pattern residue ESR may be disposed in the same layer as the second active pattern ACT2. Specifically, the etch stop pattern residue ESR may be disposed to overlap the first area A1 and the second area A2 of the first active pattern ACT1.

[0100] The etch stop pattern residue (ESR) may refer to the residual amount of the etch stop pattern (e.g., Fig.14 The material remaining around the contact hole during the process of etching the contact hole with the etch stop pattern ES.

[0101] In an embodiment, the second active pattern ACT2 and the etch stop pattern residue ESR may include the same oxide semiconductor. In an embodiment, for example, the oxide semiconductor may include IGZO. In an embodiment, for example, the second active pattern ACT2 and the etch stop pattern residue ESR may be formed simultaneously. However, the present disclosure is not limited thereto.

[0102] A fourth insulating layer IN4 may be disposed on the second active pattern ACT2 and the etch stop pattern residue ESR. The fourth insulating layer IN4 is also referred to as a 'third gate insulating layer'.

[0103] In an embodiment, for example, the fourth insulating layer IN4 may include an inorganic insulating material. In an embodiment, for example, the inorganic insulating material may include silicon nitride (SiNx ), silicon oxynitride (SiO x N y ) or aluminum oxide (AlO x ) etc. These materials may be used alone or in any combination with each other. The fourth insulating layer IN4 may have a single layer or a multi-layer structure. However, the present disclosure is not limited thereto. In an embodiment, for example, the fourth insulating layer IN4 may include an organic material.

[0104] In an embodiment, for example, the third gate electrode pattern GA3 may be disposed on the second gate electrode pattern GA2. In an embodiment, for example, the third gate electrode pattern GA3 may be disposed on the fourth insulating layer IN4.

[0105] In an embodiment, for example, the third gate electrode pattern GA3 may include a conductive material. However, the present disclosure is not limited thereto.

[0106] exist Figure 4 In the embodiment, the first transistor has a top gate structure and the second transistor has a double gate structure, but the present disclosure is not limited thereto.

[0107] A fifth insulating layer IN5 may be disposed on the third gate electrode pattern GA3. The fifth insulating layer IN5 is also referred to as a 'second interlayer insulating layer'.

[0108] In an embodiment, for example, the fifth insulating layer IN5 may include an inorganic insulating material. In an embodiment, for example, the inorganic insulating material may include silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) or aluminum oxide (AlO x ) and the like. These materials may be used alone or in any combination with each other. The fifth insulating layer IN5 may have a single layer or a multi-layer structure. However, the present disclosure is not limited thereto. In an embodiment, for example, the fifth insulating layer IN5 may include an organic material.

[0109] The first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, the second drain electrode DE2 and the metal pattern connection electrode MCE may be formed on the second active pattern ACT2. In an embodiment, for example, the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, the second drain electrode DE2 and the metal pattern connection electrode MCE may be disposed on the fifth insulating layer IN5.

[0110] In an embodiment, for example, each of the first source electrode SE1 and the first drain electrode DE1 may be formed through a first contact hole (eg, Fig.19The first hole OS1 and the fourth hole OS4 of the first active pattern ACT1 are connected to the first active pattern ACT1. In an embodiment, for example, the first source electrode SE1 may be connected to the first area A1 of the first active pattern ACT1. The first drain electrode DE1 may be connected to the second area A2 of the first active pattern ACT1.

[0111] In addition, each of the second source electrode SE2 and the second drain electrode DE2 may be connected to the second active pattern ACT2 through a second contact hole. In an embodiment, for example, the second source electrode SE2 may be connected to the third area A3 of the second active pattern ACT2. The second drain electrode DE2 may be connected to the fourth area A4 of the second active pattern ACT2.

[0112] In addition, the metal pattern connection electrode MCE can be connected through the third contact hole (eg, Fig.19 The second hole OS2, the third hole OS3, and the fifth hole OS5 of the light emitting device are connected to the metal pattern MP. Accordingly, a power supply voltage may be provided to the light emitting device.

[0113] However, the present disclosure is not limited thereto. In an embodiment, for example, positions of the first source electrode SE1 and the first drain electrode DE1 may be changed, and positions of the second source electrode SE2 and the second drain electrode DE2 may also be changed.

[0114] The first contact hole and the third contact hole may be formed at the same time. For this purpose, in an embodiment, the etching rate of the first insulating layer IN1, the etching rate of the second insulating layer IN2, the etching rate of the third insulating layer IN3, the etching rate of the fourth insulating layer IN4, and the etching rate of the fifth insulating layer IN5 may be greater than the etching stop pattern (e.g., Fig.17 The etching rate of the etching stop pattern ES).

[0115] In an embodiment, when the first to fifth insulating layers IN1, IN2, IN3, IN4 and IN5 may include an inorganic material, an etching selectivity ratio between at least one of the first to fifth insulating layers IN1, IN2, IN3, IN4 and IN5 and the etching stop pattern may be about 15:1 or greater.

[0116] In an embodiment, when the first to fifth insulating layers IN1, IN2, IN3, IN4 and IN5 may include an organic material, an etching selectivity ratio between at least one of the first to fifth insulating layers IN1, IN2, IN3, IN4 and IN5 and the etching stop pattern may be about 1000:1 or greater.

[0117] The first contact hole and the third contact hole may be formed after an etching stop pattern having etching selectivity is provided at a location where the first contact hole is to be formed. When a loss occurs in the etching stop pattern at a location where the first contact hole is to be formed, a deeper hole may be formed at a location where the third contact hole is to be formed.

[0118] The display device according to the comparative example may not include an etching stop pattern. Accordingly, a substrate SUB may be formed, a third contact hole may be formed (a primary contact hole forming process), a second active pattern ACT2 may be formed, a first contact hole and a third contact hole may be formed (a secondary contact hole forming process), and a light emitting device may be formed.

[0119] The display device in the embodiment of the present disclosure may include an etching stop pattern. The etching stop pattern may control the etching time. Accordingly, the first contact hole and the third contact hole may be formed simultaneously after the substrate SUB is formed to the second active pattern ACT2. That is, the one-time contact hole forming process in the manufacturing process of the display device according to the comparative example may be omitted. Accordingly, the display device (for example, Figure 3 The efficiency of the manufacturing process of one of the multiple display devices DD).

[0120] In an embodiment, for example, each of the first source electrode SE1 , the first drain electrode DE1 , the second source electrode SE2 , the second drain electrode DE2 , and the metal pattern connection electrode MCE may include a conductive metal, a metal alloy, a conductive metal oxide, or a transparent conductive material, etc. However, the present disclosure is not limited thereto.

[0121] In an embodiment, for example, each of the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, the second drain electrode DE2, and the metal pattern connection electrode MCE may have a multilayer structure. In an embodiment, for example, the multilayer structure may include a first conductive layer including titanium, a second conductive layer including aluminum, and a third conductive layer including titanium. However, the present disclosure is not limited thereto.

[0122] The sixth insulating layer IN6 may be disposed on the first source electrode SE1, the second source electrode SE2, the first drain electrode DE1, the second drain electrode DE2, and the metal pattern connection electrode MCE. The sixth insulating layer IN6 may provide a flat top surface. The sixth insulating layer IN6 is also referred to as a "first planarization layer" or a "first via insulating layer".

[0123] In an embodiment, for example, the sixth insulating layer IN6 may include an organic insulating material. In an embodiment, for example, the organic insulating material may include a photoresist, a polyacrylic resin, a polyimide resin, or an acrylic resin, etc. These materials may be used alone or in any combination with each other. The sixth insulating layer IN6 may have a single-layer or multi-layer structure. However, the present disclosure is not limited thereto. In an embodiment, for example, the sixth insulating layer IN6 may include an inorganic material.

[0124] In an embodiment, the light emitting device layer EDL may be disposed on the device wiring layer DRL. The light emitting device layer EDL may include a connection electrode TCE and a light emitting device ED.

[0125] The connection electrode TCE may be disposed on the first drain electrode DE1 (or the first source electrode SE1 ). The connection electrode TCE may contact the first drain electrode DE1 (or the first source electrode SE1 ).

[0126] In an embodiment, for example, the connection electrode TCE may include a conductive metal, an alloy of metals, a conductive metal oxide, or a transparent conductive material, etc. However, the present disclosure is not limited thereto. In an alternative embodiment, the connection electrode TCE may be omitted.

[0127] The seventh insulating layer IN7 may be disposed on the connection electrode TCE. The seventh insulating layer IN7 may provide a flat top surface. The seventh insulating layer IN7 may also be referred to as a “second planarization layer” or a “second via insulating layer”.

[0128] In an embodiment, for example, the seventh insulating layer IN7 may include an organic insulating material. However, the present disclosure is not limited thereto. In an embodiment, for example, the seventh insulating layer IN7 may include an inorganic material.

[0129] In an embodiment, the light emitting device ED may be disposed on the etch stop pattern residue ESR and the second active pattern ACT2. In an embodiment, for example, the light emitting device ED may be disposed on the seventh insulating layer IN7. In an embodiment, for example, the light emitting device ED may include a first electrode EL1, a light emitting material layer OL, and a second electrode EL2.

[0130] The first electrode EL1 may be disposed on the seventh insulating layer IN7. In an embodiment, for example, the first electrode EL1 may be an anode electrode. In an embodiment, for example, the first electrode EL1 may include a conductive oxide. The conductive oxide may include indium tin oxide, indium zinc oxide, zinc oxide, indium oxide, indium gallium oxide, or aluminum zinc oxide, etc. In another embodiment, the first electrode EL1 may include a highly reflective metal. The highly reflective metal may include silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), or chromium (Cr), etc. These materials may be used alone or in any combination with each other. However, the present disclosure is not limited thereto.

[0131] The pixel defining layer PDL may be disposed on the first electrode EL1. The pixel defining layer PDL may define a pixel opening exposing a portion of a top surface of the first electrode EL1. In an embodiment, for example, the pixel defining layer PDL may include an insulating material.

[0132] The light emitting material layer OL may be disposed in the pixel opening defined by the pixel defining layer PDL. In an embodiment, for example, the light emitting material layer OL may include an organic light emitting material. The light emitting material layer OL may further include one or more functional layers. The functional layer may be a layer that helps to improve the light emitting efficiency of the light emitting device ED.

[0133] The second electrode EL2 may be disposed on the light emitting material layer OL. In an embodiment, the second electrode EL2 may be a cathode electrode. In an embodiment, for example, the second electrode EL2 may include a highly reflective metal. However, the present disclosure is not limited thereto. The positions of the anode electrode and the cathode electrode may be changed. In an embodiment, for example, the cathode electrode may include a conductive oxide.

[0134] In the above description, each of the plurality of display devices DD includes an organic light-emitting device (hereinafter, also referred to as an organic light-emitting element) ED including an organic light-emitting material, but the present disclosure is not limited thereto. In an embodiment, for example, each of the display devices DD may be a display device capable of self-luminescence, such as an organic light-emitting display panel using an organic light-emitting diode as a light-emitting element, a nano-LED display panel using a nano-LED as a light-emitting element, a quantum dot organic light-emitting display panel using an organic light-emitting diode and a quantum dot, or a quantum dot nano-LED display panel using an ultra-small light-emitting diode and a quantum dot, etc.

[0135] In another embodiment, the plurality of display devices DD may be non-emissive display devices such as liquid crystal display panels, electrophoretic display panels, or electrowetting display panels, etc. In an embodiment, for example, each of the plurality of display devices DD may further include a separate light source (eg, a backlight unit).

[0136] In addition, for ease of explanation, Figure 4 Only the layers up to the light emitting element ED are shown in FIG. Figure 5 , only the layers up to the metal pattern connection electrode MCE are shown. However, in the embodiment of the present disclosure, each of the plurality of display devices DD may further include various other layers, and the layers described above may be omitted.

[0137] In the above, only the layers up to the metal pattern connection electrode MCE connected to the third metal pattern MP3 are illustrated, but the present disclosure is not limited thereto. In an embodiment, for example, the metal pattern connection electrode MCE may be provided in the display area.

[0138] Figures 6 to 21 It is a graphic Figure 3 A cross-sectional view of a method for manufacturing a display device of the present invention. In the following, the above reference will be omitted or simplified. Figures 1 to 5 The description of the spliced ​​display device TDD overlaps with the description.

[0139] refer to Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 In embodiments, a substrate SUB including a metal pattern MP may be formed on a carrier substrate CSUB.

[0140] In an embodiment, the first base substrate BS1 may be formed on a carrier substrate CSUB. In an embodiment, the first base substrate BS1 may include or consist of a material having a flexible property. In an embodiment, for example, in order to support the first base substrate BS1, the first base substrate BS1 may be formed on a carrier substrate CSUB having a rigid property.

[0141] Before forming the first base substrate BS1, an auxiliary layer ADL may be formed on the carrier substrate CSUB. In an embodiment, for example, the auxiliary layer ADL may include a material that is easily removed by laser. The auxiliary layer ADL may include a material that is easily removed by laser. Figure 4 The light emitting device ED) is then removed from the carrier substrate CSUB to help the carrier substrate CSUB to be easily attached to the substrate (e.g., Figure 4 The substrate SUB) is separated from the material.

[0142] In an embodiment, the first base substrate BS1 may include or consist of plastic having a flexible property. In an embodiment, for example, the plastic may be polyimide. In an embodiment, for example, the first base substrate BS1 may be formed by a coating process. However, the present disclosure is not limited thereto.

[0143] like Figure 7, Figure 8 and Fig. 9 As shown in , in an embodiment, a metal pattern MP may be formed on the first base substrate BS1. In an embodiment, a first buffer layer 120 may be formed on the first base substrate BS1. For example, a hole COH may be defined to pass through the first buffer layer 120 to expose a portion of the top surface of the first base substrate BS1. The metal pattern MP may be formed on the first buffer layer 120. At this time, the metal pattern MP may contact the first base substrate BS1 through the hole COH.

[0144] The metal pattern MP may include or consist of a conductive metal material. In an embodiment, for example, the metal pattern MP may be formed by a photo process. However, the present disclosure is not limited thereto.

[0145] like Fig.10 As shown in FIG. 1 , in an embodiment, a second base substrate BS2 may be formed on the first base substrate BS1 and the metal pattern MP. Accordingly, a substrate SUB may be formed.

[0146] In an embodiment, the second base substrate BS2 may include or consist of plastic having flexible properties. In an embodiment, for example, the plastic may include polyimide. In an embodiment, for example, the second base substrate BS2 may be formed by a coating process.

[0147] However, the present disclosure is not limited thereto. In an embodiment, for example, one of the first base substrate BS1 and the second base substrate BS2 may be omitted.

[0148] In the manufacturing method of the display device according to the comparative example, after the substrate SUB is formed, the photo process may be performed. However, in the manufacturing method of the display device according to the present disclosure, after the substrate SUB is formed by etching the stop pattern, the photo process may be omitted. Figures 14 to 21 To provide an etch stop pattern (e.g., Fig.14 However, the present disclosure is not limited thereto.

[0149] refer to Fig.11 , in an embodiment, a first active pattern ACT1 may be formed on a substrate SUB.

[0150] In an embodiment, for example, the third buffer layer 200 may be formed on the substrate SUB. In an embodiment, the third buffer layer 200 may include or consist of an inorganic insulating material. In an embodiment, for example, the third buffer layer 200 may be formed by a deposition process. However, the present disclosure is not limited thereto.

[0151] In an embodiment, for example, the first active pattern ACT1 may be formed on the third buffer layer 200. For convenience of explanation, Fig.11 In the embodiment, the first active pattern ACT1 includes a first region A1, a second region A2, and a first channel region CH1 between the first region A1 and the second region A2, wherein the first active pattern ACT1 may be doped using a first gate electrode pattern GA1 described later as a mask.

[0152] In an embodiment, for example, the first active pattern ACT1 may include or consist of a silicon semiconductor. In an embodiment, for example, the first active pattern ACT1 may be formed by a deposition process (e.g., a chemical vapor deposition ("CVD") process), a crystallization process of a silicon semiconductor material (e.g., an excimer laser annealing ("ELA") process), a photo process, etc.

[0153] refer to Fig.12 , in an embodiment, a first gate electrode pattern GA1 may be formed on the first active pattern ACT1.

[0154] A first insulating layer IN1 may be formed on the first active pattern ACT1. In an embodiment, for example, the first insulating layer IN1 may include or consist of an inorganic insulating material. In an embodiment, for example, the first insulating layer IN1 may be formed by a deposition process.

[0155] In an embodiment, a first gate electrode pattern GA1 may be formed on the first insulating layer IN1. The first gate electrode pattern GA1 may overlap the first channel region CH1.

[0156] In an embodiment, for example, the first gate electrode pattern GA1 may include or consist of a metallic material. In an embodiment, for example, the first gate electrode pattern GA1 may be formed by a deposition process (eg, a sputtering process) and a photo process.

[0157] Thereafter, a doping process may be performed to form the first active pattern ACT1. Accordingly, the first channel region CH1 and the first gate electrode pattern GA1 of the first active pattern ACT1 may overlap each other. However, the present disclosure is not limited thereto.

[0158] refer to Fig.13 , the second gate electrode pattern GA2 and the first capacitor electrode pattern CEP1 may be formed on the first gate electrode pattern GA1.

[0159] In an embodiment, for example, a second insulating layer IN2 may be formed on the first gate electrode pattern GA1. In an embodiment, for example, the second insulating layer IN2 may include or consist of an inorganic insulating material. In an embodiment, for example, the second insulating layer IN2 may be formed by a deposition process. However, the present disclosure is not limited thereto.

[0160] The second gate electrode pattern GA2 and the first capacitor electrode pattern CEP1 may be formed on the second insulating layer IN2. The second gate electrode pattern GA2 and the first capacitor electrode pattern CEP1 may be spaced apart from each other in the second direction DR2.

[0161] In an embodiment, for example, each of the second gate electrode pattern GA2 and the first capacitor electrode pattern CEP1 may include or consist of a metal material. In an embodiment, for example, each of the second gate electrode pattern GA2 and the first capacitor electrode pattern CEP1 may be formed by a deposition process (e.g., a sputtering process) and a photo process. However, the present disclosure is not limited thereto.

[0162] refer to Fig.14 In an embodiment, an etch stop pattern ES may be formed on the first capacitor electrode pattern CEP1, and a second active pattern ACT2 may be formed on the second gate electrode pattern GA2.

[0163] In an embodiment, a third insulating layer IN3 may be formed on the second gate electrode pattern GA2 and the first capacitor electrode pattern CEP1. In an embodiment, the third insulating layer IN3 may include or consist of an inorganic insulating material. In an embodiment, for example, the third insulating layer IN3 may be formed by a deposition process. However, the present disclosure is not limited thereto.

[0164] In an embodiment, a second active pattern ACT2 and an etch stop pattern ES may be formed on the third insulating layer IN3. In an embodiment, the etch stop pattern ES may be formed to overlap the first area A1 and the second area A2 of the first active pattern ACT1. The second active pattern ACT2 may be spaced apart from the etch stop pattern ES in the second direction DR2. The second active pattern ACT2 may include a third area A3, a fourth area A4, and a second channel area CH2 disposed between the third area A3 and the fourth area A4.

[0165] In an embodiment, the first active pattern ACT1 and the second active pattern ACT2 may include materials different from each other. As described above, the first active pattern ACT1 may include or consist of a silicon semiconductor. The second active pattern ACT2 may include or consist of an oxide semiconductor.

[0166] In an embodiment, the etch stop pattern ES and the second active pattern ACT2 may be formed simultaneously. In this case, the etch stop pattern ES and the second active pattern ACT2 may include the same oxide semiconductor.

[0167] In an embodiment, the second active pattern ACT2 and the etch stop pattern ES may include or consist of an IGZO material. In an embodiment, for example, the second active pattern ACT2 and the etch stop pattern ES may be formed by a deposition process (eg, a sputtering process) and a photo process. However, the present disclosure is not limited thereto.

[0168] refer to Fig.15 , a third gate electrode pattern GA3 may be formed on the second active pattern ACT2 and the etch stop pattern ES. The third gate electrode pattern GA3 may be formed to overlap a portion of the second active pattern ACT2.

[0169] In an embodiment, a fourth insulating layer IN4 may be formed on the second active pattern ACT2 and the etch stop pattern ES. In an embodiment, for example, the fourth insulating layer IN4 may include or consist of an inorganic insulating material. In an embodiment, for example, the fourth insulating layer IN4 may be formed by a deposition process. However, the present disclosure is not limited thereto.

[0170] A third gate electrode pattern GA3 may be formed on the fourth insulating layer IN4. In an embodiment, for example, the third gate electrode pattern GA3 may include or consist of a metal material. In an embodiment, for example, the third gate electrode pattern GA3 may be formed by a deposition process (for example, a sputtering process) and a photo process. However, the present invention is not limited thereto.

[0171] refer to Fig.16 In an embodiment, an interlayer insulating layer covering the etch stop pattern ES may be formed. In an embodiment, for example, the interlayer insulating layer may refer to a fifth insulating layer IN5.

[0172] In an embodiment, for example, a fifth insulating layer IN5 may be formed on the third gate electrode pattern GA3. In an embodiment, for example, the fifth insulating layer IN5 may include or consist of an inorganic insulating material. In an embodiment, for example, the fifth insulating layer IN5 may be formed by a deposition process. However, the present disclosure is not limited thereto.

[0173] In an embodiment, the etching rate of the first insulating layer IN1, the etching rate of the second insulating layer IN2, the etching rate of the third insulating layer IN3, the etching rate of the fourth insulating layer IN4, and the etching rate of the fifth insulating layer IN5 may be greater than the etching stop pattern (eg, Fig.17 The etching rate of the etching stop pattern ES).

[0174] In an embodiment, when the first to fifth insulating layers (IN1, IN2, IN3, IN4 and IN5) may include an inorganic material, an etching selectivity ratio between at least one of the first to fifth insulating layers IN1, IN2, IN3, IN4 and IN5 and the etching stop pattern may be about 15:1 or greater.

[0175] In an embodiment, when the first to fifth insulating layers IN1, IN2, IN3, IN4 and IN5 may include an organic material, an etching selectivity ratio between at least one of the first to fifth insulating layers IN1, IN2, IN3, IN4 and IN5 and the etching stop pattern may be about 1000:1 or greater.

[0176] As described above, when the etching selectivity ratio between the insulating layer and the etch stop pattern is less than the above numerical range, it may be difficult to simultaneously form the contact holes exposing the top surfaces of the metal pattern MP and the first active pattern ACT1 .

[0177] refer to Fig.17 , Fig.18 and Fig.19 By the process of defining the first contact hole, the first hole OS1, the second hole OS2, the third hole OS3, the fourth hole OS4 and the fifth hole OS5 may be formed. In the embodiment, for example, the process of defining the first contact hole may be a dry etching process.

[0178] like Fig.17 As shown in FIG. 1 , in an embodiment, a process of defining a first contact hole may start by defining a first hole OS1 and a second hole OS2 together. The first hole OS1 and the second hole OS2 may penetrate the fourth insulating layer IN4 and the fifth insulating layer IN5 .

[0179] The first hole OS1 may expose the etch stop pattern ES. The second hole OS2 may expose the interlayer insulating layer. The first hole OS1 and the second hole OS2 may be defined together. In an embodiment, for example, the interlayer insulating layer may be a third insulating layer IN3. However, the present disclosure is not limited thereto.

[0180] like Fig.18 As shown in FIG. 1 , in an embodiment, a third hole OS3 extending from the second hole OS2 and exposing the top surface of the substrate SUB may be defined. In an embodiment, the third hole OS3 may expose the top surface of the second base substrate BS2.

[0181] In an embodiment, an etch rate of the etch stop pattern ES is determined by insulating layers (eg, first, second, and third insulating layers IN1 , IN2 , and IN3 ) disposed under the etch stop pattern ES.

[0182] When loss occurs in the etch stop pattern ES, the etching time of the etch stop pattern ES may be adjusted. In an embodiment, for example, the etching time may be adjusted by adjusting the etching power.

[0183] While a portion of the insulating layer is etched, the etch stop pattern ES may remain, or only a relatively small amount of the etch stop pattern ES may be etched. In an embodiment, for example, the etch stop pattern ES may remain until a portion of the top surface of the second base substrate BS2 is exposed.

[0184] like Fig.19 As shown in , in an embodiment, the process of defining the first contact hole may be completed by defining the fourth hole OS4 and the fifth hole OS5.

[0185] The fourth hole OS4 may extend from the first hole OS1 and may penetrate the etch stop pattern ES, the first insulating layer IN1, the second insulating layer IN2, and the third insulating layer IN3. Accordingly, the top surface of the first active pattern ACT1 may be exposed. During the process of defining the fourth hole OS4, the etch stop pattern residue ESR may remain.

[0186] The fifth hole OS5 may extend from the third hole OS3, and may penetrate the second base substrate BS2 and the second buffer layer 140. Accordingly, a top surface of the metal pattern (eg, the third metal pattern MP3) may be exposed.

[0187] In an embodiment, a fourth hole OS4 may be defined in the first portion PA1. The first portion PA1 may be Figure 2 In an embodiment, a fifth hole OS5 may be defined in the second portion PA2. The second portion PA2 may correspond to the display area DA. Figure 2 The non-display area NA corresponds to the non-display area NA. Accordingly, the power supply voltage can be supplied through the pad (for example, the pad set in the non-display area NA) and the line set in the fifth hole OS5. By receiving the power supply voltage from four directions, the brightness deviation can be improved, and the power consumption can be improved.

[0188] In the process of defining the first contact hole, the first hole OS1, the second hole OS2, the third hole OS3, the fourth hole OS4 and the fifth hole OS5 may be defined together. Accordingly, the efficiency of the manufacturing process of the display device may be improved. In addition, after forming the substrate SUB, by defining the first hole OS1, the second hole OS2, the third hole OS3, the fourth hole OS4 and the fifth hole OS5 using one mask, the manufacturing cost may be reduced.

[0189] refer to Fig.19 , Fig. 20 and Fig.21 In an embodiment, a light emitting device ED may be formed on the metal pattern connection electrode MCE. After the light emitting device ED is formed, the carrier substrate CSUB may be removed.

[0190] In an embodiment, for example, Fig. 20 Only shown Fig.19 The first part PA1, and Fig.21 Only shown Fig.19 The second part of PA2. Fig.19 The first part PA1 can be connected with Figure 2 corresponds to the display area DA, and Fig. 20 The second part PA2 can be used with Figure 2 Corresponding to the non-display area NA.

[0191] like Fig.19 and Fig. 20 As shown in , the first source electrode SE1 and the first drain electrode DE1 may be formed to fill the first hole OS1 and the fourth hole OS4 .

[0192] In an embodiment, for example, each of the first source electrode SE1 and the first drain electrode DE1 may include or consist of a metal material. In an embodiment, for example, each of the first source electrode SE1 and the first drain electrode DE1 may be formed by a deposition process (eg, a sputtering process) and a photo process. However, the present disclosure is not limited thereto.

[0193] like Fig.21 As shown in , the metal pattern connection electrode MCE may be formed to fill the second hole OS2 , the third hole OS3 , and the fifth hole OS5 .

[0194] In an embodiment, for example, the metal pattern connection electrode MCE may include or consist of a metal material. In an embodiment, for example, the metal pattern connection electrode MCE may be formed by a deposition process (eg, a sputtering process) and a photo process. However, the present disclosure is not limited thereto.

[0195] After the process of defining the first contact holes (e.g., the first hole OS1, the second hole OS2, the third hole OS3, the fourth hole OS4, and the fifth hole OS5), a secondary contact hole forming process may be performed. Through the secondary contact hole forming process, the second source electrode and the second drain electrode (e.g., Fig. 20 The second source electrode SE2 and the second drain electrode DE2) are connected to the second active pattern ACT2.

[0196] Return to reference Fig. 20 , a first source electrode SE1, a first drain electrode DE1, a second source electrode SE2, a second drain electrode DE2, and a metal pattern connection electrode MCE may be formed on the fifth insulating layer IN5. In an embodiment, a sixth insulating layer IN6 may be formed on the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, the second drain electrode DE2, and the metal pattern connection electrode MCE. For example, the sixth insulating layer IN6 may include or consist of an inorganic insulating material. In an embodiment, for example, the sixth insulating layer IN6 may be formed by a deposition process. However, the present disclosure is not limited thereto.

[0197] A connection electrode TCE may be formed on the sixth insulating layer IN6. The connection electrode TCE may be connected to the first drain electrode DE1 (or the first source electrode SE1) through a contact hole penetrating the sixth insulating layer IN6. In an embodiment, for example, the connection electrode TCE may include or consist of a metal material. In an embodiment, for example, the connection electrode TCE may be formed by a deposition process (for example, a sputtering process) and a photo process. However, the present disclosure is not limited thereto.

[0198] A seventh insulating layer IN7 may be formed on the connection electrode TCE. In an embodiment, for example, the seventh insulating layer IN7 may include or consist of an inorganic insulating material. In an embodiment, for example, the seventh insulating layer IN7 may be formed by a deposition process. However, the present disclosure is not limited thereto.

[0199] In an embodiment, a first electrode EL1, a light emitting material layer OL, and a second electrode EL2 may be sequentially formed on the seventh insulating layer IN7. Accordingly, a light emitting device layer EDL including a light emitting device ED may be formed.

[0200] The first electrode EL1 may be formed on the seventh insulating layer IN7. In an embodiment, for example, the first electrode EL1 may include or consist of a metal material. In an embodiment, for example, the first electrode EL1 may be formed by a deposition process (eg, a sputtering process) and a photo process. However, the present disclosure is not limited thereto.

[0201] A pixel defining layer PDL may be formed on the first electrode EL1 . The pixel defining layer PDL may define a pixel opening exposing a portion of a top surface of the first electrode EL1 .

[0202] The light emitting material layer OL may be formed in the pixel opening defined by the pixel defining layer PDL. In an embodiment, for example, the light emitting material layer OL may be formed by an inkjet process. However, the present disclosure is not limited thereto. In an embodiment, the light emitting material layer OL may be formed by various processes such as a patterning process.

[0203] The second electrode EL2 may be formed on the light emitting material layer OL. In an embodiment, for example, the second electrode EL2 may include or consist of a metal material. In an embodiment, for example, the second electrode EL2 may be formed by a deposition process (eg, a sputtering process) and a photo process. However, the present disclosure is not limited thereto.

[0204] In an embodiment, after the light emitting device layer EDL is formed, the carrier substrate CSUB may be removed. In an embodiment, for example, the carrier substrate CSUB may be separated from the substrate SUB by a laser lift off ("LLO") process.

[0205] In an embodiment, for example, the physical properties of the auxiliary layer ADL may be changed by laser. Due to the change in the physical properties, the auxiliary layer ADL may easily separate the carrier substrate CSUB from the substrate SUB. However, the present disclosure is not limited thereto.

[0206] The manufacturing method of the display device in the embodiment of the present disclosure and the display device manufactured by the method can be applied to computers (e.g., laptop computers), mobile phones, smart phones, smart tablets, portable multimedia players ("PMP"), personal digital assistants ("PDA") or MP3 players, etc.

[0207] The present disclosure should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure thorough and complete, and to fully convey the concept of the present invention to those skilled in the art. Although the present invention has been specifically shown and described with reference to the embodiments of the present invention, it will be appreciated by those of ordinary skill in the art that various changes in form and detail may be made thereto without departing from the spirit and scope of the present invention as defined by the claims.

Claims

1. A method for manufacturing a display device, the method comprising: preparing a substrate including a metal pattern and defining a display area and a non-display area therein; forming a first active pattern disposed on the substrate and including a first region, a second region, and a first channel region disposed between the first region and the second region; forming a first gate electrode pattern overlapping the first channel region on the first active pattern; forming a second active pattern on the first gate electrode pattern; forming an etch stop pattern in the same layer as the second active pattern and overlapping the first region and the second region of the first active pattern; forming an interlayer insulating layer covering the etch stop pattern; defining a first hole exposing the etch stop pattern and a second hole penetrating the interlayer insulating layer; defining a third hole extending from the second hole and exposing a top surface of the substrate; defining a fourth hole extending from the first hole and penetrating the etch stop pattern and a fifth hole extending from the third hole and exposing the metal pattern; forming a metal pattern connection electrode disposed on the metal pattern and connected to the metal pattern through the fifth hole; as well as A light emitting device is formed on the metal pattern connection electrode.

2. The method according to claim 1, wherein: The preparation of the substrate includes: forming a first base substrate on a carrier substrate; forming the metal pattern on the first base substrate; and A second base substrate is formed on the first base substrate and the metal pattern.

3. The method according to claim 2, wherein: The third hole exposes a top surface of the second base substrate.

4. The method according to claim 2, wherein: The first base substrate and the second base substrate include polyimide.

5. The method according to claim 1, further comprising: After forming the first active pattern, forming a first insulating layer covering the first active pattern; as well as After forming the first gate electrode pattern, forming a second insulating layer covering the first gate electrode pattern, The etching rate of the first insulating layer, the etching rate of the second insulating layer and the etching rate of the interlayer insulating layer are greater than the etching rate of the etching stop pattern.

6. The method according to claim 5, wherein: When each of the first insulating layer, the second insulating layer and the interlayer insulating layer includes an inorganic material, an etching selectivity ratio between at least one of the first insulating layer, the second insulating layer and the interlayer insulating layer including the inorganic material and the etching stop pattern is 15:1 or greater.

7. The method according to claim 5, wherein: When each of the first insulating layer, the second insulating layer and the interlayer insulating layer includes an organic material, an etching selectivity ratio between at least one of the first insulating layer, the second insulating layer and the interlayer insulating layer including the organic material and the etching stop pattern is 1000:1 or greater.

8. The method according to any one of claims 1 to 7, wherein: The etch stop pattern and the second active pattern are formed simultaneously.

9. The method according to claim 8, wherein: The etch stop pattern and the second active pattern include the same oxide semiconductor.

10. The method according to claim 9, wherein: The etch stop pattern and the second active pattern include indium gallium zinc oxide.

Images