Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to the field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: an interposer including deep trench capacitor arrays and isolation structures disposed between the deep trench capacitor arrays; wherein the deep groove capacitor array comprises a plurality of deep groove capacitors, and the isolation structure at least partially surrounds the deep groove capacitor on the outermost edge side of the deep groove capacitor array.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor technology, packaging different types of chips together through an interposer has gradually become a trend in packaging technology. In related technologies, a deep trench capacitor (DTC) is usually provided in the interposer as a decoupling capacitor to reduce signal noise and leakage between adjacent semiconductor devices coupled to the interposer.

[0003] However, since the deep trench capacitor array on the interposer does not have an isolation structure, the deep trench capacitor array has a large keep-out zone (KOZ). There is a large parasitic capacitance between the deep trench capacitor array and other devices on the interposer, which can easily interfere with other devices. Summary of the invention

[0004] In view of this, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same in order to solve the technical problems existing in the background technology.

[0005] An embodiment of the present disclosure provides a semiconductor structure, comprising: an interposer, the interposer comprising a deep trench capacitor array and an isolation structure arranged between the deep trench capacitor arrays; wherein the deep trench capacitor array comprises a plurality of deep trench capacitors, and the isolation structure at least partially surrounds the deep trench capacitors at the outermost side of the deep trench capacitor array.

[0006] In some embodiments, the deep trench capacitor includes: a first electrode layer, a capacitor dielectric layer, a second electrode layer and a conductive layer; wherein the first electrode layer covers the inner wall of the deep trench in the intermediate layer and extends to the upper surface of the intermediate layer; the capacitor dielectric layer covers the first electrode layer; the second electrode layer covers the capacitor dielectric layer; and the conductive layer covers the second electrode layer.

[0007] In some embodiments, the isolation structure includes a first isolation structure, an isolation trench is provided in the interlayer between the deep trench capacitor arrays, and the first isolation structure is located in the isolation trench; for one of the deep trench capacitor arrays, on the side away from the first isolation structure, the ends of the first electrode layer, the capacitor dielectric layer, the second electrode layer and the conductive layer of the deep trench capacitor on the outermost side located on the upper surface of the interlayer completely overlap; on the side close to the first isolation structure, the deep trench capacitor on the outermost side exposes a portion of the first electrode layer, the ends of the capacitor dielectric layer, the second electrode layer and the conductive layer of the deep trench capacitor on the outermost side located on the upper surface of the interlayer completely overlap, and the remaining portion of the first electrode layer located on the upper surface of the interlayer is covered by the capacitor dielectric layer.

[0008] In some embodiments, the semiconductor structure further includes a dielectric material layer, wherein the dielectric material layer covers the conductive layer in the deep trench and completely fills the deep trench.

[0009] In some embodiments, the semiconductor structure further includes an insulating layer, the insulating layer is located between the deep trench capacitor array and the intermediate layer, and is exposed on the intermediate layer on a side of the deep trench capacitors at the outermost side away from the first isolation structure.

[0010] In some embodiments, the isolation structure further includes a second isolation structure, and the second isolation structure covers the deep trench capacitor array, the first isolation structure, and the exposed insulating layer.

[0011] In some embodiments, in a cross section perpendicular to a first direction, the cross section of the first isolation structure is rectangular, trapezoidal, inverted trapezoidal or elliptical; the first direction is perpendicular to the vertical direction.

[0012] In some embodiments, the isolation trench has an aspect ratio of 2-10.

[0013] In some embodiments, projections of the plurality of deep trench capacitors on the upper surface of the interposer along the vertical direction are arranged in a regular hexagonal shape.

[0014] The disclosed embodiment also provides a method for manufacturing a semiconductor structure, comprising: providing an interposer; forming an initial deep trench capacitor array structure in the interposer, the initial deep trench capacitor array structure comprising a plurality of initial deep trench capacitor structures; etching the initial deep trench capacitor array structure for a first time, exposing a first electrode layer at the periphery of the initial deep trench capacitor structure at the outermost edge of the initial deep trench capacitor array structure to form an intermediate deep trench capacitor array structure; etching the intermediate deep trench capacitor array structure for a second time, etching the exposed first electrode layer away from the side of the initial deep trench capacitor structure at the outermost edge to form an isolation trench, and cutting off adjacent capacitor units in the intermediate deep trench capacitor array structure to form a deep trench capacitor array, the isolation trench being located in the interposer between the deep trench capacitor arrays; filling the isolation trench with isolation material to form an isolation structure; the isolation structure at least partially surrounds the deep trench capacitor at the outermost edge of the deep trench capacitor array.

[0015] In some embodiments, an initial deep trench capacitor array structure is formed in the interposer, comprising: forming a deep trench array in the interposer, the deep trench array comprising a plurality of deep trenches; depositing insulating material on the upper surface of the interposer and in the deep trenches to form an insulating layer, the insulating layer covering the inner walls of the deep trenches and extending to the upper surface of the interposer; depositing the first electrode layer, the capacitor dielectric layer, the second electrode layer and the conductive layer in sequence on the insulating layer to form the initial deep trench capacitor array structure; wherein the first electrode layer covers the insulating material layer; the capacitor dielectric layer covers the first electrode layer; the second electrode layer covers the capacitor dielectric layer; and the conductive layer covers the second electrode layer.

[0016] In some embodiments, after forming an initial deep trench capacitor array structure in the interposer, the method further includes: depositing a dielectric material on the conductive layer, the dielectric material covering the conductive layer in the deep trench and completely filling the deep trench to form a dielectric material layer.

[0017] In some embodiments, the initial deep trench capacitor array structure is etched for the first time, including: forming a patterned first mask layer on the initial deep trench capacitor array structure; etching the initial deep trench capacitor array structure for the first time according to the patterned first mask layer, forming a first trench around the initial deep trench capacitor structure at the outermost side of the initial deep trench capacitor array structure, the first trench exposing the first electrode layer; and the remaining initial deep trench capacitor array structure serves as the intermediate deep trench capacitor array structure.

[0018] In some embodiments, the intermediate deep trench capacitor array structure is etched a second time, including: forming a patterned second mask layer on the intermediate deep trench capacitor array structure; etching the intermediate deep trench capacitor array structure a second time according to the patterned second mask layer to form the isolation trench on a side of the first trench away from the initial deep trench capacitor structure on the outermost side; and cutting off adjacent capacitor units in the intermediate deep trench capacitor array structure to expose part of the insulating layer; the isolation trench extends into the intermediate layer; and the remaining intermediate deep trench capacitor array structure serves as the deep trench capacitor array.

[0019] In some embodiments, an isolation material is filled in the isolation trench to form an isolation structure, including: depositing an isolation material on an interposer having the deep trench capacitor array formed thereon, wherein a portion of the isolation material fills the isolation trench to form a first isolation structure; a portion of the isolation material covers the deep trench capacitor array, the first isolation structure and the exposed insulating layer to form a second isolation structure, wherein the first isolation structure and the second isolation structure constitute an isolation structure.

[0020] It can be seen that the embodiment of the present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: an interposer, the interposer includes a deep trench capacitor array and an isolation structure disposed between the deep trench capacitor arrays; the deep trench capacitor array includes a plurality of deep trench capacitors, and the isolation structure at least partially surrounds the deep trench capacitors at the edge of the deep trench capacitor array.

[0021] In the disclosed embodiment, an isolation structure is provided between the deep trench capacitor arrays, and the isolation structure at least partially surrounds the deep trench capacitors at the outermost side of the deep trench capacitor arrays. Thus, the deep trench capacitor arrays can be isolated from other devices located on the interposer, which is beneficial for reducing the parasitic capacitance between the deep trench capacitor arrays and other devices on the interposer, thereby reducing the interference caused by the deep trench capacitor arrays to other devices and improving the electrical performance of the semiconductor structure.

[0022] The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1A vertical cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure Figure 1 ;

[0025] Figure 2 A schematic top view of a semiconductor structure provided by an embodiment of the present disclosure;

[0026] Figure 3 for Figure 2 An enlarged schematic diagram of the dotted box area in FIG.

[0027] Figure 4 A microscopic image of a semiconductor structure provided by an embodiment of the present disclosure;

[0028] Figure 5 A vertical cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure Figure 2 ;

[0029] Figure 6 A schematic diagram of a process for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0030] Figure 7 A schematic diagram of the structure of the semiconductor structure provided in the embodiment of the present disclosure during the manufacturing process Figure 1 ;

[0031] Figure 8 A schematic diagram of the structure of the semiconductor structure provided in the embodiment of the present disclosure during the manufacturing process Figure 2 ;

[0032] Fig. 9 A schematic diagram of the structure of the semiconductor structure provided in the embodiment of the present disclosure during the manufacturing process Figure 3 ;

[0033] Fig.10 A schematic diagram of the structure of the semiconductor structure provided in the embodiment of the present disclosure during the manufacturing process Figure 4 ;

[0034] Fig.11 A schematic diagram of the structure of the semiconductor structure provided in the embodiment of the present disclosure during the manufacturing process Figure 5 ;

[0035] Fig.12 A schematic diagram of the structure of the semiconductor structure provided in the embodiment of the present disclosure during the manufacturing process Figure 6 ;

[0036] Fig.13 A schematic diagram of the structure of the semiconductor structure provided in the embodiment of the present disclosure during the manufacturing process Figure 7 ;

[0037] Fig.14 A schematic diagram of the structure of the semiconductor structure provided in the embodiment of the present disclosure during the manufacturing process Figure 8 ;

[0038] Fig.15 A schematic diagram of the structure of the semiconductor structure provided in the embodiment of the present disclosure during the manufacturing process Figure 9 ;

[0039] Fig.16 Structural diagram of semiconductor structure during manufacturing process provided for related technologies Figure 1 ;

[0040] Fig.17 Structural diagram of semiconductor structure during manufacturing process provided for related technologies Figure 2 ;

[0041] Fig.18 Structural diagram of semiconductor structure during manufacturing process provided for related technologies Figure 3 ;

[0042] Fig.19 Structural diagram of semiconductor structure during manufacturing process provided for related technologies Figure 4 ;

[0043] Fig. 20 Structural diagram of semiconductor structure during manufacturing process provided for related technologies Figure 5 ;

[0044] Fig.21 Structural diagram of semiconductor structure during manufacturing process provided for related technologies Figure 6 ;

[0045] Fig. 22 Structural diagram of semiconductor structure during manufacturing process provided for related technologies Figure 7 ;

[0046] Fig.23 Structural diagram of semiconductor structure during manufacturing process provided for related technologies Figure 8 ;

[0047] Fig.24 Structural diagram of semiconductor structure during manufacturing process provided for related technologies Figure 9 . DETAILED DESCRIPTION

[0048] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0049] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0050] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0051] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0052] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0053] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "composition" and / or "comprising" when used in this specification determine the existence of the features, integers, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items. All numerical ranges herein include endpoint values.

[0054] With the development of semiconductor technology, traditional two-dimensional packaging can no longer meet the needs of the industry. Therefore, vertical interconnection stacking packaging based on through silicon via technology (TSV) is to package different types of chips together through a silicon interposer. This packaging method has the key technical advantages of short-distance interconnection and high-density integration, and has gradually led the development of packaging technology.

[0055] In the related art, a deep trench capacitor (DTC) is usually provided in the interposer as a decoupling capacitor to reduce signal noise and leakage between adjacent semiconductor devices coupled to the interposer. However, since the deep trench capacitor array on the interposer does not have an isolation structure, the deep trench capacitor array has a large exclusion area (the exclusion area refers to the area where no circuit elements such as transistors are arranged around the deep trench capacitor array), and there is a large parasitic capacitance between the deep trench capacitor array and other devices on the interposer (including between the deep trench capacitor array and the deep trench capacitor array), which is easy to cause interference to other devices.

[0056] Based on this, the present disclosure proposes the following technical solutions:

[0057] The present disclosure provides a semiconductor structure, Figure 1 A vertical cross-sectional schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure; Figure 2 A schematic top view of a semiconductor structure provided in an embodiment of the present disclosure; Figure 3 For attachment Figure 2 Enlarged schematic diagram of the dotted box area.

[0058] See attached Figure 1 The semiconductor structure includes: an interposer 10, the interposer 10 includes a deep trench capacitor array 11 (such as the attached Figure 2 as shown) and an isolation structure 12 disposed between the deep trench capacitor arrays 11.

[0059] The deep trench capacitor array 11 includes a plurality of deep trench capacitors 110 , and the isolation structure 12 at least partially surrounds the deep trench capacitors 110 at the outermost side of the deep trench capacitor array 11 (ie, the periphery of the deep trench capacitor array).

[0060] It should be noted that the attached Figure 1 The first direction x and the Figure 2 The vertical direction z shown is the direction perpendicular to the paper surface. Figure 1 Only the positional relationship between the deep trench capacitor 110 at the edge of the deep trench capacitor array 11 and the isolation structure 12 is shown, and no further description will be given later.

[0061] In the embodiments of the present disclosure, see the attached Figure 1 , the interposer 10 is a conduit for transmitting electrical signals among multiple chips in the package. The interposer 10 can realize the interconnection between chips, and can also realize the interconnection with the package substrate, acting as a bridge between multiple bare chips and circuit boards. For example, the interposer 10 can connect memory chips (e.g., dynamic random access memory (DRAM)) and logic chips (e.g., central processing unit (CPU), graphics processing unit (GPU)). The material of the interposer 10 can be silicon, polysilicon, germanium, silicon germanium, silicon carbide and other materials.

[0062] In some embodiments of the present disclosure, see the attached Figure 2 , the projections of the multiple deep trench capacitors 110 on the upper surface of the interposer 10 along the vertical direction z are arranged in a regular hexagon. Specifically, the projections of the six adjacent deep trench capacitors 110 on the plane of the interposer 10 are arranged in a regular hexagon, each vertex of the regular hexagon is provided with a deep trench capacitor 110, and the center of the regular hexagon is provided with a deep trench capacitor 110. In other words, the arrangement of the deep trench capacitors 110 is a hexagonal closet packed structure (HCP).

[0063] It is understandable that the arrangement of the multiple deep trench capacitors 110 is a hexagonal closest packing structure, which can obtain a closely arranged deep trench capacitor array 11 , thereby increasing the capacitance value of the deep trench capacitor array 11 .

[0064] In some embodiments of the present disclosure, see the attached Figure 1 The deep trench capacitor 110 includes: a first electrode layer 111, a capacitor dielectric layer 112, a second electrode layer 113 and a conductive layer 114; wherein the first electrode layer 111 covers the inner wall of the deep trench T0 in the intermediate layer 10 and extends to the upper surface of the intermediate layer 10; the capacitor dielectric layer 112 covers the first electrode layer 111; the second electrode layer 113 covers the capacitor dielectric layer 112; and the conductive layer 114 covers the second electrode layer 113.

[0065] In some other embodiments, the deep trench capacitor may include a plurality of electrode layers and a plurality of capacitor dielectric layers that are alternately stacked, for example, the deep trench capacitor may be a double-sided deep trench capacitor, so that the capacitance value of the deep trench capacitor may be increased.

[0066] It should be noted that the deep trench T0 refers to the trench where the deep trench capacitor 110 is located in the interposer 10 , and the deep trench T0 has a high aspect ratio. For example, the aspect ratio of the deep trench T0 may be 10, 15 or 20.

[0067] In the embodiments of the present disclosure, see the attached Figure 1 , the materials of the first electrode layer 111, the second electrode layer 113 and the conductive layer 114 can be at least one of doped silicon, polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride and other conductive materials. Specifically, the materials of the first electrode layer 111 and the second electrode layer 113 are titanium nitride, and the material of the conductive layer 114 is polysilicon. The material of the capacitor dielectric layer 112 can be at least one of insulating materials such as aluminum oxide (Al2O3) and zirconium oxide (ZrO). The capacitor dielectric layer 112 can also include other insulating materials with a relatively high dielectric constant (high-k), such as a material with a dielectric constant greater than 3.9.

[0068] In the embodiments of the present disclosure, see the attached Figure 1 , the isolation structure 12 at least partially surrounds the deep trench capacitor 110 at the outermost side of the deep trench capacitor array 11. That is, the isolation structure 12 may partially surround the deep trench capacitor 110 at the outermost side of the deep trench capacitor array 11, or may completely surround the deep trench capacitor 110 at the outermost side of the deep trench capacitor array 11. Below, the isolation structure 12 completely surrounds the deep trench capacitor 110 at the outermost side of the deep trench capacitor array 11 as an example for description.

[0069] In some embodiments of the present disclosure, see the attached Figure 1 The isolation structure 12 includes a first isolation structure 13 . An isolation trench T1 is provided in the interposer 10 between the deep trench capacitor arrays 11 . The first isolation structure 13 is located in the isolation trench T1 .

[0070] In some embodiments of the present disclosure, see the attached Figure 1 The depth-to-width ratio of the isolation trench T1 is 2-10, including end value. For example, the depth-to-width ratio of the isolation trench T1 can be 2, 5, 7, or 10.

[0071] It should be noted that the size of the isolation trench T1 can be determined according to actual needs, and the main considerations include the number, size and layout of the deep trench capacitors, the capacitance value, the operating voltage, the tolerance range of the peripheral circuit, and the distance between the device to be isolated and the deep trench capacitor array, etc. For example, when the distance between the device to be isolated and the deep trench capacitor array 11 is closer, the isolation trench T1 can be set deeper and wider.

[0072] In some embodiments of the present disclosure, see the attached Figure 1 In the cross section perpendicular to the first direction x, the cross-sectional shape of the first isolation structure 13 can be a rectangle, a trapezoid, an inverted trapezoid or an ellipse; the first direction x is perpendicular to the vertical direction z. The cross-sectional shape of the first isolation structure 13 is not specifically limited here. In the following, the cross-sectional shape of the first isolation structure 13 is a rectangle as an example for description.

[0073] In the embodiments of the present disclosure, see the attached Figure 1 The material of the first isolation structure 13 may include insulating materials such as oxide, nitride or oxynitride, and the first isolation structure 13 may also adopt an oxide-nitride-oxide (ONO) stacked structure. Specifically, the material of the first isolation structure 13 is silicon oxide.

[0074] It can be understood that by providing an isolation structure between the deep trench capacitor arrays 11, and the isolation structure 12 at least partially surrounds the deep trench capacitor 110 at the outermost side of the deep trench capacitor array 11, the deep trench capacitor array 11 can be isolated from other devices located on the intermediate layer 10, which is beneficial to reduce the parasitic capacitance between the deep trench capacitor array 11 and other devices on the intermediate layer 10, thereby reducing the interference caused by the deep trench capacitor array 11 to other devices and improving the electrical performance of the semiconductor structure.

[0075] Attached Figure 4 A microscopic image of a semiconductor structure provided in an embodiment of the present disclosure.

[0076] In the embodiments of the present disclosure, see the attached Figure 4 The isolation trench T1 is located in the etching overlap region 120. Here, the etching overlap region 120 is a region where the first etching region 121 and the second etching region 122 partially overlap. The first etching region 121 and the second etching region 122 are respectively obtained by the first etching and the second etching of forming the deep trench capacitor array 11.

[0077] In the embodiments of the present disclosure, see the attached Figure 2 and attached Figure 3In the cross section perpendicular to the vertical direction z, the first etched region 121, the second etched region 122 and the etched overlap region 120 are rectangular ring structures. That is, in the cross section perpendicular to the vertical direction z, the first isolation structure 13 is a rectangular ring structure, so that the first isolation structure 13 can completely surround the deep trench capacitor 110 at the edge of the deep trench capacitor array 11.

[0078] It should be noted that the first etching area 121, the second etching area 122 and the etching overlap area 120 here refer to an area divided on the plane of the interposer 10, rather than an actual area formed when etching is performed in the interposer 10. In other words, the first etching area 121, the second etching area 122 and the etching overlap area 120 are areas occupying a part of the area on the interposer 10. No further description will be given later.

[0079] It can be understood that the etching overlap region 120 is a partially overlapping region of the first etching region 121 and the second etching region 122 respectively obtained by the first etching and the second etching to form the deep trench capacitor array 11. In other words, when preparing the first isolation structure 13, the original two photomasks required for preparing the deep trench capacitor array 11 can be used. The process of preparing the first isolation structure 13 does not require the use of a new photomask, nor does it require the addition of a new process, and its preparation process is simple and the production cost is low.

[0080] In some embodiments of the present disclosure, see the attached Figure 1 , for a deep trench capacitor array 11, on the side away from the first isolation structure 13, the ends of the first electrode layer 111, the capacitor dielectric layer 112, the second electrode layer 113 and the conductive layer 114 of the deep trench capacitor 110 at the edge side, which are located on the upper surface of the interposer 10, completely overlap;

[0081] On the side close to the first isolation structure 13, the deep trench capacitor 110 at the edge exposes a portion of the first electrode layer 111, and the ends of the capacitor dielectric layer 112, the second electrode layer 113 and the conductive layer 114 of the deep trench capacitor 110 at the edge located on the upper surface of the intermediate layer 10 completely overlap, and the remaining portion of the first electrode layer 111 located on the upper surface of the intermediate layer 10 is covered by the capacitor dielectric layer 112.

[0082] It can be understood that, on the one hand, by setting the ends of the first electrode layer 111, the capacitor dielectric layer 112, the conductive layer 114, and the second electrode layer 113 in the deep trench capacitor 110 on the interposer 10 to completely overlap or partially overlap, the uniformity of the electrode lead-out in the deep trench capacitor 110 can be improved, thereby reducing the parasitic resistance and improving the performance of the deep trench capacitor 110. On the other hand, on the side close to the first isolation structure 13, the deep trench capacitor 110 at the edge side exposes part of the first electrode layer 111, which can facilitate the subsequent electrical connection with the conductive plug.

[0083] In some embodiments of the present disclosure, see the attached Figure 1 The semiconductor structure further includes a dielectric material layer 16, which covers the conductive layer 114 in the deep trench T0 and completely fills the deep trench T0. Here, the dielectric material layer 16 can be completely filled in the deep trench T0, which can improve the situation in the related art where polysilicon is used to fill the deep trench, which easily leads to incomplete filling of the deep trench and the appearance of gaps.

[0084] In the embodiment of the present disclosure, the material of the dielectric material layer 16 can be at least one of silicon oxide, silicon nitride, and silicon oxynitride. Specifically, the material of the dielectric material layer 16 is silicon oxide.

[0085] In some embodiments of the present disclosure, see the attached Figure 1 The semiconductor structure further includes an insulating layer 15, which is located between the deep trench capacitor array 11 and the interposer 10, and is exposed on the interposer 10 on the side of the deep trench capacitor 110 at the most edge away from the first isolation structure 13. Here, the insulating layer 15 is located between the deep trench capacitor array 11 and the interposer 10 to provide electrical isolation between the deep trench capacitor 110 and the interposer 10.

[0086] In the embodiment of the present disclosure, the material of the insulating layer 15 can be at least one of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. Specifically, the material of the insulating layer 15 is silicon oxide.

[0087] Attached Figure 5 A vertical cross-sectional schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure;

[0088] In some embodiments of the present disclosure, see the attached Figure 5 The isolation structure 12 further includes a second isolation structure 14, which covers the deep trench capacitor array 11, the first isolation structure 13 and the exposed insulating layer 15. In this way, the second isolation structure 14 can isolate the deep trench capacitor array 11 from the outside world and protect the deep trench capacitor array 11.

[0089] In the embodiments of the present disclosure, see the attached Figure 5The material of the second isolation structure 14 may include oxide, nitride or oxynitride, and the second isolation structure 14 may also adopt an oxide-nitride-oxide (ONO) stacked structure. The materials of the second isolation structure 14 and the first isolation structure 13 may be the same or different. Specifically, the material of the second isolation structure 14 is silicon oxide.

[0090] The present disclosure also provides a method for manufacturing a semiconductor structure. Figure 6 A schematic diagram of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure is shown in the attached figure. Figure 6 As shown, the method comprises the following steps:

[0091] Step S101: providing an interposer 10;

[0092] Step S102: forming an initial deep trench capacitor array structure 23 in the interposer 10 , wherein the initial deep trench capacitor array structure 23 includes a plurality of initial deep trench capacitor structures 230 ;

[0093] Step S103: performing a first etching on the initial deep trench capacitor array structure 23 to expose the first electrode layer 111 at the periphery of the initial deep trench capacitor structure 230 at the outermost side of the initial deep trench capacitor array structure 23 to form an intermediate deep trench capacitor array structure 24;

[0094] Step S104: performing a second etching on the middle deep trench capacitor array structure 24, etching the side of the exposed first electrode layer 111 away from the initial deep trench capacitor structure 230 at the outermost side to form an isolation trench T1, and cutting off adjacent capacitor units in the middle deep trench capacitor array structure 24 to form a deep trench capacitor array 11, wherein the isolation trench T1 is located in the interlayer 10 between the deep trench capacitor arrays 11;

[0095] Step S105 : filling the isolation trench T1 with an isolation material to form an isolation structure 12 ; the isolation structure 12 at least partially surrounds the deep trench capacitor 110 at the outermost side of the deep trench capacitor array 11 .

[0096] Attached Figure 7 To Attachment Fig.15 FIG. 1 is a schematic diagram of the structure of the semiconductor structure of the embodiment of the present disclosure during the manufacturing process. Figure 7 To Attachment Fig.15 The manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure is further described.

[0097] First, see the attached Figure 7 To Attachment Fig.10, executing step S101 : providing an interposer 10 ; executing step S102 : forming an initial deep trench capacitor array structure 23 in the interposer 10 , the initial deep trench capacitor array structure 23 including a plurality of initial deep trench capacitor structures 230 .

[0098] In the embodiments of the present disclosure, see the attached Figure 7 , the interposer 10 is a conduit for transmitting electrical signals among multiple chips in the package. The interposer 10 can realize the interconnection between chips, and can also realize the interconnection with the package substrate, acting as a bridge between multiple bare chips and circuit boards. For example, the interposer 10 can connect memory chips (e.g., dynamic random access memory (DRAM)) and logic chips (e.g., central processing unit (CPU), graphics processing unit (GPU)). The material of the interposer 10 can be silicon, polysilicon, germanium, silicon germanium, silicon carbide and other materials.

[0099] In some embodiments of the present disclosure, see the attached Figure 7 To Attachment Fig.10 , forming an initial deep trench capacitor array structure 23 in the interposer 10, including:

[0100] A deep trench array is formed in the interposer 10 , wherein the deep trench array includes a plurality of deep trenches T0 ;

[0101] Depositing an insulating material on the upper surface of the interposer 10 and in the deep trench T0 to form an insulating layer 15, wherein the insulating layer 15 covers the inner wall of the deep trench T0 and extends to the upper surface of the interposer 10;

[0102] A first electrode layer 111, a capacitor dielectric layer 112, a second electrode layer 113 and a conductive layer 114 are sequentially deposited on the insulating layer 15 to form an initial deep trench capacitor array structure 23; wherein the first electrode layer 111 covers the insulating material layer; the capacitor dielectric layer 112 covers the first electrode layer 111; the second electrode layer 113 covers the capacitor dielectric layer 112; and the conductive layer 114 covers the second electrode layer 113.

[0103] In the embodiment of the present disclosure, the specific steps of forming the deep trench array in the interposer 10 include forming a patterned deep trench mask layer 20 (such as the attached Figure 7 ), the interposer 10 is etched according to the patterned deep trench mask layer 20 to form a plurality of deep trenches T0 (as shown in the attached Figure 8 Here, the deep trench T0 has a high aspect ratio. For example, the aspect ratio of the deep trench T0 can be 10, 15 or 20.

[0104] In the embodiments of the present disclosure, see the attached Fig. 9The material of the insulating layer 15 can be at least one of silicon oxide, silicon nitride, and silicon oxynitride. Specifically, the material of the insulating layer 15 is silicon oxide. Here, the insulating layer 15 formed by depositing an insulating material can be used to provide electrical isolation between the interposer 10 and the deep trench capacitor formed subsequently.

[0105] In the embodiments of the present disclosure, see the attached Fig.10 , the materials of the first electrode layer 111, the second electrode layer 113 and the conductive layer 114 can be at least one of doped silicon, polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride and other conductive materials. Specifically, the materials of the first electrode layer 111 and the second electrode layer 113 are titanium nitride, and the material of the conductive layer 114 is polysilicon. The material of the capacitor dielectric layer 112 can be at least one of insulating materials such as aluminum oxide (Al2O3) and zirconium oxide (ZrO). The capacitor dielectric layer 112 can also include other insulating materials with a relatively high dielectric constant (high-k), such as a material with a dielectric constant greater than 3.9.

[0106] In the embodiment of the present disclosure, the insulating layer 15, the first electrode layer 111, the capacitor dielectric layer 112, the second electrode layer 113 and the conductive layer 114 can be deposited by one or more processes selected from the group consisting of chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

[0107] In some embodiments of the present disclosure, see the attached Fig.10 After forming the initial deep trench capacitor array structure 23 in the interposer 10 , the method further includes: depositing a dielectric material on the conductive layer 114 , the dielectric material covers the conductive layer 114 in the deep trench T0 , and completely fills the deep trench T0 to form a dielectric material layer 16 .

[0108] Here, the dielectric material layer 16 can be completely filled in the deep trench T0, which can improve the situation in the related art where polysilicon is used to fill the deep trench, which easily leads to incomplete filling of the deep trench and the presence of gaps.

[0109] In the embodiment of the present disclosure, the material of the dielectric material layer 16 can be at least one of silicon oxide, silicon nitride, and silicon oxynitride. Specifically, the material of the dielectric material layer 16 is silicon oxide.

[0110] Next, step S103 is performed: the initial deep trench capacitor array structure 23 is etched for the first time to expose the first electrode layer 111 at the periphery of the initial deep trench capacitor structure 230 at the outermost side of the initial deep trench capacitor array structure 23 to form an intermediate deep trench capacitor array structure 24 .

[0111] In some embodiments of the present disclosure, see the attached Fig.11 and attached Fig.12 , performing a first etching on the initial deep trench capacitor array structure 23, including:

[0112] forming a patterned first mask layer 21 on the initial deep trench capacitor array structure 23;

[0113] According to the patterned first mask layer 21, the initial deep trench capacitor array structure 23 is etched for the first time, and a first trench T2 is formed on the periphery of the initial deep trench capacitor structure 230 at the outermost side of the initial deep trench capacitor array structure 23, and the first trench T2 exposes the first electrode layer 111; the remaining initial deep trench capacitor array structure 23 serves as the middle deep trench capacitor array structure 24. Here, part of the first electrode layer 111 is exposed through the first trench T2, which is conducive to the electrical connection with the conductive plug formed subsequently.

[0114] It should be noted that the periphery of the initial deep trench capacitor structure 230 on the outermost side of the initial deep trench capacitor array structure 23 refers to the area where the initial deep trench capacitor structure 230 is away from the side of the initial deep trench capacitor array structure 23 and is located on the upper part of the intermediate layer 10.

[0115] In the disclosed embodiment, the initial deep trench capacitor array structure 23 may be etched by plasma etching, or other dry etching processes such as reactive ion etching, sputtering etching, magnetic field enhanced reactive ion etching, reactive ion beam etching or high density plasma etching.

[0116] In the embodiments of the present disclosure, Fig.12 The initial deep trench capacitor array structure 23 is first etched through the patterned first mask layer 21 to obtain a first etched region 121 . The first trench T2 is located in the first etched region 121 .

[0117] Next, execute step S104: perform a second etching on the middle deep trench capacitor array structure 24, etch the side of the exposed first electrode layer 111 away from the edge of the initial deep trench capacitor structure 230 to form an isolation trench T1, and cut off adjacent capacitor units in the middle deep trench capacitor array structure 24 to form a deep trench capacitor array 11, and the isolation trench T1 is located in the intermediate layer 10 between the deep trench capacitor arrays 11.

[0118] In some embodiments of the present disclosure, see the attached Fig.13 and attached Fig.14 , performing a second etching on the middle deep trench capacitor array structure 24, including:

[0119] forming a patterned second mask layer 22 on the middle deep trench capacitor array structure 24;

[0120] According to the patterned second mask layer 22, the middle deep trench capacitor array structure 24 is etched for the second time to form an isolation trench T1 on the side of the initial deep trench capacitor structure 230 away from the outermost side of the first trench T2; and adjacent capacitor units in the middle deep trench capacitor array structure 24 are cut off to expose part of the insulating layer 15; the isolation trench T1 extends into the intermediate layer 10; and the remaining middle deep trench capacitor array structure 24 serves as the deep trench capacitor array 11.

[0121] It should be noted that the middle deep trench capacitor array structure 24 is etched for the second time to cut off adjacent capacitor units in the middle deep trench capacitor array structure 24 to form a deep trench capacitor array 11 including a plurality of deep trench capacitors 110. In some other embodiments, the second etching can also be used to cut off the connection between the deep trench capacitor array 11 and other devices, which is not specifically limited here.

[0122] In the embodiments of the present disclosure, see the attached Fig.13 The patterned second mask layer 22 covers part of the first trench T2, that is, the opening of the first mask used to form the patterned first mask layer 21 partially overlaps with the opening of the second mask used to form the patterned second mask layer 22. As a result, the second etched area 122 obtained by the second etching partially overlaps with the first etched area 121, forming an etched overlap area 120. See the attached Fig.14 , the isolation trench T1 is located in the etching overlap region 120 .

[0123] In the embodiment of the present disclosure, the depth-to-width ratio of the isolation trench T1 is 2-10, including end values. For example, the depth-to-width ratio of the isolation trench T1 can be 2, 5, 7, or 10.

[0124] Attached Fig.16 To Attachment Fig.24 A schematic diagram of the structure of a semiconductor structure in the manufacturing process provided for the related art. As can be seen from the figure, in the related art, the preparation steps of the deep trench capacitor array 11 are:

[0125] First, an initial capacitor structure 27 (such as the attached Fig.16 To Attachment Fig.19 Then, a patterned third mask layer 25 is formed on the initial capacitor structure 27 using a second photomask, and the initial capacitor structure 27 is etched to form an intermediate capacitor structure 28 (as shown in the attached figure). Fig. 20 , 21 Then, a patterned fourth mask layer 26 is formed on the intermediate capacitor structure 28 using a first mask, and the intermediate capacitor structure 28 is etched to expose a portion of the first electrode layer 111 located on the upper surface of the interposer 10, thereby forming a deep trench capacitor array (as shown in the attached figure). Fig. 22 , 23Finally, a protective layer 29 is formed on the deep trench capacitor array 11 (as shown in the attached figure). Fig.24 shown).

[0126] Here, the two photomasks used in the preparation of the deep trench capacitor array 11 in the present disclosure are the same as the two photomasks used in the preparation of the deep trench capacitor 110 in the related art. However, the present disclosure adjusts the opening positions of the first photomask and the second photomask so that the openings of the first photomask and the second photomask partially overlap, and can use the original two photomasks required for preparing the deep trench capacitor array 11 to etch the isolation trench T1 while preparing the deep trench capacitor array 11, for the subsequent formation of the first isolation structure 13. In this way, the trench isolation (Trench isolation) of the deep trench capacitor array 11 can be established without adding additional processes.

[0127] It can be understood that by partially overlapping the first mask and the second mask required for preparing the deep trench capacitor array 11 in the related art, the deep trench capacitor array 11 and the subsequent first isolation structure 13 are prepared using the original two masks. The process of preparing the first isolation structure 13 does not require the use of a new mask or the addition of a new process, which can simplify the process steps, save production costs, and improve production efficiency.

[0128] In addition, in the related art, when the initial capacitor structure 27 is etched twice, the electrodes in the capacitor structure are cut off first, and then the first electrode layer 111 required for connecting with the conductive plug is exposed. The openings of the photomasks used in the two etchings here do not have overlapping areas, that is, the two etchings do not have overlapping areas, and the process of cutting off the electrodes is completed by one etching.

[0129] In the two etching processes of the present disclosure, a portion of the first electrode layer 111 (such as the attached Fig.12 Then, during the second etching, the exposed portion of the first electrode layer 111 is cut off (as shown in the attached Fig.14 As shown in FIG. 1 , the first electrode layer 111 can be cut off by two-step etching, which can reduce the difficulty of the electrode cutting process.

[0130] In the embodiments of the present disclosure, see the attached Figure 2 , the projections of the multiple deep trench capacitors 110 on the upper surface of the interposer 10 along the vertical direction z are arranged in a regular hexagonal shape. In other words, the arrangement of the deep trench capacitors 110 is a hexagonal closest packing structure. In this way, a closely arranged deep trench capacitor array 11 can be obtained, thereby increasing the capacitance value of the deep trench capacitor array 11.

[0131] In the embodiments of the present disclosure, see the attached Fig.14For a deep trench capacitor array 11, on the side away from the isolation trench T1, the ends of the first electrode layer 111, the capacitor dielectric layer 112, the second electrode layer 113 and the conductive layer 114 of the deep trench capacitor 110 on the outermost side located on the upper surface of the intermediary layer 10 completely overlap; on the side close to the isolation trench T1, the deep trench capacitor 110 on the outermost side exposes part of the first electrode layer 111, and the ends of the capacitor dielectric layer 112, the second electrode layer 113 and the conductive layer 114 of the deep trench capacitor 110 on the outermost side located on the upper surface of the intermediary layer 10 completely overlap, and the remaining part of the first electrode layer 111 located on the upper surface of the intermediary layer 10 is covered by the capacitor dielectric layer 112.

[0132] It can be understood that by setting the ends of the first electrode layer 111, the capacitor dielectric layer 112, the conductive layer 114 and the second electrode layer 113 located on the intermediate layer 10 in the deep trench capacitor 110 to completely overlap or partially overlap, the uniformity of the electrode lead-out in the deep trench capacitor 110 can be improved, thereby reducing the parasitic resistance and improving the performance of the deep trench capacitor 110.

[0133] Finally, step S105 is performed: filling the isolation trench T1 with an isolation material to form an isolation structure 12 ; the isolation structure 12 at least partially surrounds the deep trench capacitor 110 at the outermost side of the deep trench capacitor array 11 .

[0134] In some embodiments of the present disclosure, see the attached Fig.15 , filling the isolation trench T1 with an isolation material to form an isolation structure 12, including:

[0135] An isolation material is deposited on the intermediate layer 10 formed with the deep trench capacitor array 11, wherein part of the isolation material fills the isolation trench T1 to form a first isolation structure 13; part of the isolation material covers the deep trench capacitor array 11, the first isolation structure 13 and the exposed insulating layer 15 to form a second isolation structure 14. The first isolation structure 13 and the second isolation structure 14 constitute an isolation structure 12.

[0136] It can be understood that by depositing the isolation material on the interposer 10 and forming the first isolation structure 13 and the second isolation structure 14 at the same time, it is helpful to simplify the process and reduce the difficulty of preparation and production cost.

[0137] In the disclosed embodiment, the isolation structure 12 may partially surround the deep trench capacitor 110 at the outermost side of the deep trench capacitor array 11 , or may completely surround the deep trench capacitor 110 at the outermost side of the deep trench capacitor array 11 .

[0138] In the embodiments of the present disclosure, see the attached Fig.15In the cross section perpendicular to the first direction x, the cross section of the first isolation structure 13 may be rectangular, trapezoidal, inverted trapezoidal or elliptical, which is not specifically limited here.

[0139] In the embodiments of the present disclosure, see the attached Fig.15 The materials of the first isolation structure 13 and the second isolation structure 14 may include oxide, nitride or oxynitride, etc. Specifically, the materials of the first isolation structure 13 and the second isolation structure 14 are silicon oxide.

[0140] It should be noted that, in some other embodiments, the first isolation structure 13 and the second isolation structure 14 may also be formed by two deposition processes, and the materials of the first isolation structure 13 and the second isolation structure 14 may be prepared by selecting different materials according to actual needs.

[0141] It should be noted that the semiconductor structure and the manufacturing method thereof provided in the embodiments of the present disclosure can be applied to DRAM structures or other semiconductor devices, and no further limitation is given here. The embodiments of the semiconductor structure provided in the present disclosure and the embodiments of the manufacturing method of the semiconductor structure belong to the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict.

[0142] The above are only preferred embodiments of the present disclosure and are not intended to limit the protection scope of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: An interposer, the interposer comprising a deep trench capacitor array and an isolation structure disposed between the deep trench capacitor arrays; wherein, The deep trench capacitor array includes a plurality of deep trench capacitors, and the isolation structure at least partially surrounds the deep trench capacitors at the outermost side of the deep trench capacitor array.

2. The semiconductor structure according to claim 1, characterized in that: The deep trench capacitor comprises: a first electrode layer, a capacitor dielectric layer, a second electrode layer and a conductive layer; wherein, The first electrode layer covers the inner wall of the deep groove in the intermediary layer and extends to the upper surface of the intermediary layer; the capacitor dielectric layer covers the first electrode layer; the second electrode layer covers the capacitor dielectric layer; and the conductive layer covers the second electrode layer.

3. The semiconductor structure according to claim 2, characterized in that: The isolation structure includes a first isolation structure, an isolation trench is provided in the intermediary layer between the deep trench capacitor arrays, and the first isolation structure is located in the isolation trench; for one of the deep trench capacitor arrays, On a side away from the first isolation structure, ends of the first electrode layer, the capacitor dielectric layer, the second electrode layer, and the conductive layer of the deep trench capacitor on the outermost side located on the upper surface of the interposer completely overlap; On the side close to the first isolation structure, the deep trench capacitor on the outermost side exposes a portion of the first electrode layer, and the ends of the capacitor dielectric layer, the second electrode layer and the conductive layer of the deep trench capacitor on the outermost side located on the upper surface of the intermediate layer completely overlap, and the remaining portion of the first electrode layer located on the upper surface of the intermediate layer is covered by the capacitor dielectric layer.

4. The semiconductor structure according to claim 3, characterized in that: The semiconductor structure further includes a dielectric material layer, wherein the dielectric material layer covers the conductive layer in the deep trench and completely fills the deep trench.

5. The semiconductor structure according to claim 4, characterized in that: The semiconductor structure further includes an insulating layer, which is located between the deep trench capacitor array and the intermediate layer, and is exposed on the intermediate layer at a side of the deep trench capacitor at the outermost side away from the first isolation structure.

6. The semiconductor structure according to claim 5, characterized in that: The isolation structure further includes a second isolation structure, which covers the deep trench capacitor array, the first isolation structure and the exposed insulating layer.

7. The semiconductor structure according to any one of claims 3 to 5, characterized in that: In a cross section perpendicular to a first direction, the cross section of the first isolation structure is in a rectangular, trapezoidal, inverted trapezoidal or elliptical shape; the first direction is perpendicular to the vertical direction.

8. The semiconductor structure according to any one of claims 3 to 5, characterized in that: The depth-to-width ratio of the isolation trench is 2-10.

9. The semiconductor structure according to any one of claims 1 to 5, characterized in that: The projections of the plurality of deep trench capacitors on the upper surface of the interposer along the vertical direction are arranged in a regular hexagon.

10. A method for manufacturing a semiconductor structure, characterized in that: include: Provide an intermediary layer; forming an initial deep trench capacitor array structure in the interposer, the initial deep trench capacitor array structure comprising a plurality of initial deep trench capacitor structures; Performing a first etching on the initial deep trench capacitor array structure to expose a first electrode layer at the periphery of the initial deep trench capacitor structure at the outermost side of the initial deep trench capacitor array structure to form an intermediate deep trench capacitor array structure; Performing a second etching on the middle deep trench capacitor array structure, etching the side of the exposed first electrode layer away from the initial deep trench capacitor structure at the edge to form an isolation trench, and cutting off adjacent capacitor units in the middle deep trench capacitor array structure to form a deep trench capacitor array, wherein the isolation trench is located in an intermediate layer between the deep trench capacitor arrays; Filling the isolation trench with isolation material to form an isolation structure; The isolation structure at least partially surrounds the deep trench capacitor at the outermost side of the deep trench capacitor array.

11. The method for manufacturing a semiconductor structure according to claim 10, characterized in that: An initial deep trench capacitor array structure is formed in the interposer, comprising: forming a deep trench array in the interposer, the deep trench array comprising a plurality of deep trenches; Depositing an insulating material on the upper surface of the interposer and in the deep trench to form an insulating layer, wherein the insulating layer covers the inner wall of the deep trench and extends to the upper surface of the interposer; The first electrode layer, capacitor dielectric layer, second electrode layer and conductive layer are sequentially deposited on the insulating layer to form the initial deep trench capacitor array structure; wherein the first electrode layer covers the insulating material layer; the capacitor dielectric layer covers the first electrode layer; the second electrode layer covers the capacitor dielectric layer; and the conductive layer covers the second electrode layer.

12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: After forming an initial deep trench capacitor array structure in the interposer, the method comprises: A dielectric material is deposited on the conductive layer, wherein the dielectric material covers the conductive layer in the deep trench and completely fills the deep trench to form a dielectric material layer.

13. The method for manufacturing a semiconductor structure according to claim 12, characterized in that: Performing a first etching on the initial deep trench capacitor array structure includes: forming a patterned first mask layer on the initial deep trench capacitor array structure; According to the patterned first mask layer, the initial deep trench capacitor array structure is etched for the first time, and a first trench is formed on the periphery of the initial deep trench capacitor structure at the outermost side of the initial deep trench capacitor array structure, and the first trench exposes the first electrode layer; the remaining initial deep trench capacitor array structure serves as the intermediate deep trench capacitor array structure.

14. The method for manufacturing a semiconductor structure according to claim 13, characterized in that: Performing a second etching on the middle deep trench capacitor array structure includes: forming a patterned second mask layer on the middle deep trench capacitor array structure; According to the patterned second mask layer, the intermediate deep trench capacitor array structure is etched for a second time to form the isolation trench on the side of the first trench away from the initial deep trench capacitor structure on the outermost side; and adjacent capacitor units in the intermediate deep trench capacitor array structure are cut off to expose part of the insulating layer; the isolation trench extends into the intermediate layer; and the remaining intermediate deep trench capacitor array structure serves as the deep trench capacitor array.

15. The method for manufacturing a semiconductor structure according to claim 14, characterized in that: Filling the isolation trench with isolation material to form an isolation structure, including: An isolation material is deposited on the interposer formed with the deep trench capacitor array, wherein part of the isolation material fills the isolation trench to form a first isolation structure; part of the isolation material covers the deep trench capacitor array, the first isolation structure and the exposed insulating layer to form a second isolation structure, and the first isolation structure and the second isolation structure constitute an isolation structure.

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