Semiconductor device and method of integrating ewlb with e-bar structure and RF antenna interposer

Abstract

A semiconductor device has an electrical component and a plurality of e-bar structures disposed adjacent to the electrical component. The antenna interposer is disposed over the first surface of the e-bar structure. A redistribution layer is formed over a second surface of the e-bar structure opposite the first surface of the e-bar structure. The redistribution layer has a conductive layer and an insulating layer formed over the conductive layer. An encapsulant is deposited over the electrical component. The antenna interposer has a first conductive layer, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the insulating layer. The second conductive layer may be arranged as a plurality of islands or in a serpentine pattern.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods for integrating an eWLB with a vertical e-bar structure and an RF antenna interposer. Background Art

[0002] Semiconductor devices are commonly found in modern electrical products. Semiconductor devices perform a wide variety of functions such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electrical devices, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor devices typically include a semiconductor die or substrate with an electrical interconnect structure, such as a redistribution layer (RDL) formed over one or more surfaces of the semiconductor die or substrate to perform necessary electrical functions. A vertical interconnect structure disposed adjacent to the semiconductor die is electrically connected to the RDL, and an encapsulant covers the vertical interconnect structure and the semiconductor die.

[0004] Semiconductor devices may require antennas for RF communications. It would be desirable to integrate antenna functionality with the vertical and horizontal interconnect features of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1a-1c illustrates a semiconductor wafer having a plurality of semiconductor dies separated by saw streets;

[0006] Figure 2a-2l The process of forming an e-bar substrate is illustrated;

[0007] Figure 3a-3c Another process of forming an e-bar substrate is illustrated;

[0008] Figures 4a-4d The process of configuring an electrical component having adjacent e-bar structures as an eWLB is illustrated;

[0009] Figure 5a-5e Another process of configuring an electrical component having adjacent e-bar structures as an eWLB is illustrated;

[0010] Figure 6a-6f The process of forming the encapsulant and RDL around the electrical components and e-bar structure is illustrated;

[0011] Figures 7a-7f A process of forming an antenna interposer is illustrated;

[0012] Figures 8a-8dThe diagram shows the integration of the eWLB with the antenna interposer;

[0013] Fig. 9 The figure shows a singulated AoP with over-molded electrical components;

[0014] Fig.10 An AoP with exposed electrical components is illustrated;

[0015] Fig.11 Illustration of AoP with partial underfill around bumps on antenna interposer;

[0016] Fig.12 illustrates an AoP with underfill between the eWLB and the antenna interposer; and

[0017] Fig.13 A printed circuit board (PCB) is illustrated with different types of packages disposed on a surface of the PCB. DETAILED DESCRIPTION

[0018] In the following description with reference to the accompanying drawings, the present invention is described in one or more embodiments, wherein the same numerals represent the same or similar elements. Although the present invention is described with respect to the best mode for achieving the purpose of the present invention, it will be appreciated by those skilled in the art that the present invention is intended to cover substitutions, modifications and equivalents that may be included in the spirit and scope of the present invention as defined by the appended claims and their equivalents, which are supported by the following disclosure and the accompanying drawings. The features shown in the figures are not necessarily drawn to scale. In the various figures, elements with similar functions are given the same reference numerals. The term "semiconductor die" as used herein refers to both the singular and plural forms of the word, and accordingly may refer to both a single semiconductor device and a plurality of semiconductor devices.

[0019] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components such as transistors and diodes have the ability to control the flow of current. Passive electrical components such as capacitors, inductors, and resistors create the relationship between voltage and current necessary to perform the circuit function.

[0020] Back-end manufacturing refers to cutting or singulating the completed wafer into individual semiconductor dies, and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. In order to singulate the semiconductor dies, the wafer is scribed and broken along the non-functional area of ​​the wafer (called saw road or scribe line). The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor dies are arranged on a package substrate, which includes pins or contact pads for interconnection with other system components. Then, the contact pads formed above the semiconductor die are connected to the contact pads in the package. Electrical connection can be achieved with a conductive layer, a bump, a columnar bump, a conductive glue, or a wire bond. A sealant or other molding material is deposited above the package to provide physical support and electrical isolation. The completed package is then inserted into the electrical system, and the functions of the semiconductor device are made available to other system components.

[0021] Figure 1a A semiconductor wafer 100 is shown having a base substrate material 102 such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or electrical components 104 are formed on the wafer 100 separated by non-active inter-die wafer regions or saw streets 106. The saw streets 106 provide a dicing area to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0022] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or inactive surface 108 and an active surface 110, wherein the active surface 110 contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuits, such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), memory, or other signal processing circuits. The semiconductor die 104 may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0023] Conductive layer 112 is formed over active surface 110 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. Conductive layer 112 may be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. Conductive layer 112 operates as a contact pad electrically connected to the circuit on active surface 110.

[0024] exist Figure 1c 1 , semiconductor wafer 100 is singulated through saw streets 106 using a saw blade or laser cutting tool 118 into individual semiconductor dies 104. Individual semiconductor dies 104 may be inspected and electrically tested to identify known good dies or known good units (KGD / KGU) after singulation.

[0025] Figure 2a A portion of a base or core layer 120 for an embedded bar (e-bar) wafer or substrate 122 is illustrated, which includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials with similar insulating and structural properties. The core layer 120 can also be a multi-layer flexible laminate, ceramic, copper clad laminate (CCL), glass, or epoxy molding compound. In another embodiment, the base core layer 120 can also be any suitable laminated interposer, PCB, wafer form, bar interposer, lead frame, or other type of substrate. The core layer 120 can include one or more laminated layers of polytetrafluoroethylene (PTFE) prepreg (prepreg), FR-4, FR-1, CEM-1, or CEM-3 combined with phenolic cotton paper, epoxy resin, resin, woven glass, matte glass, polyester fiber, and other reinforcing fibers or fabrics. Core layer 120 has a thickness T1 of 150.0 micrometers (μm), and includes a first major surface 124 and a second major surface 126 opposite to surface 124 .

[0026] exist Figure 2b In the embodiment of the present invention, a laser direct ablation (LDA) or etching process using a laser 129 is used to form an opening or via 128 in the surface 124 of the core layer 120 to a depth of about half of T1.

[0027] exist Figure 2c In the embodiment of the present invention, a conductive layer 130 is formed in the opening 128 using PVD, CVD, electrolytic plating, electroless plating process or other suitable metal deposition process. The conductive layer 130 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. Portions of the conductive layer 130 can be electrically shared or electrically isolated, depending on the design and function of the electrical components attached thereto.

[0028] exist Figure 2d In the embodiment, a conductive layer 132 is formed over the conductive layer 130 and the surface 124 of the core layer 120 using PVD, CVD, electrolytic plating, electroless plating process or other suitable metal deposition process. The conductive layer 132 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. In one embodiment, the conductive layer 132 has a thickness of 24.0+7.0 μm. Portions of the conductive layer 132 can be electrically shared or electrically isolated, depending on the design and function of the electrical components attached thereto.

[0029] An insulating or passivation layer 134 is formed over the conductive layer 132 and the surface 124 of the core layer 120 using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 134 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials with similar insulating and structural properties. In one embodiment, the insulating layer 134 has a thickness of 64.0 μm. Figure 2e In the embodiment, LDA or an etching process using a laser such as 129 is used to remove portions of insulating layer 134 to form openings or vias 138 extending to conductive layer 132 for further electrical interconnection.

[0030] exist Figure 2f In the embodiment of the present invention, a conductive layer 140 is formed in the opening 138 using PVD, CVD, electrolytic plating, electroless plating or other suitable metal deposition process. The conductive layer 140 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. Portions of the conductive layer 140 can be electrically shared or electrically isolated, depending on the design and function of the electrical components attached thereto.

[0031] exist Figure 2g In the embodiment, PVD, CVD, electrolytic plating, electroless plating process or other suitable metal deposition process is used to form a conductive layer 144 over the conductive layer 140 and the insulating layer 134. The conductive layer 144 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. The conductive layer 144 operates as a contact pad for the RDL formed later. In one embodiment, the conductive layer 144 has a thickness of 24.0+7.0 μm. The conductive layer 144 operates as a contact pad for the bump formed later. Portions of the conductive layer 144 can be electrically shared or electrically isolated, depending on the design and function of the electrical components attached thereto.

[0032] An insulating or passivation layer 146 is formed over the conductive layer 144 and the insulating layer 134 using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 146 comprises one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. In one embodiment, the insulating layer 146 has a thickness of 15.0+7.5 μm. An LDA or etching process using a laser such as 129 is used to remove portions of the insulating layer 146 to form openings or vias 148 extending to the conductive layer 144 for further electrical interconnection.

[0033] From Figure 2g The partially e-bar substrate is inverted and an opening or via 150 is formed in the surface 126 of the core layer 120 using an LDA or etching process using a laser such as 129 and extending to the conductive layer 130, such as Figure 2h As shown in .

[0034] exist Figure 2i In, similar to Figure 2c , a conductive layer 152 is formed in the opening 150. Similar to Figure 2d , a conductive layer 154 is formed over the conductive layer 152 and the surface 126 of the core layer 120. In one embodiment, the conductive layer 154 has a thickness of 24.0+7.0 μm. An insulating or passivation layer 156 is formed over the conductive layer 152 and the surface 126 of the core layer 120. In one embodiment, the insulating layer 156 has a thickness of 24.0+7.0 μm. Portions of the insulating layer 156 are removed using a laser such as 129 to form openings or vias 158 extending to the conductive layer 152 for further electrical interconnection, similar to Figure 2e .

[0035] exist Figure 2j In, similar to Figure 2f , a conductive layer 160 is formed in the opening 158. Similar to Figure 2g , a conductive layer 162 is formed over the conductive layer 160 and the insulating layer 156. Specifically, the conductive layer 162 is made to have a thickness of about 24.0+7.0 μm. The conductive layer 162 operates as a contact pad for a bump formed later. An insulating or passivation layer 164 is formed over the conductive layer 160 and the insulating layer 156. In one embodiment, the insulating layer 164 has a thickness of 15.0+7.5 μm. Portions of the insulating layer 164 are removed using a laser such as 129 to form an opening or via 167 extending to the conductive layer 162 for further electrical interconnection.

[0036] The combination of conductive layers 130, 132, 140, 144, 152, 154, 160, and 162 and core layer 120 and insulating layers 134, 146, 156, and 164 constitute an e-bar wafer or substrate 168. Conductive layers 130, 132, 140, 144, 152, 154, 160, and 162 provide vertical electrical interconnections through e-bar substrate 168. Figure 2k 1 is a top view of an e-bar substrate 168 having an array of e-bar structures 170a - 170h , as conductive layer 162 is visible through insulating layer 164 .

[0037] exist Figure 2l , a laser cutting tool or saw blade 172 is used to singulate the e-bar substrate 168, leaving individual e-bar structures 170a-170d. After singulation, each e-bar structure 170a-170d is made of conductive layers 130, 132, 140, 144, 152, 154, 160 and 162 from the e-bar substrate 168, as well as a portion of the core layer 120 and insulating layers 134, 146, 156 and 164. In one embodiment, the e-bar substrates 170a-170d have a height H1 of 420μm+35μm, depending on the substrate 120 and the package thickness. With respect to the core layer 120, the e-bar substrates 170a-170d are rigid and generally incompressible to support cover structures, such as RDLs, as described below.

[0038] In another embodiment, Figure 3a A portion of a base or core layer 180 for an e-bar wafer or substrate 182 is illustrated, which includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials with similar insulating and structural properties. The core layer 180 may also be a multilayer flexible laminate, ceramic, CCL, glass, or epoxy molding compound. In another embodiment, the base core layer 180 may also be any suitable laminated interposer, PCB, wafer form, bar interposer, lead frame, or other type of substrate. The core layer 180 may include one or more laminated layers of PTFE prepreg, FR-4, FR-1, CEM-1, or CEM-3 combined with phenolic cotton paper, epoxy resin, resin, woven glass, matte glass, polyester fiber, and other reinforcing fibers or fabrics. The core layer 180 has a thickness T2 of 150.0 μm and includes a first major surface 183 and a second major surface 184 opposite to the surface 183.

[0039] An etching process or LDA is used to form openings or vias in the surface 183 of the core layer 180. Similar to Figure 2b, the vias may extend through the core layer 180, or to a depth of about half of T2. A conductive layer 186 is formed within the opening using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition process. The conductive layer 186 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. Portions of the conductive layer 186 may be electrically shared or electrically isolated, depending on the design and function of the electrical components attached thereto. Figure 2b-2c , if half of the via is filled with conductive layer 186, the other half of the via and conductive layer 186 will be similar to Figure 2h-2i to form.

[0040] exist Figure 3b In the embodiment, a conductive layer 188 is formed over the conductive layer 186 and the surface 183 of the core layer 180 using PVD, CVD, electrolytic plating, electroless plating process or other suitable metal deposition process. The conductive layer 188 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. In one embodiment, the conductive layer 188 has a thickness of 24.0+7.0 μm. Portions of the conductive layer 188 can be electrically shared or electrically isolated, depending on the design and function of the electrical components attached thereto.

[0041] An insulating or passivation layer 190 is formed over the conductive layer 188 and the surface 183 of the core layer 180 using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 190 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. In one embodiment, the insulating layer 190 has a thickness of 64.0 μm.

[0042] Conductive layer 192 is formed over conductive layer 186 and surface 184 of core layer 180 using PVD, CVD, electrolytic plating, electroless plating process or other suitable metal deposition process. Conductive layer 192 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. In one embodiment, conductive layer 192 has a thickness of 24.0+7.0 μm. Portions of conductive layer 192 can be electrically shared or electrically isolated, depending on the design and function of the electrical components attached thereto.

[0043] An insulating or passivation layer 194 is formed over the conductive layer 192 and the surface 184 of the core layer 180 using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 194 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. In one embodiment, the insulating layer 194 has a thickness of 64.0 μm.

[0044] The combination of conductive layers 186, 188 and 192 and core layer 180 and insulating layers 190 and 194 constitutes an e-bar wafer or substrate 196. Conductive layers 186, 188 and 192 provide vertical electrical interconnections through e-bar substrate 196. A cross-sectional top view of conductive layer 186 or 188 would be similar to Figure 2k , as an array of e-bar structures.

[0045] exist Figure 3c , a laser cutting tool or saw blade 198 is used to singulate the e-bar substrate 196, leaving individual e-bar structures 200a-200d. After singulation, each e-bar structure 200a-200d is made of conductive layers 186, 188 and 192 from the e-bar substrate 196 and a portion of the core layer 180 and insulating layers 190 and 194. In one embodiment, the e-bar structures 200a-200d have a height H2 of 420μm+35μm, depending on the substrate 180 and the package thickness. With respect to the core layer 180, the e-bar structures 200a-200d are rigid and generally incompressible to support a cover structure, such as an RDL, as described below.

[0046] Figure 4a A temporary substrate or carrier 202 is shown that includes a sacrificial core material such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost rigid material for structural support. Substrate 202 has a major surface 203 and a major surface 205 opposite surface 203. In one embodiment, carrier 202 is a support structure having a temporary bonding layer 204 formed over the carrier. Temporary bonding layer 204 can be a film or foil bonded to surface 203.

[0047] Use pick and place operations to move Figure 3c The e-bar structures 200a-200d are positioned above the carrier 202. The e-bar structures 200a-200d are placed in contact with the bonding layer 204. Alternatively, the e-bar structures 170a-170d may be disposed above the bonding layer 204 and placed in contact with the bonding layer 204.

[0048] exist Figure 4bIn FIG. 2 , electrical components 206 a-206 b are disposed above a surface 203 of a substrate 202. The electrical components 206 a-206 b may be similar to those from Figure 1c or make it similar to the semiconductor die 104 from Figure 1c The semiconductor die 104 is oriented with the conductive layer 112 oriented toward the surface 203 of the substrate 202. Alternatively, the electrical components 206a-206b may include other semiconductor dies, semiconductor packages, surface mount devices, RF components, discrete electrical devices, or integrated passive devices (IPDs).

[0049] A pick and place operation is used to position the electrical components 206a-206b on the substrate 202. The electrical components 206a-206b are placed in contact with the bonding layer 204 between the e-bar structures 200a-200b and 200c-200d, respectively. Figure 4c The electrical components 206a-206b and the e-bar structures 200a-200d are illustrated joined to the substrate 202 as an assembly 207. The electrical components 206a-206b may be mounted to the substrate 202 before the e-bar structures 200a-200d. Figure 4d 2 is a top view of assembly 207 in which individual e-bar structures such as 200 a - 200 d are formed around or near the sides of electrical components 206 a - 206 b above bonding layer 204 and substrate 202 .

[0050] In another embodiment, from Figure 3b The e-bar substrate 196 is disposed above and in contact with the bonding layer 204. In this case, the e-bar structure is not singulated into a single unit, but rather remains an integral part of the e-bar substrate 196, such as Figure 5a E-bar substrate 196 may have additional e-bar structures such as 200a-2001 such that they are similar to e-bar structures 200a-200d. Openings 208 are formed to accommodate electrical components 206a-206b. Figure 5b is a perspective view of an e-bar substrate 196 having e-bar structures 200a - 2001 and openings 208 .

[0051] exist Figure 5c In, similar to Figure 4b , so that the electrical components 206a-206b are in contact with the bonding layer 204. Figure 5b The e-bar substrate 196 is disposed over and in contact with the bonding layer 204, with the electrical components 206a-206b occupying the openings 208, Figure 5dElectrical components 206 a - 206 b and the e-bar substrate 196 are illustrated with integrated e-bar structures 200 a - 200 l bonded to the substrate 202 as an assembly 210 . Figure 5e is a top view of assembly 210 , wherein e-bar substrate 196 includes integrated e-bar structures 200 a - 200 l disposed around or adjacent to the sides of electrical components 206 a - 206 b above substrate 202 .

[0052] from Figure 4c-4d Component 207 or from Figure 5d-5e Component 210 continues as Figure 6a As shown in , sealant or molding compound 212 is deposited over and around electrical components 206a-206b and e-bar structures (or e-bar substrate 196) such as 200a-200d using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating or other suitable applicators. To simplify the description, assembly 207 is used for the remaining figures. A similar process will apply to assembly 210. Sealant 212 can be a liquid or granular polymer composite material, such as an epoxy resin with filler, an epoxy acrylate with filler, or a polymer with a suitable filler. Sealant 212 is non-conductive, provides structural support, and protects the semiconductor device from external elements and contaminants in the environment.

[0053] exist Figure 6b In the embodiment, the carrier 202 and the bonding layer 204 are removed by chemical etching, chemical mechanical polishing (CMP), mechanical stripping, mechanical grinding, thermal baking, ultraviolet (UV) light or wet stripping to expose the conductive layer 112 of the electrical components 206a-206b, the conductive layer 192 of the e-bar structure 200a-200d, and the surface 214 of the sealant 212. The reconstructed embedded wafer level ball grid array package (eWLB) 216 including the electrical components 206a-206b, the e-bar structure 200a-200d, and the sealant 212 is prepared for the surface 110 of the electrical components 206a-206b, the surface 214 of the sealant 212, and the multi-layer RDL build-up interconnect structure above the conductive layer 112 to provide electrical interconnection for the semiconductor die and external electrical components. The reconstructed eWLB 216 is operated as a substrate with an e-bar structure to form a multi-layer RDL build-up interconnect structure.

[0054] Figure 6cA multi-redistribution layer (RDL) interconnect structure 218 including a conductive layer 220 and an insulating layer 222 is shown. Conductive layer 220 is formed using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 220 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Conductive layer 220 is an RDL because it redistributes electrical signals across and over electrical components 206a-206b and encapsulant 212. Portions of conductive layer 220 may be electrically shared or electrically isolated depending on the design and function of semiconductor die 104 and other electrical components attached thereto. Insulating layer 222 is formed over and around conductive layer 220 using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 222 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. Figure 6d In the embodiment, LDA or an etching process using a laser 224 is used to remove portions of encapsulant 212 to form openings or vias 225 extending to conductive layer 188 of e-bar structures 200a-200d for further electrical interconnection.

[0055] exist Figure 6e In the embodiment, encapsulant 212 undergoes a grinding operation using grinder 226 to planarize surface 228 of encapsulant 212 , surface 230 of conductive layer 188 , and insulating layer 190 . Figure 6f Planarized surface 228 of encapsulant 212 and surface 230 of conductive layer 188 are shown as eWLB 232 having e-bar structures 200 a - 200 d .

[0056] Figures 7a-7f The process of forming an RF antenna interposer or substrate is illustrated. Figure 7a In the embodiment, the insulating layer 242 is made of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, polymer, BCB, PBO and other materials with similar insulating and structural properties. A conductive layer 244 is formed above a surface 245 of the insulating layer 242. The conductive layer 244 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. The conductive layer 244 provides horizontal electrical interconnection across the insulating layer 242 (including the surface 245). A plurality of vias are formed through the insulating layer 242 by etching, drilling or LDA. The vias are filled with a conductive material to form a conductive via 246 for vertical electrical interconnection through the insulating layer 242 to the conductive layer 244.

[0057] exist Figure 7bIn the embodiment, a conductive layer 248 is formed over the insulating layer 242. The conductive layer 248 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. The conductive layer 248 provides horizontal electrical interconnection across the insulating layer 242 and is electrically connected to the conductive via 246. An insulating layer 250 is formed over the conductive layer 248. The insulating layer 250 is made of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, polymer, BCB, PBO and other materials with similar insulating and structural properties. A plurality of vias are formed through the insulating layer 250 by etching, drilling or LDA. The vias are filled with a conductive material to form a conductive via 251 for vertical electrical interconnection through the insulating layer 250 to the conductive layer 248. A conductive layer 252 is formed over the insulating layer 250. The conductive layer 252 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. In one embodiment, conductive layer 252 provides a ground plane across insulating layer 250 and is electrically connected to conductive vias 251 .

[0058] exist Figure 7c In the embodiment, an insulating layer 254 is formed over the conductive layer 252. The insulating layer 254 is made of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, polymer, BCB, PBO, and other materials with similar insulating and structural properties. A plurality of vias are formed through the insulating layer 254 by etching, drilling, or LDA. The vias are filled with a conductive material to form a conductive via 256 for vertical electrical interconnection through the insulating layer 254 to the conductive layer 252. A conductive layer 258 is formed over the insulating layer 254. The conductive layer 258 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layer 258 provides horizontal electrical interconnection across the insulating layer 254 and is electrically connected to the conductive via 256. The conductive layer 258 can be configured as an RF antenna embedded in the RF antenna interposer 270, similar to the RF antenna 194. The insulating layer 260 is formed over the conductive layer 258. The insulating layer 260 is made of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, polymer, BCB, PBO and other materials with similar insulating and structural properties. A plurality of vias are formed through the insulating layer 260 by etching, drilling or LDA. The vias are filled with a conductive material to form a conductive via 262 for vertical electrical interconnection through the insulating layer 260 to the conductive layer 258. A conductive layer 264 is formed over a surface 266 of the insulating layer 260 and is electrically connected to the conductive via 262. The conductive layer 264 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. The conductive layer 264 operates as an RF antenna 274 exposed from a surface 266 of the RF antenna interposer 270.

[0059] Conductive bump material is deposited over conductive layer 244 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. A suitable attachment or bonding process is used to bond the bump material to conductive layer 244. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 268. In one embodiment, bump 268 is formed over an under-bump metallization (UBM) having a wetting layer, a barrier layer and an adhesive layer. Bump 268 can also be compression bonded or thermocompressed bonded to conductive layer 244. Bump 268 represents a type of interconnect structure that can be formed over conductive layer 244. The interconnect structure can also use bonding wires, conductive pastes, columnar bumps, microbumps or other electrical interconnects.

[0060] Figure 7d 260 is a top view of the RF antenna interposer 270. The conductive layer 264 includes an array of islands of conductive material in the form of the conductive layer 264 suitable for providing transmission and reception of RF signals, i.e., an RF antenna. Specifically, the array of islands of the conductive layer 264 is exposed from the surface 266 and extends substantially across the surface of the RF antenna interposer 270 to improve RF transmission and reception performance and quality. In one embodiment, the entire array of islands of conductive material can be used as a single antenna 274 for RF transmission and reception of electrical components 206-206b in the eWLB 232. Alternatively, the first group of conductive material islands 272a is used as a first antenna 274a to provide RF transmission and reception for the first electrical component 206a. The second group of conductive material islands 272b is used as a second antenna 194b to provide RF transmission and reception for the second electrical component 206b.

[0061] Figure 7e 2 is a top view of an alternative embodiment of an RF antenna interposer 270. Conductive layer 264 includes a spirally shaped conductive material in the form of conductive layer 264 suitable for providing transmission and reception of RF signals. Specifically, the spirally shaped conductive layer 264 is exposed from surface 266 and extends substantially across the surface of the RF antenna interposer 270 to improve RF transmission and reception performance and quality. Conductive layer 264 acts as a spiral RF antenna 274 to provide RF transmission and reception for electrical components 206a-206b. Conductive layer 264 can have other shapes, such as circular, elliptical, or other geometric patterns.

[0062] Figure 7f26 is a top view of another embodiment of an RF antenna interposer 270. Conductive layer 264 includes a plurality of spirally shaped conductive materials suitable for providing transmission and reception of RF signals. Specifically, the spirally shaped conductive layer 264 is exposed from surface 266 and extends substantially across the surface of the RF antenna interposer 270 to improve RF transmission and reception performance and quality. In one embodiment, conductive layer 264a is used as a first spiral RF antenna 274a to provide RF transmission and reception for the first electrical component 206a. Conductive layer 264b is used as a second spiral RF antenna 274b to provide RF transmission and reception for the second electrical component 206b.

[0063] exist Figure 8a In, from Figures 7a-7f The RF antenna interposer 270 is positioned from Figure 6f 268 is aligned with the conductive layer 188. The RF antenna interposer 270 has a substantially same or similar footprint as the eWLB 232 and occupies substantially the same or similar area. The RF antenna interposer 270 is lowered so that the bumps 268 contact the conductive layer 188, and the bumps are reflowed to electrically and mechanically join and integrate the RF antenna interposer to the eWLB 232, as shown in FIG. Figure 8b As shown in component 280 in FIG.

[0064] exist Figure 8c In the embodiment, a conductive bump material is deposited over the conductive layer 220 of the RDL 218 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the conductive layer 220 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 300. In one embodiment, the bump 300 is formed over the UBM having a wetting layer, a barrier layer and an adhesive layer. The bump 300 can also be compression bonded or thermocompressed bonded to the conductive layer 220. The bump 300 represents a type of interconnect structure that can be formed over the conductive layer 220. The interconnect structure can also use bonding wires, conductive pastes, columnar bumps, microbumps or other electrical interconnects.

[0065] exist Figure 8d, the eWLB 232 with integrated RF antenna interposer 270 (shown as component 280) is singulated using a laser cutting tool or saw blade 302, leaving individual eWLB antenna-on-package (AoP) 310a, as a combination of the eWLB 232a and the RF antenna interposer 270a; and eWLB AoP 310b, as a combination of the eWLB 232b and the RF antenna interposer 270b, i.e., each as an eWLB package-on-package (PoP).

[0066] Fig. 9 The eWLB AoP 310a is illustrated after singulation. The RF antenna interposer 270a provides antenna functionality for the RF electrical component 206a through the e-bar structures 200a-200b. Similarly, the RF antenna interposer 270b provides antenna functionality for the RF electrical component 206b through the e-bar structures 200c-200d. A portion of the encapsulant 212 remains above the surface 108 of the electrical component 206a. The eWLB AoPs 310a and 310b are each a secondary molded eWLB-PoP structure with an e-bar vertical interconnect and a top antenna patterned substrate. The RDL 218 provides electrical connection through the bump 300.

[0067] AoP 310a uses eWLB processes such as LDA, grinding to expose e-bar structures 200a-200d, and antenna interposer stacking to achieve eWLB-PoP structure. E-bar structures 200a-200d provide vertical electrical interconnection between RF antenna 270a and electrical components 206a. Robust signal routing and design to have better high-speed and high-frequency performance.

[0068] Fig.10 An embodiment of eWLB AoP 314 is illustrated where encapsulant 212 is coplanar with the top surfaces of e-bars 200a-200b and surface 108 of electrical component 206a. The top surface of electrical component 206a is exposed from the eWLB-PoP structure while retaining the e-bar vertical interconnects and top antenna patterning substrate.

[0069] Fig.11 An embodiment of eWLB AoP 320 is illustrated with a partial underfill material 322 deposited around bumps 268. Underfill material 322 may be an epoxy. The partial underfill protects bumps 268 and enhances heat dissipation.

[0070] Fig.12An embodiment of the eWLB AoP 330 is illustrated in which an underfill material 336 is deposited to completely cover the package between the RF antenna interposer 270a and the eWLB 232a. The underfill material 336 may be an epoxy. The complete underfill material 336 protects the bumps and electrical components 206a and enhances heat dissipation.

[0071] Fig.13 An electrical device 400 is illustrated having a chip carrier substrate or PCB 402 with multiple semiconductor packages disposed on a surface of the PCB 402, including eWLB AoPs 310, 314, 320, and 330. Depending on the application, the electrical device 400 may have one type of semiconductor package, or multiple types of semiconductor packages.

[0072] The electrical device 400 may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electrical device 400 may be a subcomponent of a larger system. For example, the electrical device 400 may be a part of a tablet computer, a cellular phone, a digital camera, a communication system, or other electrical device. Alternatively, the electrical device 400 may be a network interface card, or other signal processing card that may be inserted into a computer. The semiconductor package may include a microprocessor, a memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, a discrete device, or other semiconductor die or electrical component. Miniaturization and weight reduction are essential for the product to be accepted by the market. The distance between semiconductor devices may be reduced to achieve higher density.

[0073] exist Fig.13 In the embodiment of the present invention, PCB 402 provides a general substrate for structural support and electrical interconnection of semiconductor packages disposed on the PCB. Conductive signal traces 404 are formed over the surface or within the layers of PCB 402 using evaporation, electrolytic plating, electroless plating, screen printing or other suitable metal deposition processes. Signal traces 404 provide electrical communication between each semiconductor package, mounted components and other external system components. Traces 404 also provide power and ground connections to each semiconductor package.

[0074] In some embodiments, the semiconductor device has two packaging levels. The first level packaging is a technology for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have a first level packaging, wherein the die is mechanically and electrically directly disposed on the PCB. For purposes of illustration, several types of first level packaging are shown on PCB 402, including wire bonding packaging 406 and flip chip 408. In addition, several types of second level packaging including ball grid array (BGA) 410, bump chip carrier (BCC) 412, land grid array (LGA) 416, multi-chip module (MCM) or SIP module 418, quad flat no-lead package (QFN) 420, quad flat package 422, embedded wafer level ball grid array (eWLB) 424 and wafer level chip scale package (WLCSP) 426 are shown disposed on PCB 402. In one embodiment, the eWLB 424 is a fan-out wafer level package (Fo-WLP) and the WLCSP 426 is a fan-in wafer level package (Fi-WLP). Depending on the system requirements, any combination of semiconductor packages configured with any combination of first and second level packaging styles and other electrical components can be connected to the PCB 402. In some embodiments, the electrical device 400 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate prefabricated components into electrical devices and systems. Because semiconductor packages include complex functions, electrical devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting device is less likely to fail and is less expensive to manufacture, resulting in a lower cost to the consumer.

[0075] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A semiconductor device, comprising: a substrate comprising a plurality of e-bar structures disposed adjacent to an electrical component; and An antenna interposer is disposed over the first surface of the substrate. 2 . The semiconductor device according to claim 1 , further comprising a redistribution layer formed over a second surface of the substrate opposite to the first surface of the substrate. 3 . The semiconductor device of claim 1 , further comprising an encapsulant deposited over the electrical component.

4. The semiconductor device according to claim 1, wherein: The antenna interposer comprises: a first conductive layer; an insulating layer formed over the first conductive layer; and A second conductive layer is formed over the insulating layer.

5. The semiconductor device according to claim 4, wherein: The second conductive layer operates as an antenna.

6. A semiconductor device comprising: Electrical components; a plurality of e-bar structures disposed adjacent to the electrical component; and An antenna interposer is disposed over the first surface of the e-bar structure. 7 . The semiconductor device of claim 6 , further comprising a redistribution layer formed over a second surface of the e-bar structure opposite to the first surface of the e-bar structure. 8 . The semiconductor device of claim 6 , further comprising an encapsulant deposited over the electrical component.

9. The semiconductor device according to claim 6, wherein: The antenna interposer comprises: a first conductive layer; an insulating layer formed over the first conductive layer; and A second conductive layer is formed over the insulating layer.

10. The semiconductor device according to claim 9, wherein The second conductive layer is arranged as a plurality of islands or in a serpentine pattern.

11. A method for manufacturing a semiconductor device, comprising: Providing electrical components; Disposing a plurality of e-bar structures adjacent to the electrical component; and An antenna interposer is disposed over the first surface of the e-bar structure. 12 . The method of claim 11 , further comprising forming a redistribution layer over a second surface of the e-bar structure opposite the first surface of the e-bar structure.

13. The method of claim 11 further comprising depositing an encapsulant over the electrical component.

14. The method of claim 11, wherein providing the antenna interposer comprises: forming a first conductive layer; forming an insulating layer over the first conductive layer; and A second conductive layer is formed over the insulating layer. 15 . The method of claim 14 , wherein the second conductive layer is arranged as a plurality of islands or in a serpentine pattern.

Images