Semiconductor device including semiconductor package having capacitor embedded in dielectric layer

Abstract

There is provided a semiconductor device including a semiconductor package having a capacitor embedded in a dielectric layer, the semiconductor package including: a redistribution layer including at least one insulating layer in which a plurality of wiring patterns are formed; a semiconductor chip on the redistribution layer connected to at least one of the plurality of wiring patterns; and a capacitor disposed in the redistribution layer.

Description

[0001] This application is based on and claims priority to U.S. Provisional Application No. 63 / 524,746 filed in the United States Patent and Trademark Office on July 3, 2023, and U.S. Non-provisional Application No. 18 / 626,727 filed in the United States Patent and Trademark Office on April 4, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] Apparatus and methods relate to a semiconductor device including a semiconductor package in which a capacitor is embedded in a dielectric layer of a redistribution layer. Background Art

[0003] As the requirements for semiconductor devices including high device density and high device performance increase, semiconductor packages including multiple semiconductor chips and connection structures (such as redistribution layers) are also required to serve the high performance of semiconductor devices including semiconductor packages. However, when the semiconductor package is provided with one or more passive devices (such as capacitors and resistors), the semiconductor device including one or more of the semiconductor packages may have a correspondingly increased size.

[0004] The information disclosed in this background technology section is known or derived by the inventor before or during the process of implementing the embodiments of the present application, or is technical information acquired in the process of implementing the embodiments. Therefore, the information disclosed in this background technology section may contain information that does not form prior art known to the public. Summary of the invention

[0005] A semiconductor package or a semiconductor device including a semiconductor package is disclosed, wherein the semiconductor package includes a dielectric layer of a redistribution layer and a decoupling capacitor embedded in the dielectric layer, while the semiconductor package of the related art includes a decoupling capacitor outside the redistribution layer (e.g., the top surface and the bottom surface of the redistribution layer). For the decoupling capacitor embedded in the dielectric layer, an integrated silicon capacitor (ISC) with a very low profile and high capacitance density can be used. The semiconductor package can be a fan-out wafer level package (FOWLP) (not limited thereto).

[0006] According to one or more embodiments, a semiconductor device is provided, which may include: a redistribution layer including: at least one insulating layer in which a plurality of wiring patterns are formed; at least one semiconductor chip disposed above or below the redistribution layer and connected to at least one of the plurality of wiring patterns; and at least one capacitor disposed in the redistribution layer. Here, the capacitor may be an ISC.

[0007] According to one or more embodiments, the capacitor may be arranged in the redistribution layer to be closer to a top surface of the redistribution layer facing the semiconductor chip than to a bottom surface of the redistribution layer facing away from the semiconductor chip.

[0008] According to an embodiment, the capacitor may be arranged in at least one insulating layer such that one of the top surface and the bottom surface of the first capacitor is within the at least one insulating layer, and the other of the top surface and the bottom surface is within the at least one insulating layer or is coplanar with the top surface or the bottom surface of the at least one insulating layer.

[0009] According to one or more embodiments, there is provided an electronic device which may include: a semiconductor chip; an insulating layer disposed on the semiconductor chip in a first direction and including a first wiring pattern connected to the semiconductor chip in the insulating layer; and a capacitor disposed in the insulating layer.

[0010] According to an embodiment, an electronic system is provided, which may include: a first semiconductor package and a second semiconductor package, wherein each of the first semiconductor package and the second semiconductor package includes a redistribution layer, and a plurality of wiring patterns are formed in the redistribution layer; a semiconductor chip, above or below the redistribution layer, connected to at least one of the plurality of wiring patterns; and a capacitor, disposed in the redistribution layer.

[0011] According to an embodiment, a method for manufacturing a semiconductor device is provided. The method may include: forming a redistribution layer including at least one insulating layer on a carrier substrate; forming a plurality of wiring patterns in the at least one insulating layer; connecting a capacitor and wiring patterns among the plurality of wiring patterns to each other in the redistribution layer; disposing a semiconductor chip above or below the redistribution layer and connecting the wiring patterns to the semiconductor chip; and removing the carrier substrate. Here, the capacitor may be an integrated silicon capacitor (ISC).

[0012] In the case where the capacitor is embedded in the redistribution layer, the semiconductor package can achieve power delivery to the semiconductor chip with low impedance and low noise, and a smaller occupied space in a semiconductor device including the semiconductor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 A schematic cross-sectional side view of a semiconductor package including a plurality of decoupling capacitors (or decoupling capacitors) according to an embodiment is shown;

[0015] Figure 2shows a schematic cross-sectional side view of a semiconductor package including a plurality of decoupling capacitors according to another embodiment;

[0016] Figure 3 shows a schematic cross-sectional side view of a semiconductor package including a plurality of decoupling capacitors according to yet another embodiment;

[0017] Figure 4 A flow chart illustrating a method of manufacturing a semiconductor package including one or more ISCs according to an embodiment;

[0018] FIG. 5A to FIG. 5G According to an embodiment, the Figure 4 An intermediate semiconductor package after various steps of a flowchart for manufacturing a semiconductor package including one or more ISCs;

[0019] Figure 5A According to the embodiment, Figure 4 The intermediate semiconductor package after step S10;

[0020] Figure 5B According to the embodiment, Figure 4 The intermediate semiconductor package after step S20;

[0021] Figure 5C According to the embodiment, Figure 4 The intermediate semiconductor package after step S30;

[0022] Figure 5D According to the embodiment, Figure 4 The intermediate semiconductor package after step S40;

[0023] Figure 5E According to the embodiment, Figure 4 The intermediate semiconductor package after step S50;

[0024] Fig. 5F According to the embodiment, Figure 4 The intermediate semiconductor package after step S60;

[0025] Figure 5G According to the embodiment, Figure 4 The intermediate semiconductor package after step S70; and

[0026] Figure 6 is a diagram showing a method including Figure 2 and / or Figure 3 Schematic block diagram of an electronic device including at least one of the semiconductor packages shown in . DETAILED DESCRIPTION

[0027] The disclosed embodiments described herein are example embodiments, therefore, the disclosure is not limited thereto, and may be implemented in various other forms. Each embodiment provided in the following description does not exclude being associated with one or more features of another example or another embodiment also provided herein, or being associated with one or more features of another example or another embodiment not provided herein but consistent with the disclosure. For example, unless otherwise mentioned in the description of different examples or embodiments, even if the matters described in a specific example or embodiment are not described in different examples or embodiments of the matters, the matters may also be understood to be related to or combined with different examples or embodiments. In addition, it should be understood that the entire description of the disclosed principles, aspects, examples, and embodiments is intended to cover its structural and functional equivalents. In addition, these equivalents should be understood to include not only currently known equivalents, but also equivalents to be developed in the future (i.e., invented as all devices that perform the same function, regardless of their structure). For example, as long as the disclosure can be applied to the channel layer, sacrificial layer, and isolation layer described herein, the channel layer, sacrificial layer, and isolation layer described herein may adopt different types or forms.

[0028] It will be understood that when an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as an "element") of a semiconductor device is referred to as being "on," "over," "up," "under," "below," "connected to," or "bonded to" another element of the semiconductor device, the element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as an "element") of the semiconductor device may be directly on, over, over, under, under, under, connected to, or bonded to the other element, or there may be one or more intervening elements. In contrast, when an element of a semiconductor device is referred to as being "directly on," "directly over," "directly on," "directly below," "directly below," "directly below," "directly below," "directly connected to," or "directly bonded to" another element of the semiconductor device, there are no intervening elements. Like reference numerals refer to like elements throughout this disclosure.

[0029] For ease of description, spatially relative terms (such as "above", "above", "on", "upper", "below", "below", "lower", "lower", "left", "right", "lower left", "lower right", "upper left", "upper right", "center", "middle", etc.) may be used herein to describe the relationship of one element to another one or more elements as shown in the drawings. It will be understood that the spatially relative terms are intended to cover different orientations of the semiconductor device in use or operation in addition to the orientations depicted in the drawings. For example, if the semiconductor device in the drawings is flipped, the element described as being "below" or "lower" of another element will be positioned as being "above" the other element. Therefore, the term "below" may cover both the above and below orientations. The semiconductor device may be positioned in other ways (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein are interpreted accordingly. As another example, elements referred to as "left" elements and "right" elements may be "right" elements and "left" elements when the device or structure including these elements is positioned differently. Therefore, in the following description, as long as the structural relationship of the "left" element and the "right" element is clearly understood in the context of the description, the "left" element and the "right" element may also be referred to as the "first" element or the "second" element, respectively. Similarly, in the case of having a necessary description for distinguishing the "lower" element and the "upper" element, the terms "lower" element and "upper" element may be referred to as the "first" element and the "second" element, respectively.

[0030] It will be understood that although the terms "first," "second," "third," "fourth," "fifth," "sixth," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the disclosed teachings.

[0031] As used herein, when a statement such as "at least one of..." follows a list of elements, the statement modifies the entire list of elements rather than the individual elements in the list. For example, the statement "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. Herein, when the term "same" or "equal" is used to compare the size of two or more elements, the term may cover "substantially the same" or "substantially equal" sizes.

[0032] It will also be understood that when a method of manufacturing a device or structure is described as including a plurality of steps or operations, a particular step or operation described as being performed after a particular step or operation may be performed before or simultaneously with the additional step or operation, unless the additional step or operation is described as being performed before the additional step or operation. In addition, a method may include additional steps or operations not mentioned in the description.

[0033] Many embodiments are described herein with reference to cross-sectional views which are schematic illustrations of embodiments (and intermediate structures). Therefore, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances will be expected. Therefore, the embodiments should not be interpreted as limited to the specific shapes of the regions shown herein, but rather include deviations in shapes, for example, caused by manufacturing. The various regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the disclosure. In addition, in the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0034] For the sake of brevity, conventional elements, structures or layers included in semiconductor packages including connection pads, adhesive layers, isolation layers, barrier metal patterns, seed layers, etc. may be described in detail herein or may not be described in detail herein. For example, when the specific connection pads of the semiconductor chip connected to the solder balls or bumps in the semiconductor package are irrelevant to the novel features of the embodiment, these structural elements may be omitted herein. In addition, when the materials forming the known structural elements are irrelevant to the novel features of the embodiment, the description of these materials may be omitted herein. Here, the term "connection" between two structures or elements may represent the electrical connection between them. For example, the connection between a semiconductor chip, a semiconductor package and / or a semiconductor device may represent that two or more corresponding elements are electrically connected to each other. In addition, the term "isolation" between two structures or elements relates to electrical insulation or separation between them. For example, isolating wiring patterns from each other may represent that wiring patterns are not electrically connected to each other.

[0035] In the following, reference is made to Figures 1 to 6 Various disclosed embodiments are described.

[0036] Compared to other types of semiconductor chips (such as memory chips), high-performance semiconductor chips (such as central processing units (CPUs), graphics processing units (GPUs), artificial intelligence (AI) chips, etc.) consume greater amounts of power. For example, the power consumption of these high-performance chips can reach very high levels (e.g., about 1000W) in terms of thermal design power consumption (TDP). The greater power consumption poses challenges to designing a power delivery network (PDN) for high-performance chips, and therefore, when semiconductor packages including high-performance chips are designed and manufactured, there is an increased need to design a PDN with low impedance across multiple frequency ranges.

[0037] The semiconductor device may include one or more semiconductor packages, each of which includes one or more semiconductor chips. The semiconductor package may include one or more decoupling capacitors (or decoupling capacitors, decoupling capacitors) for controlling impedance and removing noise in a power delivery path to "one or more semiconductor chips disposed on a redistribution layer (or redistribution layer) in the semiconductor package". As a decoupling capacitor, a semiconductor package of the related art includes one or more capacitors (such as, multilayer ceramic capacitors (MLCCs), metal-insulator-metal (MiM) capacitors, deep trench capacitors (DTCs), etc.).

[0038] How these decoupling capacitors in a semiconductor package are configured may affect power delivery performance of a semiconductor device including a semiconductor package including various high-performance semiconductor chips that require a greater amount of operating power.

[0039] Figure 1 A schematic cross-sectional side view of a semiconductor package including a plurality of decoupling capacitors according to an embodiment is shown.

[0040] Reference Figure 1 , a semiconductor package 10 may include a redistribution layer (RDL) 100, a semiconductor chip 200, and a plurality of decoupling capacitors 300, wherein the semiconductor chip 200 is vertically disposed (e.g., in a D3 direction) above the redistribution layer 100 and a plurality of connection terminals 205 are formed between the redistribution layer 100 and the semiconductor chip 200, and the plurality of decoupling capacitors 300 are disposed on a bottom surface of the redistribution layer 100.

[0041] The semiconductor package 10 may be a fan-out wafer level package (FOWLP), which is characterized by one or more redistribution layers connecting one or more semiconductor chips or dies to a package substrate. Compared to other types of semiconductor packages (such as fan-in packages, wire-bonded packages, etc.), FOWLP allows for smaller package sizes and improved electrical performance. In FOWLP, the lateral edges of the package outline may extend in the D1 direction beyond the D2 direction. Figure 1 2. For example, the lateral width of the redistribution layer 100 formed under the semiconductor chip 200 may be greater than the lateral width of the semiconductor chip 200. The decoupling capacitor 300 may be disposed in the semiconductor package 10 to control impedance and reduce noise applied to the semiconductor chip 200 through the redistribution layer 100.

[0042] The semiconductor chip 200 may be one of a system on chip (SoC), a microprocessor chip (such as a CPU, a GPU, a neural processor (NPU), etc.), an AI chip, an application specific integrated circuit (ASIC) chip, an image sensor chip, a power management chip, and a memory chip (not limited thereto). The SoC may include a CPU, a GPU, an NPU, or an AI module.

[0043] The redistribution layer 100 may include a plurality of wiring patterns 110, lower connection patterns 115, and upper connection patterns 125. The plurality of wiring patterns 110, the lower connection patterns 115, and the upper connection patterns 125 are formed by including the wiring patterns 110, the lower connection patterns 115, and the upper connection patterns 125 in the manner described above. Figure 1 Wiring patterns in a plurality of dielectric layers (eg, insulating layers) (eg, first to fourth dielectric layers L1 to L4 ) vertically stacked and connected in such an order as shown in FIG. 1 are connected to one another.

[0044] Each of the wiring patterns 110 included in the dielectric layers L1 to L4 may include at least one line portion 110H and / or at least one via portion 110V connected to each other in a single dielectric layer among the dielectric layers L1 to L4, or at least one line portion 110H and / or at least one via portion 110V connected to each other across two or more dielectric layers among the dielectric layers L1 to L4. For example, the vertical thickness of one line portion 110H of the wiring pattern 110 may be in the range of 2 micrometers to 8 micrometers (μm), and the vertical thickness of each of the dielectric layers L1 to L4 may be in the range of 3 micrometers to 10 micrometers (not limited thereto). Here, the vertical thickness refers to the thickness of the line portion 110H in relation to the dielectric layers L1 to L4. Figure 1The thickness is measured in the D3 direction where the D1 direction and the D2 direction intersect as shown in FIG. Therefore, in the dielectric layers L1 to L4, one of the top surface and the bottom surface of the line portion 110H of the wiring pattern 110 may be disposed in a single dielectric layer, and the other of the top surface and the bottom surface of the line portion 110H may be disposed in a single dielectric layer or coplanar with the top surface or the bottom surface of the single dielectric layer. The wiring pattern 110 may also be referred to as a wiring track. For example, the semiconductor chip 200 may be connected to the wiring pattern 110.

[0045] In the present embodiment, the number of dielectric layers forming the redistribution layer 100 is four (4). However, the disclosure is not limited thereto, and according to other embodiments, more or less than four (4) dielectric layers (eg, one dielectric layer) may form the redistribution layer 100.

[0046] The mold layer 150 may be formed to surround the semiconductor chip 200 and fill a gap between the semiconductor chip 200 and the underlying redistribution layer 100 .

[0047] The redistribution layer 100 may connect a plurality of chip connection pads 215 formed on the bottom surface of the semiconductor chip 200 to a plurality of external terminals 105 on the bottom surface of the redistribution layer 100, so that the semiconductor chip 200 may be connected to one or more external devices or other semiconductor packages. For example, each of the lower connection patterns 115 of the redistribution layer 100 may have at least a portion exposed through the bottom surface of the redistribution layer 100 and connected to one of the external terminals 105. In addition, each of the upper connection patterns 125 may have at least a portion exposed through the top surface of the redistribution layer 100 and connected to one of the chip connection pads 215 through one of the connection terminals 205. The connection terminals 205 and the external terminals 105 may be solder balls or bumps (not limited thereto).

[0048] The wiring pattern 110 may be formed of a metal material such as copper (Cu) (not limited thereto). The lower connection pattern 115 and the upper connection pattern 125 may be formed of a metal material such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), titanium (Ti), tantalum (Ta) or compounds thereof (not limited thereto). The connection terminal 205, the connection pad 215 and the external terminal 105 may be formed of a metal material such as copper (Cu), tin (Sb), lead (Pb), silver (Ag) or compounds thereof (not limited thereto). The wiring pattern 110, the lower connection pattern 115, the upper connection pattern 125, the connection terminal 205, the connection pad 215 and the external terminal 105 may be formed of the same or different metal materials.

[0049] Each of the dielectric layers L1 to L4 may be formed of an organic material having an insulating property, such as a photosensitive polymer such as photosensitive polyimide (not limited thereto), so that the wiring pattern may be electrically isolated from another wiring pattern in the redistribution layer 100 .

[0050] As will be referred to later Figure 4 as well as FIG. 5A to FIG. 5G As described above, the dielectric layers L1 to L4 may be formed at different steps in time, and therefore, even if two adjacent dielectric layers may be formed of the same material, there may be a boundary, a connection surface, or an interface between the two adjacent dielectric layers. However, at least because the two adjacent dielectric layers may be formed of the same material and by the same process, even if they may be formed at different steps in time, there may not be such a boundary, a connection surface, or an interface between the two adjacent dielectric layers.

[0051] Since each decoupling capacitor 300 is disposed on the bottom surface of the redistribution layer 100, each decoupling capacitor 300 may be referred to as a bottom side capacitor (or land side capacitor, LSC). The decoupling capacitor 300 may or may not be connected to the wiring pattern 110 in the redistribution layer 100. When the decoupling capacitor 300 is connected to the wiring pattern 110, the decoupling capacitor 300 may be connected so that at least two terminals of the decoupling capacitor 300 are connected in parallel to the semiconductor chip 200. Each decoupling capacitor 300 may have a size of hundreds of microns (μm) (e.g., approximately 1.0×0.5×0.35 mm for 0402 MLCC), while each of the dielectric layers L1 to L4 may have a much thinner vertical thickness in the range of 3 microns to 10 microns. Therefore, the semiconductor package 10 may be configured so that the decoupling capacitor 300 is disposed on the bottom surface of the redistribution layer 100 between the external terminals 105, which may be solder balls or bumps. However, according to another embodiment, the semiconductor package 10 may be configured to have a decoupling capacitor on a top surface thereof, in which case the capacitor may be referred to as a die side capacitor (DSC).

[0052] However, as described below, the decoupling capacitor may not be limited to an MLCC, a MiM capacitor, or a deep trench capacitor, and may not necessarily be disposed on the bottom surface or the top surface of the redistribution layer 100 .

[0053] Figure 2 A schematic cross-sectional side view of a semiconductor package including a plurality of decoupling capacitors according to another embodiment is shown.

[0054] Reference Figure 2 In addition to the decoupling capacitor 300, the semiconductor package 20 may include Figure 1Therefore, repeated description thereof may be omitted, and the same reference numerals representing those structural elements are used hereinafter, while different aspects of the semiconductor package 20 are described hereinafter.

[0055] Compared to the capacitors 300 disposed on the bottom surface of the redistribution layer 100 , the semiconductor package 20 may be characterized by at least a plurality of integrated silicon capacitors (ISCs) 400 disposed inside the redistribution layer 100 as decoupling capacitors of the semiconductor package 20 .

[0056] The ISC 400 may take the form of a vertical cylindrical array including a plurality of capacitor vias between two or more connection terminals, and may have a very low profile (e.g., approximately 0.5 mm×0.5 mm×2.0 μm). Therefore, the vertical thickness of the ISC 400 in the D3 direction may be less than the vertical thickness of each of the dielectric layers L1 to L4 in the D3 direction (the vertical thickness of each of the dielectric layers L1 to L4 in the D3 direction may be in the range of 3 microns to 10 microns), so that the ISC 400 may be embedded in each of the dielectric layers L1 to L4, or across two or more of the dielectric layers L1 to L4. In addition, the ISC 400 may have a high capacitance density similar to that of an MLCC. For example, the ISC may have hundreds of nF / mm 2 Capacitance value (for example, 1350nF / mm 2 or higher nF / mm 2 ).

[0057] Due to the low profile and high capacitance density described above, the ISC 400 can be embedded in the redistribution layer 100 at a desired location for Figure 1 Since ISC 400 may have a smaller thickness than each of dielectric layers L1 to L4, ISC 400 may be included in one of these dielectric layers such that one of the top and bottom surfaces of ISC 400 is within a single dielectric layer (e.g., L2 or L3) and the other of the top and bottom surfaces of ISC 400 is within the single dielectric layer or is coplanar with the top or bottom surface of the single dielectric layer.

[0058] The ISC 400 may be a first ISC 400-1 or a second ISC 400-2. For example, the top surface of the ISC 400 may be coplanar with the top surface of the dielectric layer. The first ISC 400-1 may be connected to at least one of the wiring patterns 110. For example, the first ISC 400-1 may be interposed between a line portion 110H of a wiring pattern 110 in one dielectric layer (e.g., L3) and a line portion 110H of a wiring pattern 110 in an adjacent dielectric layer (e.g., L4). The line portion 110H of the wiring pattern 110 in the dielectric layer L3 may extend in the D2 direction, and the line portion 110H of the wiring pattern 110 in the dielectric layer L4 may extend in the D1 direction. The two wiring patterns 110 connected to the first ISC 400-1 in two adjacent dielectric layers may be connected to a power supply transmission path between a voltage source and the semiconductor chip 200. The power delivery path may include an external terminal 105, a lower connection pattern 115, a wiring pattern 110, an upper connection pattern 125, a connection terminal 205, and a chip connection pad 215. As another example, the second ISC 400-2 may be formed on a line portion 110H extending in the direction D2 in one dielectric layer (e.g., L2 or L3), but may not be connected to the power delivery path that connects the voltage source to the semiconductor chip 200. Therefore, the second ISC 400-2 may be used as a dummy capacitor that may only support the structural configuration of the redistribution layer 100. In one example, the wiring pattern 110 connected to the second ISC 400-2 may be electrically isolated from any wiring pattern connected to the semiconductor chip 200.

[0059] The wiring pattern 110 may also connect the semiconductor chip 200 to another semiconductor chip or circuit element in another semiconductor package or semiconductor device. For example, a signal wiring path may be formed through one of the connection pads 215, one of the connection terminals 205, one of the upper connection patterns 125, one or more of the wiring patterns 110 connected to one of the first ISCs 400-1, one of the lower connection patterns 115, and one of the external terminals 105.

[0060] Although the thickness of each of the line portion 110H and the ISC 400 of the wiring pattern 110 may be less than the thickness of the signal dielectric layer among the dielectric layers L1 to L4, the wiring pattern 110 having the ISC 400 thereon may also have a thickness less than or equal to the thickness of a single dielectric layer. For example, although the bottom surface of the line portion 110H of the wiring pattern 110 extending in the D2 direction in the third dielectric layer L3 may be coplanar with the boundary between the third dielectric layer L3 and the second dielectric layer L2, the top surface of the ISC 400 formed on this line portion 110H of the wiring pattern 110 may be coplanar with the boundary between the third dielectric layer L3 and the fourth dielectric layer L4. Therefore, the total thickness of the line portion 110H and the ISC 400 of the wiring pattern 110 in the third dielectric layer L3 may be equal to the thickness of the dielectric layer L3. However, the disclosure is not limited thereto, and according to an embodiment, the wiring pattern 110 having the ISC 400 thereon may have a thickness greater or less than the thickness of a single dielectric layer in the redistribution layer 100. However, according to an embodiment, the total thickness of the line portion 110H of the wiring pattern 110 and the ISC 400 may still be less than the thickness of the redistribution layer 100, and further, according to an embodiment, the total thickness of the wiring pattern 110 including the line portion 110H and the via portion 110V may be less than the thickness of the redistribution layer 100.

[0061] The ISC 400 having a high capacitance density may be disposed in the redistribution layer 100 sufficiently close to the semiconductor chip 200 (e.g., closer to the top surface than to the bottom surface of the redistribution layer 100) to better control the impedance and noise applied to the semiconductor chip 200, thereby improving the power delivery performance. For example, among the top surface of the redistribution layer 100 facing the semiconductor chip 200 in the D3 direction and the bottom surface of the redistribution layer 100 facing away from the semiconductor chip 200 in the D3 direction, the first ISC 400-1 may be disposed closer to the top surface of the redistribution layer 100 facing the semiconductor chip 200 in the D3 direction.

[0062] In addition, since the semiconductor package 20 can omit Figure 1 By removing the DSC or LSC like the capacitor 300 in the semiconductor package 10 shown in FIG. 1 and disposed on the top surface or the bottom surface of the redistribution layer 100, the overall size of the semiconductor package 20 can be reduced. For example, although the external terminals 105 that can be solder balls or bumps can form a ball grid array (BGA) of the semiconductor packages 10 and 20, removing the capacitor 300 that is an LSC between the external terminals 105 formed on the bottom surface of the redistribution layer 100 can reduce the constraints on the package design including the ball design for the BGA semiconductor package.

[0063] exist Figure 1In the semiconductor package 10 shown in FIG. 1 , the height of the external terminal 105 of the semiconductor package 10 in the D3 direction may be greater than the height of the capacitor 300 formed on the bottom surface of the redistribution layer 100 at one side of the external terminal 105, so that the capacitor 300 may not be physically affected by the connection of the semiconductor package 10 with another device or package through the external terminal 105. However, in the semiconductor package 20 of the present embodiment, since such a capacitor 300 does not exist on the bottom surface of the redistribution layer 100, the height of the external terminal 105 may also not be constrained. For example, the external terminal 105 may be formed by a smaller size solder ball at a smaller pitch and profile, which helps to reduce the overall stacking height of the semiconductor package 20.

[0064] The above embodiment of disposing the ISC 400 inside the redistribution layer 100 may also be applied to a ground grid array (LGA) semiconductor package (i.e., a semiconductor package 20 without external terminals 105 (solder balls or bumps)). In this case, the lower connection pattern 115 may form an LGA, and eliminating the capacitor 300 as an LSC from the bottom surface of the redistribution layer 100 may eliminate the need for a cavity inside an original equipment manufacturer (OEM) socket to improve the structural integrity of the OEM socket. Therefore, manufacturing simplicity and cost reduction may also be achieved.

[0065] Furthermore, the low impedance and high capacitance density of the ISC 400 in the semiconductor package 20 with reduced footprint may better serve high-performance processors (such as CPUs, GPUs, AI chips, etc.) that require high power consumption to be implemented in the semiconductor package.

[0066] In the above embodiments, one redistribution layer (i.e., redistribution layer 100) is formed in the semiconductor package 20 to connect the semiconductor chip 200 to a voltage source or another semiconductor device or package through the external terminal 105. However, according to embodiments, one or more additional redistribution layers may be formed above, below, or to the side of the redistribution layer 100 in the semiconductor package 20 to provide at least one additional redistribution path to the semiconductor chip 200. For example, the semiconductor chip 200 may be connected to another circuit element or semiconductor chip in another semiconductor package or device through an additional redistribution path provided by the additional redistribution layer in the semiconductor package 20. Here, the additional redistribution path may be a power delivery path or a signal routing path from or to the semiconductor package 20.

[0067] Since one or more additional redistribution layers are connected to the semiconductor chip 200, the length of a power delivery path or a signal routing path may also increase, which may subsequently increase impedance and / or noise in the semiconductor package 20. However, according to an embodiment, one or more ISCs 400 may also be included in the additional redistribution layers to reduce impedance and / or noise and suppress an increase in the overall size of the semiconductor package 20.

[0068] Meanwhile, according to another embodiment, the redistribution layer 100 having the ISC 400 embedded therein may be vertically disposed above the semiconductor package 20, wherein the redistribution layer 100 having the ISC 400 embedded therein and the semiconductor package 20 have corresponding connection patterns and terminals therebetween, thereby forming a different semiconductor package. In this embodiment, the ISC 400 may be disposed in the redistribution layer 100 to be closer to the bottom surface of the redistribution layer 100 than to the top surface of the redistribution layer 100, so as to better control impedance and noise applied to the semiconductor chip 200 vertically disposed below the redistribution layer 100.

[0069] Furthermore, two or more semiconductor chips may be vertically formed above or below the redistribution layer including the ISC, with corresponding connection patterns and terminals therebetween. Figure 3 A schematic cross-sectional side view of a semiconductor package including a plurality of decoupling capacitors according to yet another embodiment is shown.

[0070] Reference Figure 3 , the semiconductor package 30 may include structural elements and configurations including the ISC 400 that are the same as or similar to those of the semiconductor package 20 including the ISC 400. However, the semiconductor package 30 may be characterized in that an additional semiconductor chip 500 may be vertically disposed above the redistribution layer 100 within a lateral edge of the package outline. Therefore, repeated descriptions thereof may be omitted, and the same reference numerals representing those structural elements are used hereinafter.

[0071] Similar to the semiconductor package 20, the semiconductor package 30 may include an ISC 400 inside the redistribution layer 100, and the ISC 400 may be as described above with reference to FIG. Figure 2 4. However, in the semiconductor package 30, the ISC 400-1 may be connected to the semiconductor chips 200 and 500 to control the impedance and noise applied to the two chips, respectively. Since the LSC or DSC may not be included in the semiconductor package 30, the semiconductor package 30 may also provide a reduced footprint similar to the semiconductor package 20.

[0072] In the semiconductor package 30, the semiconductor chips 200 and 500 may be connected to each other through the wiring pattern 110 in the redistribution layer 100, and in this case, the semiconductor chips 200 and 500 may be connected to the same one or more ISCs 400, and these ISCs 400 may be connected to a voltage source to reduce impedance and noise in a power supply transmission path. Additionally or alternatively, these ISCs 400 may be included in a signal routing path between the two semiconductor chips 200 and 500 to reduce impedance and noise in the signal routing path.

[0073] exist Figure 3 In the embodiment, two semiconductor chips 200 and 500 are vertically formed above one redistribution layer (i.e., redistribution layer 100) including the ISC 400 in the semiconductor package 30. However, the disclosure is not limited thereto, and according to an embodiment, the semiconductor package 30 may be configured such that one or more additional redistribution layers may be formed above, below, or laterally of the redistribution layer 100 in the semiconductor package 30 to provide at least one additional redistribution path to at least one of the semiconductor chips 200 and 500. For example, at least one of the semiconductor chips 200 and 500 may be connected to another circuit element or semiconductor chip in another semiconductor package or device through an additional redistribution path provided by the additional redistribution layer in the semiconductor package 30. For example, at least one of the wiring pattern 110 connected to the semiconductor chip 200 and the wiring pattern 110 connected to the semiconductor chip 500 may be connected to at least one of the semiconductor chips 200 and 500.

[0074] Since one or more additional redistribution layers are connected to at least one of the semiconductor chips 200 and 500, the length of a power delivery path or a signal routing path may also increase, which may subsequently increase impedance and / or noise in the semiconductor package 30. However, according to an embodiment, one or more ISCs 400 may also be included in the additional redistribution layers to reduce impedance and / or noise and suppress an increase in the overall size of the semiconductor package 30.

[0075] also, Figure 3The semiconductor chips 200 and 500 are shown to be disposed together at the same height above the redistribution layer 100 in the semiconductor package 30. However, the disclosure is not limited thereto, and according to an embodiment, the semiconductor chips 200 and 500 may be formed at different heights above the redistribution layer 100. For example, one or more additional redistribution layers may be formed below the semiconductor chip at a higher height among the two semiconductor chips 200 and 500, and the additional redistribution layers may provide at least one additional redistribution path to the semiconductor package 30. Similar to the above embodiment, one or more ISCs 400 may be included in the additional redistribution layer to reduce impedance and / or noise, and to suppress an increase in the overall size of the semiconductor package 30. For example, among the top surface of the redistribution layer 100 facing the semiconductor chips 200 and 500 and the bottom surface of the redistribution layer 100 facing away from the semiconductor chips 200 and 500, the first ISC 400-1 and the second ISC 400-2 may be disposed closer to the top surface of the redistribution layer 100 facing the semiconductor chips 200 and 500.

[0076] In the following, reference is made to Figure 4 as well as FIG. 5A to FIG. 5G Methods of making semiconductor packages including one or more ISCs are provided.

[0077] Figure 4 A flowchart of a method of manufacturing a semiconductor package including one or more ISCs according to an embodiment is shown, and FIG. 5A to FIG. 5G According to an embodiment, the Figure 4 1 . An intermediate semiconductor package 20 ′ is shown following various steps of a flow chart of manufacturing a semiconductor package including one or more ISCs.

[0078] The semiconductor package manufactured by the method described below can be used with Figure 2 1 and 2 , and thus, repeated descriptions may be omitted and the same reference numerals denoting structural elements of the semiconductor package 20 are used hereinafter.

[0079] In step S10, Figure 5AAs shown in , the first dielectric layer L1 may be formed on the carrier substrate 101 by a coating process or a deposition process. In addition, a first photolithography / mask / etching / deposition operation may be performed on the first dielectric layer L1 to form a lower connection pattern 115, a line portion 110H of each wiring pattern 110 connected to the lower connection pattern 115, and a via portion 110V in the first dielectric layer L1. In addition, the line portion 110H of the wiring pattern 110 of the second dielectric layer L2 to be formed in a subsequent step over the dielectric layer L1 may also be formed by the first photolithography / mask / etching / deposition operation in this step. Some of the line portions 110H of the second dielectric layer L2 may be formed to extend in the D1 direction and be connected to the lower connection pattern 115 through the wiring pattern 110 in the first dielectric layer L1, and some of the line portions 110H may be formed to extend in the D2 direction and be connected to the ISC 400 in a subsequent step.

[0080] The first dielectric layer L1 may be patterned by, for example, photolithography, laser drilling, reactive ion etching (RIE), etc. to form via openings, which are then filled with one or more metal materials deposited by, for example, electroplating, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), combinations thereof, etc. (not limited thereto) to form lower connection patterns 115 and wiring patterns 110. The lower connection pattern 115 may be formed such that its bottom surface contacts the carrier substrate 101.

[0081] The metal material forming the lower connection pattern 115 and the wiring pattern 110 may be selected from copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), titanium (Ti), tantalum (Ta), or compounds thereof (not limited thereto). The lower connection pattern 115 and the wiring pattern 110 may be formed of the same or different materials.

[0082] The carrier substrate 101 on which the first dielectric layer L1 is formed may be, for example, a glass, silicon or ceramic substrate (not limited thereto). The coating or deposition process for forming the dielectric layer L1 may use spin coating, slit coating, CVD, etc. of an organic material such as a photosensitive polymer (e.g., photosensitive polyimide) (not limited thereto).

[0083] In step S20, Figure 5B As shown in FIG. 1 , a second ISC 400-2 may be formed on at least one line portion 110H of at least one selected wiring pattern 110 of a dielectric layer L2. The second ISC 400-2 may be formed on the wiring pattern 110 extending in the D2 direction by, for example, soldering (not limited thereto).

[0084] The second ISC 400 - 2 formed in this step may be a dummy capacitor that is not connected to a power delivery path in the semiconductor package 20 to be completed in a subsequent step based on the intermediate semiconductor package obtained in this step.

[0085] In step S30, Figure 5C As shown in , a second dielectric layer L2 may be formed on the first dielectric layer L1 by the same or similar coating or deposition process performed in step S10 to surround the wiring pattern 110 in the second dielectric layer L2. In addition, a second photolithography / masking / etching / deposition operation may be performed to form a line portion 110H of the wiring pattern 110 of the third dielectric layer L3 and a via portion 110V of the wiring pattern 110 connected to the line portion 110H in the second dielectric layer L2. These line portions 110h may be formed to extend in the D2 direction and connected to the ISC 400 in a subsequent step.

[0086] In step S40, Figure 5D As shown in FIG. 4 , an ISC 400 - 1 and another ISC 400 - 2 (not limited thereto) may be formed on corresponding line portions 110H of selected wiring patterns 110 of the third dielectric layer L3 by soldering as in step S20 .

[0087] Similar to the ISC 400-2 formed in the second dielectric layer L2 in step S20, the ISC 400-2 formed in this step may not be connected to the power transmission path in the semiconductor package 20 to be completed in a subsequent step. However, the ISC 400-1 formed in this step may be connected to the power transmission path in the semiconductor package 20.

[0088] In step S50, if Figure 5E As shown in FIG. 5 , a third dielectric layer L3 may be formed on the second dielectric layer to surround the wiring pattern 110 formed in step S40 and the ISCs 400 - 1 and 400 - 2 on the wiring pattern 110 .

[0089] In addition, the fourth dielectric layer L4 may be formed on the third dielectric layer L3 by the same or similar coating or deposition process performed in steps S10 and S30, thereby completing the redistribution layer 100. In addition, a third photolithography / masking / etching / deposition operation may be performed on the fourth dielectric layer L4 to form the remaining line portions 110H of the wiring pattern 110 on the corresponding via portions 110V of the wiring pattern 110 in the third dielectric layer L3, and to form the upper connection pattern 125 on these line portions 110H of the wiring pattern 110.

[0090] In step S60, if Fig. 5FAs shown in , connection terminals 205 may be respectively formed on the upper connection patterns 125, and the semiconductor chip 200 may be placed on the redistribution layer 100 by respectively bonding the chip connection pads 215 of the semiconductor chip 200 to the connection terminals 205. In addition, the mold layer 150 may be formed to surround the semiconductor chip 200 and fill the gap between the semiconductor chip 200 and the underlying redistribution layer 100.

[0091] When the connection terminal 205 is a solder ball or a bump, solder transfer, solder ball placement, electroplating, printing, etc. may be used to form the connection terminal 205 on the upper connection pattern 125. Bonding the semiconductor chip 200 to the connection terminal 205 may be performed by, for example, soldering. The connection terminal 205 and the chip connection pad 215 may be formed of the same or different metal materials selected from copper (Cu), tin (Sb), lead (Pb), silver (Ag), or compounds thereof (not limited thereto).

[0092] In step S70, if Figure 5G As shown in FIG. 1 , the carrier substrate 101 may be removed from the intermediate semiconductor package obtained in the previous operation, and external terminals 105 may be formed on the bottom surface of the redistribution layer 100 to be connected to the lower connection patterns 115, respectively, thereby forming Figure 2 The semiconductor package 20 is shown in FIG.

[0093] The external terminal 105 may be formed of a metal material such as copper (Cu), tin (Sb), lead (Pb), silver (Ag), or a compound thereof (not limited thereto). The external terminal may be formed of the same material as or different from the connection terminal 205 .

[0094] The removal of the carrier substrate 101 may be performed by, for example, mechanical grinding, etc., and the connection of the external terminals 105 to the lower connection patterns 115 may be performed by, for example, soldering, etc.

[0095] Figure 6 is a diagram showing a method including Figure 2 and / or Figure 3 Schematic block diagram of an electronic system of multiple semiconductor packages shown in .

[0096] Reference Figure 6 , the electronic device 1000 may include a printed circuit board (PCB) 1010, which may be a motherboard on which a plurality of semiconductor packages 1011 to 1015 are mounted. The electronic device 1000 may also include a plurality of other components 1020. The PCB 1010 may be a package substrate, which includes a substrate core formed of epoxy resin and a plurality of vias penetrating the substrate core. The package substrate may also include a plurality of connection terminals formed on the front side surface and / or the rear side surface and connected to the through vias. The package substrate may be connected to a redistribution layer (such as, Figure 2 or Figure 3 Redistribution layer 100).

[0097] The semiconductor package 1011 may include a SoC for controlling the overall operation of the electronic device 1000, and the SoC for controlling the overall operation of the electronic device 1000 may include at least one of a CPU, a GPU, an AI module, a modem, one or more memory units, a power management unit, etc. The other semiconductor packages 1012 to 1015 may include a memory chip, various other processor chips, a communication chip, and an interface chip, respectively. The communication chip 1014 included in the semiconductor package may be configured to also perform wireless or wired communication functions associated with the SoC. At least one of the semiconductor packages 1011 to 1015 may be composed of Figure 2 The semiconductor package 20 shown in FIG. Figure 3 The semiconductor package 30 shown in FIG.

[0098] Other components 1020 included in the electronic device 1000 may include a storage device, a camera module, a speaker, a microphone, a display / touch screen, a battery, etc. The storage device may be configured to store user data. The storage device may be an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash memory (UFS) device, etc. The display may be implemented to display data processed by the SoC and / or receive data through a touch screen panel of the display.

[0099] The foregoing is an illustration of exemplary embodiments and should not be construed as limiting the disclosure. Although a few exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the above embodiments without substantially departing from the disclosure.

Claims

1. A semiconductor device comprising: a redistribution layer including an insulating layer in which a first wiring pattern is formed; a first semiconductor chip located on the redistribution layer in a first direction and connected to the first wiring pattern; as well as The first capacitor is disposed in the redistribution layer.

2. The semiconductor device according to claim 1, wherein The first capacitor is arranged in the insulating layer so that one of the top surface and the bottom surface of the first capacitor is within the insulating layer in a first direction, and the other of the top surface and the bottom surface of the first capacitor is within the insulating layer in the first direction or is coplanar with the top surface or the bottom surface of the insulating layer.

3. The semiconductor device according to claim 2, wherein: A top surface of the first capacitor is coplanar with a top surface of the insulating layer.

4. The semiconductor device according to claim 1, wherein The first capacitor is disposed closer in the first direction to a top surface of the redistribution layer facing the first semiconductor chip than the first capacitor is close to a bottom surface of the redistribution layer facing away from the first semiconductor chip in the first direction.

5. The semiconductor device according to claim 1, wherein The first capacitor is connected to a first wiring pattern connected to the first semiconductor chip.

6. The semiconductor device according to claim 5, further comprising: a second capacitor connected to a second wiring pattern formed in the redistribution layer, The second wiring pattern is electrically isolated from any wiring pattern connected to the first semiconductor chip.

7. The semiconductor device according to claim 1, wherein a first capacitor is connected to a first wiring pattern, The first wiring pattern is electrically isolated from any wiring pattern connected to the first semiconductor chip.

8. The semiconductor device according to claim 1, further comprising: a second semiconductor chip located on the redistribution layer in the first direction, the second semiconductor chip being connected to a second wiring pattern in the redistribution layer; as well as The second capacitor is disposed in the redistribution layer.

9. The semiconductor device according to claim 8, wherein: The first capacitor and the second capacitor are connected to the first wiring pattern and the second wiring pattern, respectively, Here, at least one of the first wiring pattern and the second wiring pattern is connected to at least one of the first semiconductor chip and the second semiconductor chip.

10. The semiconductor device according to claim 8, wherein The first and second capacitors are disposed closer to a top surface of the redistribution layer facing the first and second semiconductor chips than to a bottom surface of the redistribution layer facing away from the first and second semiconductor chips.

11. The semiconductor device according to any one of claims 1 to 10, further comprising: connecting terminals between the redistribution layer and the first semiconductor chip, The connection terminals include solder balls or bumps that connect the first wiring pattern or another wiring pattern in the redistribution layer to the first semiconductor chip.

12. An electronic device comprising: Semiconductor chips; an insulating layer disposed on the semiconductor chip in a first direction and including a first wiring pattern connected to the semiconductor chip in the insulating layer; as well as The capacitor is disposed in the insulating layer.

13. The electronic device according to claim 12, wherein: The capacitor is arranged in the insulating layer so as to be closer in the first direction to a top surface of the insulating layer facing the semiconductor chip than to a bottom surface of the insulating layer facing away from the semiconductor chip in the first direction.

14. The electronic device according to claim 12, wherein: The insulating layer includes a plurality of layers stacked in a first direction, and The thickness of the capacitor in the first direction is smaller than the thickness of one of the multiple layers in the first direction.

15. The electronic device according to claim 12, wherein: The insulating layer includes a second wiring pattern, The capacitor is connected to the semiconductor chip through one of the first wiring pattern and the second wiring pattern.

16. The electronic device according to any one of claims 12 to 15, further comprising: The connection terminal is formed between the insulating layer and the semiconductor chip, The connection terminals include solder balls or bumps that connect the first wiring pattern to the semiconductor chip.

17. An electronic system comprising: A first semiconductor package is provided on a substrate, and the first semiconductor package comprises: A first redistribution layer includes a first insulating layer in which a first wiring pattern is formed; a semiconductor chip disposed on the first redistribution layer and connected to the first wiring pattern; and The first capacitor is disposed in the first redistribution layer.

18. The electronic system according to claim 17, wherein: The first capacitor is arranged in the first insulating layer so that one of the top surface and the bottom surface of the first capacitor is within the first insulating layer in the first direction, and the other of the top surface and the bottom surface of the first capacitor is within the first insulating layer in the first direction or is coplanar with the top surface or the bottom surface of the first insulating layer.

19. The electronic system according to claim 18, wherein: The first capacitor is disposed closer in the first direction to a top surface of the first redistribution layer facing the semiconductor chip than the first capacitor is closer in the first direction to a bottom surface of the first redistribution layer facing away from the semiconductor chip.

Images