Preparation method of semiconductor test structure

Abstract

The invention relates to a preparation method of a semiconductor test structure. The preparation method comprises the steps of providing a substrate; forming a plurality of mask strips which are distributed at intervals along the first direction and extend along the second direction on the top surface of the substrate; at least taking a plurality of mask strips as masks, and executing ion implantation processes with the same energy and different doses on the initial test region to obtain a target test structure comprising two doped regions; determining a first target test association relationship among the injected ion doses, the diffusion widths and the breakdown voltages of different target test structures according to the injected ion doses, the diffusion widths and the breakdown voltages of the plurality of target test structures, and determining a second target test association relationship among the injected ion doses, the diffusion widths and the breakdown voltages of the to-be-tested target test structures according to the actual injected dose and the actual breakdown voltage of the to-be-tested target test structure; and determining the actual diffusion width of the to-be-tested target test junction. Based on the existing technological process, no extra photomask is needed. Through a simple and effective target test structure, a target test association relationship for monitoring the actual diffusion width of ion implantation is obtained, so that the influence of implantation on the performance of a device under different dose conditions is reflected.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a method for preparing a semiconductor test structure. Background Art

[0002] Ion implantation is one of the indispensable means of material modification in the modern integrated circuit manufacturing process. Its essence is to focus the ionized impurity atoms or molecules into an ion beam, and inject it into the semiconductor substrate with specific energy and dosage according to the design, so as to achieve the doping requirements. When the ion beam is incident on the surface of the material, its energetic ions are affected by the interaction between the target atomic nucleus and the surrounding electron cloud, and their speed and direction change, and finally form a certain spatial distribution in the substrate. However, during the device debugging process, the injected impurity ions will collide with the silicon atoms in the substrate, resulting in lateral diffusion (scattering), which will increase the diffusion range of the injected ions, such as Figure 1 As shown, the device structure is different from the actual layout design, which in turn affects the device performance.

[0003] This not only affects the accuracy of the circuit layout, but the lateral diffusion of ions may also lead to unexpected changes in circuit characteristics, such as weakened current control, shifting threshold voltage, etc. Therefore, monitoring the degree of lateral diffusion of ion implantation is essential to ensure optimized performance of electronic devices and stable circuit characteristics. Summary of the invention

[0004] Based on this, it is necessary to provide a method for preparing a semiconductor test structure to address the technical problems in the prior art, which can at least be used to monitor the lateral diffusion width of ion implantation, and thus better be used for optimizing and debugging the ions required for the device.

[0005] In a first aspect, the present application provides a method for preparing a semiconductor structure, comprising: providing a substrate; forming a plurality of mask strips spaced apart along a first direction and extending along a second direction on a top surface of the substrate; the substrate between two adjacent mask strips is used to form an initial test area; two adjacent initial test areas are used to form an initial test structure; adjacent initial test structures are spaced apart along the first direction; the first direction and the second direction intersect and are parallel to the top surface of the substrate;

[0006] Using at least a plurality of mask strips as masks, an ion implantation process is performed into the initial test region to obtain a target test structure including two doping regions, wherein the ion implantation energies of different target test structures are the same but the doses are different;

[0007] According to the implanted ion dose, diffusion width and breakdown voltage of multiple target test structures, a first target test association relationship between the implanted ion dose, diffusion width and breakdown voltage of different target test structures is determined; the first target test association relationship is used to determine the actual diffusion width of the target test junction to be tested according to the actual implanted dose and actual breakdown voltage of the target test junction to be tested.

[0008] In the above-mentioned method for preparing a semiconductor test structure of an ion implantation actual diffusion width, by performing an ion implantation process with the same energy and different doses during its structural process, target test structures corresponding to the implantation doses are prepared in sequence. Since the conductivity type of the doped region and the substrate is different, a target test junction to be tested is formed in the target test structure, and the electrical performance of each target test junction to be tested is measured to collect the corresponding breakdown voltage. According to the implantation ion dose, diffusion width and breakdown voltage of multiple target test structures, a first target test association relationship between the implantation ion dose, diffusion width and breakdown voltage is established.

[0009] In short, this method can effectively and dynamically monitor and quantify the lateral diffusion behavior of ions under different doses but constant energy, reflect the actual diffusion width of the target test junction under different dose conditions to determine the actual ion implantation range, reduce redundant repeated experiments and data analysis work in the subsequent device debugging process, and lay the foundation for subsequent optimization of device design and research work.

[0010] In some embodiments, the substrate includes a base and a first-type semiconductor layer located on the base; the doped region is a second doped region; and a plurality of mask strips are formed on the top surface of the substrate, including: forming a mask layer on the top surface of the first-type semiconductor layer; and patterning the mask layer to obtain a plurality of mask strips that are spaced apart along a first direction and extend along a second direction.

[0011] In some embodiments, an ion implantation process is performed on the initial test area, including: forming an ion implantation mask above the initial test structure; using the ion implantation mask and multiple mask strips as a mask plate, adopting a self-alignment process, performing an ion implantation process on the initial test structure to obtain multiple target test structures.

[0012] In some embodiments, the first type is P-type and the second type is N-type; or the first type is N-type and the second type is P-type.

[0013] In some embodiments, the spacing between adjacent mask strips is greater than or equal to a preset threshold.

[0014] In a second aspect, the present application further provides a method for preparing a semiconductor test structure, comprising: providing a substrate; forming a plurality of mask strips spaced apart along a first direction and extending along a second direction on a top surface of the substrate; the substrate between two adjacent mask strips is used to form an initial test area; two adjacent initial test areas are used to form an initial test structure; adjacent initial test structures are spaced apart along the first direction; the first direction and the second direction intersect and are both parallel to the top surface of the substrate;

[0015] Using at least a plurality of mask strips as masks, an ion implantation process is performed into an initial test region to obtain a target test structure including two doped regions, wherein implanted ion energies and doses of different target test structures are the same and target sizes are different; the target size is the spacing between adjacent mask strips along a first direction, or the length of the mask strips along the first direction;

[0016] According to the target sizes, diffusion widths and breakdown voltages of multiple target test structures, a second target test association relationship between the target sizes, diffusion widths and breakdown voltages of different target test structures is determined; the second target test association relationship is used to determine the measured diffusion width of the target test junction to be tested based on the actual target size and actual breakdown voltage of the target test junction to be tested.

[0017] In the above-mentioned method for preparing another semiconductor test structure of actual diffusion width of ion implantation, similarly, by performing ion implantation processes with the same energy and different doses during its structural process, target test structures corresponding to the implantation doses are prepared one by one in sequence, and target test junctions to be tested are formed, and the electrical performance of each target test junction to be tested is measured to collect the corresponding breakdown voltage. The above process is repeated for multiple test structures with different target sizes to determine the second target test correlation relationship between the target size, diffusion width and breakdown voltage of different target test structures.

[0018] Based on the original preparation method, this method adjusts the target size of the target test structure and simultaneously monitors the ion implantation range corresponding to different implanted ion doses under multiple target sizes, thereby broadening the diversity of semiconductor test structures.

[0019] In some embodiments, the substrate includes a base and a first-type semiconductor layer located on the base; the doped region is a second-type doped region; and a plurality of mask strips are formed on the top surface of the substrate, including: forming a mask layer on the top surface of the first-type semiconductor layer; and patterning the mask layer to obtain a plurality of mask strips that are spaced apart along a first direction and extend along a second direction.

[0020] In some embodiments, the first type is P-type and the second type is N-type; or the first type is N-type and the second type is P-type.

[0021] In some embodiments, the target size is the spacing between adjacent mask strips along a first direction; when the target size is maximum and adjacent doping regions are in contact, the minimum breakdown voltage and the maximum diffusion width are obtained; when the target size is minimum, the maximum breakdown voltage and the minimum diffusion width are obtained; the maximum value of the diffusion width and the minimum value of the diffusion width are used to determine whether the measured diffusion width of the target test junction to be tested is abnormal.

[0022] In some embodiments, the target size is the length of the mask strip along the first direction; when the target size is the minimum value and adjacent doping regions are in contact, the minimum value of the breakdown voltage and the maximum value of the diffusion width are obtained; when the target size is the maximum value, the maximum value of the breakdown voltage and the minimum value of the diffusion width are obtained; the maximum value of the diffusion width and the minimum value of the diffusion width are used to determine whether the measured diffusion width of the target test junction to be tested is abnormal.

[0023] In the above embodiments, the unexpected technical effects of the present application are:

[0024] Based on the existing process flow, through a simple and effective target test structure, the first target test correlation relationship between the implanted ion dose, diffusion width and breakdown voltage of different target test structures and the second target test correlation relationship between the target size, diffusion width and breakdown voltage are established. Through the first target test correlation relationship and the second target test correlation relationship, the actual width of the lateral diffusion of ion implantation of various target sizes under different doses and the same energy can be monitored, thereby reflecting the actual ion implantation range under different dose conditions, so as to better optimize and debug the ions required by the device.

[0025] These methods not only achieve dynamic quantification of ion lateral diffusion behavior, reveal the impact of different doses on device performance, and reduce repeated experiments, but also achieve real-time monitoring of multi-size diffusion widths by adjusting the target size, significantly improving the diversity of test structures, and providing effective tools and foundations for optimizing device design and reducing subsequent research work. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 A comparison chart of the layout design diffusion width and the actual diffusion width in the device structure;

[0028] Figure 2A schematic diagram of a process for preparing a semiconductor test structure provided in an embodiment;

[0029] Figure 3 A schematic cross-sectional view of a structure obtained by forming a mask strip in step S1044 in a method for preparing a semiconductor structure provided in an embodiment;

[0030] Figure 4 It is a schematic cross-sectional view of a structure obtained after forming a doped region in step S1062 in a method for preparing a semiconductor structure provided in an embodiment;

[0031] Figure 5 It is a schematic cross-sectional view of a structure obtained after an electrical connection is formed in step S1064 in a method for preparing a semiconductor structure provided in an embodiment;

[0032] Figure 6 A schematic cross-sectional view of a structure obtained after performing ion implantation processes with the same energy and different doses;

[0033] Figure 7 for Figure 6 A schematic cross-sectional view of the structure obtained after the electrical connector is formed;

[0034] Figure 8 A schematic flow chart of a method for preparing a semiconductor test structure provided in another embodiment;

[0035] Fig. 9 It is a schematic cross-sectional view of a structure obtained after forming a doped region in step S206 in a method for preparing a semiconductor structure provided in an embodiment;

[0036] Fig.10 It is a schematic cross-sectional view of a structure obtained after the target size D1 is changed in the method for preparing a semiconductor structure provided in an embodiment;

[0037] Fig.11 It is a schematic cross-sectional view of a structure obtained after the target size D2 is changed in the method for preparing a semiconductor structure provided in an embodiment;

[0038] Fig.12a A schematic cross-sectional view of a structure corresponding to the step of obtaining a minimum breakdown voltage and a maximum diffusion width in a method for preparing a semiconductor structure provided in an embodiment;

[0039] Figure 12b for Fig.12a A schematic diagram of the structure in the plane formed by the first direction and the second direction;

[0040] Fig.13a A schematic cross-sectional view of a corresponding structure when obtaining a maximum breakdown voltage and a minimum diffusion width in a method for preparing a semiconductor structure provided in an embodiment;

[0041] Fig.13b for Fig.13a A schematic diagram of the structure in the plane formed by the first direction and the second direction;

[0042] Fig.14a A schematic cross-sectional view of a corresponding structure when ion implantation diffuses normally in a method for preparing a semiconductor structure provided in an embodiment;

[0043] Fig.14b for Fig.14a The structure is a schematic diagram of a plane formed by the first direction and the second direction.

[0044] Description of reference numerals:

[0045] 10. Substrate; 101. Base; 102. First type semiconductor layer; 11. Dielectric layer; 12. Mask strip; 13. Doping region; 131. First doping region; 132. Second doping region; 14. Electrical connection. DETAILED DESCRIPTION

[0046] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0048] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0049] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0050] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0051] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the present application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present application.

[0052] See also Figure 2 The present application provides a method for preparing a semiconductor test structure, including: step S102-step S108.

[0053] Step S102: providing a substrate 10.

[0054] In some embodiments, the substrate 10 includes a base 101 and a first-type semiconductor layer 102 located on the base 101 ; the doped region 13 is a second-type doped region.

[0055] In some embodiments, the first type is P-type and the second type is N-type; or the first type is N-type and the second type is P-type.

[0056] Specifically, the substrate 10 may include a word line structure and a capacitor contact structure, etc., which are not closely related to the invention of this solution and are therefore omitted.

[0057] The substrate 101 provides mechanical support for the first-type semiconductor layer 102 .

[0058] The first-type semiconductor layer 102 may be a single-layer structure or a multi-layer structure. For example, the semiconductor layer may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the first-type semiconductor layer 102 may also include substrates such as Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. Therefore, the type of the first-type semiconductor layer 102 should not limit the scope of protection of the present disclosure.

[0059] Step S104: forming a plurality of mask strips 12 spaced apart along a first direction and extending along a second direction on the top surface of the substrate 10; the substrate between two adjacent mask strips 12 is used to constitute an initial test area; two adjacent initial test areas are used to constitute an initial test structure; adjacent initial test structures are spaced apart along the first direction; the first direction and the second direction intersect and are parallel to the top surface of the substrate 10.

[0060] See also Figure 3 In some embodiments, step S104 further includes:

[0061] Step S1042 : forming a mask layer (not shown) on the top surface of the first-type semiconductor layer 102 .

[0062] See also Figure 3 , step S1044: patterning the mask layer to obtain a plurality of mask strips 12 that are spaced apart along the first direction and extend along the second direction.

[0063] For example, the dielectric layer may be formed of silicon dioxide (SiO2) or a material with a high-k dielectric constant. For example, the material of the dielectric layer includes aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3).

[0064] In this embodiment, the material of the mask layer includes polysilicon.

[0065] See also Figure 4-Figure 7 , step S106: using at least a plurality of mask strips 12 as masks, performing an ion implantation process into the initial test area to obtain a target test structure including two doping regions 13, wherein the ion implantation energies of different target test structures are the same and the doses are different.

[0066] In some embodiments, step S106 further includes:

[0067] Step S1062: forming an ion implantation mask above the initial test structure; using the ion implantation mask and a plurality of mask strips 12 as masks, a self-alignment process is adopted to perform an ion implantation process on the initial test structure to obtain a plurality of target test structures.

[0068] Step S1064 : after each target test structure is obtained, an electrical connection member 14 is disposed on the top surface of the doped region 13 .

[0069] See also Figure 4-Figure 5 , specifically, Figure 4As shown, the ion implantation process adopts a self-aligned process, which is placed after the etching mask strip 12, and the second type ions are implanted into the first type semiconductor layer 102 based on the same mask, which prevents the implantation deviation caused by the lithography alignment error, and does not require additional masks, so the process is simple. Figure 5 As shown, after performing the ion implantation process with a certain dose, a first doping region 131 and a second doping region 132 are formed in the first type semiconductor layer 102 and are spaced apart along the first direction. An electrical connector 14 is provided on the top surface of the doping region 13, wherein the electrical connector 14 is configured as follows: a first end A is connected to the first doping region 131, and a second end B is connected to the second doping region 132.

[0070] See also Figure 6-Figure 7 , Figure 6 Schematic diagram of multiple target test structures obtained by performing multiple ion implantation operations into the initial test structure, ensuring constant energy but increasing dose at each step. Figure 7 Schematic diagram after setting the electrical connector 14 for the target test structure.

[0071] Step S108: Determine a first target test association relationship between the implanted ion dose, diffusion width and breakdown voltage of different target test structures based on the implanted ion dose, diffusion width and breakdown voltage of multiple target test structures; the first target test association relationship is used to determine the actual diffusion width of the target test junction to be tested based on the actual implanted dose and actual breakdown voltage of the target test junction to be tested.

[0072] Please continue reading Figure 7 Specifically, the first doping region 131 and the second doping region 132 have opposite conductivity types to the first semiconductor layer 102, forming an NPN structure or a PNP structure. Any end of the electrical connector 14 is grounded to zero voltage, and the other end is subjected to a positive voltage scan, that is, the applied voltage value is gradually increased, and the test current value is read in real time until a critical breakdown occurs in the target test junction to be tested, and the test current value increases sharply, and the voltage value at this time is recorded as the breakdown voltage.

[0073] In some embodiments, the spacing between adjacent mask strips 12 is greater than or equal to a preset threshold.

[0074] Please continue reading Figure 7, D represents the spacing between adjacent mask strips 12, and is also the window size for performing the ion implantation process. It should be noted that it is required here that D is designed to be as large as possible to achieve the purpose of covering the diffusion width of different doses. W represents the diffusion width of the target test junction. When D is known, through the ion implantation process performed on multiple target test structures, data related to their implanted ion dose, diffusion width and breakdown voltage are collected to determine the first target test correlation relationship between the implanted ion dose, diffusion width and breakdown voltage of different target test structures. The first target test correlation relationship reflects the actual diffusion width of the target test junction to be tested under different actual dose conditions to determine the actual ion implantation range, reduce redundant repeated experiments and data analysis work in the subsequent device debugging process, and lay the foundation for subsequent optimization of device design and research work.

[0075] The semiconductor structure obtained after steps S102-S108 can be referred to Figure 7 In order to facilitate understanding of this application, Figure 7 This is an example of a semiconductor structure prepared by the preparation method of the present application. There may be other suitable examples of semiconductor structures prepared by the present application, and the present application does not limit them.

[0076] See also Figure 8 , the present application provides another method for preparing a semiconductor test structure, steps S202 to S208.

[0077] Step S202: providing a substrate 10.

[0078] In some embodiments, the substrate 10 includes a base 101 and a first-type semiconductor layer 102 on the base 101; the doped region 13 is a second-type doped region. The materials of the base 101 and the first-type semiconductor layer 102 are the same as those described above, and will not be described in detail here.

[0079] In some embodiments, the first type is P type and the second type is N type; or the first type is N type and the second type is P type. Different conductivity types are used to form a target test junction to be tested.

[0080] Step S204: forming a plurality of mask strips spaced apart along a first direction and extending along a second direction on the top surface of the substrate; the substrate between two adjacent mask strips is used to constitute an initial test area; two adjacent initial test areas are used to constitute an initial test structure; adjacent initial test structures are spaced apart along the first direction; the first direction and the second direction intersect and are parallel to the top surface of the substrate.

[0081] In some embodiments, step S204 further includes:

[0082] Step S2042: forming a mask layer (not shown) on the top surface of the first-type semiconductor layer 102;

[0083] Step S2044: patterning the mask layer to obtain a plurality of mask strips 12 spaced apart along the first direction and extending along the second direction. The mask strips 12 are used as a mask for performing an ion implantation process.

[0084] Step S206: Using at least a plurality of mask strips 12 as masks, perform an ion implantation process into the initial test area to obtain a target test structure including two doping regions 13, wherein different target test structures have the same implanted ion energy and dosage and different target sizes; the target size is the spacing between adjacent mask strips 12 along the first direction, or the length of the mask strips 12 along the first direction.

[0085] See also Fig. 9 Specifically, during ion implantation with the same energy and the same dose, this structure can also monitor implantation diffusion widths of various sizes simultaneously by changing the spacing between adjacent mask strips 12 or the length of the mask strips 12 along the first direction. D1 is used to represent that the target size is the spacing between adjacent mask strips along the first direction; D2 is used to represent that the target size is the length of the mask strips 12 along the first direction; and BV is used to represent the breakdown voltage (BV).

[0086] Step S208: Determine a second target test association relationship between the target sizes, diffusion widths and breakdown voltages of different target test structures based on the target sizes, diffusion widths and breakdown voltages of multiple target test structures; the second target test association relationship is used to determine the measured diffusion width of the target test junction to be tested based on the actual target size and actual breakdown voltage of the target test junction to be tested.

[0087] See also Figure 10-11 Specifically, by adjusting the target size D1 or D2 of the target test structure, the ion implantation process is performed on multiple target test structures with different target sizes, and data related to the implanted ion dose, diffusion width and breakdown voltage are collected to determine the second target test correlation relationship between the target size, diffusion width and breakdown voltage of different target test structures. Based on the original preparation method, this method controls the target size of the target test structure, such as D1 or D2, as an adjustable variable to achieve the purpose of simultaneously monitoring the ion implantation range corresponding to different implanted ion doses under multiple target sizes, broadening the diversity of semiconductor test structures and providing a theoretical basis for the regulation of subsequent devices.

[0088] See also Figure 12a-Figure 14bIn some embodiments, the target size is the spacing between adjacent mask strips 12 along the first direction; when the target size is maximum and adjacent doping regions are in contact, the minimum breakdown voltage (BVmin) and the maximum diffusion width (Wmax) are obtained; when the target size is minimum, the maximum breakdown voltage (BVmax) and the minimum diffusion width (Wmin) are obtained; the maximum diffusion width (Wmax) and the minimum diffusion width (Wmin) are used to determine whether the measured diffusion width of the target test junction to be tested is abnormal.

[0089] Specifically, Fig.12a As shown, D1 is the maximum value, which means that the window size for performing the ion implantation process can cover the diffusion width of the target test junction introduced by different doses. When the implanted ion dose makes the first doping region 131 contact the second doping region 132, the voltage value measured in this state is recorded as the minimum breakdown voltage (BVmin) and the maximum diffusion width (Wmax). Figure 12b It is a schematic diagram of the structure on a plane formed by the first direction and the second direction.

[0090] like Fig.13a As shown, when D1 is minimum and the size of the doped region 13 along the first direction is substantially consistent with D1 after the ion implantation process, the voltage value measured in this state is recorded as the maximum breakdown voltage (BVmax) and the minimum diffusion width (Wmin). Fig.13b It is a schematic diagram of the structure on a plane formed by the first direction and the second direction.

[0091] Normal diffusion width is Fig.14a As shown, the breakdown voltage and the diffusion width are between the two extreme values ​​mentioned above. The diffusion width is directly monitored according to the test results to see if it is within the expected range. If it is within the range, the second target test association relationship is determined, and then the second target test association relationship is used to determine the measured diffusion width of the target test junction to be tested according to the actual target size and the actual breakdown voltage of the target test junction to be tested, and the difference between the actual diffusion range and the expected value is checked to improve the device debugging efficiency. Fig.14b It is a schematic diagram of the structure on a plane formed by the first direction and the second direction.

[0092] Please refer to Figures 12-14. In some embodiments, the target size is the length of the mask strip 12 along the first direction; when the target size is the minimum value and adjacent doping regions are in contact, the minimum value of the breakdown voltage (BVmin) and the maximum value of the diffusion width (Wmax) are obtained; when the target size is the maximum value, the maximum value of the breakdown voltage (BVmin) and the minimum value of the diffusion width (Wmin) are obtained; the maximum value of the diffusion width (Wmax) and the minimum value of the diffusion width (Wmin) are used to determine whether the measured diffusion width of the target test junction to be tested is abnormal.

[0093] For example, the specific implementation scheme corresponding to the target size D2 is consistent with the target size D1, and will not be repeated here.

[0094] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0095] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor test structure, characterized in that: include: providing a substrate; forming a plurality of mask strips on the top surface of the substrate, which are spaced apart along a first direction and extend along a second direction; The substrate between two adjacent mask strips is used to form an initial test area; Two adjacent initial test areas are used to form an initial test structure; the adjacent initial test structures are spaced apart along the first direction; the first direction and the second direction intersect and are both parallel to the top surface of the substrate; At least using the plurality of mask strips as masks, performing an ion implantation process into the initial test region to obtain a target test structure including two doping regions, wherein implanted ions of different target test structures have the same energy and different doses; According to the implanted ion dose, diffusion width and breakdown voltage of the multiple target test structures, a first target test association relationship between the implanted ion dose, diffusion width and breakdown voltage of different target test structures is determined; the first target test association relationship is used to determine the measured diffusion width of the target test junction to be tested according to the actual implanted ion dose and actual breakdown voltage of the target test junction to be tested.

2. The method for preparing a semiconductor test structure according to claim 1, characterized in that: The substrate comprises a base and a first-type semiconductor layer located on the base; the doped region is a second-type doped region; Forming the plurality of mask strips on the top surface of the substrate comprises: forming a mask layer on the top surface of the first-type semiconductor layer; The mask layer is patterned to obtain a plurality of mask strips that are spaced apart along the first direction and extend along the second direction.

3. The method for preparing a semiconductor test structure according to claim 1, characterized in that: Performing an ion implantation process on the initial test area includes: forming an ion implantation mask over the initial test structure; The ion implantation mask and the plurality of mask strips are used as mask plates, and a self-alignment process is adopted to perform an ion implantation process on the initial test structure to obtain the plurality of target test structures.

4. The method for preparing a semiconductor test structure according to claim 2, characterized in that: The first type is P type, and the second type is N type; or The first type is N type, and the second type is P type.

5. The method for preparing a semiconductor test structure according to any one of claims 1 to 4, characterized in that: The spacing between adjacent mask strips is greater than or equal to a preset threshold.

6. A method for preparing a semiconductor test structure, characterized in that: include: providing a substrate; forming a plurality of mask strips on the top surface of the substrate, which are spaced apart along a first direction and extend along a second direction; The substrate between two adjacent mask strips is used to form an initial test area; Two adjacent initial test areas are used to form an initial test structure; Adjacent initial test structures are distributed at intervals along the first direction; the first direction and the second direction intersect and are both parallel to the top surface of the substrate; At least using the plurality of mask strips as masks, performing an ion implantation process into the initial test area to obtain a target test structure including two doped regions, wherein the implanted ion energies and doses of different target test structures are the same and the target sizes are different; the target size is the spacing between adjacent mask strips along the first direction, or the length of the mask strips along the first direction; According to the target sizes, diffusion widths and breakdown voltages of the multiple target test structures, a second target test association relationship between the target sizes, diffusion widths and breakdown voltages of different target test structures is determined; the second target test association relationship is used to determine the measured diffusion width of the target test junction to be tested based on the actual target size and actual breakdown voltage of the target test junction to be tested.

7. The method for preparing a semiconductor test structure according to claim 6, characterized in that: The substrate comprises a base and a first-type semiconductor layer located on the base; the doped region is a second-type doped region; Forming the plurality of mask strips on the top surface of the substrate comprises: forming a mask layer on the top surface of the first-type semiconductor layer; The mask layer is patterned to obtain a plurality of mask strips that are spaced apart along the first direction and extend along the second direction.

8. The method for preparing a semiconductor test structure according to claim 7, characterized in that: The first type is P type, and the second type is N type; or The first type is N type, and the second type is P type.

9. The method for preparing a semiconductor test structure according to any one of claims 6 to 8, characterized in that: The target size is the spacing between adjacent mask strips along the first direction; When the target size is at a maximum value and adjacent doping regions are in contact, obtaining a minimum value of the breakdown voltage and a maximum value of the diffusion width; When the target size is the minimum value, the maximum value of the breakdown voltage and the minimum value of the diffusion width are obtained; the maximum value of the diffusion width and the minimum value of the diffusion width are used to determine whether the measured diffusion width of the target test junction to be tested is abnormal.

10. The method for preparing a semiconductor test structure according to any one of claims 6 to 8, characterized in that: The target size is the length of the mask strip along the first direction; When the target size is at a minimum value and adjacent doping regions are in contact, obtaining a minimum value of the breakdown voltage and a maximum value of the diffusion width; When the target size is at a maximum value, the maximum value of the breakdown voltage and the minimum value of the diffusion width are obtained; the maximum value of the diffusion width and the minimum value of the diffusion width are used to determine whether the measured diffusion width of the target test junction to be tested is abnormal.

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