MIM capacitor and manufacturing method thereof

Abstract

The invention provides an MIM capacitor and a manufacturing method thereof. The method comprises the following steps: forming a first interlayer dielectric layer and forming a metal intermediate layer embedded into the front surface of the first interlayer dielectric layer; forming a diffusion barrier layer covering the metal interposer; forming a second interlayer dielectric layer and forming a capacitor groove in the second interlayer dielectric layer; forming an MIM capacitor in the capacitor groove, wherein the MIM capacitor conformally covers the inner wall of the capacitor groove and encloses an accommodating space with a top opening in the capacitor groove; and forming an upper polar plate connecting part and an interlayer connecting part, the upper polar plate connecting part being located in the accommodating space, and the interlayer connecting part penetrating through the second interlayer dielectric layer. According to the 2.5 D three-dimensional MIM capacitor, interconnection of the lower pole plate metal layer is carried out by introducing the metal intermediate layer, the pole plate structure is optimized to obtain the three-dimensional MIM capacitor, the upper pole plate metal layer is subjected to a Damascus copper interconnection process, the 2.5 D three-dimensional MIM capacitor structure embedded with the metal interconnection layer is finally obtained, the occupied area is smaller under the same capacitance requirement, and the integration degree is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a MIM capacitor and a manufacturing method thereof. Background Art

[0002] MIM capacitor (Metal-Insulator-Metal Capacitor) is a passive component widely used in integrated circuits. It consists of two metal layers and an insulating layer sandwiched in between. The main functions and characteristics of MIM capacitors are as follows:

[0003] (1) Capacitor function: MIM capacitors are mainly used to store charge and energy in integrated circuits. They can be used as components of filters, oscillators, timing circuits, etc. In analog and radio frequency (RF) circuits, MIM capacitors are particularly important due to their stable capacitance and low parasitic effects.

[0004] (2) Precise capacitance value: The capacitance value of MIM capacitors is relatively precise and does not change with bias voltage, which makes them very useful in applications that require precise control of capacitance value.

[0005] (3) Low parasitic effects: MIM capacitors have lower parasitic capacitance and parasitic inductance, which is particularly important for high-frequency applications because parasitic effects can affect the performance of the circuit.

[0006] (4) Structural features: MIM capacitors are usually composed of two layers of metal, with a layer of insulating material (such as an oxide layer) in between. The capacitance value can be adjusted by changing the area of ​​the metal layer and the thickness of the insulating layer.

[0007] (5) High K MIM capacitor: High K MIM capacitor refers to a MIM capacitor that uses a high dielectric constant (K value) material as the insulating layer. High K materials can significantly increase the capacitance value while reducing the device area. This type of capacitor is very useful in applications that require high capacitance density, especially under the miniaturization and high integration requirements of integrated circuits.

[0008] (6) Performance improvement: By optimizing the design of MIM capacitors, such as reducing the thickness of the dielectric layer or using a laminated metal structure, the capacitance per unit area can be further increased while maintaining or improving other performance indicators, such as the Q value (quality factor).

[0009] (7) Application areas: MIM capacitors are used in a variety of integrated circuits, including but not limited to analog integrated circuits, radio frequency integrated circuits, data converters, power management chips, etc.

[0010] In summary, MIM capacitors play a key role in integrated circuits, especially in analog and RF circuit design. The emergence of high-K MIM capacitors makes it possible to achieve higher capacitance density in a limited space, which is of great significance to the development of integrated circuit technology.

[0011] With the demand for higher integration, how to further make MIM capacitors occupy a smaller area under the same capacitance requirement has become an important technical problem that technical personnel in this field need to solve urgently.

[0012] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0013] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a MIM capacitor and a method for manufacturing the same, so as to solve the problem in the prior art that the integration level needs to be further improved.

[0014] To achieve the above object and other related objects, the present invention provides a method for manufacturing a MIM capacitor, comprising the following steps:

[0015] Providing a semiconductor substrate, and forming a first interlayer dielectric layer on the semiconductor substrate;

[0016] forming a metal interposer embedded in the front side of the first interlayer dielectric layer;

[0017] forming a diffusion barrier layer covering the metal interposer;

[0018] forming a second interlayer dielectric layer on the first interlayer dielectric layer, wherein the second interlayer dielectric layer covers the diffusion barrier layer;

[0019] forming a capacitor trench in the second interlayer dielectric layer, wherein the diffusion barrier layer is exposed at the bottom of the capacitor trench;

[0020] A MIM capacitor is formed in the capacitor groove, wherein the MIM capacitor comprises a lower plate metal layer, an isolation layer and an upper plate metal layer stacked in sequence, the MIM capacitor conformally covers the inner wall of the capacitor groove and encloses a receiving space with a top opening in the capacitor groove, and the bottom surface of the lower plate metal layer is connected to the diffusion barrier layer;

[0021] An upper plate connection portion and an interlayer connection portion are formed, wherein the upper plate connection portion is located in the receiving space, the interlayer connection portion penetrates the second interlayer dielectric layer, and the bottom end of the interlayer connection portion is connected to the diffusion barrier layer.

[0022] Optionally, there are multiple capacitor grooves, and the multiple capacitor grooves are spaced apart and distributed in the second interlayer dielectric layer. A MIM capacitor is correspondingly arranged in each capacitor groove, and the lower plate metal layers of the multiple MIM capacitors are connected in parallel through the diffusion barrier layer and the metal intermediate layer.

[0023] Optionally, forming the MIM capacitor, the upper plate connection portion and the interlayer connection portion comprises the following steps:

[0024] Depositing a lower plate metal layer, an isolation layer and an upper plate metal layer in sequence to obtain a laminated structure, wherein the laminated structure conformally covers the top surface of the second interlayer dielectric layer and the inner wall of the capacitor groove, and encloses the receiving space in the capacitor groove;

[0025] Removing a predetermined area of ​​the stacked structure to expose the top surface of the second interlayer dielectric layer;

[0026] forming an interlayer connection groove in the second interlayer dielectric layer, wherein the bottom of the interlayer connection groove exposes the diffusion barrier layer;

[0027] forming an upper metal layer, wherein the upper metal layer covers the exposed surface of the second interlayer dielectric layer and fills the capacitor trench and the interlayer connection trench;

[0028] Performing a planarization process until the second interlayer dielectric layer is exposed;

[0029] Among them, the part of the stacked structure remaining in the receiving space constitutes the MIM capacitor, the part of the upper metal layer remaining in the capacitor groove constitutes the upper electrode connecting part, and the part of the upper metal layer remaining in the interlayer connecting groove constitutes the interlayer connecting part.

[0030] Optionally, the method further includes forming a rewiring layer on the second interlayer dielectric layer, and the upper plate connection portion and the interlayer connection portion are both electrically connected to the rewiring layer.

[0031] Optionally, both the first interlayer dielectric layer and the second interlayer dielectric layer include an etch stop layer and a low-K dielectric layer located on the etch stop layer.

[0032] Optionally, the isolation layer of the MIM capacitor includes a high-K dielectric layer.

[0033] The present invention also provides a MIM capacitor, comprising:

[0034] Semiconductor substrate;

[0035] A first interlayer dielectric layer, located on the semiconductor substrate;

[0036] A metal interposer layer embedded in the front surface of the first interlayer dielectric layer;

[0037] a diffusion barrier layer covering the metal interposer;

[0038] a second interlayer dielectric layer, located on the first interlayer dielectric layer and covering the diffusion barrier layer;

[0039] A capacitor trench is located in the second interlayer dielectric layer;

[0040] A MIM capacitor is located in the capacitor groove and includes a lower plate metal layer, an isolation layer and an upper plate metal layer stacked in sequence, the MIM capacitor conformally covers the inner wall of the capacitor groove and encloses a receiving space with a top opening in the capacitor groove, and the bottom surface of the lower plate metal layer is connected to the diffusion barrier layer;

[0041] An upper plate connecting portion is located in the receiving space;

[0042] The interlayer connection portion penetrates through the second interlayer dielectric layer, and the bottom end of the interlayer connection portion is connected to the diffusion barrier layer.

[0043] Optionally, there are multiple capacitor grooves, and the multiple capacitor grooves are spaced apart and distributed in the second interlayer dielectric layer. A MIM capacitor is correspondingly arranged in each capacitor groove, and the lower plate metal layers of the multiple MIM capacitors are connected in parallel through the diffusion barrier layer and the metal intermediate layer.

[0044] Optionally, a rewiring layer is further included on the second interlayer dielectric layer, and the upper plate connection portion and the interlayer connection portion are both electrically connected to the rewiring layer.

[0045] Optionally, both the first interlayer dielectric layer and the second interlayer dielectric layer include an etch stop layer and a low-K dielectric layer located on the etch stop layer.

[0046] Optionally, the isolation layer of the MIM capacitor includes a high-K dielectric layer.

[0047] Optionally, the material of the metal intermediate layer includes copper, the material of the diffusion barrier layer includes TaN, the material of the lower plate metal layer includes TiN, and the material of the upper plate metal layer includes TiN.

[0048] As described above, the method for making a MIM capacitor of the present invention includes the following steps: forming a first interlayer dielectric layer on a semiconductor substrate, forming a metal interlayer embedded in the front of the first interlayer dielectric layer, forming a diffusion barrier layer covering the metal interlayer, forming a second interlayer dielectric layer, forming a capacitor groove in the second interlayer dielectric layer, forming a MIM capacitor in the capacitor groove, the MIM capacitor conformally covers the inner wall of the capacitor groove and encloses a receiving space with a top opening in the capacitor groove, forming an upper plate connection part and an interlayer connection part, the upper plate connection part is located in the receiving space, and the interlayer connection part runs through the second interlayer dielectric layer. The present invention interconnects the metal layer of the lower plate of the MIM capacitor by introducing a metal interlayer, and optimizes the plate structure to obtain a three-dimensional MIM capacitor. The upper plate metal layer is interconnected by a Damascus copper process, and finally a 2.5D three-dimensional MIM capacitor structure embedded in the metal interconnection layer is obtained, which occupies a smaller area under the same capacitance requirement, which is conducive to improving the integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 Shown is a schematic diagram of a MIM capacitor structure.

[0050] Figure 2 FIG. 4 is a process flow chart showing a method for manufacturing a MIM capacitor according to the present invention.

[0051] Figure 3 It is a schematic diagram showing the structure after the first interlayer dielectric layer is formed in the manufacturing method of the MIM capacitor of the present invention.

[0052] Figure 4 The method for making a MIM capacitor of the present invention is shown as forming a metal interlayer embedded in the front side of the first interlayer dielectric layer.

[0053] Figure 5 It is a schematic structural diagram of the method for manufacturing the MIM capacitor of the present invention after a barrier material layer is deposited on the first interlayer dielectric layer.

[0054] Figure 6 It is a schematic diagram showing the structure after removing unnecessary parts of the barrier material layer according to the manufacturing method of the MIM capacitor of the present invention.

[0055] Figure 7 It is a schematic structural diagram showing the structure presented after forming a second interlayer dielectric layer on the first interlayer dielectric layer according to the manufacturing method of the MIM capacitor of the present invention.

[0056] Figure 8 It is a schematic structural diagram showing the structure after forming a capacitor trench in the second interlayer dielectric layer according to the manufacturing method of the MIM capacitor of the present invention.

[0057] Fig. 9The structure schematic diagram is shown after the manufacturing method of the MIM capacitor of the present invention sequentially deposits a lower plate metal layer, an isolation layer and an upper plate metal layer to obtain a laminated structure.

[0058] Fig.10 It is a schematic diagram showing the structure presented after removing the stacked structure in a preset area to expose the top surface of the second interlayer dielectric layer in the manufacturing method of the MIM capacitor of the present invention.

[0059] Fig.11 It is a schematic diagram showing the structure after the upper metal layer is formed according to the manufacturing method of the MIM capacitor of the present invention.

[0060] Fig.12 It is a schematic diagram showing the structure of the MIM capacitor after the planarization treatment according to the manufacturing method of the present invention.

[0061] Fig.13 It is a schematic diagram showing the structure after the rewiring layer is formed according to the manufacturing method of the MIM capacitor of the present invention.

[0062] Description of Reference Numerals

[0063] 101 Lower plate metal layer

[0064] 102 Isolation Layer

[0065] 103 Upper plate metal layer

[0066] Steps S1 to S7

[0067] 2. First interlayer dielectric layer

[0068] 201 Etch stop layer

[0069] 202 Low K dielectric layer

[0070] 3 Metal interposer

[0071] 4 Diffusion barrier

[0072] 5 Second interlayer dielectric layer

[0073] 501 Etch stop layer

[0074] 502 Low K dielectric layer

[0075] 6 Capacitor Grooves

[0076] 7 Lower plate metal layer

[0077] 8 Isolation layer

[0078] 9 Upper plate metal layer

[0079] 10 Interlayer connection groove

[0080] 11 Upper Metal Layer

[0081] 12 Upper metal layer

[0082] 13 Upper plate connection

[0083] 14 Interlayer connection

[0084] 15 Dielectric layer

[0085] 1501 Etch stop layer

[0086] 1502 Low K dielectric layer

[0087] 16 Plug

[0088] 17 Metal Connection DETAILED DESCRIPTION

[0089] like Figure 1 As shown, a MIM capacitor structure includes a lower plate metal layer 101, an isolation layer 102 and an upper plate metal layer 103 stacked from bottom to top, the lower plate metal layer 101 and the upper plate metal layer 103 are both horizontally extended, and the area occupied by the MIM capacitor is the lateral area of ​​the space, which is difficult to meet the needs of further integration. The present invention can achieve a smaller occupied area under the same capacitance requirement by optimizing the plate structure and the interconnection structure.

[0090] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0091] See also Figures 1 to 13 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0092] The present invention provides a method for manufacturing a MIM capacitor. Figure 2 , shown as a process flow chart of the method, comprising the following steps:

[0093] S1: providing a semiconductor substrate, and forming a first interlayer dielectric layer on the semiconductor substrate;

[0094] S2: forming a metal interposer embedded in the front side of the first interlayer dielectric layer;

[0095] S3: forming a diffusion barrier layer covering the metal interposer;

[0096] S4: forming a second interlayer dielectric layer on the first interlayer dielectric layer, wherein the second interlayer dielectric layer covers the diffusion barrier layer;

[0097] S5: forming a capacitor trench in the second interlayer dielectric layer, wherein the diffusion barrier layer is exposed at the bottom of the capacitor trench;

[0098] S6: forming a MIM capacitor in the capacitor groove, wherein the MIM capacitor comprises a lower plate metal layer, an isolation layer and an upper plate metal layer stacked in sequence, wherein the MIM capacitor conformally covers the inner wall of the capacitor groove and encloses a receiving space with a top opening in the capacitor groove, and the bottom surface of the lower plate metal layer is connected to the diffusion barrier layer;

[0099] S7: forming an upper electrode plate connection portion and an interlayer connection portion, wherein the upper electrode plate connection portion is located in the receiving space, the interlayer connection portion penetrates the second interlayer dielectric layer, and the bottom end of the interlayer connection portion is connected to the diffusion barrier layer.

[0100] The above steps are described in detail below with reference to the structure diagram.

[0101] First see Figure 3 , perform the step S1: provide a semiconductor substrate, and form a first interlayer dielectric layer 2 on the semiconductor substrate.

[0102] Specifically, the semiconductor substrate may be silicon, silicon on insulator or other suitable semiconductor substrates, in which the required semiconductor elements may be prefabricated, and the surface of the semiconductor substrate may be provided with a metal layer. For the sake of simplicity, the semiconductor substrate and its surface metal layer are not shown in the drawings.

[0103] As an example, the first interlayer dielectric layer 2 includes an etch stop layer 201 and a low-K dielectric layer 202 located on the etch stop layer 201 .

[0104] Specifically, the etch stop layer 201 (ESL) is used to control the depth of etching in the subsequent etching step to ensure that the etching stops automatically after reaching a predetermined depth, thereby preventing excessive etching from damaging the underlying material layer. The etch stop layer is usually made of materials with specific etching properties, such as silicon nitride (Si3N4), silicon oxide layer (SiO2) or other inorganic or organic materials. The selection of these materials depends on the required etching depth, etching selectivity and compatibility with surrounding materials. In some embodiments, the etch stop layer 201 uses SiCN, which helps to achieve accurate, efficient and reliable etching.

[0105] Specifically, low-k dielectric material refers to an insulating material with a lower dielectric constant (K). In semiconductor devices, the dielectric constant is a parameter that measures the ability of a material to store charge in an electric field. The dielectric constant of low-k dielectrics is lower than that of traditional silicon oxide layers (SiO2), usually defined as K<4.0. When low-k dielectrics are used in integrated circuits (ICs) as insulating materials for interconnect layers, the interconnect capacitance can be reduced, thereby reducing the power consumption of the integrated circuit and increasing the signal transmission speed. This is because a lower dielectric constant means that the material stores less charge under the same electric field, thereby reducing the capacitance effect. There are many types of low-k dielectrics, including organic low-k materials, inorganic low-k materials, nanoporous low-k materials, etc. These materials achieve lower dielectric constants through different chemical compositions and microstructure designs. However, low-k dielectrics also bring some challenges, such as low mechanical strength, reliability issues, and compatibility with existing processes. Therefore, in practical applications, it is necessary to comprehensively consider the performance and cost of low-k dielectrics, as well as the integration process with other materials to achieve optimal device performance, which is not specifically limited in the present invention.

[0106] Please see again Figure 4 , perform the step S2: forming a metal interlayer 3 embedded in the front side of the first interlayer dielectric layer 2.

[0107] In one embodiment, the material of the metal intermediary layer 3 includes copper, and manufacturing the metal intermediary layer 3 includes the following steps:

[0108] (1) depositing a buffer layer such as a TEOS layer on the first interlayer dielectric layer 2;

[0109] (2) depositing a hard mask layer such as a TiN layer on the buffer layer;

[0110] (3) forming an anti-reflective coating such as a BARC layer on the hard mask layer;

[0111] (4) forming a photoresist layer on the anti-reflective coating;

[0112] (5) patterning the hard mask layer by using processes such as exposure, development, and etching to open an area where the MIM capacitor needs to be fabricated;

[0113] (6) etching the first interlayer dielectric layer 2 based on the patterned hard mask layer to obtain a groove of a preset depth;

[0114] (7) sequentially depositing a barrier layer and a seed layer in the groove region;

[0115] (8) subjecting the silicon wafer having the barrier layer and the seed layer to a copper chemical electroplating process;

[0116] (9) Flatten the entire pattern by chemical mechanical polishing.

[0117] Please see again Figure 5-Figure 6 , performing the step S3: forming a diffusion barrier layer 4 covering the metal interposer 3 .

[0118] Specifically, the diffusion barrier layer (Barrier Layer) is used to prevent or limit the mutual diffusion between different materials to ensure the performance and reliability of the device. In one embodiment, the material of the diffusion barrier layer 4 includes TaN.

[0119] As an example, a barrier material layer 4 (eg, Figure 5 As shown), then remove the unnecessary part of the barrier material layer 4 by photolithography and etching process, and retain the part of the barrier material layer 4 covering the metal intermediate layer 3 (as shown Figure 6 shown).

[0120] Please see again Figure 7 , performing the step S4: forming a second interlayer dielectric layer 5 on the first interlayer dielectric layer 2 , wherein the second interlayer dielectric layer 5 covers the diffusion barrier layer 4 .

[0121] As an example, the second interlayer dielectric layer 5 includes an etch stop layer 501 and a low-K dielectric layer 502 located on the etch stop layer 501 .

[0122] Please see again Figure 8 , performing the step S5: forming a capacitor trench 6 in the second interlayer dielectric layer 5 , wherein the bottom of the capacitor trench 6 exposes the diffusion barrier layer 4 .

[0123] In one embodiment, manufacturing the capacitor trench 6 includes the following steps:

[0124] (1) depositing a buffer layer such as a TEOS layer on the second interlayer dielectric layer 5;

[0125] (2) depositing a hard mask layer such as a TiN layer on the buffer layer;

[0126] (3) forming an anti-reflective coating such as a BARC layer on the hard mask layer;

[0127] (4) forming a photoresist layer on the anti-reflective coating;

[0128] (5) patterning the hard mask layer by using processes such as exposure, development, and etching to open an area where a capacitor trench needs to be formed;

[0129] (6) Etching the second interlayer dielectric layer 5 based on the patterned hard mask layer to obtain a capacitor trench 6 with a preset depth.

[0130] In some embodiments, there are multiple capacitor trenches 6 , and the multiple capacitor trenches 6 are distributed in the second interlayer dielectric layer 5 at intervals.

[0131] Then, the step S6 and the step S7 are performed to obtain the MIM capacitor 12 , the upper plate connecting portion 13 and the interlayer connecting portion 14 .

[0132] In one embodiment, see Figures 9 to 12 The formation of the MIM capacitor 12, the upper plate connection portion 13 and the interlayer connection portion 14 includes the following steps:

[0133] like Fig. 9 As shown, the lower plate metal layer 7, the isolation layer 8 and the upper plate metal layer 9 are deposited in sequence to obtain a laminated structure, which conformally covers the top surface of the second interlayer dielectric layer 5 and the inner wall of the capacitor groove 6, and encloses a receiving space with a top opening in the capacitor groove 6.

[0134] In some embodiments, the material of the lower plate metal layer 7 includes TiN, and the material of the upper plate metal layer 9 includes TiN.

[0135] In some embodiments, the isolation layer 8 includes a high-k dielectric layer, wherein the high-k dielectric refers to an insulating material with a higher dielectric constant, which is usually higher than the traditional silicon oxide layer (SiO2). When it is used as the isolation layer of the MIM capacitor, the capacitance value can be significantly increased while reducing the area of ​​the device. Commonly used high-k materials include H f O2 (hafnium oxide), ZrO2 (zirconium oxide), Ta2O5 (tantalum oxide), etc. can be selected according to actual needs and are not specifically limited in the present invention.

[0136] like Fig.10As shown, the stacked structure in a preset area is removed by processes such as photolithography and etching to expose the top surface of the second interlayer dielectric layer 5, and the preset area includes an area where an interlayer connection groove is to be formed, and then an interlayer connection groove 10 is formed in the second interlayer dielectric layer 5 by processes such as photolithography and etching, and the bottom of the interlayer connection groove 10 exposes the diffusion barrier layer 4.

[0137] like Fig.11 As shown, an upper metal layer 11 is formed, and the upper metal layer 11 covers the exposed surface of the second interlayer dielectric layer 5 and fills the capacitor groove 6 and the interlayer connection groove 10. In one embodiment, the material of the upper metal layer 11 includes copper, and the upper metal layer 11 is obtained by sequentially depositing a barrier layer and a seed layer in the groove area, and subjecting the silicon wafer having the barrier layer and the seed layer to a copper chemical electroplating process.

[0138] like Fig.12 As shown, a planarization process is performed by chemical mechanical polishing or other suitable methods until the second interlayer dielectric layer 5 is exposed, wherein the portion of the stacked structure remaining in the capacitor groove 6 constitutes the MIM capacitor 12, the bottom surface of the lower electrode metal layer 7 of the MIM capacitor 12 is connected to the diffusion barrier layer 4, the portion of the upper metal layer 11 remaining in the accommodating space constitutes the upper electrode connecting portion 13, which is used to connect the upper electrode metal layer 9 of the MIM capacitor 12, the portion of the upper metal layer 11 remaining in the interlayer connection groove 10 constitutes the interlayer connecting portion 14, the interlayer connecting portion 13 passes through the second interlayer dielectric layer 5, and the bottom end of the interlayer connecting portion 13 is connected to the diffusion barrier layer 4.

[0139] Specifically, since the MIM capacitor 12 conformally covers the inner wall of the capacitor groove 6 and encloses a receiving space with a top opening in the capacitor groove 6, the substrate structure of the MIM capacitor 12 is no longer flat, and not only occupies the lateral space but also the longitudinal space to form a three-dimensional structure. Under the same capacitance requirement, it occupies a smaller area, which is conducive to improving the integration.

[0140] Specifically, when there are multiple capacitor grooves 6 , one MIM capacitor 12 is correspondingly disposed in each capacitor groove 6 , and the bottom plate metal layers 7 of multiple MIM capacitors 12 are connected in parallel through the diffusion barrier layer 4 and the metal intermediate layer 3 .

[0141] It should be pointed out that, compared with the MIM capacitor with a flat plate structure, the MIM capacitor of the present invention can produce more MIM capacitors when occupying the same lateral area, and the capacitance value of a single MIM capacitor is larger. By further connecting multiple MIM capacitors with a three-dimensional structure in parallel, the capacitance value under the same area can be greatly increased, or the occupied area can be greatly reduced under the same capacitance requirements, thereby greatly improving the integration. In addition, the upper plate connection portion 13 can be made in the receiving space surrounded by the MIM capacitor, and the final result is a 2.5D three-dimensional MIM capacitor structure embedded in the metal interconnect layer, which has a higher integration.

[0142] In some embodiments, see Fig.13 , further comprising the step of forming a rewiring layer on the second interlayer dielectric layer 5, wherein the upper plate connection portion 13 and the interlayer connection portion 14 are both electrically connected to the rewiring layer.

[0143] As an example, the rewiring layer includes a dielectric layer 15 and a plug 16 and a metal connection 17 embedded in the dielectric layer 15 . The dielectric layer 15 includes an etch stop layer 1501 and a low-K dielectric layer 1502 located on the etch stop layer 1501 .

[0144] In other embodiments, the rewiring layer may also include more dielectric layers and more metal connection layers as required.

[0145] Specifically, when there are multiple MIM capacitors 12 , the upper plate metal layers 9 of the multiple MIM capacitors 12 are connected in parallel via multiple corresponding upper plate connecting portions 13 and the rewiring layer.

[0146] Thus, a MIM capacitor is manufactured, which includes a semiconductor substrate, a first interlayer dielectric layer 2, a metal interlayer 3, a diffusion barrier layer 4, a second interlayer dielectric layer 5, a capacitor groove 6, a MIM capacitor 12, an upper plate connection portion 13 and an interlayer connection portion 14, wherein the first interlayer dielectric layer 2 is located on the semiconductor substrate, the metal interlayer 3 is embedded in the front of the first interlayer dielectric layer 2, the diffusion barrier layer 4 covers the metal interlayer 3, the second interlayer dielectric layer 5 is located on the first interlayer dielectric layer 2 and covers the diffusion barrier layer 4, the capacitor groove 6, the MIM capacitor 12, the upper plate connection portion 13 and the ... The groove 6 is located in the second interlayer dielectric layer 5, the MIM capacitor 12 is located in the capacitor groove 6 and includes a lower plate metal layer 7, an isolation layer 8 and an upper plate metal layer 9 stacked in sequence, the MIM capacitor 12 conformally covers the inner wall of the capacitor groove 6 and encloses a receiving space with a top opening in the capacitor groove 6, the bottom surface of the lower plate metal layer 7 is connected to the diffusion barrier layer 4, the upper plate connecting part 13 is located in the receiving space, the interlayer connecting part 14 passes through the second interlayer dielectric layer 5, and the bottom end of the interlayer connecting part 14 is connected to the diffusion barrier layer 4.

[0147] In some embodiments, the number of the capacitor grooves 6 is multiple, and the multiple capacitor grooves 6 are spaced apart and distributed in the second interlayer dielectric layer 5. A MIM capacitor 12 is correspondingly arranged in each of the capacitor grooves 6, and the lower electrode metal layers 7 of the multiple MIM capacitors 12 are connected in parallel through the diffusion barrier layer 4 and the metal intermediate layer 3.

[0148] In some embodiments, the MIM capacitor further includes a rewiring layer located on the second interlayer dielectric layer 5 , and the upper plate connection portion 13 and the interlayer connection portion 14 are both electrically connected to the rewiring layer.

[0149] In some embodiments, both the first interlayer dielectric layer 2 and the second interlayer dielectric layer 5 include an etch stop layer and a low-K dielectric layer located on the etch stop layer.

[0150] In some embodiments, the isolation layer of the MIM capacitor 12 includes a high-K dielectric layer.

[0151] In some embodiments, the material of the metal intermediate layer 3 includes copper, the material of the diffusion barrier layer 4 includes TaN, the material of the bottom plate metal layer 7 includes TiN, and the material of the top plate metal layer 9 includes TiN.

[0152] In summary, the method for making a MIM capacitor of the present invention comprises the following steps: forming a first interlayer dielectric layer on a semiconductor substrate, forming a metal interlayer embedded in the front of the first interlayer dielectric layer, forming a diffusion barrier layer covering the metal interlayer, forming a second interlayer dielectric layer, forming a capacitor groove in the second interlayer dielectric layer, forming a MIM capacitor in the capacitor groove, the MIM capacitor conformally covers the inner wall of the capacitor groove and encloses a receiving space with a top opening in the capacitor groove, forming an upper plate connection part and an interlayer connection part, the upper plate connection part is located in the receiving space, and the interlayer connection part runs through the second interlayer dielectric layer. The present invention interconnects the metal layer of the lower plate of the MIM capacitor by introducing a metal interlayer, and optimizes the plate structure to obtain a three-dimensional MIM capacitor. The upper plate metal layer is interconnected by a Damascus copper process, and finally a 2.5D three-dimensional MIM capacitor structure embedded in the metal interconnection layer is obtained, which occupies a smaller area under the same capacitance requirement, which is conducive to improving the integration. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0153] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a MIM capacitor, characterized in that: The following steps are involved: Providing a semiconductor substrate, and forming a first interlayer dielectric layer on the semiconductor substrate; forming a metal interposer embedded in the front side of the first interlayer dielectric layer; forming a diffusion barrier layer covering the metal interposer; forming a second interlayer dielectric layer on the first interlayer dielectric layer, wherein the second interlayer dielectric layer covers the diffusion barrier layer; forming a capacitor trench in the second interlayer dielectric layer, wherein the diffusion barrier layer is exposed at the bottom of the capacitor trench; A MIM capacitor is formed in the capacitor groove, wherein the MIM capacitor comprises a lower plate metal layer, an isolation layer and an upper plate metal layer stacked in sequence, the MIM capacitor conformally covers the inner wall of the capacitor groove and encloses a receiving space with a top opening in the capacitor groove, and the bottom surface of the lower plate metal layer is connected to the diffusion barrier layer; An upper plate connection portion and an interlayer connection portion are formed, wherein the upper plate connection portion is located in the receiving space, the interlayer connection portion penetrates the second interlayer dielectric layer, and the bottom end of the interlayer connection portion is connected to the diffusion barrier layer.

2. The method for manufacturing a MIM capacitor according to claim 1, characterized in that: There are multiple capacitor grooves, which are spaced apart and distributed in the second interlayer dielectric layer. A MIM capacitor is correspondingly arranged in each capacitor groove, and the bottom plate metal layers of the multiple MIM capacitors are connected in parallel through the diffusion barrier layer and the metal intermediate layer.

3. The method for manufacturing a MIM capacitor according to claim 1, characterized in that: Forming the MIM capacitor, the upper plate connection portion and the interlayer connection portion comprises the following steps: Depositing a lower plate metal layer, an isolation layer and an upper plate metal layer in sequence to obtain a laminated structure, wherein the laminated structure conformally covers the top surface of the second interlayer dielectric layer and the inner wall of the capacitor groove, and encloses the receiving space in the capacitor groove; Removing a predetermined area of ​​the stacked structure to expose the top surface of the second interlayer dielectric layer; forming an interlayer connection groove in the second interlayer dielectric layer, wherein the bottom of the interlayer connection groove exposes the diffusion barrier layer; forming an upper metal layer, wherein the upper metal layer covers the exposed surface of the second interlayer dielectric layer and fills the capacitor trench and the interlayer connection trench; Performing a planarization process until the second interlayer dielectric layer is exposed; Among them, the part of the stacked structure remaining in the receiving space constitutes the MIM capacitor, the part of the upper metal layer remaining in the capacitor groove constitutes the upper electrode connecting part, and the part of the upper metal layer remaining in the interlayer connecting groove constitutes the interlayer connecting part.

4. The method for manufacturing a MIM capacitor according to claim 1, characterized in that: The method also includes the step of forming a rewiring layer on the second interlayer dielectric layer, wherein the upper plate connection portion and the interlayer connection portion are both electrically connected to the rewiring layer.

5. The method for manufacturing a MIM capacitor according to claim 1, characterized in that: The first interlayer dielectric layer and the second interlayer dielectric layer both include an etch stop layer and a low-K dielectric layer located on the etch stop layer.

6. The method for manufacturing a MIM capacitor according to claim 1, characterized in that: The isolation layer of the MIM capacitor includes a high-K dielectric layer.

7. A MIM capacitor, characterized in that: include: Semiconductor substrate; A first interlayer dielectric layer, located on the semiconductor substrate; A metal interposer layer embedded in the front surface of the first interlayer dielectric layer; a diffusion barrier layer covering the metal interposer; a second interlayer dielectric layer, located on the first interlayer dielectric layer and covering the diffusion barrier layer; A capacitor trench is located in the second interlayer dielectric layer; A MIM capacitor is located in the capacitor groove and includes a lower plate metal layer, an isolation layer and an upper plate metal layer stacked in sequence, the MIM capacitor conformally covers the inner wall of the capacitor groove and encloses a receiving space with a top opening in the capacitor groove, and the bottom surface of the lower plate metal layer is connected to the diffusion barrier layer; An upper plate connecting portion is located in the receiving space; The interlayer connection portion penetrates through the second interlayer dielectric layer, and the bottom end of the interlayer connection portion is connected to the diffusion barrier layer.

8. The MIM capacitor according to claim 7, characterized in that: There are multiple capacitor grooves, which are spaced apart and distributed in the second interlayer dielectric layer. A MIM capacitor is correspondingly arranged in each capacitor groove, and the bottom plate metal layers of the multiple MIM capacitors are connected in parallel through the diffusion barrier layer and the metal intermediate layer.

9. The MIM capacitor according to claim 7, characterized in that: It also includes a rewiring layer located on the second interlayer dielectric layer, and the upper plate connecting portion and the interlayer connecting portion are both electrically connected to the rewiring layer.

10. The MIM capacitor according to claim 7, characterized in that: The first interlayer dielectric layer and the second interlayer dielectric layer both include an etch stop layer and a low-K dielectric layer located on the etch stop layer.

11. The MIM capacitor according to claim 7, characterized in that: The isolation layer of the MIM capacitor includes a high-K dielectric layer.

12. The MIM capacitor according to claim 7, characterized in that: The material of the metal intermediate layer includes copper, the material of the diffusion barrier layer includes TaN, the material of the lower plate metal layer includes TiN, and the material of the upper plate metal layer includes TiN.

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