Full-digital control programmable titanium sapphire femtosecond oscillator carrier envelope offset frequency locking device

Abstract

The invention discloses a full-digital control programmable titanium sapphire femtosecond oscillator carrier envelope offset frequency locking device. Comprising an avalanche photodetector, a power divider, a first radio frequency conditioning circuit, a second radio frequency conditioning circuit, a phase frequency detection circuit, a programmable proportion circuit, a programmable integrating circuit, a programmable biasing circuit, an anti-phase summation circuit, a programmable amplitude limiting circuit, an anti-saturation integrating circuit, an output buffer circuit, a main control circuit and an upper computer. According to the device, the carrier envelope offset frequency can be locked to the repetition frequency, the full-digital control programmable PI circuit is adopted, the innovative functions of anti-saturation integration and output amplitude limiting are combined, and the device has the advantages of being low in delay, high in precision, high in stability and high in safety.

Description

Technical Field

[0001] The invention belongs to the field of femtosecond laser technology in optoelectronic information science, and specifically relates to a fully digitally controlled programmable titanium sapphire femtosecond oscillator carrier envelope offset frequency locking device. Background Art

[0002] Attosecond laser pulses are one of the most effective tools for studying ultrafast physical processes. They can be used to perform tomographic imaging of molecular atoms, capture the evolution of hole density after ionization of atoms or even biological / chemical molecules, and the time delay of electron ionization in different states of gas molecules, atoms, and solid surfaces in real time. Attosecond pulses can not only study the movement of outer electrons, but can also be combined with X-ray diffraction, electron diffraction and other methods to provide imaging technology with ultrafast time resolution for studying solid materials, biological materials, etc., providing a new research method for condensed matter physics, new materials, ultrafast chemistry, nuclear physics and other research.

[0003] As the seed light source of the attosecond beamline, the stability of the carrier envelope phase of the Ti:Sapphire femtosecond oscillator plays a vital role in generating isolated attosecond pulses. The carrier envelope phase (CEP) refers to the phase difference between the envelope of the optical pulse and the peak value of the internal electric field. When the laser pulse passes through the medium, the group velocity and phase velocity of the pulse are not equal due to dispersion, and the carrier peak and envelope peak will have a phase difference during the propagation of the optical pulse. It will affect the intensity distribution of the electric field in the pulse, and the impact on periodic pulses is particularly obvious. When it is 0 or π, the carrier and envelope peaks coincide, and the envelope strength is the highest; however, when When the value is other than , the electric field intensity in the envelope will decrease. Therefore, carrier-envelope phase control technology is very important for the titanium sapphire oscillator to produce stable optical pulse output, and becomes a key technology in the process of generating isolated attosecond pulses. The femtosecond laser pulse sequence is expressed in the frequency domain as a repetition frequency of the oscillator f. rep is a comb-shaped longitudinal mode sequence with intervals. The frequency of the nth longitudinal mode can be expressed as f n =nf rep +f ceo , f ceo It is the starting point of the entire comb spectrum structure, also known as the carrier envelope offset frequency. The carrier envelope offset frequency and the carrier envelope phase have the following relationship:

[0004]

[0005] Therefore, locking the carrier envelope phase can be achieved by locking the carrier envelope offset frequency. In the process of generating isolated attosecond pulses, it is necessary to select pulse sequences with the same carrier envelope phase in the optical pulses at a certain period. To achieve this, the carrier envelope offset frequency needs to be locked to one-mth of the repetition frequency, so that every m pulses have the same carrier envelope phase.

[0006] The PI servo controller is the basis for ensuring high-precision locking of the carrier envelope offset frequency and repetition frequency. At present, there is no integrated frequency locking device that can directly lock the carrier envelope offset frequency of the titanium sapphire oscillator to a repetition frequency of one-m. Laser frequency locking devices can be divided into two categories: digital and analog. The bandwidth of digital frequency locking devices is generally only tens of KHz. At the same time, digital operations will bring high delays, which will cause the locking time to become longer and difficult to lock; therefore, analog PI controllers are usually used to lock the carrier envelope offset frequency. Conventional analog PI controllers can achieve a bandwidth of several MHz, but they need to manually adjust the P and I parameters. The adjustment steps are cumbersome and high-precision tuning cannot be achieved. In addition, conventional analog PI controllers have integral saturation problems, which will introduce serious overshoot to the control system. At the same time, since the output amplitude of ordinary PI controllers is uncontrollable, there is a risk of damaging the controlled system. Finally, conventional analog PI controllers generally have only one integral loop, which cannot quickly suppress high-frequency and low-frequency interference, and the loop dynamic performance is poor, which makes the controlled system still drift slowly after locking, and there is a risk of losing lock. Summary of the invention

[0007] In order to make up for the deficiencies of the prior art, the present invention provides a fully digitally controlled programmable titanium sapphire femtosecond oscillator carrier envelope offset frequency locking device, which adopts a programmable PI circuit with anti-saturation integral function to overcome the problems that the parameters of the traditional analog PI controller cannot be accurately tuned and the integral circuit is easy to saturate. It can accurately lock the carrier envelope offset frequency of the titanium sapphire oscillator to the eighth frequency of the repetition frequency, and has the advantages of low delay, anti-saturation, and precise tuning. In order to achieve the above purpose, the specific technical scheme of the present invention is as follows:

[0008] The fully digitally controlled programmable Ti:Sapphire femtosecond oscillator carrier envelope offset frequency locking device specifically comprises:

[0009] Avalanche photodetectors for detecting carrier envelope offset frequency and repetition rate;

[0010] A power divider, used for equally dividing the power of the avalanche photoelectric detection output signal into two output signals;

[0011] A first radio frequency conditioning circuit is used to filter and amplify the first output signal of the power divider to extract the carrier envelope offset frequency;

[0012] A second radio frequency conditioning circuit is used to filter, attenuate, divide the frequency, and amplify the second output signal of the power divider to extract the repetition frequency;

[0013] A frequency and phase detection circuit, used to identify the phase difference between the repetition frequency and the carrier envelope offset frequency;

[0014] A programmable proportional circuit for amplifying or attenuating a phase error signal;

[0015] A programmable integrator circuit for filtering and integrating a phase error signal;

[0016] A programmable bias circuit for fine-tuning the bias voltage in the output signal of the PI circuit;

[0017] Inverting summing circuit, used to sum the outputs of proportional circuits, integration circuits, and bias circuits;

[0018] Programmable limiter circuit, used to set output upper limit voltage and output lower limit voltage;

[0019] An anti-saturation integration circuit, used for generating an anti-saturation integration trigger signal, triggering the integration circuit to stop integration at critical saturation;

[0020] The output buffer circuit is used to isolate the output load and enhance the circuit's load capacity.

[0021] The avalanche photodetector detects an optical beat frequency signal including a carrier envelope offset frequency and a repetition frequency, and is divided into two output signals after passing through the power divider. One signal is input into the first radio frequency conditioning circuit for extracting the carrier envelope offset frequency, and the other signal is input into the second radio frequency conditioning circuit for extracting the repetition frequency. The carrier envelope offset frequency and the repetition frequency are input into the frequency and phase detection circuit together to obtain a phase error signal between the two. The phase error signal passes through the programmable proportional device and the programmable integrator in sequence to achieve amplification, attenuation, integration, and filtering, and is summed with the bias voltage generated by the programmable bias circuit at the output end. The programmable limiter circuit is used to limit the upper and lower limit voltages output by the PI circuit, and is combined with the anti-saturation integration circuit to generate a trigger signal for anti-saturation integration. The integration circuit stops integration when it is critically saturated, and saturation of the integration circuit is avoided from the hardware. Finally, the output of the PI circuit is output to the external controlled system through the buffer circuit. The entire device sends instructions to the main control circuit through the upper computer software, and the main control circuit writes data into each module, thereby realizing parameter tuning of full digital control.

[0022] Furthermore, the output signal of the avalanche photodetector is connected to the input end of the power divider, and the power divider divides the input signal into two paths and then outputs them, the first path of output is connected to the input end of the first RF conditioning circuit, and is used to extract the carrier envelope offset frequency; the second path of output is connected to the input end of the second RF conditioning circuit, and is used to extract the repetition frequency;

[0023] The output of the first radio frequency conditioning circuit is connected to the input end of the frequency and phase detection circuit, and the first radio frequency conditioning circuit sequentially comprises a first bandpass filter, a fixed gain amplifier circuit and a first voltage-controlled gain amplifier circuit, wherein the first bandpass filter is used to filter out other frequency components that are irrelevant to the carrier envelope offset frequency, and the fixed gain amplifier circuit and the first voltage-controlled gain amplifier circuit are used to realize programmable amplification of the carrier envelope offset frequency;

[0024] The output of the second RF conditioning circuit is connected to the input end of the frequency and phase detection circuit. The second conditioning circuit comprises a π-type attenuation circuit, a second bandpass filter, a frequency division circuit, a third bandpass filter, and a second voltage-controlled gain amplifier circuit in sequence. The π-attenuation circuit is used to attenuate the power of the repetition frequency to prevent excessive input power from damaging the frequency division device. The second bandpass filter is used to filter out frequency components that are not related to the repetition frequency. The frequency division circuit is used to divide the repetition frequency by eight. The third bandpass filter is used to filter the square wave output by the frequency division circuit into a sine wave. The second voltage-controlled gain amplifier circuit is used to achieve programmable amplification or attenuation of the repetition frequency.

[0025] Furthermore, the frequency and phase detection circuit includes a digital frequency and phase detector and an active loop filter. The frequency and phase detector is a voltage-type output with a polarity control function; the active loop filter is a third-order loop for filtering out high-frequency components in the output signal.

[0026] Furthermore, the programmable proportional circuit includes an instrument amplifier circuit, a polarity control circuit, a programmable attenuation circuit, and a programmable amplifier circuit. The instrument amplifier circuit is used for low-noise pre-amplification of the phase error signal, the polarity control circuit is used to change the positive and negative polarity of the error signal, and the programmable attenuation circuit and the programmable amplifier circuit are used to achieve high-precision attenuation and high-precision amplification of the error signal.

[0027] The gain of the instrument amplifier circuit is eight times, and the programmable attenuation circuit can achieve 65536 levels of attenuation of the error signal. The programmable amplifier circuit is composed of three groups of fixed gain amplifier circuits connected in series. The amplification factor of the first-stage fixed gain amplifier circuit is 32 times, the amplification factor of the second-stage fixed gain amplifier circuit is 8 times, and the amplification factor of the third-stage fixed gain amplifier circuit is 2 times. The three groups of fixed gain amplifier circuits can be turned on or off independently. When all the three groups of amplifier circuits are turned on, the gain is 512 times, and when all are turned off, the gain is 1 times; the programmable attenuation circuit is implemented by multiplication DAC and IV conversion circuit, and the gain of the attenuation circuit is changed by writing digital code to control the output resistance of the multiplication DAC. The multiplication DAC is 16 bits and can achieve 0-65535 levels of attenuation. The larger the input code, the smaller the attenuation.

[0028] Furthermore, the programmable integration circuit includes a fast integration circuit and a slow integration circuit. The fast integration circuit includes a first integration circuit, a second integration circuit, and a third integration circuit; the slow integration circuit includes a fourth integration circuit; the first integration circuit, the second integration circuit, and the third integration circuit are connected in series, and the first integration circuit, the second integration circuit, and the third integration circuit are all provided with four groups of integration capacitors for coarse adjustment of the unit gain bandwidth; the bandwidth adjustment range of the three groups of integration circuits is 0.1Hz to 100KHz, and the second integration circuit and the third integration circuit can be independently turned on or off; the bandwidth adjustment range of the fourth integration circuit is 0.001Hz to 100Hz; the first integration circuit, the second integration circuit, the third integration circuit, and the fourth integration circuit can be reset independently.

[0029] Among them, the first integration circuit, the second integration circuit, the third integration circuit, and the fourth integration circuit are all implemented by multiplication DAC and integration circuits, and the unit gain bandwidth of the integration circuit is changed by writing digital code to control the output resistance of the multiplication DAC. The multiplication DAC is 16 bits, and the larger the input code, the lower the unit gain bandwidth; the integration circuit achieves fine adjustment of the unit gain bandwidth by changing the input code.

[0030] Furthermore, the programmable bias circuit includes a first bias circuit and a second bias circuit, the bias adjustment range of both is -10V to 10V, and the bias adjustment accuracy of both is 0.15mV.

[0031] Furthermore, the inverting summing circuit includes a first summing circuit and a second summing circuit, wherein the first summing circuit is used to sum the outputs of the first integration circuit, the second integration circuit, the third integration circuit, and the first bias circuit; the second summing circuit is used to sum the outputs of the fourth integration circuit and the second bias circuit; and the first summing circuit and the second summing circuit can independently control whether the output of the circuit participates in the summing.

[0032] Furthermore, the programmable limiting circuit includes a fast integration limiting circuit and a slow integration limiting circuit, and the fast integration limiting circuit and the slow integration limiting circuit both include an upper limit limiting circuit and a lower limit limiting circuit, the limiting range of the upper limit limiting circuit is 0V to 10V, and the limiting accuracy is 0.15mV; the limiting range of the lower limit limiting circuit is -10V to 0V, and the limiting accuracy is 0.15mV.

[0033] Furthermore, the anti-saturation integration circuit includes a first comparator, a second comparator, a third comparator and a multiplexer, wherein the first comparator is used to determine the polarity of the current error signal, the second comparator is used to determine whether the output of the PI circuit reaches the upper limit voltage, and the third comparator is used to determine whether the output of the PI circuit reaches the lower limit voltage; the conditional integration strategy of the anti-saturation integration circuit is as follows:

[0034] When the error signal polarity is positive, if the PI circuit output reaches the upper limit voltage, the multiplexer is triggered to output an anti-saturation signal;

[0035] When the error signal polarity is negative, if the PI circuit output reaches the lower limit voltage, the multiplexer is triggered to output an anti-saturation signal;

[0036] When the error signal polarity is positive, if the PI circuit output reaches the lower limit voltage, the multiplexer is not triggered to output the anti-saturation signal;

[0037] When the error signal polarity is negative, if the PI circuit output reaches the upper limit voltage, the multiplexer is not triggered to output the anti-saturation signal;

[0038] When the PI circuit output reaches neither the upper limit voltage nor the lower limit voltage, the multiplexer is not triggered to output an anti-saturation signal regardless of the polarity of the error signal.

[0039] Furthermore, the output buffer circuit includes a first buffer circuit and a second buffer circuit, the first output buffer circuit is used for the output of the fast integration circuit; the second output buffer circuit is used for the output of the slow integration circuit, and the output circuit uses an optocoupler to isolate the load.

[0040] Compared with the prior art, the present invention has the following advantages:

[0041] (1) Low latency. The analog PI circuit structure is adopted, and there is no latency problem caused by the calculation processing in the digital frequency locking controller, thus ensuring that the controller can respond to the influence of external interference on the Ti:Sapphire oscillator in a timely manner.

[0042] (2) High locking stability. The multi-stage PI circuit structure with fast and slow dual feedback loops can not only effectively suppress high-frequency interference in the error signal, but also eliminate the slow drift of the carrier envelope offset frequency caused by changes in operating temperature and pump power.

[0043] (3) Large bandwidth adjustment range. The strategy of coarsely adjusting the unit gain integral bandwidth based on switching capacitors and finely adjusting the unit gain integral bandwidth by changing the input code makes it possible to adjust the bandwidth of the PI control circuit from mHz to hundreds of kHz, with very high frequency resolution.

[0044] (4) Good safety. The use of limiting circuit and anti-saturation integral circuit structure, combined with the conditional integration strategy, can effectively eliminate the saturation problem of the integrator, avoid the serious overshoot caused by integrator saturation, reduce the risk of damaging the controlled object, and improve the reliability of the controller.

[0045] (5) Easy operation and high parameter tuning accuracy. The fully digital control architecture is adopted, and the upper computer sends digital codes to the main control to achieve the setting of circuit parameters and the precise tuning of P and I parameters. There is no need for manual switching adjustment like the traditional analog PI controller; and the more bits the digital code has, the higher the accuracy of parameter tuning. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is the overall structural principle diagram of the present invention;

[0047] Figure 2 is a schematic diagram of a radio frequency conditioning circuit of the present invention;

[0048] Figure 3 is a schematic diagram of a programmable proportional circuit of the present invention;

[0049] Figure 4 The schematic diagram of the programmable integrator circuit of the present invention;

[0050] Figure 5 It is a principle diagram of the programmable limiting circuit and the anti-saturation integration circuit of the present invention. DETAILED DESCRIPTION

[0051] The following is a further description of a fully digitally controlled programmable Ti:Sapphire femtosecond oscillator carrier envelope offset frequency locking device according to the present invention in conjunction with the accompanying drawings.

[0052] like Figure 1As shown, a fully digitally controlled programmable titanium sapphire femtosecond oscillator carrier envelope offset frequency locking device includes an avalanche photodetector, a power divider, a first radio frequency conditioning circuit, a second radio frequency conditioning circuit, a frequency discrimination and phase discrimination circuit, a programmable proportional circuit, a programmable integration circuit, a programmable bias circuit, an inverting summing circuit, a programmable limiting circuit, an anti-saturation integration circuit, an output buffer circuit, a main control circuit, and a host computer. Among them, the avalanche photodetector is used to detect the optical beat frequency signal containing the carrier envelope offset frequency and the repetition frequency, and the output signal of the avalanche photodetector is connected to the input end of the power divider, and the power divider divides the input into two output signals. The first output signal is input to the first radio frequency conditioning circuit to extract the carrier envelope offset frequency; the second output signal is input to the second radio frequency conditioning circuit to extract the repetition frequency. The carrier envelope offset frequency and the repetition frequency are input to the frequency discrimination and phase discrimination circuit together to obtain the phase error signal of the two. The phase error signal passes through the programmable proportional device and the programmable integrator in turn to achieve amplification, attenuation, integration, and filtering. The programmable bias circuit generates a bias voltage and superimposes it on the output of the PI circuit through the inverting summing circuit; the output of the inverting summing circuit is connected to the input of the programmable limiter circuit. The programmable limiter circuit is used to limit the upper and lower limit voltages of the PI circuit output. The anti-saturation integral circuit is used to generate an anti-saturation integral trigger signal, which can stop the integral circuit from integrating when it is critically saturated to avoid saturation of the integral circuit. The output of the limiter circuit is connected to the input of the output buffer circuit, which is used to isolate the load and output the feedback signal to the controlled system. The main control circuit is used to set the circuit parameters, and the host computer communicates with the main control circuit to achieve full digital control parameter tuning.

[0053] like Figure 2 The schematic diagram of the radio frequency conditioning circuit of the present invention is shown. The radio frequency conditioning circuit includes a first radio frequency conditioning circuit and a second radio frequency conditioning circuit. In the present embodiment, the first radio frequency conditioning circuit is used to extract the carrier envelope offset frequency, the carrier envelope offset frequency is 8MHz, and the power is about -50dBm. The first radio frequency conditioning circuit includes a first bandpass filter, a fixed gain amplifier circuit and a first voltage-controlled gain amplifier circuit in sequence. The passband range of the first bandpass filter is 6MHz to 12.4MHz, which is used to filter out other frequency components including the repetition frequency. The fixed gain amplifier in the fixed gain amplifier circuit selects a high-speed amplifier with low noise and low harmonic distortion with a loss compensation structure to provide low-noise front-end amplification to achieve a signal-to-noise ratio higher than 30dB. The first voltage-controlled gain amplifier circuit is used to realize programmable amplification of the carrier envelope offset frequency. The voltage-controlled amplifier can provide a gain of 0dB to 40dB, the control voltage is between 0V and 2V, the control voltage and the gain are linear in decibels, and the purpose of the voltage-controlled amplification is to adjust the amplitude of the carrier envelope offset frequency to meet the input requirements of the continuous frequency and phase detection circuit.

[0054] In this implementation case, the second RF conditioning circuit is used to extract the repetition frequency. The repetition frequency is 64MHz, and the power is about 6dBm. The second conditioning circuit includes a π-type attenuation circuit, a second bandpass filter, a three-stage D flip-flop, a third bandpass filter, and a second voltage-controlled gain amplifier circuit in sequence. The π-type attenuation circuit is used to attenuate the power of the repetition frequency to prevent excessive input power from damaging the frequency division device; the repetition frequency can be attenuated by 6dB, the purpose of which is to reduce the amplitude of the repetition frequency to protect the frequency division circuit. The passband range of the second bandpass filter is 58MHz to 68MHz, and it is used to filter other frequency components including the carrier envelope offset frequency. The three-stage D flip-flop constitutes an eight-frequency division circuit, and each stage of the D flip-flop can provide two-frequency division. The three-stage D flip-flop adopts a cascade structure, which can realize the division of the repetition frequency of 64MHz into 8MHz. The third bandpass filter circuit is used to filter out the high-order harmonic components in the divided signal and filter the square wave output by the frequency division circuit into a sine wave. The second voltage-controlled gain amplifier circuit can provide a gain of -20dB to 20dB, which is used to amplify or attenuate the repetition frequency after frequency division. The control voltage is between 0V and 2V, and the control voltage and gain are linear in decibels. The purpose of voltage-controlled amplification is to adjust the amplitude of the repetition frequency to meet the input requirements of the continuous frequency and phase detection circuit.

[0055] In this embodiment, the frequency and phase detection circuit includes a digital frequency and phase detector and an active loop filter. The frequency and phase detector is a voltage type output with a polarity control function; the active loop filter is a third-order loop for filtering out high-frequency components in the output signal.

[0056] like Figure 3 Shown is a schematic diagram of the programmable proportional circuit of the present invention. In this embodiment, the programmable proportional circuit includes an instrument amplifier circuit, a polarity control circuit, a programmable attenuation circuit, and a three-stage fixed gain amplifier circuit in sequence. The instrument amplifier circuit has an eight-fold fixed gain and is used for low-noise front-end amplification of the error signal. The polarity control circuit is used to change the polarity of the error signal. The polarity is controlled by an analog switch. When the switch is closed, the output and input polarities are the same. When the switch is open, the output and input polarities are opposite. The programmable attenuator consists of a multiplication DAC and an IV conversion circuit. The output current is changed by controlling the output impedance of the R-2R ladder resistor network inside the multiplication DAC through a digital code. Different currents can obtain different output voltages after passing through the IV conversion circuit. The multiplication DAC input code and output voltage have the following relationship

[0057]

[0058] Where D is the input code, R FBis the internal feedback resistor of the multiplication DAC, and n is the number of bits of the multiplication DAC. The number of bits of the multiplication DAC is 16 bits, the attenuation coefficient is between 0 and 1, the input and output voltage range is between -15V and 15V, and the minimum attenuation accuracy can reach 0.3mV. The gains of the three-stage fixed gain amplifier circuit are 32 times, 8 times, and 2 times respectively. Each stage of the amplifier circuit uses an independent analog switch to control the gain to turn on or off. The three-stage fixed gain amplifier circuit can provide 7 gains of 512 times, 256 times, 64 times, 32 times, 16 times, 2 times, and 1 times.

[0059] like Figure 4 The schematic diagram of the programmable integrator (PI) circuit of the present invention is shown. In this embodiment, the programmable PI circuit includes a fast PI circuit and a slow PI circuit. The fast PI circuit includes a first integrator circuit, a second integrator circuit, a third integrator circuit, a first bias circuit, and a first summing circuit. The input and output of the three integrator circuits satisfy the following relationship:

[0060]

[0061] Among them, C1 is the integration capacitor, R1 is the integration resistor of the integrator. In this implementation case, each level of the integrator is equipped with four groups of capacitors, which are 1nF, 44nF, 550nF, and 4.7uF respectively; R1 is implemented by the R-2R resistor network of the multiplication DAC. The unit gain bandwidth of the three groups of integrators is determined by C1 and R1, and has the following relationship:

[0062]

[0063] The three groups of integrators can change the unity gain bandwidth by adjusting C1 and R1. When switching different integration capacitors, the unity gain bandwidth of the integrator can be roughly adjusted. When changing the input code of the multiplication DAC, the unity gain bandwidth of the integrator can be finely adjusted. The bandwidth adjustment range of the three groups of integrators is 1Hz ~ 100KHz. When the unity gain bandwidth of the three groups of integrators is set to the same, an attenuation of -60dB / dec can be provided.

[0064] The first bias circuit is used to generate the output bias of the fast integration circuit. The output bias can be used to fine-tune the output voltage to achieve precise locking. The voltage tuning accuracy of the first bias circuit is 0.15mV. The first summing circuit is used to sum the proportional circuit output, the fast integration circuit output, and the first bias circuit output to obtain the total output signal. The three outputs can independently control whether to participate in the summation to obtain a fast integration output signal. The fast integration circuit has an anti-saturation function. When the external input anti-saturation integration trigger signal is valid, the integrator enters the anti-saturation state. At this time, the input will switch to GND, and the integrator will maintain the current integration value.

[0065] The slow PI circuit includes a fourth integration circuit, a second bias circuit, and a second summing circuit. The fourth integration circuit has a larger integration capacitor than the first integration circuit, which makes the slow integration circuit have a very long integration saturation time, and its unit gain bandwidth is located near 0Hz, which can effectively suppress the low-frequency interference in the controlled system. The fourth integration circuit has four sets of integration capacitors, namely 1uF, 33uF, 100uF, and 550uF. The unit gain bandwidth of the slow integration circuit is set to a minimum of 0.001Hz. The second bias circuit is used to set the output bias of the slow integration circuit. The voltage tuning accuracy of the second bias circuit is 0.15mV. The second summing circuit is used to sum the outputs of the fourth integration circuit and the second bias circuit to obtain a slow integration output signal. The two outputs can independently control whether to participate in the summing.

[0066] like Figure 5 The figure shows the schematic diagram of the limiting and anti-saturation circuit. In this implementation case, the limiting and anti-saturation circuit can be divided into a fast PI limiting and anti-saturation output circuit and a slow PI limiting output circuit. The fast PI limiting and anti-saturation output circuit includes an upper limit limiting circuit, a lower limit limiting circuit, a first comparator, a second comparator, a third comparator, a multiplexer, and an output buffer circuit. The upper limit limiting circuit and the lower limit limiting circuit adopt a bias limiting structure. The upper limit voltage range is 0V to 10V, the lower limit voltage range is -10V to 0V, and the adjustment accuracy is 0.15mV. The anti-saturation integration circuit is implemented with a three-level comparator and a multiplexer. The first comparator is used to compare whether the polarity of the current input error signal is positive or negative, the second comparator is used to compare whether the current PI controller output exceeds the upper limit voltage, and the third comparator is used to compare whether the current PI controller output is lower than the lower limit voltage. The three-level comparator is combined into the following conditional integration strategy:

[0067] ① When the error signal is positive, if the PI controller output reaches the upper limit voltage, the continuous integration integrator will saturate the upper limit, so the anti-saturation trigger signal is set to valid;

[0068] ② When the error signal is negative, if the PI controller output reaches the lower limit voltage, the continued integration integrator will saturate the lower limit, so the anti-saturation trigger signal is set to valid;

[0069] ③ When the error signal is positive, if the PI controller output reaches the lower limit voltage, the integrator continues to integrate and exits saturation, so the anti-saturation integral trigger signal is set to invalid;

[0070] ④ When the error signal is negative, if the PI controller output reaches the upper limit voltage, the integrator continues to integrate and exits saturation, so the anti-saturation integral trigger signal is set to invalid;

[0071] ⑤ When the PI controller output reaches neither the upper limit nor the lower limit, the integrator is maintained regardless of the polarity of the error signal, and the anti-saturation integral trigger signal is set to invalid.

[0072] The slow PI limiting circuit includes a second upper limit limiting circuit, a second lower limit limiting circuit and a second output buffer circuit. The limiting voltage of the second upper limit limiting circuit is 0V~10V, the limiting voltage of the second lower limit limiting circuit is -10V~0V, and the adjustment accuracy is 0.15mV. The first buffer circuit and the second buffer circuit are used to isolate the load and improve the load capacity of the entire device.

[0073] It can be seen that the output buffer circuit includes a first buffer circuit and a second buffer circuit. The first output buffer circuit is used for the output of the fast integration circuit; the second output buffer circuit is used for the output of the slow integration circuit. The output circuit uses an optocoupler to isolate the load.

[0074] In addition, in this embodiment, the programmable bias circuit includes a first bias circuit and a second bias circuit, the bias adjustment range is -10V to 10V, and the bias adjustment accuracy is 0.15mV. The inverting summing circuit includes a first summing circuit and a second summing circuit, the first summing circuit is used to sum the outputs of the first integration circuit, the second integration circuit, the third integration circuit, and the first bias circuit; the second summing circuit is used to sum the outputs of the fourth integration circuit and the second bias circuit; the first summing circuit and the second summing circuit can independently control whether the output of the circuit participates in the summing.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A fully digitally controlled programmable Ti:Sapphire femtosecond oscillator carrier envelope offset frequency locking device, characterized in that: The device comprises: Avalanche photodetectors for detecting carrier envelope offset frequency and repetition rate; A power divider, used for equally dividing the power of the avalanche photoelectric detection output signal into two output signals; A first radio frequency conditioning circuit is used to filter and amplify the first output signal of the power divider to extract the carrier envelope offset frequency; A second radio frequency conditioning circuit is used to filter, attenuate, divide the frequency, and amplify the second output signal of the power divider to extract the repetition frequency; A frequency and phase detection circuit, used to identify the phase difference between the repetition frequency and the carrier envelope offset frequency; A programmable proportional circuit for amplifying or attenuating a phase error signal; A programmable integrator circuit for filtering and integrating a phase error signal; A programmable bias circuit for fine-tuning the bias voltage in the output signal of the PI circuit; Inverting summing circuit, used to sum the outputs of proportional circuits, integration circuits, and bias circuits; Programmable limiter circuit, used to set output upper limit voltage and output lower limit voltage; An anti-saturation integration circuit, used for generating an anti-saturation integration trigger signal, triggering the integration circuit to stop integration at critical saturation; The output buffer circuit is used to isolate the output load and enhance the circuit's load capacity.

2. The fully digitally controlled programmable Ti:Sapphire femtosecond oscillator carrier envelope offset frequency locking device according to claim 1, characterized in that: The output signal of the avalanche photodetector is connected to the input end of the power divider, and the power divider divides the input signal into two paths and then outputs them, the first path of output is connected to the input end of the first RF conditioning circuit, and is used to extract the carrier envelope offset frequency; the second path of output is connected to the input end of the second RF conditioning circuit, and is used to extract the repetition frequency; The output of the first radio frequency conditioning circuit is connected to the input end of the frequency and phase detection circuit, and the first radio frequency conditioning circuit sequentially comprises a first bandpass filter, a fixed gain amplifier circuit and a first voltage-controlled gain amplifier circuit, wherein the first bandpass filter is used to filter out other frequency components that are irrelevant to the carrier envelope offset frequency, and the fixed gain amplifier circuit and the first voltage-controlled gain amplifier circuit are used to realize programmable amplification of the carrier envelope offset frequency; The output of the second RF conditioning circuit is connected to the input end of the frequency and phase detection circuit. The second conditioning circuit comprises a π-type attenuation circuit, a second bandpass filter, a frequency division circuit, a third bandpass filter, and a second voltage-controlled gain amplifier circuit in sequence. The π-attenuation circuit is used to attenuate the power of the repetition frequency to prevent excessive input power from damaging the frequency division device. The second bandpass filter is used to filter out frequency components that are not related to the repetition frequency. The frequency division circuit is used to divide the repetition frequency by eight. The third bandpass filter is used to filter the square wave output by the frequency division circuit into a sine wave. The second voltage-controlled gain amplifier circuit is used to achieve programmable amplification or attenuation of the repetition frequency.

3. The fully digitally controlled programmable Ti:Sapphire femtosecond oscillator carrier envelope offset frequency locking device according to claim 1, characterized in that: The frequency and phase detection circuit includes a digital frequency and phase detector and an active loop filter. The frequency and phase detector is a voltage type output with a polarity control function; the active loop filter is a third-order loop for filtering out high-frequency components in the output signal.

4. The fully digitally controlled programmable Ti:Sapphire femtosecond oscillator carrier envelope offset frequency locking device according to claim 1, characterized in that: The programmable proportional circuit includes an instrument amplifier circuit, a polarity control circuit, a programmable attenuation circuit, and a programmable amplifier circuit. The instrument amplifier circuit is used for low-noise pre-amplification of the phase error signal, the polarity control circuit is used for changing the positive and negative polarities of the error signal, and the programmable attenuation circuit and the programmable amplifier circuit are used for achieving high-precision attenuation and high-precision amplification of the error signal.

5. The fully digitally controlled programmable Ti:Sapphire femtosecond oscillator carrier envelope offset frequency locking device according to claim 1, characterized in that: The programmable integration circuit includes a fast integration circuit and a slow integration circuit. The fast integration circuit includes a first integration circuit, a second integration circuit, and a third integration circuit. The slow integration circuit includes a fourth integration circuit. The first integration circuit, the second integration circuit, and the third integration circuit are connected in series. The first integration circuit, the second integration circuit, and the third integration circuit are all provided with four groups of integration capacitors for coarse adjustment of the unit gain bandwidth. The bandwidth adjustment range of the three groups of integration circuits is 0.1Hz to 100KHz. The second integration circuit and the third integration circuit can be independently turned on or off. The bandwidth adjustment range of the fourth integration circuit is 0.001Hz to 100Hz. The first integration circuit, the second integration circuit, the third integration circuit, and the fourth integration circuit can be reset independently.

6. The fully digitally controlled programmable Ti:Sapphire femtosecond oscillator carrier envelope offset frequency locking device according to claim 5, characterized in that: The programmable bias circuit includes a first bias circuit and a second bias circuit, the bias adjustment range of both is -10V to 10V, and the bias adjustment accuracy of both is 0.15mV.

7. The fully digitally controlled programmable Ti:Sapphire femtosecond oscillator carrier envelope offset frequency locking device according to claim 6, characterized in that: The inverting summing circuit includes a first summing circuit and a second summing circuit. The first summing circuit is used to sum the outputs of the first integration circuit, the second integration circuit, the third integration circuit, and the first bias circuit; the second summing circuit is used to sum the outputs of the fourth integration circuit and the second bias circuit; the first summing circuit and the second summing circuit can independently control whether the output of the circuit participates in the summing.

8. The fully digitally controlled programmable Ti:Sapphire femtosecond oscillator carrier envelope offset frequency locking device according to claim 1, characterized in that: The programmable limiting circuit includes a fast integration limiting circuit and a slow integration limiting circuit. The fast integration limiting circuit and the slow integration limiting circuit both include an upper limit limiting circuit and a lower limit limiting circuit. The limiting range of the upper limit limiting circuit is 0V to 10V, and the limiting accuracy is 0.15mV; the limiting range of the lower limit limiting circuit is -10V to 0V, and the limiting accuracy is 0.15mV.

9. The fully digitally controlled programmable Ti:Sapphire femtosecond oscillator carrier envelope offset frequency locking device according to claim 1, characterized in that: The anti-saturation integration circuit includes a first comparator, a second comparator, a third comparator and a multiplexer, wherein the first comparator is used to determine the polarity of the current error signal, the second comparator is used to determine whether the output of the PI circuit reaches an upper limit voltage, and the third comparator is used to determine whether the output of the PI circuit reaches a lower limit voltage; the conditional integration strategy of the anti-saturation integration circuit is as follows: When the error signal polarity is positive, if the PI circuit output reaches the upper limit voltage, the multiplexer is triggered to output an anti-saturation signal; When the error signal polarity is negative, if the PI circuit output reaches the lower limit voltage, the multiplexer is triggered to output an anti-saturation signal; When the error signal polarity is positive, if the PI circuit output reaches the lower limit voltage, the multiplexer is not triggered to output the anti-saturation signal; When the error signal polarity is negative, if the PI circuit output reaches the upper limit voltage, the multiplexer is not triggered to output the anti-saturation signal; When the PI circuit output reaches neither the upper limit voltage nor the lower limit voltage, the multiplexer is not triggered to output an anti-saturation signal regardless of the polarity of the error signal.

10. The fully digitally controlled programmable Ti:Sapphire femtosecond oscillator carrier envelope offset frequency locking device according to claim 1, characterized in that: The output buffer circuit includes a first buffer circuit and a second buffer circuit. The first output buffer circuit is used for the output of the fast integration circuit; the second output buffer circuit is used for the output of the slow integration circuit. The output circuit uses an optocoupler to isolate the load.

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