Charge pump with adjustable ripples

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a charge pump with adjustable ripples. The circuit comprises an oscillator circuit, a logic circuit, a charging and discharging circuit, a voltage detection circuit, a current bias circuit, a feedback circuit and the like, and the oscillator circuit generates stable periodic clock signals and provides the clock signals for the logic circuit of the charge pump; the logic circuit generates two non-overlapping logic control signals to control the charging and discharging time of the charge pump charging and discharging circuit; the charging and discharging circuit charges and discharges the capacitor under the action of the logic control signal and outputs charge pump voltage; the voltage detection circuit is mainly used for detecting the voltage difference between the output voltage of the charge pump and the power supply voltage, reducing the voltage difference in equal proportion and comparing with the reference voltage; the current bias circuit is mainly used for providing a proper bias current value for the charge-discharge circuit and the current detection circuit of the charge pump.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a charge pump with adjustable ripple. Background Art

[0002] The charge pump circuit is a very important part of the integrated circuit, and is widely used in the buck-boost system of the drive circuit system chip and the power management chip. The charge pump is divided into a bootstrap charge pump and a non-bootstrap charge pump. The bootstrap charge pump consists of a bootstrap capacitor and a charging path, with a simple structure and fast charging speed. However, if the ground potential of the charging path is the same as the source potential (for example, the H-bridge drive circuit), the bootstrap charge pump cannot work, so the bootstrap charge pump circuit is often combined with a trickle charge pump, which is similar to the non-bootstrap charge pump and has the same disadvantages; the non-bootstrap charge pump is often a modified structure of the Dickson charge pump structure or a modified structure of the four-phase clock charge pump. The structure is a half-bridge or full-bridge switch structure that charges and discharges the capacitor, so that the charge pump output voltage rises to drive the drive circuit to work normally, but the ripple of its output voltage can only be adjusted by changing the size of the capacitor, and the adjustment range is relatively limited.

[0003] With the widespread application of drive circuit systems, especially the application of half-bridge, full-bridge drive and high-side drive of buck circuits, charge pumps play an indispensable role. At the same time, the ripple size of the charge pump output voltage is also related to whether the drive circuit and peripheral circuits (such as overcurrent detection circuits, etc.) can work normally. If the voltage ripple after boosting is too large, the drive circuit signal may not be able to flip normally in a too small source rail range, causing logical errors in the drive load, and even causing the protection circuit to not work properly, and fail to protect the drive system. The traditional charge pump structure can only adjust the ripple size of the charge pump output voltage by adjusting the charge and discharge capacitors. The adjustment range is limited and will increase the area of ​​the system chip, which increases the cost to a certain extent. Summary of the invention

[0004] In order to solve the problems that the existing charge pump circuit has few ripple adjustment means and poor effect, the present invention proposes a novel charge pump circuit structure with adjustable ripple.

[0005] The technical solution of the present invention is:

[0006] A ripple adjustable charge pump comprises an oscillator circuit, a logic circuit, a current bias circuit, a charge and discharge circuit, a voltage detection circuit and a feedback circuit;

[0007] The oscillator circuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first capacitor, a first resistor, a NAND gate, a SMIT trigger, and a D trigger; wherein the input end of the first inverter is connected to a low-level signal of an enable signal, and the output end is connected to the gate of the first NMOS tube, the gate of the third PMOS tube, the gate of the third NMOS tube, and an input end of the NAND gate; the source of the first PMOS tube is connected to a power supply, and the gate and drain thereof are interconnected; the drain of the first NMOS tube is connected to the drain of the first PMOS tube, and the source of the first NMOS tube is grounded after passing through a first resistor; the source of the second PMOS tube is connected to a power supply, and the gate thereof is connected to a The drain of the first PMOS tube and the drain of the second PMOS tube are connected to the enable end of the NAND gate; the source of the third PMOS tube is connected to the power supply, and the drain thereof is connected to the output end of the NAND gate, the input end of the SMIT trigger, the drain of the second NMOS tube, and one end of the first capacitor; the source of the second NMOS tube is connected to the drain of the third NMOS tube, and the source of the third NMOS tube and the other end of the first capacitor are grounded; the output end of the SMIT trigger is connected to the input end of the second inverter, the output end of the second inverter is connected to the input end of the third inverter, the other input end of the NAND gate, and the gate of the second NMOS tube; the output end of the third inverter is connected to the input end of the D trigger, the output end of the D trigger is connected to the input end of the fourth inverter, the output end of the fourth inverter is connected to the input end of the fifth inverter, and the output end of the fifth inverter outputs a clock signal;

[0008] The input of the logic circuit is a clock signal. Under the action of the clock signal, the logic circuit generates a two-phase clock signal, and the two-phase clock signals are mutually inverted signals, which are defined as ctrl and ctrl_not respectively;

[0009] The current bias circuit includes a fourth PMOS tube, a fifth PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, and a second resistor; wherein the source of the fourth PMOS tube is connected to a power supply, and its gate and drain are interconnected; the drain of the fourth NMOS tube is connected to the drain of the fourth PMOS tube, the gate of the fourth NMOS tube is connected to a high-level signal of an enable signal, and the source of the fourth NMOS tube is grounded after passing through the second resistor; the source of the fifth PMOS tube is connected to a power supply, and its gate is connected to the drain of the fourth PMOS tube; the drain of the fifth NMOS tube is connected to the fifth PMOS tube. The drain of the S tube, the gate of the fifth NMOS tube is connected to the low level signal of the enable signal, and the source of the fifth NMOS tube is grounded; the drain and gate of the sixth NMOS tube are connected to the drain of the fifth PMOS tube, and the source of the sixth NMOS tube is grounded; the gate of the seventh NMOS tube, the gate of the eighth NMOS tube, and the gate of the ninth NMOS tube are connected to the drain of the fifth PMOS tube, the source of the seventh NMOS tube, the source of the eighth NMOS tube, and the source of the ninth NMOS tube are grounded, the drain of the seventh NMOS tube outputs the first bias signal, the drain of the eighth NMOS tube outputs the second bias signal, and the drain of the ninth NMOS tube outputs the third bias signal;

[0010] The charge and discharge circuit includes a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a third resistor, a second capacitor, a third capacitor, a first Zener diode, a first high-voltage NMOS tube, a second high-voltage NMOS tube, a third high-voltage NMOS tube, and a fourth high-voltage NMOS tube; wherein the source of the sixth PMOS tube is connected to the charge pump output voltage, and the gate and drain thereof are interconnected; the drain of the tenth NMOS tube is connected to the drain of the sixth PMOS tube, the gate of the tenth NMOS tube is connected to ctrl_not, and the source thereof is connected to the first bias signal; the source of the seventh PMOS tube is connected to the charge pump output voltage, and the gate thereof is connected to the drain of the sixth PMOS tube; the source of the eighth PMOS tube is connected to the charge pump input voltage, and the gate and drain thereof are interconnected; the drain of the eleventh NMOS tube is connected to the drain of the eighth PMOS tube, the gate of the eleventh NMOS tube is connected to ctrl_not, and the source thereof is connected to the second Bias signal; the source of the ninth PMOS tube is connected to the charge pump input voltage, and its gate is connected to the drain of the eighth PMOS tube; the anode of the first Zener diode is connected to the drain of the ninth PMOS tube, and the cathode of the first Zener diode is connected to the drain of the seventh PMOS tube, the gate of the first high-voltage NMOS tube, the drain of the twelfth NMOS tube, and one end of the third resistor; the other end of the third resistor is grounded; the drain of the first high-voltage NMOS tube is connected to the charge pump input voltage, and its source is connected to the drain of the second high-voltage NMOS tube and one end of the second capacitor; the gate of the twelfth NMOS tube is connected to ctrl, and its source is grounded; the gate of the second high-voltage NMOS tube is connected to ctrl, and its source is grounded; the drain of the third high-voltage NMOS tube is connected to the charge pump output voltage and one end of the third capacitor, and its gate and drain are interconnected; the drain of the fourth high-voltage NMOS tube is connected to the drain of the third high-voltage NMOS tube and the other end of the second capacitor, and the gate and source of the fourth high-voltage NMOS tube are connected to the charge pump input voltage and the other end of the third capacitor;

[0011] The voltage detection circuit comprises a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor; wherein the gate and drain of the thirteenth NMOS tube are connected to the third bias signal, and the source thereof is grounded; one end of the fourth resistor and one end of the sixth resistor are connected to the charge pump output voltage, the other end of the fourth resistor and one end of the fifth resistor are connected to the charge pump input voltage, the other end of the fifth resistor is connected to the source of the tenth PMOS tube, and the gate and drain of the tenth PMOS tube are interconnected; the source of the eleventh PMOS tube is connected to the drain of the tenth PMOS tube, and the gate and drain thereof are interconnected; the gate of the fourteenth NMOS tube is connected to the third bias signal, the drain thereof is connected to the drain of the eleventh PMOS tube, and the source of the fourteenth PMOS tube is grounded; The source of the MOS tube is connected to the other end of the sixth resistor, and the gate thereof is connected to the drain of the tenth PMOS tube; the source of the thirteenth PMOS tube is connected to the drain of the twelfth PMOS tube, and the gate thereof is connected to the drain of the eleventh PMOS tube; the gate of the fifteenth NMOS tube is connected to the third bias signal, the drain thereof is connected to the drain of the thirteenth PMOS tube, and the source of the fifteenth PMOS tube is grounded; the drain of the sixteenth NMOS tube is connected to the other end of the sixth resistor, the gate thereof is connected to the drain of the thirteenth PMOS tube, the source of the sixteenth NMOS tube is connected to the ground after passing through the seventh resistor, the eighth resistor, and the ninth resistor in sequence, and the connection point between the source of the sixteenth NMOS tube and the seventh resistor outputs a detection voltage signal; the drain of the seventeenth NMOS tube is connected to the connection point of the seventh resistor and the eighth resistor, and the gate thereof is connected to the first resistor control signal; the drain of the eighteenth NMOS tube is connected to the source of the seventeenth NMOS tube, the connection point of the eighth resistor and the ninth resistor, the gate of the eighteenth NMOS tube is connected to the second resistor control signal, and the source of the eighteenth NMOS tube is grounded;

[0012] The feedback circuit includes a first comparator, a second comparator, and an NOR gate; wherein the positive input terminal of the first comparator is connected to the first reference signal, the negative input terminal is connected to the detection voltage signal, and the output terminal is connected to one input terminal of the NOR gate; the negative input terminal of the second comparator is connected to the detection voltage signal, the positive input terminal is connected to the second reference signal and the third reference signal respectively through two switching tubes, and the output terminal is connected to the other input terminal of the NOR gate, and the enable signals of the two switching tubes are the voltage signals of the other end of the fifth resistor and the other end of the sixth resistor respectively; the NOR gate outputs a high-level signal or a low-level signal of the enable signal.

[0013] The beneficial effect of the present invention is that it can output a voltage with a small ripple. It is characterized in that the feedback module composed of a comparator in the structure adjusts the ripple of the charge pump output voltage and the difference with the power supply voltage to meet the requirements of the source rail of different drive circuits. The ripple adjustment ensures the normal operation of the subsequent drive circuit and the normal function of the protection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A charge pump circuit structure with adjustable ripple according to the present invention;

[0015] Figure 2 A circuit diagram of an oscillator circuit of a charge pump circuit structure with adjustable ripple according to the present invention;

[0016] Figure 3 A circuit diagram of a current bias circuit of a charge pump circuit structure with adjustable ripple according to the present invention;

[0017] Figure 4 A circuit diagram of a charge-discharge circuit of a charge pump circuit structure with adjustable ripple according to the present invention;

[0018] Figure 5 A circuit diagram of a voltage detection circuit of a charge pump circuit structure with adjustable ripple according to the present invention;

[0019] Figure 6 is an output voltage simulation diagram of the charge pump circuit of the present invention;

[0020] Figure 7 It is a simulation diagram of the output voltage ripple of the charge pump circuit of the present invention. DETAILED DESCRIPTION

[0021] The present invention is described in detail below with reference to the accompanying drawings.

[0022] The overall circuit structure of the present invention is as follows Figure 1 As shown, it includes an oscillator circuit, a logic circuit, a charge and discharge circuit, a current detection circuit, a current bias circuit, a feedback circuit, etc. First, the oscillator circuit generates a clock signal and provides it to the logic circuit. Under the action of the clock signal, the logic circuit generates a two-phase clock signal (the two-phase clock signals are mutually inverted signals) to act on the power switch of the charge and discharge circuit. The output voltage VCP of the charge pump is generated through the charging and discharging operations of the charge and discharge circuit. At the same time, the VCP voltage is proportionally reduced by the voltage detection circuit and compared with the different reference voltages of the feedback module comparator to obtain the output signal to act on the oscillator circuit to complete the closed-loop operation.

[0023] Figure 2The circuit diagram of the oscillator circuit is shown in Figure 1, which mainly includes a current source composed of CMOS tubes PM1, PM2, NM1, resistor R1 and NAND gate Nand, a discharge current source composed of NAND gate Nand and NM2, NM3, a charge and discharge capacitor C1, a SMIT trigger, a D trigger and multiple inverters. Its main working principle is to control Figure 2 The state of the NM3 tube in the middle further controls the voltage on the capacitor C1, and the periodic charging and discharging of the capacitor C1 is realized through the feedback loop, and the output end of the D flip-flop is brought out, which is the output clock signal, providing a clock signal for the subsequent logic circuit. The working stages include: the first stage: the current source composed of the CMOS tubes PM1, PM2, NM1, resistor R1 and the NAND gate Nand generates a bias voltage to act on the gate of PM2, so that the PM2 tube is turned on, and the output voltage of the inverter INV2 is initially low. At this time, the NM2 tube is in the off state. The EN_L signal is the feedback output signal, and the initial state is low. The output voltage of INV2 and the EN_L signal are output through the NAND gate Nand. The high-level signal is used to charge and discharge the capacitor C1. The upper plate of C1 accumulates a large amount of charge, and the voltage on the capacitor C1 gradually rises. At this time, the output signal of the inverter INV2 changes from the initial low-level signal to a high-level signal, and the oscillation The output voltage of the inverter is also changed from low level to high level through the D flip-flop and the inverter shaping output; the second stage: when the output signal of the inverter INV2 changes from the initial low level signal to the high level signal, the NM2 tube changes from the off state to the on state, and the output of the NAND gate Nand also changes to a low level. The capacitor C1 begins to discharge along the NM2 tube and the NM3 tube path. At this time, the output signal of the inverter INV2 changes from the initial high level signal to a low level signal, and the oscillator output voltage is also changed from a high level to a low level through the D flip-flop and the inverter shaping output. Repeat the steps from the first stage to the second stage, so that the capacitor C is periodically charged and discharged, and the output end of the D flip-flop is led out, which is a periodic clock signal.

[0024] The logic circuit is used to generate two non-overlapping logic control signals to control the charge and discharge time of the charge pump charge and discharge circuit. The logic control signal has a certain dead time to prevent the switch tubes of the same bridge arm from opening and closing at the same time, thereby generating excessive current.

[0025] Figure 3 The figure shows the circuit diagram of the current bias circuit. The current source composed of CMOS tubes PM4, NM4 and resistor R2 generates the basic current. PM4 and PM5 tubes form a current mirror structure. The width-to-length ratio of the CMOS tube is set appropriately to copy the current in proportion. Similarly, NM6 to NM9 tubes form a current mirror structure to output the required bias current in proportion.

[0026] Figure 4The figure shows the circuit diagram of the charge and discharge circuit. The Ibias1 and Ibias2 current signals in the figure are provided by the current bias circuit. The ctrl and ctrl_not signals provided by the logic circuit are a pair of reverse signals. The ctrl_not signal controls the opening and closing of the NM10 and NM11 tubes, controls the Ibias1 and Ibias2 currents to act in the current mirror, and then affects the opening and closing of the power switch tube NLDM1. The ctrl signal controls the opening and closing of the power switch tube NLDM2. The normal operation of the module circuit is mainly divided into two stages, namely the charging stage and the discharging stage. The first stage is the charging stage, the ctrl signal is high, the ctrl_not signal is low, the power tube NLDM2 is turned on, and the power tube NLDM1 is turned off, forming a path of the power supply VM, NLDM4 (NLDM4 tube gate-source short-circuited, mainly using the principle of its body diode conduction), pump capacitor C2, NLDM2, and low potential GND, and the current flowing through charges the capacitor C2; the second stage is the discharging stage, the ctrl signal is low, the ctrl_not signal is high, the power tube NLDM1 is turned on, and the power tube NLDM2 is turned off, forming The power supply voltage VM, NLDM1, pump capacitor C2, NLDM3 (NLDM3 gate-source terminal is short-circuited, mainly using the principle of its body diode conduction), charge pump output voltage VCP, capacitor C3, power supply voltage VM path, the current flowing through the capacitor C2 charges the capacitor C3, charge pump output voltage VCP = It / C2 + VM, if not restricted, theoretically VCP can be up to 2 times of VM, which requires a feedback circuit to limit the voltage difference between VCP and VM, so that VCP reaches the required value (the difference between VCP and VM is set according to the process conditions, generally 5V (thin gate oxide process), 12V (thick gate oxide process)).

[0027] Figure 5 The circuit diagram of the voltage detection circuit is shown in FIG. The current I3 flowing through the NM16 tube is obtained mainly through the current mirror structure composed of the NM13~NM15 tubes and the PM10~PM13 tubes. The difference between the charge pump voltage VCP and the power supply voltage VM is reflected by the resistance value of the resistors R7~R9. The Ibias current in the figure is generated by the current bias module ( Figure 3 ) provides the Ibias3 current, Figure 5The current I1 in the figure is the path current from point A to the low potential GND, the current I2 is the path current from point B to the low potential GND through the PM12 tube, PM13 tube, and NM15 tube, and the current I3 is the path current from point B to the low potential GND through the NM16 tube and resistors R7~R9. At the same time, the current mirror structure composed of CMOS tubes NM13, NM14, and NM15 tubes can obtain I1=I2 (the width-to-length ratios of NM1, NM2, and NM3 are equal) (the width-to-length ratios of PM10~PM13 tubes are equal), the resistor R5 is equal to the resistor R6, and the current I flowing through the resistor R6 is R6 =I2+I3, current I1=I2=(VM-VA) / R5, current I3=I R6 -I2(=I1),I R6 =(VCP-VB) / R6=(VCP-VA) / R6, current I3=(VCP-VA) / R6-(VM-VA) / R5, I3=(VCP-VM) / R5, V out =(VCP-VM)(R5 / R7); output voltage V out It is a multiple of the voltage difference between VCP and VM, which can be adjusted by Trim <0> 、Trim <1> The port adjusts the resistance of the resistor string R7~R9 and sets the appropriate V out Output voltage, output voltage V out and Figure 1 The reference voltage of the comparator is compared with VREF1 <VREF3<VREF2,

[0028] The feedback circuit is mainly composed of two parts. One part is used to detect the voltage value of the charge pump output voltage VCP. When the difference between VCP and the power supply voltage VM reaches the set threshold, the oscillator stops working to reduce the loss of the circuit. The other part is that when the output voltage VCP of the charge pump reaches the required voltage value, the charging and discharging operation stops. At this time, the VCP voltage will gradually decrease. When VCP drops to the set threshold, the oscillator will be restarted, the charging and discharging operation will proceed normally, and the VCP voltage will recover. Figure 1 The comparator in (deleted) Figure 1 The comparator COMP1 in the circuit is the undervoltage comparator of the charge pump. Figure 5 The output voltage V out When the threshold VREF1 is not reached, the comparator output signal A is high level, and the NOR gate signal is pulled low, which will force the oscillator to work, and the output voltage of the charge pump will gradually increase. Figure 1The output signal B of the overvoltage comparator COMP2 in the circuit changes from the initial low level to the high level (the initial state B and B_not signals are both low level, acting on switches Q1 and Q2, then VREF2 and VREF3 are not connected to the positive end of the comparator COMP2, because the undervoltage comparator forces the charge pump to work, and the negative end voltage V out gradually increases, and the B signal changes from low level to high level), then VREF2 is connected to the positive end of comparator COMP2. As VCP gradually increases, V out > VREF1, the output signal A of comparator COMP1 changes from high level to low level, and the undervoltage state is released, but VCP has not risen to the set threshold, and the output signal B of comparator COMP2 is still high level. At this time, the oscillator still works normally, and the VCP voltage continues to rise. out >VREF2, the output signal B of comparator COMP2 changes from high level to low level, and the A and B signals control the oscillator to stop working after passing through the NOR gate. The subsequent logic circuit and the charge and discharge circuit are no longer charged normally, and the VCP voltage no longer continues to rise, and the required VCP voltage is obtained; at this time, the voltage drop at the output end of the charge pump VCP will slowly decrease, because the B signal changes from high level to low level, and the B_not signal changes from low level to high level. VREF3 is connected to the positive end of comparator COMP2, and the voltage difference between VCP and VM drops to V out

Claims

1. A charge pump with adjustable ripple, characterized in that: It includes an oscillator circuit, a logic circuit, a current bias circuit, a charge and discharge circuit, a voltage detection circuit and a feedback circuit; The oscillator circuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first capacitor, a first resistor, a NAND gate, a SMIT trigger, and a D trigger; wherein the input end of the first inverter is connected to a low-level signal of an enable signal, and the output end is connected to the gate of the first NMOS tube, the gate of the third PMOS tube, the gate of the third NMOS tube, and an input end of the NAND gate; the source of the first PMOS tube is connected to a power supply, and the gate and drain thereof are interconnected; the drain of the first NMOS tube is connected to the drain of the first PMOS tube, and the source of the first NMOS tube is grounded after passing through a first resistor; the source of the second PMOS tube is connected to a power supply, and the gate thereof is connected to a The drain of the first PMOS tube and the drain of the second PMOS tube are connected to the enable end of the NAND gate; the source of the third PMOS tube is connected to the power supply, and the drain thereof is connected to the output end of the NAND gate, the input end of the SMIT trigger, the drain of the second NMOS tube, and one end of the first capacitor; the source of the second NMOS tube is connected to the drain of the third NMOS tube, and the source of the third NMOS tube and the other end of the first capacitor are grounded; the output end of the SMIT trigger is connected to the input end of the second inverter, the output end of the second inverter is connected to the input end of the third inverter, the other input end of the NAND gate, and the gate of the second NMOS tube; the output end of the third inverter is connected to the input end of the D trigger, the output end of the D trigger is connected to the input end of the fourth inverter, the output end of the fourth inverter is connected to the input end of the fifth inverter, and the output end of the fifth inverter outputs a clock signal; The input of the logic circuit is a clock signal. Under the action of the clock signal, the logic circuit generates a two-phase clock signal, and the two-phase clock signals are mutually inverted signals, which are defined as ctrl and ctrl_not respectively; The current bias circuit includes a fourth PMOS tube, a fifth PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, and a second resistor; wherein the source of the fourth PMOS tube is connected to a power supply, and its gate and drain are interconnected; the drain of the fourth NMOS tube is connected to the drain of the fourth PMOS tube, the gate of the fourth NMOS tube is connected to a high-level signal of an enable signal, and the source of the fourth NMOS tube is grounded after passing through the second resistor; the source of the fifth PMOS tube is connected to a power supply, and its gate is connected to the drain of the fourth PMOS tube; the drain of the fifth NMOS tube is connected to the fifth PMOS tube. The drain of the S tube, the gate of the fifth NMOS tube is connected to the low level signal of the enable signal, and the source of the fifth NMOS tube is grounded; the drain and gate of the sixth NMOS tube are connected to the drain of the fifth PMOS tube, and the source of the sixth NMOS tube is grounded; the gate of the seventh NMOS tube, the gate of the eighth NMOS tube, and the gate of the ninth NMOS tube are connected to the drain of the fifth PMOS tube, the source of the seventh NMOS tube, the source of the eighth NMOS tube, and the source of the ninth NMOS tube are grounded, the drain of the seventh NMOS tube outputs the first bias signal, the drain of the eighth NMOS tube outputs the second bias signal, and the drain of the ninth NMOS tube outputs the third bias signal; The charge and discharge circuit includes a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a third resistor, a second capacitor, a third capacitor, a first Zener diode, a first high-voltage NMOS tube, a second high-voltage NMOS tube, a third high-voltage NMOS tube, and a fourth high-voltage NMOS tube; wherein the source of the sixth PMOS tube is connected to the charge pump output voltage, and the gate and drain thereof are interconnected; the drain of the tenth NMOS tube is connected to the drain of the sixth PMOS tube, the gate of the tenth NMOS tube is connected to ctrl_not, and the source thereof is connected to the first bias signal; the source of the seventh PMOS tube is connected to the charge pump output voltage, and the gate thereof is connected to the drain of the sixth PMOS tube; the source of the eighth PMOS tube is connected to the charge pump input voltage, and the gate and drain thereof are interconnected; the drain of the eleventh NMOS tube is connected to the drain of the eighth PMOS tube, the gate of the eleventh NMOS tube is connected to ctrl_not, and the source thereof is connected to the second Bias signal; the source of the ninth PMOS tube is connected to the charge pump input voltage, and its gate is connected to the drain of the eighth PMOS tube; the anode of the first Zener diode is connected to the drain of the ninth PMOS tube, and the cathode of the first Zener diode is connected to the drain of the seventh PMOS tube, the gate of the first high-voltage NMOS tube, the drain of the twelfth NMOS tube, and one end of the third resistor; the other end of the third resistor is grounded; the drain of the first high-voltage NMOS tube is connected to the charge pump input voltage, and its source is connected to the drain of the second high-voltage NMOS tube and one end of the second capacitor; the gate of the twelfth NMOS tube is connected to ctrl, and its source is grounded; the gate of the second high-voltage NMOS tube is connected to ctrl, and its source is grounded; the drain of the third high-voltage NMOS tube is connected to the charge pump output voltage and one end of the third capacitor, and its gate and drain are interconnected; the drain of the fourth high-voltage NMOS tube is connected to the drain of the third high-voltage NMOS tube and the other end of the second capacitor, and the gate and source of the fourth high-voltage NMOS tube are connected to the charge pump input voltage and the other end of the third capacitor; The voltage detection circuit comprises a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor; wherein the gate and drain of the thirteenth NMOS tube are connected to the third bias signal, and the source thereof is grounded; one end of the fourth resistor and one end of the sixth resistor are connected to the charge pump output voltage, the other end of the fourth resistor and one end of the fifth resistor are connected to the charge pump input voltage, the other end of the fifth resistor is connected to the source of the tenth PMOS tube, and the gate and drain of the tenth PMOS tube are interconnected; the source of the eleventh PMOS tube is connected to the drain of the tenth PMOS tube, and the gate and drain thereof are interconnected; the gate of the fourteenth NMOS tube is connected to the third bias signal, the drain thereof is connected to the drain of the eleventh PMOS tube, and the source of the fourteenth PMOS tube is grounded; The source of the MOS tube is connected to the other end of the sixth resistor, and the gate thereof is connected to the drain of the tenth PMOS tube; the source of the thirteenth PMOS tube is connected to the drain of the twelfth PMOS tube, and the gate thereof is connected to the drain of the eleventh PMOS tube; the gate of the fifteenth NMOS tube is connected to the third bias signal, the drain thereof is connected to the drain of the thirteenth PMOS tube, and the source of the fifteenth PMOS tube is grounded; the drain of the sixteenth NMOS tube is connected to the other end of the sixth resistor, the gate thereof is connected to the drain of the thirteenth PMOS tube, the source of the sixteenth NMOS tube is connected to the ground after passing through the seventh resistor, the eighth resistor, and the ninth resistor in sequence, and the connection point between the source of the sixteenth NMOS tube and the seventh resistor outputs a detection voltage signal; the drain of the seventeenth NMOS tube is connected to the connection point of the seventh resistor and the eighth resistor, and the gate thereof is connected to the first resistor control signal; the drain of the eighteenth NMOS tube is connected to the source of the seventeenth NMOS tube, the connection point of the eighth resistor and the ninth resistor, the gate of the eighteenth NMOS tube is connected to the second resistor control signal, and the source of the eighteenth NMOS tube is grounded; The feedback circuit includes a first comparator, a second comparator, and an NOR gate; wherein the positive input terminal of the first comparator is connected to the first reference signal, the negative input terminal is connected to the detection voltage signal, and the output terminal is connected to one input terminal of the NOR gate; the negative input terminal of the second comparator is connected to the detection voltage signal, the positive input terminal is connected to the second reference signal and the third reference signal respectively through two switching tubes, and the output terminal is connected to the other input terminal of the NOR gate, and the enable signals of the two switching tubes are the voltage signals of the other end of the fifth resistor and the other end of the sixth resistor respectively; the NOR gate outputs a high-level signal or a low-level signal of the enable signal.

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