Orthogonal signal generation circuit and electronic equipment

Abstract

The embodiment of the invention provides an orthogonal signal generation circuit and electronic equipment. The orthogonal signal generation circuit comprises a single-slip module, an orthogonal frequency division module and an output module, the four-path orthogonal signal conversion module is used for converting an input first signal and outputting the converted signal into four-path target orthogonal signals. According to the orthogonal signal generation circuit provided by the embodiment of the invention, high-consistency ultra-wideband orthogonal signal output can be realized, and a high-quality local oscillator signal can be provided for an orthogonal frequency conversion transceiver; the transceiver can utilize the local oscillator signal to suppress interference of the mirror image signal and stray of signal radiation. The circuit also can directly generate four paths of orthogonal signals with preset duty ratios, reduces the image current of the mixer, has enough driving capability, and can provide enough grid turn-on voltage for the mixer. The orthogonal signal generation circuit also has the advantages of small area, low power consumption and the like, and solves the problems of the orthogonal signal generation circuit in the related technology.

Description

Technical Field

[0001] The present disclosure relates to the technical field of radio frequency integrated circuits, and in particular to an orthogonal signal generating circuit and electronic equipment. Background Art

[0002] Orthogonal frequency conversion technology can eliminate the image signal by superimposing two orthogonal signals, which can be used to solve the image suppression problem in wireless receivers or the image spurious problem in wireless transmitters. Traditional orthogonal signal generation circuits include multiphase networks based on resistors, capacitors and inductors, orthogonal frequency dividers based on master-slave trigger circuits, and orthogonal inductor-capacitor oscillators, all of which have defects in practical applications. For multiphase networks, the amplitude and bandwidth of their output signals usually have a mutually restrictive relationship. In practical applications, multiple multiphase networks need to be cascaded, which will lead to a huge attenuation of the signal amplitude, thereby greatly increasing the complexity of the post-stage buffer. For orthogonal frequency dividers based on master-slave trigger circuits, their circuits are restricted by the charging and discharging speed of the input and output capacitors and the signal delay caused by them, and it is difficult to process high-frequency input signals above 10GHz. For orthogonal inductor-capacitor oscillators, the power consumption is twice that of general oscillators, and the presence of inductors will greatly increase the area of ​​the entire circuit. Summary of the invention

[0003] The embodiments of the present disclosure provide an orthogonal signal generating circuit and an electronic device to solve the problems in the related art that the orthogonal signal generating circuit is complex, has a large area and is difficult to process high-frequency input signals.

[0004] Based on the above problems, in a first aspect, an embodiment of the present disclosure provides an orthogonal signal generating circuit, including: a single-slip module, an orthogonal frequency division module and an output module; Wherein, the single slip module is connected to the orthogonal frequency division module, and the single slip module and the output module respectively include a corresponding number of inverters; the inverter includes: a PMOS tube and an NMOS tube, the gate of the PMOS tube is connected to the gate of the NMOS tube as the inverter input end, and the drain of the PMOS tube is connected to the drain of the NMOS tube as the inverter output end; The single-slip differential module is used to convert the input first signal into a first differential signal and a second differential signal, and transmit the first differential signal and the second differential signal to the orthogonal frequency division module; The orthogonal frequency division module is used to convert the received first differential signal and second differential signal into four orthogonal signals; The output module is connected to the orthogonal frequency division module, and is used for receiving the orthogonal signal and outputting the orthogonal signal as four target orthogonal signals after shaping.

[0005] In combination with the first aspect, in a possible implementation manner, the single-slip module includes: a bias input circuit, a switch inverter, a first differential output circuit, a second differential output circuit, and a feedback circuit; The bias input circuit is connected to the switch inverter, and is used to remove the DC voltage in the input first signal, introduce a preset bias voltage, and output a second signal; The switch inverter is used to control the on and off of the single-slip module; and / or convert the second signal into a third signal and output the third signal; The first differential output circuit and the second differential output circuit are respectively connected to the switch inverter, and are used to convert the third signal into a pair of differential signals; The feedback circuit is connected to the first differential output circuit and the second differential output circuit respectively, and is used for providing feedback to stabilize the differential states of the first differential output circuit and the second differential output circuit.

[0006] In combination with the first aspect, in a possible implementation manner, the bias input circuit includes: a first capacitor, a first resistor, a second resistor, a third resistor and a first switch; The first signal is input from one end of the first capacitor, and the other end of the first capacitor is respectively connected to one end of the first resistor, one end of the second resistor, one end of the third resistor and a switch inverter; the first capacitor is used to remove the DC voltage in the first signal; the other end of the first resistor is connected to the output end of the first switch; the first switch input end inputs an off-chip bias voltage, and the first switch control end inputs a first enable signal, and the first enable signal is used to control the on and off of the first switch; the other end of the second resistor is connected to a power supply; the other end of the third resistor is grounded; The bias input circuit is further used to introduce a preset bias voltage through the second resistor, the third resistor and the first switch, increase the bias voltage for the input first signal, and output a second signal.

[0007] In combination with the first aspect, in a possible implementation manner, the switch inverter includes: a first inverter, a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor; The first inverter input end is connected to the bias input circuit, and the first inverter output end is connected to the first differential output circuit, the second differential output circuit and the second NMOS tube; the first inverter is used to convert the input second signal into a third signal; the first PMOS tube drain is connected to the PMOS tube source in the first inverter, the first PMOS tube source is connected to the power supply, and the second enable signal is input to the first PMOS tube gate to control the first PMOS tube to be turned on or off; the first NMOS tube drain is connected to the NMOS tube source in the first inverter, the first NMOS tube source is grounded, and the third enable signal is input to the first NMOS tube gate to control the first NMOS tube to be turned on or off; the second NMOS tube drain is connected to the first inverter output end, the second NMOS tube source is grounded, and the fourth enable signal is input to the second NMOS tube gate to control the second NMOS tube to be turned on or off; The first NMOS tube, the first PMOS tube and the second PMOS tube are turned on and off by an enable signal, so as to eliminate the influence of the static current in the switching inverter.

[0008] In combination with the first aspect, in a possible implementation manner, the first differential output circuit includes: a second inverter, a third inverter, a fourth inverter, and a fifth inverter; The input end of the second inverter is connected to the switch inverter for receiving the third signal; the input end of the third inverter is connected to the output end of the second inverter; the input end of the fourth inverter is connected to the output end of the third inverter; the input end of the fifth inverter is connected to the output end of the fourth inverter and the feedback circuit; the output end of the fifth inverter is connected to the orthogonal frequency division module, and outputs a first differential signal; The first differential output circuit is used to adjust the phase of the input signal and output a first differential signal after shaping the signal.

[0009] In combination with the first aspect, in a possible implementation manner, the second differential output circuit includes: a transmission gate, a sixth inverter, a seventh inverter, and an eighth inverter; The transmission gate comprises: a second PMOS tube and a third NMOS tube; the drain of the second PMOS tube is connected to the drain of the third NMOS tube as the transmission gate input, the source of the second PMOS tube is connected to the source of the third NMOS tube as the transmission gate output, the gate of the second PMOS tube is grounded, and the gate of the third NMOS tube is connected to a power supply; The transmission gate input end is connected to the switch inverter for receiving the third signal; the input end of the sixth inverter is connected to the transmission gate output end; the input end of the seventh inverter is connected to the output end of the sixth inverter; the input end of the eighth inverter is connected to the output end of the seventh inverter and the feedback circuit; the output end of the eighth inverter is connected to the orthogonal frequency division module and outputs a second differential signal; The second differential output circuit is used to adjust the phase of the input signal and output a second differential signal after shaping the signal.

[0010] In combination with the first aspect, in a possible implementation manner, the feedback circuit includes: a ninth inverter and a tenth inverter; The ninth inverter input terminal is connected to the seventh inverter output terminal, and the ninth inverter output terminal is connected to the fourth inverter output terminal; the tenth inverter input terminal is connected to the fourth inverter output terminal, and the tenth inverter output terminal is connected to the seventh inverter output terminal.

[0011] In combination with the first aspect, in a possible implementation, the orthogonal frequency division module includes: a first NAND gate circuit, a second NAND gate circuit, a third NAND gate circuit, a fourth NAND gate circuit, a fifth NAND gate circuit, a sixth NAND gate circuit, a seventh NAND gate circuit and an eighth NAND gate circuit; wherein the first NAND gate circuit, the second NAND gate circuit, the third NAND gate circuit and the fourth NAND gate circuit are respectively connected to the single-slip differential module, receive the input first differential signal and / or the second differential signal, and respectively output orthogonal signals to the output module; The fifth NAND gate circuit, the sixth NAND gate circuit, the seventh NAND gate circuit and the eighth NAND gate circuit include: a third PMOS transistor, a fourth PMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor; The gate of the third PMOS tube is connected to the gate of the fifth NMOS tube as the first input terminal of the NAND gate, the source of the third PMOS tube is connected to the source of the fourth PMOS tube and the power supply, the drain of the third PMOS tube is connected to the drain of the fourth NMOS tube and the drain of the fourth PMOS tube as the first output terminal of the NAND gate; the gate of the fourth PMOS tube is connected to the gate of the fourth NMOS tube as the second input terminal of the NAND gate; the source of the fourth NMOS tube is connected to the drain of the fifth NMOS tube; the source of the fifth NMOS tube is grounded; The first NAND gate circuit, the second NAND gate circuit, the third NAND gate circuit and the fourth NAND gate circuit include: a fifth PMOS transistor, a sixth PMOS transistor, a sixth NMOS transistor and a seventh NMOS transistor; The gate of the fifth PMOS tube is connected to the gate of the sixth NMOS tube as the third input terminal of the NAND gate, the source of the fifth PMOS tube is connected to the source of the sixth PMOS tube and the power supply, the drain of the fifth PMOS tube is connected to the drain of the sixth PMOS tube and the drain of the sixth NMOS tube as the second output terminal of the NAND gate; the gate of the sixth PMOS tube is connected to the gate of the seventh NMOS tube as the fourth input terminal of the NAND gate; the source of the sixth NMOS tube is connected to the drain of the seventh NMOS tube; the source of the seventh NMOS tube is grounded.

[0012] In combination with the first aspect, in a possible implementation manner, the fourth input terminal of the NAND gate of the first NAND gate circuit is connected to the single-slip differential module to receive the second differential signal, the third input terminal of the NAND gate of the first NAND gate circuit is connected to the first output terminal of the NAND gate of the fifth NAND gate circuit, and the second output terminal of the NAND gate of the first NAND gate circuit is connected to the first input terminal of the NAND gate of the sixth NAND gate circuit and the output module; The first input terminal of the NAND gate of the fifth NAND gate circuit is connected to the first output terminal of the NAND gate of the seventh NAND gate circuit, and the second input terminal of the NAND gate of the fifth NAND gate circuit is connected to the second output terminal of the NAND gate of the fourth NAND gate circuit; The fourth input terminal of the NAND gate of the fourth NAND gate circuit is connected to the single-slip differential module to receive the first differential signal, the third input terminal of the NAND gate of the fourth NAND gate circuit is connected to the first output terminal of the NAND gate of the eighth NAND gate circuit, and the second output terminal of the NAND gate of the fourth NAND gate circuit is connected to the output module; The first input terminal of the NAND gate of the eighth NAND gate circuit is connected to the first output terminal of the NAND gate of the sixth NAND gate circuit, and the second input terminal of the NAND gate of the eighth NAND gate circuit is connected to the second output terminal of the NAND gate of the third NAND gate circuit; The fourth input terminal of the NAND gate of the third NAND gate circuit is connected to the single-slip differential module to receive the second differential signal, the third input terminal of the NAND gate of the third NAND gate circuit is connected to the first output terminal of the NAND gate of the seventh NAND gate circuit, and the second output terminal of the NAND gate of the third NAND gate circuit is connected to the output module; The first input terminal of the NAND gate of the seventh NAND gate circuit is connected to the first output terminal of the NAND gate of the fifth NAND gate circuit, and the second input terminal of the NAND gate of the seventh NAND gate circuit is connected to the second output terminal of the NAND gate of the second NAND gate circuit; The fourth input terminal of the NAND gate of the second NAND gate circuit is connected to the single-slip differential module to receive the first differential signal, the third input terminal of the NAND gate of the second NAND gate circuit is connected to the first output terminal of the NAND gate of the sixth NAND gate circuit, and the second output terminal of the NAND gate of the second NAND gate circuit is connected to the output module; The first input terminal of the NAND gate of the sixth NAND gate circuit is connected to the first output terminal of the NAND gate of the eighth NAND gate circuit, and the second input terminal of the NAND gate of the sixth NAND gate circuit is connected to the second output terminal of the NAND gate of the first NAND gate circuit.

[0013] In combination with the first aspect, in a possible implementation manner, the output module includes: a first inverter chain, a second inverter chain, a third inverter chain, and a fourth inverter chain; The inverter chain is composed of a preset number of inverters connected in series, and the preset number is an odd number; the input end of the first inverter in the inverter chain is respectively connected to the orthogonal frequency division module, and the input end of any inverter except the first inverter in the inverter chain is connected to the output end of the previous inverter, and the output end of the inverter at the end of the inverter chain outputs the corresponding target orthogonal signal; Any two inverter chains among the first inverter chain, the second inverter chain, the third inverter chain and the fourth inverter chain have the same structure and the same number of inverters.

[0014] In combination with the first aspect, in a possible implementation manner, the single-slip differential module is used to receive an input first signal, convert the first signal into a pair of differential signals including a first differential signal and a second differential signal based on an enable signal; and input the differential signal into the orthogonal frequency division module; The orthogonal frequency division module is used to generate four orthogonal signals with preset duty cycles based on the orthogonal frequency division module state and the differential signal period when the differential signal is received; and input the orthogonal signals into the output module; The inverter chain in the output module is used to respectively receive corresponding orthogonal signals, adjust the duty cycle of the orthogonal signals, and generate target orthogonal signals.

[0015] A second aspect of an embodiment of the present disclosure provides an electronic device, comprising: an orthogonal signal generating circuit as described in any one of the first aspects.

[0016] The beneficial effects of the embodiments of the present disclosure include: The embodiments of the present disclosure provide an orthogonal signal generating circuit and an electronic device, comprising: a single-slip module, an orthogonal frequency division module and an output module; wherein the single-slip module is connected to the orthogonal frequency division module, and the single-slip module and the output module respectively include a corresponding number of inverters; the inverter includes: a PMOS tube and an NMOS tube, the gate of the PMOS tube is connected to the gate of the NMOS tube as the inverter input end, and the drain of the PMOS tube is connected to the drain of the NMOS tube as the inverter output end; the single-slip module is used to convert an input first signal into a first differential signal and a second differential signal, and transmit the first differential signal and the second differential signal to the orthogonal frequency division module; the orthogonal frequency division module is used to convert the received first differential signal and the second differential signal into four orthogonal signals; the output module is connected to the orthogonal frequency division module, used to receive the orthogonal signal, and output the orthogonal signal as four target orthogonal signals after shaping. The orthogonal signal generating circuit provided by the embodiment of the present disclosure can realize highly consistent ultra-wideband orthogonal signal output, and can provide high-quality local oscillator signals for orthogonal frequency conversion transceivers; the transceiver can use the local oscillator signal to suppress the interference of the image signal and the spurious signal radiation. The circuit can also directly generate four-way orthogonal signals with a preset duty cycle, reduce the image current of the mixer, and have sufficient driving capability to provide the mixer with sufficient gate turn-on voltage. The orthogonal signal generating circuit also has the advantages of small area and low power consumption, and solves the problems existing in the orthogonal signal generating circuit in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of the structure of an orthogonal signal generating circuit provided in an embodiment of the present disclosure; Figure 2 A structural diagram of a single-slip module provided in an embodiment of the present disclosure; Figure 3 A structural diagram of a bias input circuit provided in an embodiment of the present disclosure; Figure 4 A structural diagram of a switching inverter provided in an embodiment of the present disclosure; Figure 5 A structural diagram of a first differential output circuit provided in an embodiment of the present disclosure; Figure 6 A structural diagram of a second differential output circuit provided in an embodiment of the present disclosure; Figure 7 A structural diagram of a feedback circuit provided in an embodiment of the present disclosure; Figure 8 A structural diagram of an orthogonal frequency division module provided in an embodiment of the present disclosure; Fig. 9 A structural diagram of a first NAND gate circuit, a second NAND gate circuit, a third NAND gate circuit and a fourth NAND gate circuit provided in an embodiment of the present disclosure; Fig.10 A structural diagram of a fifth NAND gate circuit, a sixth NAND gate circuit, a seventh NAND gate circuit and an eighth NAND gate circuit provided in an embodiment of the present disclosure; Fig.11a A schematic diagram of a low level output of a NAND gate circuit provided in an embodiment of the present disclosure; Fig.11b A schematic diagram of a high level output of a NAND gate circuit provided in an embodiment of the present disclosure; Fig.12 A schematic diagram of an on-chip layout design method for an orthogonal frequency division module provided in an embodiment of the present disclosure; Fig.13 A schematic diagram of in-phase / quadrature (I / Q) amplitude / phase error and image suppression ratio of an output signal of an orthogonal signal generating circuit provided in an embodiment of the present disclosure; Fig.14 A structural diagram of an inverter chain of an output module provided in an embodiment of the present disclosure; Fig.15 A schematic diagram of signal changes of an orthogonal frequency division module provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] The embodiments of the present disclosure provide an orthogonal signal generating circuit and electronic device. The preferred embodiments of the present disclosure are described below in conjunction with the drawings of the specification. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present disclosure, and are not used to limit the present disclosure. In addition, the embodiments in the present application and the features in the embodiments can be combined with each other if there is no conflict.

[0019] The present disclosure provides an orthogonal signal generating circuit, such as Figure 1 As shown, it includes: a single-slip module 1, an orthogonal frequency division module 2 and an output module 3; The single slip module 1 is connected to the orthogonal frequency division module 2, and the single slip module 1 and the output module 3 respectively include a preset number of inverters; the inverter includes: a PMOS tube and an NMOS tube, the gate of the PMOS tube is connected to the gate of the NMOS tube as the inverter input end, and the drain of the PMOS tube is connected to the drain of the NMOS tube as the inverter output end; The single-slip differential module 1 is used to convert the input first signal into a first differential signal and a second differential signal, and transmit the first differential signal and the second differential signal to the orthogonal frequency division module 2; The orthogonal frequency division module 2 is used to convert the received first differential signal and the second differential signal into four orthogonal signals; The output module 3 is connected to the orthogonal frequency division module 2, and is used for receiving the orthogonal signal and outputting the orthogonal signal into four target orthogonal signals after shaping.

[0020] In the disclosed embodiment, the inverter may be a complementary metal oxide semiconductor (CMOS) inverter. The CMOS inverter is composed of a P-channel MOS tube (PMOS, Positive channel Metal Oxide Semiconductor) and an N-channel MOS tube (NMOS, Negative channel Metal Oxide Semiconductor). During the operation of the CMOS inverter, the two MOS tubes are not turned on at the same time. When the input signal at the input end of the inverter is high, the NMOS tube is turned on, the PMOS tube is turned off, and the inverter output signal is low; when the input signal at the input end of the inverter is low, the PMOS tube is turned on, the NMOS tube is turned off, and the inverter output signal is high. According to this principle, the CMOS inverter realizes the inverted output of the input signal.

[0021] In the disclosed embodiment, the orthogonal signal generating circuit includes: a single slip module 1, an orthogonal frequency division module 2 and an output module 3. Among them, the single slip module 1 includes: an inverter and a transmission gate. The first signal input from the signal input port to the single slip module 1 can be a single-ended sinusoidal signal. After being processed by the single slip module 1, the first signal is converted into a pair of differential signals consisting of a first differential signal and a second differential signal. At the same time, the single slip module 1 can also shape the sinusoidal signal into a square wave signal to meet the input requirements of the orthogonal frequency division module 2. The working state of the single slip module 1 is controlled by the input enable signal. In a possible implementation, when the enable signal is at a high level, the single slip module 1 is in a working state and outputs a differential signal pair; when the enable signal is at a low level, the single slip module 1 is in a stopped state, does not output a signal to the outside, and the entire orthogonal signal generating circuit does not work.

[0022] The orthogonal frequency division module 2 includes multiple NAND gate circuits, which can convert the differential signal into a four-phase orthogonal signal using specific timing logic. In the process of generating the orthogonal signal, the orthogonal frequency division module 2 will perform frequency division on the signal, and the frequency of the output signal is half of the input first signal.

[0023] The output module 3 includes an output buffer formed by a tapered inverter chain, and reshapes the four output signals of the orthogonal frequency division module 2 respectively to output four orthogonal signals.

[0024] The circuit provided in the embodiment of the present disclosure can be integrated into a transceiver chip. The orthogonal signals generated by the circuit can be superimposed to eliminate the image signals in the transceiver, thereby effectively avoiding the image suppression problem in the wireless receiver or the image spurious problem in the wireless transmitter.

[0025] In another embodiment provided by the present disclosure, Figure 2 As shown, the single-slip module 1 includes: a bias input circuit 11, a switch inverter 12, a first differential output circuit 13, a second differential output circuit 14, and a feedback circuit 15; The bias input circuit 11 is connected to the switch inverter 12, and the bias input circuit 11 is used to remove the DC voltage in the input first signal, introduce a preset bias voltage, and output a second signal; The switch inverter 12 is used to control the single-slip module 1 to be turned on and off; and / or to convert the second signal into a third signal and output the third signal; The first differential output circuit 13 and the second differential output circuit 14 are respectively connected to the switch inverter 12, and are used to convert the third signal into a pair of differential signals; The feedback circuit 15 is connected to the first differential output circuit 13 and the second differential output circuit 14 respectively, and is used for providing feedback to stabilize the differential states of the first differential output circuit 13 and the second differential output circuit 14 .

[0026] In the disclosed embodiment, the first signal is input into the bias input circuit 11, the bias input circuit 11 removes the original DC voltage in the first signal, introduces a stable DC voltage as a bias voltage, and inputs the signal after the stable bias voltage is introduced into the switch inverter 12 as the second signal.

[0027] The switch inverter 12 receives the enable signal and the second signal, and uses the enable signal to control the state of the single-slip module 1; at the same time, the second signal is converted into a third signal, which can be a single-ended square wave signal. The switch inverter 12 outputs the third signal to the first differential output circuit 13 and the second differential output circuit 14 respectively.

[0028] The first differential output circuit 13 further reshapes the third signal into a square wave signal using multiple inverters to form a first differential signal and output it; the second differential output circuit 14 reshapes the third signal using a transmission gate and multiple inverters, and adjusts the phase to form a second differential signal. The first differential signal and the second differential signal have the same amplitude and a phase difference of 180°.

[0029] The feedback circuit 15 is connected to the first differential output circuit 13 and the second differential output circuit 14 respectively, and is used to feedback and stabilize the states of the two paths.

[0030] In another embodiment provided by the present disclosure, Figure 3 As shown, the bias input circuit 11 includes: a first capacitor 111, a first resistor 112, a second resistor 113, a third resistor 114 and a first switch 115; The first signal is input from one end of the first capacitor 111, and the other end of the first capacitor 111 is respectively connected to one end of the first resistor 112, one end of the second resistor 113, one end of the third resistor 114 and the switch inverter 12; the first capacitor 111 is used to remove the DC voltage in the first signal; the other end of the first resistor 112 is connected to the output end of the first switch 115; the input end of the first switch 115 inputs an off-chip bias voltage, and the first switch control end 117 inputs a first enable signal, and the first enable signal is used to control the on and off of the first switch 115; the other end of the second resistor 113 is connected to the power supply; the other end of the third resistor 114 is grounded; The bias input circuit 11 is further used to introduce a preset bias voltage through the second resistor 113, the third resistor 114 and the first switch 115, to increase the bias voltage for the input first signal, and to output a second signal.

[0031] In the disclosed embodiment, the first signal is input into the bias input circuit 11 from the bias input circuit input terminal 116 (i.e., one end of the first capacitor 111 ). The capacitor can remove the DC component in the signal and remove the DC voltage in the first signal.

[0032] Furthermore, the circuit introduces a stable bias voltage for the first signal to provide a stable driving capability for the subsequent circuit; and outputs the signal from the bias input circuit output terminal 118 as a second signal. The stable bias voltage can be determined by a pair of resistors of equal resistance (i.e., the second resistor 113 and the third resistor 114). The stable bias voltage value should be stable at half the power supply voltage value, so that after the first signal is superimposed with the bias voltage, the output waveform distortion caused by the cutoff of the MOS tube inside the inverter can be avoided. In the actual production process, the error caused by the wafer process may cause the resistance values ​​of the second resistor 113 and the third resistor 114 to be different, resulting in the introduced bias voltage value being unable to be stabilized at half the power supply voltage value. To solve this problem, a preset voltage can be introduced from outside the chip to input the input terminal of the first switch 115, and under the control of the first enable signal, the preset voltage outside the chip is input into the first signal to ensure that the introduced bias voltage value is stable at half the power supply voltage value; wherein, the first enable signal is input from the first switch control terminal 117 to the first switch 115 to control the on and off of the first switch 115.

[0033] In another embodiment provided by the present disclosure, Figure 4 As shown, the switch inverter 12 includes: a first inverter 121, a first PMOS transistor 122, a first NMOS transistor 123 and a second NMOS transistor 124; The input end of the first inverter 121 is connected to the bias input circuit 11, and the output end of the first inverter 121 is connected to the first differential output circuit 13, the second differential output circuit 14 and the second NMOS tube 124; the first inverter 121 is used to convert the input second signal into a third signal; the drain of the first PMOS tube 122 is connected to the source of the PMOS tube in the first inverter 121, and the source of the first PMOS tube 122 is connected to the power supply, and the second enable signal is input to the gate of the first PMOS tube 122 to control The first PMOS tube 122 is turned on and off; the drain of the first NMOS tube 123 is connected to the source of the NMOS tube in the first inverter 121, the source of the first NMOS tube 123 is grounded, and the third enable signal is input to the gate of the first NMOS tube 123 to control the first NMOS tube 123 to be turned on and off; the drain of the second NMOS tube 124 is connected to the output end of the first inverter 121, the source of the second NMOS tube 124 is grounded, and the fourth enable signal is input to the gate of the second NMOS tube 124 to control the second NMOS tube 124 to be turned on and off; The first PMOS transistor 122 , the first NMOS transistor 123 and the second NMOS transistor 124 are turned on and off by the enable signal, so as to eliminate the influence of the static current in the switching inverter 12 .

[0034] In the disclosed embodiment, the first PMOS tube 122, the first NMOS tube 123 and the second NMOS tube 124 act as switches and are controlled by the second enable signal, the third enable signal and the fourth enable signal, respectively, wherein the third enable signal is opposite to the second enable signal and the fourth enable signal, that is, when the third enable signal is at a high level, the second enable signal and the fourth enable signal are at a low level; when the third enable signal is at a low level, the second enable signal and the fourth enable signal are at a high level.

[0035] In one possible implementation, the second enable signal is input to the second enable signal input terminal 125 (i.e., the gate of the first PMOS tube 122), the third enable signal is input to the third enable signal input terminal 126 (i.e., the gate of the first NMOS tube 123), and the fourth enable signal is input to the fourth enable signal input terminal 127 (i.e., the gate of the second NMOS tube 124).

[0036] When the second enable signal is at a low level, the source and drain of the first PMOS tube 122 are turned on, and the first inverter 121 is connected to the power supply; when the second enable signal is at a low level, the third enable signal is at a high level, the first NMOS tube 123 is turned on, and the first inverter 121 is grounded; when the second enable signal is at a low level, the fourth enable signal is at a low level, and the second NMOS tube 124 is turned off. That is, when the second enable signal and the fourth enable signal are at a low level, and the third enable signal is at a high level, the first inverter 121 is in a working state, and the second signal input from the switch inverter input terminal 128 (i.e., the first inverter 121 input terminal) is inverted, and shaped into a square wave signal (i.e., the third signal) and output through the switch inverter output terminal 129.

[0037] When the second enable signal and the fourth enable signal are at high level and the third enable signal is at low level, the first inverter 121 does not work and the second NMOS transistor 124 is turned on. The noise signal (i.e., static current) that may exist in the inverter can be introduced into the ground line through the second NMOS transistor 124, so that the switch inverter 12 in this state has no signal output.

[0038] In practical applications, the first NMOS tube 123 and the first PMOS tube 122 can be selected with a larger gate width to reduce the on-resistance, increase the charge and discharge current, and reduce the charge and discharge time of the MOS tube; the second NMOS tube 124 can be selected with a smaller gate width so that when the inverter is in the working state, the off capacitance of the second NMOS tube 124 is small enough. This design can reduce the influence of the parasitic capacitance of the MOS tube in the circuit on the signal quality.

[0039] In a possible implementation, the transceiver can determine whether the signal of the received signal frequency needs to use the orthogonal signal to eliminate the image signal therein, based on the frequency of the received signal. And send a corresponding enable signal to control the on and off of the switch inverter, thereby controlling the working state of the orthogonal signal generation circuit. The orthogonal signal generation circuit is made to switch the working state as needed, and this design can reduce the overall power consumption of the transceiver.

[0040] In another embodiment provided by the present disclosure, Figure 5 As shown, the first differential output circuit 13 includes: a second inverter 131, a third inverter 132, a fourth inverter 133 and a fifth inverter 134; The input end of the second inverter 131 is connected to the switch inverter 12 for receiving the third signal; the input end of the third inverter 132 is connected to the output end of the second inverter 131; the input end of the fourth inverter 133 is connected to the output end of the third inverter 132; the input end of the fifth inverter 134 is connected to the output end of the fourth inverter 133 and the feedback circuit 15; the output end of the fifth inverter 134 is connected to the orthogonal frequency division module 2, and outputs the first differential signal; The first differential output circuit 13 is used to adjust the phase of the input signal and output a first differential signal after signal shaping.

[0041] In the embodiment of the present disclosure, the third signal is input into the first differential output circuit 13 via the first differential output circuit input terminal 135 (i.e., the second inverter 131 input terminal); the third signal forms a first differential signal after passing through each inverter, and the first differential signal is output via the first differential output circuit output terminal 136 (i.e., the fifth inverter 134 output terminal).

[0042] The first differential output circuit 13 may be an inverter chain composed of a plurality of inverters, any inverter adjusts the phase of the input signal and outputs it after shaping. In practical applications, the size of each level of inverter (i.e., the channel length and width of the PMOS tube and the NMOS tube in the inverter) is increased successively to provide sufficient driving capability.

[0043] In another embodiment provided by the present disclosure, Figure 6 As shown, the second differential output circuit 14 includes: a transmission gate 141, a sixth inverter 142, a seventh inverter 143 and an eighth inverter 144; The transmission gate 141 includes: a second PMOS tube and a third NMOS tube; the drain of the second PMOS tube and the drain of the third NMOS tube are connected as the input end of the transmission gate 141, the source of the second PMOS tube and the source of the third NMOS tube are connected as the output end of the transmission gate 141, the gate of the second PMOS tube is grounded, and the gate of the third NMOS tube is connected to the power supply; The input end of the transmission gate 141 is connected to the switch inverter 12 for receiving the third signal; the input end of the sixth inverter 142 is connected to the output end of the transmission gate 141; the input end of the seventh inverter 143 is connected to the output end of the sixth inverter 142; the input end of the eighth inverter 144 is connected to the output end of the seventh inverter 143 and the feedback circuit 15; the output end of the eighth inverter 144 is connected to the orthogonal frequency division module 2, and outputs the second differential signal; The second differential output circuit 14 is used to adjust the phase of the input signal and output a second differential signal after signal shaping.

[0044] In the embodiment of the present disclosure, the third signal is input into the second differential output circuit 14 via the second differential output circuit input terminal 145 (i.e., the input terminal of the transmission gate 141); the third signal forms a second differential signal after passing through the transmission gate and each inverter, and the second differential signal is output via the second differential output circuit output terminal 146 (i.e., the output terminal of the eighth inverter 144).

[0045] The second differential output circuit 14 may be a circuit composed of a transmission gate 141 and an inverter chain, and the number of inverters in the inverter chain in the second differential circuit is one less than the number of inverters in the first differential output circuit 13. Because the number of inverters in the second differential circuit is one less than that in the first differential circuit, the phase of the second differential signal output by the second differential circuit differs from the phase of the first differential signal by 180°, and the first differential signal and the second differential signal form a differential signal pair.

[0046] When the gate of the third NMOS transistor of the transmission gate 141 circuit inputs a high level and the gate of the second PMOS transistor is a low level, the transmission gate 141 circuit is turned on. The transmission gate 141 circuit is used in the second differential output circuit 14 to balance the delay of the first differential signal and the second differential signal.

[0047] In another embodiment provided by the present disclosure, Figure 7 As shown, the feedback circuit 15 includes: a ninth inverter 151 and a tenth inverter 152; The input end of the ninth inverter 151 is connected to the output end of the seventh inverter 143 , and the output end of the ninth inverter 151 is connected to the output end of the fourth inverter 133 ; the input end of the tenth inverter 152 is connected to the output end of the fourth inverter 133 , and the output end of the tenth inverter 152 is connected to the output end of the seventh inverter 143 .

[0048] In the embodiment of the present disclosure, the feedback circuit 15 can use the positive feedback characteristics of the inverter to balance the voltage difference between the two circuits when the differential state of the two differential output circuit input ends is out of adjustment due to different voltage values, thereby stabilizing the differential state of the first differential signal and the second differential signal.

[0049] In another embodiment provided by the present disclosure, Figure 8 As shown, the orthogonal frequency division module 2 includes: a first NAND gate circuit 21, a second NAND gate circuit 22, a third NAND gate circuit 23, a fourth NAND gate circuit 24, a fifth NAND gate circuit 25, a sixth NAND gate circuit 26, a seventh NAND gate circuit 27 and an eighth NAND gate circuit 28; wherein the first NAND gate circuit 21, the second NAND gate circuit 22, the third NAND gate circuit 23 and the fourth NAND gate circuit 24 are respectively connected to the single-slip differential module 1, receive the input first differential signal and / or the second differential signal, and respectively output orthogonal signals to the output module 3; The fifth NAND gate circuit 25, the sixth NAND gate circuit 26, the seventh NAND gate circuit 27 and the eighth NAND gate circuit 28 are as follows: Fig. 9 As shown, it includes: a third PMOS tube 901, a fourth PMOS tube 902, a fourth NMOS tube 903 and a fifth NMOS tube 904; The gate of the third PMOS tube 901 is connected to the gate of the fifth NMOS tube 904 as the first input terminal 905 of the NAND gate, the source of the third PMOS tube 901 is connected to the source of the fourth PMOS tube 902 and the power supply, the drain of the third PMOS tube 901 is connected to the drain of the fourth NMOS tube 903 and the drain of the fourth PMOS tube 902 as the first output terminal 907 of the NAND gate; the gate of the fourth PMOS tube 902 is connected to the gate of the fourth NMOS tube 903 as the second input terminal 906 of the NAND gate; the source of the fourth NMOS tube 903 is connected to the drain of the fifth NMOS tube 904; the source of the fifth NMOS tube 904 is grounded; The first NAND gate circuit 21, the second NAND gate circuit 22, the third NAND gate circuit 23 and the fourth NAND gate circuit 24 are as follows: Fig.10 As shown, it includes: a fifth PMOS tube 1001, a sixth PMOS tube 1002, a sixth NMOS tube 1003 and a seventh NMOS tube 1004; The gate of the fifth PMOS tube 1001 is connected to the gate of the sixth NMOS tube 1003 as the third input terminal 1005 of the NAND gate, the source of the fifth PMOS tube 1001 is connected to the source of the sixth PMOS tube 1002 and the power supply, the drain of the fifth PMOS tube 1001 is connected to the drain of the sixth PMOS tube 1002 and the drain of the sixth NMOS tube 1003 as the second output terminal 1007 of the NAND gate; the gate of the sixth PMOS tube 1002 is connected to the gate of the seventh NMOS tube 1004 as the fourth input terminal 1006 of the NAND gate; the source of the sixth NMOS tube 1003 is connected to the drain of the seventh NMOS tube 1004; the source of the seventh NMOS tube 1004 is grounded.

[0050] In the present disclosure, Figure 8 As shown, the orthogonal frequency division module 2 is composed of NAND gate circuits. The NAND gate circuits of the orthogonal frequency division module 2 can be divided into two categories, wherein one category of NAND gates includes: a first NAND gate circuit 21, a second NAND gate circuit 22, a third NAND gate circuit 23 and a fourth NAND gate circuit 24, and the NAND gates are respectively connected to the single-slip module 1 to obtain the first differential signal and the second differential signal output by the single-slip module 1.

[0051] Among them, the first differential signal is input into the fourth NAND gate circuit and the second NAND gate circuit respectively from the first input terminal 201 of the orthogonal frequency division module and the third input terminal 203 of the orthogonal frequency division module (respectively the third input terminal of the NAND gate of the fourth NAND gate circuit 24 and the third input terminal of the NAND gate of the second NAND gate circuit 22), and the second differential signal is input into the first NAND gate circuit and the third NAND gate circuit respectively from the second input terminal 202 of the orthogonal frequency division module and the fourth input terminal 204 of the orthogonal frequency division module (respectively the third input terminal of the NAND gate of the first NAND gate circuit 21 and the third input terminal of the NAND gate of the third NAND gate circuit 23).

[0052] After the first differential signal and the second differential signal input to the orthogonal frequency division module are processed by the orthogonal frequency division module, the first output terminal 205 of the orthogonal frequency division module (i.e., the second output terminal of the NAND gate of the fourth NAND gate circuit 24), the second output terminal 206 of the orthogonal frequency division module (i.e., the second output terminal of the NAND gate of the first NAND gate circuit 21), the third output terminal 207 of the orthogonal frequency division module (i.e., the second output terminal of the NAND gate of the second NAND gate circuit 22) and the fourth output terminal 208 of the orthogonal frequency division module (i.e., the second output terminal of the NAND gate of the third NAND gate circuit 23) respectively output a channel of orthogonal signals to the output module 3, so as to be finally fed into the mixer.

[0053] Another type of NAND gates includes: a fifth NAND gate circuit 25, a sixth NAND gate circuit 26, a seventh NAND gate circuit 27 and an eighth NAND gate circuit 28. The input and output of this type of NAND gates are not connected to external circuits and only process the signals generated by the orthogonal frequency division module 2 itself.

[0054] In the NAND gate circuit, when all input terminals are at a high level, the gate voltages of the NMOS and PMOS tubes are both high, causing the NMOS tube to be turned on and the PMOS tube to be turned off. The output terminal of the NAND gate circuit is grounded through the NMOS tube, and the output terminal outputs a low level. If any input terminal input is at a low level, the corresponding NMOS tube is turned off and the PMOS tube is turned on. The output terminal is connected to the power supply through the PMOS tube, and the output is a high level. Fig.11a As shown in the figure, it is a schematic diagram of the NAND gate circuit outputting a low level; Fig.11b As shown, it is a schematic diagram of the high level output of the NAND gate circuit; the arrow in the above figure represents the direction of positive charge flow, and the cross represents that the corresponding MOS tube is cut off.

[0055] In another embodiment provided by the present disclosure, the orthogonal frequency division module 2 further includes: The fourth input terminal 1006 of the NAND gate of the first NAND gate circuit 21 is connected to the single-slip differential module 1 to receive the second differential signal, the third input terminal 1005 of the NAND gate of the first NAND gate circuit 21 is connected to the first output terminal 907 of the NAND gate of the fifth NAND gate circuit 25, and the second output terminal 1007 of the NAND gate of the first NAND gate circuit 21 is connected to the first input terminal 905 of the NAND gate of the sixth NAND gate circuit 26 and the output module 3; The first input terminal 905 of the NAND gate of the fifth NAND gate circuit 25 is connected to the first output terminal 907 of the NAND gate of the seventh NAND gate circuit 27, and the second input terminal 906 of the NAND gate of the fifth NAND gate circuit 25 is connected to the second output terminal 1007 of the NAND gate of the fourth NAND gate circuit 24; The fourth input terminal 1006 of the NAND gate of the fourth NAND gate circuit 24 is connected to the single-slip module 1 to receive the first differential signal, the third input terminal 1005 of the NAND gate of the fourth NAND gate circuit 24 is connected to the first output terminal 907 of the NAND gate of the eighth NAND gate circuit 28, and the second output terminal 1007 of the NAND gate of the fourth NAND gate circuit 24 is connected to the output module 3; The first input terminal 905 of the NAND gate of the eighth NAND gate circuit 28 is connected to the first output terminal 907 of the NAND gate of the sixth NAND gate circuit 26, and the second input terminal 906 of the NAND gate of the eighth NAND gate circuit 28 is connected to the second output terminal 1007 of the NAND gate of the third NAND gate circuit 23; The fourth input terminal 1006 of the NAND gate of the third NAND gate circuit 23 is connected to the single-slip module 1 to receive the second differential signal, the third input terminal 1005 of the NAND gate of the third NAND gate circuit 23 is connected to the first output terminal 907 of the NAND gate of the seventh NAND gate circuit 27, and the second output terminal 1007 of the NAND gate of the third NAND gate circuit 23 is connected to the output module 3; The first input terminal 905 of the NAND gate of the seventh NAND gate circuit 27 is connected to the first output terminal 907 of the NAND gate of the fifth NAND gate circuit 25, and the second input terminal 906 of the NAND gate of the seventh NAND gate circuit 27 is connected to the second output terminal 1007 of the NAND gate of the second NAND gate circuit 22; The fourth input terminal 1006 of the NAND gate of the second NAND gate circuit 22 is connected to the single-slip differential module 1 to receive the first differential signal, the third input terminal 1005 of the NAND gate of the second NAND gate circuit 22 is connected to the first output terminal 907 of the NAND gate of the sixth NAND gate circuit 26, and the second output terminal 1007 of the NAND gate of the second NAND gate circuit 22 is connected to the output module 3; The first NAND gate input terminal 905 of the sixth NAND gate circuit 26 is connected to the first NAND gate output terminal 907 of the eighth NAND gate circuit 28 , and the second NAND gate input terminal 906 of the sixth NAND gate circuit 26 is connected to the second NAND gate output terminal 1007 of the first NAND gate circuit 21 .

[0056] In the embodiments of the present disclosure, the above two types of NAND gate circuits are both composed of two parallel PMOS tubes and two series NMOS tubes, and both have two input terminals (i.e., the first input terminal 905 and the second input terminal 906 of the NAND gate and the third input terminal 1005 and the fourth input terminal 1006 of the NAND gate) and one output terminal (i.e., the first output terminal 907 of the NAND gate and the second output terminal 1007 of the NAND gate), each input terminal is respectively connected to the gate of a PMOS tube and the gate of an NMOS tube, and the output terminal is led out from the drain where the PMOS tube and the NMOS tube are connected. Among them, when the first NAND gate output terminal 907 of the fifth NAND gate circuit 25, the sixth NAND gate circuit 26, the seventh NAND gate circuit 27 and the eighth NAND gate circuit 28 is connected to the first NAND gate input terminal of the fifth NAND gate circuit 25, the sixth NAND gate circuit 26, the seventh NAND gate circuit 27 and the eighth NAND gate circuit 28, it is necessary to connect to the gate of the NMOS tube close to the ground line; and when it is connected to the third NAND gate input terminal of the first NAND gate circuit 21, the second NAND gate circuit 22, the third NAND gate circuit 23 and the fourth NAND gate circuit 24, it is necessary to connect to the gate of the NMOS tube close to the output terminal.

[0057] In actual application, Fig.12 As shown, in the on-chip layout, it can be designed as a bottom-in-top-out structure, the input and output of the fifth NAND gate circuit 25, the sixth NAND gate circuit 26, the seventh NAND gate circuit 27 and the eighth NAND gate circuit 28 are all completed in the upper half of the layout, and the output of the first NAND gate circuit 21, the second NAND gate circuit 22, the third NAND gate circuit 23 and the fourth NAND gate circuit 24 is divided into two parts, one part is connected to the output module 3, and the other part is connected to the fifth NAND gate circuit 25, the sixth NAND gate circuit 26, the seventh NAND gate circuit 27 and the eighth NAND gate circuit 28, participating in the timing logic of the orthogonal frequency division module 2. The former is output in the upper half of the layout, and the latter is completed in the lower half of the layout. This can improve the symmetry of the layout to a certain extent. In addition, to further ensure the symmetry of the layout, metal layers with similar square resistance and electrolyte constants are used on the symmetrical routing. The layout drawn using this topological structure will achieve high integration and high symmetry, reduce the deterioration of the orthogonal consistency of the output I / Q signals caused by the layout routing, and reduce the overall layout area. Compared with the orthogonal signal generation circuit including inductors provided in the related art, the presence of inductors results in a larger overall area. The disclosed embodiment solves the problem of poor orthogonal consistency caused by large layout area and complex layout design in the related art.

[0058] Furthermore, if Fig.13As shown, it is a schematic diagram of the layout-level simulation results of the in-phase / quadrature (I / Q, In phase / Quadrature) signal orthogonal amplitude error and phase error and its corresponding image suppression ratio that can be achieved in the 45nm CMOS silicon substrate (SOI, Silicon On Insulator) process of the disclosed embodiment. At an input of about 0-12GHz, a four-phase orthogonal frequency-divided output signal of about 0-6GHz is generated, wherein the maximum amplitude error of the I / Q signal is about 0.611dB, the maximum I / Q quadrature phase error is about 0.666°, and the minimum image suppression ratio is 27.106dB. Overall, the I / Q quadrature amplitude and phase error increases with increasing frequency. In addition, the lowest frequency applicable to the circuit can theoretically approach 0GHz, and the image suppression that can be achieved below 500MHz is greater than 35dB, which can achieve an ultra-wide relative bandwidth. However, the multi-phase network and the orthogonal frequency divider based on the master-slave trigger circuit and the orthogonal inductor-capacitor oscillator in the related technology are easily limited by the bandwidth. The relative bandwidth is usually very narrow and cannot achieve the output frequency from DC to 6GHz.

[0059] The orthogonal signal generation circuit implemented by analog ideas in the related art generally requires a radio frequency differential amplifier as a buffer, so it is also necessary to equip an additional current mirror circuit, resulting in a large power loss. The orthogonal signal generation circuit provided in the embodiment of the present disclosure relies on digital logic to implement the analog circuit. The circuit does not need to provide an additional current source, so it does not need an additional current mirror circuit. Compared with the solutions in the related art, it can reduce power consumption.

[0060] In another embodiment provided by the present disclosure, the output module 3 includes: a first inverter chain, a second inverter chain, a third inverter chain and a fourth inverter chain; The inverter chain is composed of a preset number of inverters connected in series, and the preset number is an odd number; the input end of the first inverter in the inverter chain is respectively connected to the orthogonal frequency division module 2, and the input end of any inverter except the first inverter in the inverter chain is connected to the output end of the previous inverter, and the output end of the inverter at the end of the inverter chain outputs the corresponding target orthogonal signal; Any two inverter chains among the first inverter chain, the second inverter chain, the third inverter chain and the fourth inverter chain have the same structure and the same number of inverters.

[0061] In the disclosed embodiment, the input ends of the four inverter chains are respectively connected to the first NAND gate output ends 907 of the first NAND gate circuit 21, the second NAND gate circuit 22, the third NAND gate circuit 23 and the fourth NAND gate circuit 24, and the circuit structure and device parameters of each inverter chain are exactly the same. Fig.14, which is a structural diagram of an inverter chain of any output module in this embodiment. The four orthogonal signals transmitted by the orthogonal frequency division module are respectively input into the corresponding inverter chain through each inverter chain input terminal 301, and the inverter chain shapes the input orthogonal signal and adjusts the duty cycle, and then outputs the corresponding target orthogonal signal through the inverter chain output terminal 302.

[0062] In this embodiment, each inverter chain is composed of three stages of inverters. In practical applications, it is not limited to three stages, but must be an odd number of stages. In each inverter chain, the size of the MOS tube in each stage of the inverter increases successively to provide sufficient driving capability.

[0063] In another embodiment provided by the present disclosure, the single-slip differential module 1 is used to receive an input first signal, convert the first signal into a pair of differential signals including a first differential signal and a second differential signal based on an enable signal; and input the differential signal into the orthogonal frequency division module; The orthogonal frequency division module 2 is used to generate four orthogonal signals with preset duty cycles based on the orthogonal frequency division module state and the differential signal period when receiving the differential signal; and input the orthogonal signals into the output module; The inverter chain in the output module 3 is used to receive the corresponding orthogonal signals respectively, adjust the duty cycle of the orthogonal signals, and generate target orthogonal signals.

[0064] In the present disclosure, Fig.15 As shown, in a possible implementation, assuming that the initial states of the four signals outputted from the second output terminals of the first NAND gate circuit 21, the second NAND gate circuit 22, the third NAND gate circuit 23 and the fourth NAND gate circuit 24 and the first differential signal and the second differential signal are respectively "1110" (i.e., the level states are respectively high level, high level, high level, low level) and "10" (i.e., the level states are respectively high level and low level), then the states of the four signals outputted from the first output terminals of the fifth NAND gate circuit 25, the sixth NAND gate circuit 26, the seventh NAND gate circuit 27 and the eighth NAND gate circuit 28 are "1001" (i.e., the level states are respectively high level, low level, low level, high level).

[0065] When the state of the first differential signal and the second differential signal changes to "01" (i.e., the level states are respectively low level and high level), the output signals of the second output terminals 1007 of the four NAND gates will first change, and their states will change to "0111" (i.e., the level states are respectively low level, high level, high level, and high level). During this process, the output signal of the first NAND gate circuit 21 and the output signal of the fourth NAND gate circuit change at the same time, and the output signal of the second NAND gate circuit 22 and the output signal of the third NAND gate circuit 23 remain unchanged; according to the change of the output signal of the second output terminal 1007 of the NAND gate, the output signals of the first output terminals 907 of the four NAND gates will also change, and their level states will change to "1100" (i.e., the level states are respectively high level, high level, low level, and low level). During this change process, it is actually the output signal of the sixth NAND gate circuit 26 that changes first, and then drives the output signal of the eighth NAND gate circuit 28 to change, while the output signal of the fifth NAND gate circuit 25 and the output signal of the seventh NAND gate circuit 27 remain unchanged.

[0066] Further, the states of the first differential signal and the second differential signal become "10" (i.e., the level states are high level and low level, respectively), and the signal states output by the second output terminal 1007 of the NAND gate and the first output terminal 907 of the NAND gate become "1011" (i.e., the level states are high level, low level, high level, high level, respectively) and "0110" (i.e., the level states are low level, high level, high level, low level, respectively).

[0067] Further, the states of the first differential signal and the second differential signal become "01" (i.e., the level states are low level and high level, respectively), and the signal states output by the second output terminal 1007 of the NAND gate and the first output terminal 907 of the NAND gate become "1101" (i.e., the level states are high level, high level, low level, high level, respectively) and "0011" (i.e., the level states are low level, low level, high level, high level, respectively).

[0068] Further, the states of the first differential signal and the second differential signal become "10" (i.e., the level states are high level and low level respectively), and the signal states output by the second output terminal 1007 of the NAND gate and the first output terminal 907 of the NAND gate return to "1110" (i.e., the level states are high level, high level, high level, and low level respectively) and "1001" (i.e., the level states are high level, low level, low level, and high level respectively), and the entire module completes a cycle of orthogonal generation and outputs four orthogonal square wave signals with a duty cycle of 75%.

[0069] Furthermore, by connecting an odd-numbered inverter chain, four orthogonal square wave signals with a duty cycle of 25% can be output.

[0070] An embodiment of the present disclosure provides an electronic device, an orthogonal signal generating circuit based on any one of the above embodiments.

[0071] Through the description of the above implementation methods, those skilled in the art can clearly understand that the embodiments of the present disclosure can be implemented by hardware, or by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.), including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present disclosure.

[0072] Those skilled in the art will appreciate that the accompanying drawings are merely schematic diagrams of a preferred embodiment, and the modules or processes in the accompanying drawings are not necessarily required for implementing the present disclosure.

[0073] Those skilled in the art can understand that the modules in the device in the embodiment can be distributed in the device in the embodiment according to the description of the embodiment, or can be changed accordingly and located in one or more devices different from the present embodiment. The modules in the above embodiment can be combined into one module, or can be further divided into multiple sub-modules.

[0074] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0075] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. An orthogonal signal generating circuit, characterized in that: include: Single-slip differential module, orthogonal frequency division module and output module; Wherein, the single slip module is connected to the orthogonal frequency division module, and the single slip module and the output module respectively include a corresponding number of inverters; the inverter includes: a PMOS tube and an NMOS tube, the gate of the PMOS tube is connected to the gate of the NMOS tube as the inverter input end, and the drain of the PMOS tube is connected to the drain of the NMOS tube as the inverter output end; The single-slip differential module is used to convert the input first signal into a first differential signal and a second differential signal, and transmit the first differential signal and the second differential signal to the orthogonal frequency division module; The orthogonal frequency division module is used to convert the received first differential signal and second differential signal into four orthogonal signals; The output module is connected to the orthogonal frequency division module, and is used for receiving the orthogonal signal and outputting the orthogonal signal as four target orthogonal signals after shaping.

2. The circuit according to claim 1, characterized in that The single-slip module includes: a bias input circuit, a switch inverter, a first differential output circuit, a second differential output circuit, and a feedback circuit; The bias input circuit is connected to the switch inverter, and is used to remove the DC voltage in the input first signal, introduce a preset bias voltage, and output a second signal; The switch inverter is used to control the on and off of the single-slip module; and / or convert the second signal into a third signal and output the third signal; The first differential output circuit and the second differential output circuit are respectively connected to the switch inverter, and are used to convert the third signal into a pair of differential signals; The feedback circuit is connected to the first differential output circuit and the second differential output circuit respectively, and is used for providing feedback to stabilize the differential states of the first differential output circuit and the second differential output circuit.

3. The circuit according to claim 2, characterized in that The bias input circuit includes: a first capacitor, a first resistor, a second resistor, a third resistor and a first switch; The first signal is input from one end of the first capacitor, and the other end of the first capacitor is respectively connected to one end of the first resistor, one end of the second resistor, one end of the third resistor and a switch inverter; the first capacitor is used to remove the DC voltage in the first signal; the other end of the first resistor is connected to the output end of the first switch; the first switch input end inputs an off-chip bias voltage, and the first switch control end inputs a first enable signal, and the first enable signal is used to control the on and off of the first switch; the other end of the second resistor is connected to a power supply; the other end of the third resistor is grounded; The bias input circuit is further used to introduce a preset bias voltage through the second resistor, the third resistor and the first switch, increase the bias voltage for the input first signal, and output a second signal.

4. The circuit according to claim 2, characterized in that The switch inverter comprises: a first inverter, a first PMOS transistor, a first NMOS transistor and a second NMOS transistor; The first inverter input end is connected to the bias input circuit, and the first inverter output end is connected to the first differential output circuit, the second differential output circuit and the second NMOS tube; the first inverter is used to convert the input second signal into a third signal; the first PMOS tube drain is connected to the PMOS tube source in the first inverter, the first PMOS tube source is connected to the power supply, and the second enable signal is input to the first PMOS tube gate to control the first PMOS tube to be turned on or off; the first NMOS tube drain is connected to the NMOS tube source in the first inverter, the first NMOS tube source is grounded, and the third enable signal is input to the first NMOS tube gate to control the first NMOS tube to be turned on or off; the second NMOS tube drain is connected to the first inverter output end, the second NMOS tube source is grounded, and the fourth enable signal is input to the second NMOS tube gate to control the second NMOS tube to be turned on or off; The first NMOS tube, the first PMOS tube and the second PMOS tube are turned on and off by an enable signal, so as to eliminate the influence of the static current in the switching inverter.

5. The circuit according to claim 2, characterized in that The first differential output circuit includes: a second inverter, a third inverter, a fourth inverter and a fifth inverter; The input end of the second inverter is connected to the switch inverter for receiving the third signal; the input end of the third inverter is connected to the output end of the second inverter; the input end of the fourth inverter is connected to the output end of the third inverter; the input end of the fifth inverter is connected to the output end of the fourth inverter and the feedback circuit; the output end of the fifth inverter is connected to the orthogonal frequency division module, and outputs a first differential signal; The first differential output circuit is used to adjust the phase of the input signal and output a first differential signal after shaping the signal.

6. The circuit according to claim 5, characterized in that The second differential output circuit includes: a transmission gate, a sixth inverter, a seventh inverter and an eighth inverter; The transmission gate comprises: a second PMOS tube and a third NMOS tube; the drain of the second PMOS tube is connected to the drain of the third NMOS tube as the transmission gate input, the source of the second PMOS tube is connected to the source of the third NMOS tube as the transmission gate output, the gate of the second PMOS tube is grounded, and the gate of the third NMOS tube is connected to a power supply; The transmission gate input end is connected to the switch inverter for receiving the third signal; the input end of the sixth inverter is connected to the transmission gate output end; the input end of the seventh inverter is connected to the output end of the sixth inverter; the input end of the eighth inverter is connected to the output end of the seventh inverter and the feedback circuit; the output end of the eighth inverter is connected to the orthogonal frequency division module and outputs a second differential signal; The second differential output circuit is used to adjust the phase of the input signal and output a second differential signal after shaping the signal.

7. The circuit according to claim 6, characterized in that The feedback circuit comprises: a ninth inverter and a tenth inverter; The ninth inverter input terminal is connected to the seventh inverter output terminal, and the ninth inverter output terminal is connected to the fourth inverter output terminal; the tenth inverter input terminal is connected to the fourth inverter output terminal, and the tenth inverter output terminal is connected to the seventh inverter output terminal.

8. The circuit according to claim 1, characterized in that The orthogonal frequency division module comprises: a first NAND gate circuit, a second NAND gate circuit, a third NAND gate circuit, a fourth NAND gate circuit, a fifth NAND gate circuit, a sixth NAND gate circuit, a seventh NAND gate circuit and an eighth NAND gate circuit; wherein the first NAND gate circuit, the second NAND gate circuit, the third NAND gate circuit and the fourth NAND gate circuit are respectively connected to the single-slip differential module, receive the input first differential signal and / or the second differential signal, and respectively output orthogonal signals to the output module; The fifth NAND gate circuit, the sixth NAND gate circuit, the seventh NAND gate circuit and the eighth NAND gate circuit include: a third PMOS transistor, a fourth PMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor; The gate of the third PMOS tube is connected to the gate of the fifth NMOS tube as the first input terminal of the NAND gate, the source of the third PMOS tube is connected to the source of the fourth PMOS tube and the power supply, the drain of the third PMOS tube is connected to the drain of the fourth NMOS tube and the drain of the fourth PMOS tube as the first output terminal of the NAND gate; the gate of the fourth PMOS tube is connected to the gate of the fourth NMOS tube as the second input terminal of the NAND gate; the source of the fourth NMOS tube is connected to the drain of the fifth NMOS tube; the source of the fifth NMOS tube is grounded; The first NAND gate circuit, the second NAND gate circuit, the third NAND gate circuit and the fourth NAND gate circuit include: a fifth PMOS transistor, a sixth PMOS transistor, a sixth NMOS transistor and a seventh NMOS transistor; The gate of the fifth PMOS tube is connected to the gate of the sixth NMOS tube as the third input terminal of the NAND gate, the source of the fifth PMOS tube is connected to the source of the sixth PMOS tube and the power supply, the drain of the fifth PMOS tube is connected to the drain of the sixth PMOS tube and the drain of the sixth NMOS tube as the second output terminal of the NAND gate; the gate of the sixth PMOS tube is connected to the gate of the seventh NMOS tube as the fourth input terminal of the NAND gate; the source of the sixth NMOS tube is connected to the drain of the seventh NMOS tube; the source of the seventh NMOS tube is grounded.

9. The circuit according to claim 8, characterized in that The fourth input terminal of the NAND gate of the first NAND gate circuit is connected to the single-slip differential module to receive the second differential signal, the third input terminal of the NAND gate of the first NAND gate circuit is connected to the first output terminal of the NAND gate of the fifth NAND gate circuit, and the second output terminal of the NAND gate of the first NAND gate circuit is connected to the first input terminal of the NAND gate of the sixth NAND gate circuit and the output module; The first input terminal of the NAND gate of the fifth NAND gate circuit is connected to the first output terminal of the NAND gate of the seventh NAND gate circuit, and the second input terminal of the NAND gate of the fifth NAND gate circuit is connected to the second output terminal of the NAND gate of the fourth NAND gate circuit; The fourth input terminal of the NAND gate of the fourth NAND gate circuit is connected to the single-slip differential module to receive the first differential signal, the third input terminal of the NAND gate of the fourth NAND gate circuit is connected to the first output terminal of the NAND gate of the eighth NAND gate circuit, and the second output terminal of the NAND gate of the fourth NAND gate circuit is connected to the output module; The first input terminal of the NAND gate of the eighth NAND gate circuit is connected to the first output terminal of the NAND gate of the sixth NAND gate circuit, and the second input terminal of the NAND gate of the eighth NAND gate circuit is connected to the second output terminal of the NAND gate of the third NAND gate circuit; The fourth input terminal of the NAND gate of the third NAND gate circuit is connected to the single-slip differential module to receive the second differential signal, the third input terminal of the NAND gate of the third NAND gate circuit is connected to the first output terminal of the NAND gate of the seventh NAND gate circuit, and the second output terminal of the NAND gate of the third NAND gate circuit is connected to the output module; The first input terminal of the NAND gate of the seventh NAND gate circuit is connected to the first output terminal of the NAND gate of the fifth NAND gate circuit, and the second input terminal of the NAND gate of the seventh NAND gate circuit is connected to the second output terminal of the NAND gate of the second NAND gate circuit; The fourth input terminal of the NAND gate of the second NAND gate circuit is connected to the single-slip differential module to receive the first differential signal, the third input terminal of the NAND gate of the second NAND gate circuit is connected to the first output terminal of the NAND gate of the sixth NAND gate circuit, and the second output terminal of the NAND gate of the second NAND gate circuit is connected to the output module; The first input terminal of the NAND gate of the sixth NAND gate circuit is connected to the first output terminal of the NAND gate of the eighth NAND gate circuit, and the second input terminal of the NAND gate of the sixth NAND gate circuit is connected to the second output terminal of the NAND gate of the first NAND gate circuit.

10. The circuit according to claim 1, characterized in that The output module comprises: a first inverter chain, a second inverter chain, a third inverter chain and a fourth inverter chain; The inverter chain is composed of a preset number of inverters connected in series, and the preset number is an odd number; the input end of the first inverter in the inverter chain is respectively connected to the orthogonal frequency division module, and the input end of any inverter except the first inverter in the inverter chain is connected to the output end of the previous inverter, and the output end of the inverter at the end of the inverter chain outputs the corresponding target orthogonal signal; Any two inverter chains among the first inverter chain, the second inverter chain, the third inverter chain and the fourth inverter chain have the same structure and the same number of inverters.

11. The circuit according to claim 1, characterized in that The single-slip differential module is used to receive an input first signal, convert the first signal into a pair of differential signals including a first differential signal and a second differential signal based on an enable signal; and input the differential signal into the orthogonal frequency division module; The orthogonal frequency division module is used to generate four orthogonal signals with preset duty cycles based on the orthogonal frequency division module state and the differential signal period when the differential signal is received; and input the orthogonal signals into the output module; The inverter chain in the output module is used to respectively receive corresponding orthogonal signals, adjust the duty cycle of the orthogonal signals, and generate target orthogonal signals.

12. An electronic device, characterized in that: include: An orthogonal signal generating circuit as claimed in any one of claims 1 to 11.

Images