A CTDSM circuit that can compensate for arbitrary periodic overshoot loop delays

Abstract

The present application belongs to the technical field of analog integrated circuit, and particularly relates to a CTDSM circuit capable of compensating for an arbitrary period overshoot loop delay. The present application introduces a direct feedback loop at each output end of an m-channel TI ADC, sorts the code words generated by each channel from high to low in terms of quantization degree, and then selectively feeds back the code words to the input end of the TI ADC through unit period delay from m to 1, so as to compensate for the overshoot loop delay. This method can compensate for the arbitrary period overshoot loop delay in the CTDSM with the TI ADC as a quantizer, and breaks through the limitation that the existing scheme can only compensate for one period of overshoot loop delay. The present application is applicable to the case that the TI ADC with an arbitrary number of channels is used as a CTDSM quantizer, improves the stability of the CTDSM circuit, and provides support for the development of the CTDSM in the high-speed and high-precision field.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of analog integrated circuit technology, and particularly relates to a CTDSM circuit capable of compensating for excess loop delay of an arbitrary period. BACKGROUND

[0002] Continuous-Time Delta-Sigma Modulator (CTDSM) has been widely researched and applied in the field of analog integrated circuit technology due to its high precision and high bandwidth. The quantizer in CTDSM is usually realized by cascading ADC and DAC. Due to the resolution limit of the quantizer, a certain period of time is required to complete the conversion, resulting in a delay in the output sequence. The DAC works after the ADC, and thus can only be driven by the clock signal later, further increasing the delay. The excess loop delay (ELD) in CTDSM will lead to instability of the circuit.

[0003] Suppose a first-order CTDSM with NonRetumtoZero (NRZ) encoding has an excess loop delay of t d , the circuit is shown in FIG. 1, and the Noise Transfer Function (NTF) of the CTDSM circuit can be expressed as: Figure 1

[0004]

[0005] It can be seen that compared with the CTDSM without excess loop delay, the circuit has two more poles, and the pole position is related to t d . The larger t d is, the more unstable the circuit is. When t d is greater than one period, the circuit is in an unstable state.

[0006] For the problem of compensating for excess loop delay, a design method of direct feedback path around the quantizer has been proposed in the literature, which is shown in FIG. 2. This design method introduces a feedback path at the output of the quantizer, which also passes through t d delay to the input of the quantizer, and the feedback path is introduced to offset the excess loop delay. Figure 2

[0007] However, the above scheme is only applicable to the case where the over-shoot loop delay is less than one period. If the CTDSM selects a time-interleaved (TI) ADC with multiple channel inputs as its quantizer, the over-shoot loop delay will be greater than one period. If the above quantizer direct feedback compensation scheme is used to compensate the over-shoot loop delay of the TI ADC, the un-fully quantized signal will be fed back to the input, resulting in instability of the overall circuit. For example, if a TI ADC with two channels is used to compensate the over-shoot loop delay, the input of the quantizer is:

[0008] D[n]=X[n]-Y[n-1]-Y[n-2]

[0009] where D[n] is the input signal of the quantizer in the nth period, X[n] is the discretized signal of the first-order CTDSM input signal in the nth period after loop filtering, and Y[n] is the output signal of the quantizer in the nth period.

[0010] As can be seen, in the nth period, the output values of the quantizer in the (n-1)th period and the (n-2)th period need to be fed back. However, for a TI ADC with two channels, the (n-1)th period is still in the quantization stage, and the correct output signal cannot be fed back, resulting in errors in the overall circuit. This limits the development of CTDSM in the high-speed and high-precision field. Therefore, how to compensate for the over-shoot loop delay of more than one period is a problem that needs to be solved in the research of high-performance CTDSM. SUMMARY

[0011] In view of the above problems or deficiencies, the present application provides a CTDSM circuit that can compensate for an over-shoot loop delay of any period and is suitable for a TI ADC with any number of channels as a CTDSM quantizer. By introducing multiple feedback paths that meet the design conditions from the output of the quantizer to the input of the quantizer, the over-shoot loop delay is compensated.

[0012] A CTDSM circuit that can compensate for an over-shoot loop delay of any period is composed of the following four modules, as shown in Figure 3 including module 001, module 002, module 003 and module 004.

[0013] If the number of channels of the TI ADC used as the quantizer of the CTDSM is m, the CTDSM will have an over-shoot loop delay of m periods. According to the working principle of the TI ADC, when sampling is performed in the mth period, the previous m-1 periods have already started quantization, which means that the signals sampled in the previous m-1 periods have already had code word outputs.

[0014] Module 001 comprises three parts: an adder ADDER0, a loop filter, and a sampling switch, all connected in sequence. Adder ADDER0 serves as the input to module 001, connecting the input signal X of the entire CTDSM circuit and the output signal D1 of module 004. The output of the sampling switch, serving as the output of module 001, is connected to the input of module 002. Module 001 performs a differential operation on the input signals X and D1 via adder ADDER0, and after loop filtering, discretizes the result via the sampling switch.

[0015] The module 002 is composed of m adders, which are cascaded sequentially from ADDER1 to ADDERm. The input of adder ADDER1 is connected to the output (sampling switch) of module 001 and the output signal D1 of module 004, the input of adder ADDER2 is connected to the output of ADDER1 and the output signal D2 of module 004, ..., the input of adder ADDERm is connected to the output of ADDERm-1 and the output signal D2 of module 004. m ; The output of adder ADDERm is connected to the input of module 003 as the output of module 002.

[0016] The module 003 is composed of m channels of TIADC and a multi-channel selector MCS.

[0017] The TI ADC with m channels is divided into channels CH1-CHm, and the outputs are MSB1 to MSB in a one-to-one correspondence. m m-way signal.

[0018] The multi-channel selector MCS sorts the sub-ADCs of each channel in the TI ADC according to the degree of quantization from high to low. The signal of the channel CH1 with the highest degree of quantization, which has been fully quantized, is used as the first output signal MSB1 of module 003. The remaining channels are used as the second output signal MSB2 of module 003 to the mth output signal MSB in order of the degree of quantization from high to low. m And the first output signal MSB1 of module 003 is used as the output signal Y of the entire CTDSM circuit.

[0019] The specific principle is as follows: the current working cycle is set to the m+1th working cycle. The working cycle includes the sampling cycle and quantization cycle of the CTDSM circuit. According to the working principle of the TI ADC, when sampling is performed in the m+1th working cycle, the sub-ADC of channel CH1 can output a fully quantized signal, while the sub-ADCs from channel CH2 to channel CHm are still in the quantization stage and can only output a portion of the codeword in the m+1 cycle. The function of module 003 is to sort the sub-ADCs of each channel in the TIADC from high to low according to the degree of quantization through the multi-channel selector within the current working cycle, i.e., the m+1th cycle. The signal of channel CH1 with the highest degree of quantization, i.e., the signal that has been fully quantized, is used as the first output signal MSB1 of module 003. The remaining channels are used as the second output signal MSB2 of module 003 to the mth output signal MSB in order of their degree of quantization from high to low. m And the first output signal MSB1 of module 003 is used as the output signal Y of the entire CTDSM circuit.

[0020] The module 004 is composed of m independent feedback delay loops, and the number of delay cycles of each loop decreases from m to 1. Its input is connected to the module 003 from MSB1 to MSB1 in a one-to-one correspondence. m m-way output, signal MSB1 to MSB m After the delay of m feedback delay loops corresponding to each other, the corresponding (MSB m Corresponding D m ) signal D1 to D m ; At the same time, the first output signal D1 of module 004 is also connected to the input end of module 001 (adder ADDER0).

[0021] The function of module 004 is to convert the input signal from MSB1 to MSB. m , the delay cycle number is one-to-one corresponding to the unit cycle delay from m to 1, and the output signal D1 to D m .

[0022] Furthermore, the module 002 performs a differential operation on the output signal of module 001 and the D1 signal to obtain the output of ADDER1, and then performs a differential operation on the output signal of ADDER1 and the D2 signal to obtain the output of ADDER2. The above steps are repeated to obtain the output of ADDERm. The output signal of ADDERm is the output signal of module 002, which is connected to the input of module 003.

[0023] Furthermore, the loop filter adopts a cascade integrator CIFB with feedback or a cascade integrator CIFF with feedforward.

[0024] Furthermore, the multiplexer MCS is composed of m multiplexers MUX connected in parallel, as shown in the attached diagram. Figure 4 shown.

[0025] In summary, the present invention introduces a direct feedback loop at each output of an m-channel TI ADC, sorting the generated codewords for each channel from high to low by quantization level. These codewords are then selectively fed back to the TI ADC input with unit cycle delays decreasing from m to 1, thereby compensating for overshoot loop delay. This method can compensate for overshoot loop delay of any cycle in a CTDSM using the TI ADC as the quantizer, overcoming the limitation of existing solutions that can only compensate for overshoot loop delay of a single cycle. The present invention is applicable to CTDSM quantizers using TI ADCs with any number of channels, improving the stability of the CTDSM circuit and supporting the development of CTDSM in the field of high-speed and high-precision technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 For t d Schematic diagram of a first-order CTDSM circuit with overshoot loop delay;

[0027] Figure 2 Schematic diagram of a first-order CTDSM circuit with overshoot loop delay using a quantizer direct feedback compensation scheme;

[0028] Figure 3 A schematic diagram of the compensation scheme architecture of the present invention when an m-channel TIADC is used as a CTDSM quantizer;

[0029] Figure 4 This is a schematic diagram of the multiplexer circuit in module 003;

[0030] Figure 5 4 is a circuit block diagram of a 2-cycle overshoot loop delay compensation in a CTDSM according to an embodiment;

[0031] Figure 6 FIG. 1 is a schematic diagram of a loop filter structure used in an embodiment. DETAILED DESCRIPTION

[0032] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0033] A CTDSM circuit that can compensate for any cycle overshoot loop delay is shown in the attached figure. Figure 5As shown, the CTDSM in this embodiment takes a 2-channel time-interleaved noise-shaping successive approximation register analog-to-digital converter (TI NSSAR ADC) as the core, and has 2 cycle overshoot loop delays; the loop filter architecture used by the CTDSM is a cascaded integrator CIFF with a feedforward structure, and a system block diagram thereof is as shown in Figure 6

[0034] First, let the input of the CTDSM circuit be a signal X, the output of the CTDSM circuit be Y, the input of the TI NSSAR ADC be a signal D, and the output of the TI NSSAR ADC be MSB+LSB.

[0035] Then, by attaching Figure 5 , it can be obtained that:

[0036] Y=MSB+LSB-Z -1 ·LSB

[0037] It can be known that the sampling of the input signal in the first-order CTDSM under the condition of an overshoot loop delay t d is expressed as:

[0038]

[0039] Where τ is the number of periods of the delay, and its value is a positive integer.

[0040] According to the attachment Figure 5 , it can be obtained that equation 1 is:

[0041]

[0042] Equation 2 is:

[0043]

[0044] (D-Y)Z -1 +D·(1-Z -1 )+E(1-Z -1 )-Z -1 (1-Z -1 )LSB=Y(1-Z -1 )

[0045] D+E(1-Z -1 )-Z -1 (1-Z -1 )LSB=Y (2)

[0046] Substitute equation 1 into equation 2, and it can be obtained that:

[0047] Z -3 X-Z -2 ​Y-Z -1 (1-Z -1 )[MSB+LSB-Z -1 LSB]+(1-Z -1 ) 2 E=(1-Z -1 )Y

[0048] Since:

[0049] Y=MSB+LSB-Z -1 ·LSB

[0050] Then:

[0051] Z -3 X-Z -2 Y-Z -1 (1-Z -1 )Y-(1-Z -1 ) 2 E=(1-Z -1 )Y

[0052] Y=Z -3 X+(1-Z -1 ) 2 E

[0053] Finally, the signal transfer function of the CTDSM circuit is Z -3 , and the noise transfer function is (1-Z -1 ) 2 .

[0054] As can be seen from the above embodiments, the application selectively feeds back the generated code words of each channel to the input end of the quantizer through a direct feedback loop to compensate for the overshoot loop delay, which can compensate for the overshoot loop delay of any period in the CTDSM with TIADC as the quantizer, breaking through the limitation that the existing scheme can only compensate for one period of overshoot loop delay; is suitable for the case that TI ADC with any number of channels is used as the CTDSM quantizer, improves the stability of the CTDSM circuit, and provides support for the development of CTDSM in the field of high speed and high precision.

Claims

1. A CTDSM circuit capable of compensating for any periodic overshoot loop delay, characterized in that: It includes four modules: module 001, module 002, module 003 and module 004; The module 001 includes three parts: an adder ADDER0, a loop filter, and a sampling switch connected in sequence. The input of the adder ADDER0 serves as the input of the module 001, connected to the input signal X of the entire CTDSM circuit and the output signal D1 of the module 004. The output of the sampling switch serves as the output of the module 001 and is connected to the input end of the module 002. The module 001 performs a differential operation on the input signals X and D1 through the adder ADDER0, and after loop filtering, realizes discretization through the sampling switch. The module 002 is composed of m adders, which are cascaded sequentially from ADDER1 to ADDERm; wherein the input of adder ADDER1 is connected to the output of module 001 and the output signal D1 of module 004, the input of adder ADDER2 is connected to the output of ADDER1 and the output signal D2 of module 004, ..., the input of adder ADDERm is connected to the output of ADDERm-1 and the output signal D2 of module 004. m The output of adder ADDERm is connected to the input of module 003 as the output of module 002; The module 003 is composed of m channels of TIADC and a multi-channel selector MCS; The m-channel TIADC is divided into channels CH1-CHm, and the outputs MSB1 to MSB correspond one by one. m m-way signal; The multi-channel selector MCS sorts the sub-ADCs of each channel in the TIADC according to the degree of quantization from high to low. The signal of the channel CH1 with the highest degree of quantization, which has been fully quantized, is used as the first output signal MSB1 of module 003. The remaining channels are used as the second output signal MSB2 of module 003 to the mth output signal MSB according to the degree of quantization from high to low. m And the first output signal MSB1 of module 003 is used as the output signal Y of the entire CTDSM circuit; The module 004 is composed of m independent feedback delay loops, and the number of delay cycles of each loop decreases from m to 1; its input is connected to the module 003 from MSB1 to MSB in a one-to-one correspondence. m m-way output, signal MSB1 to MSB m After the corresponding m feedback delay loops are delayed, the corresponding signals D1 to D m , MSB m Corresponding D m ; At the same time, the first output signal D1 of module 004 is also connected to the input end of module 001.

2. The CTDSM circuit capable of compensating for any periodic overshoot loop delay as claimed in claim 1, wherein: The TIADC is TI NSSAR ADC.

3. The CTDSM circuit capable of compensating for any periodic overshoot loop delay as claimed in claim 1, wherein: The module 002 performs a differential operation on the output signal of module 001 and the D1 signal to obtain the output of ADDER1, and then performs a differential operation on the output signal of ADDER1 and the D2 signal to obtain the output of ADDER2. The above steps are repeated to obtain the output of ADDERm. The output signal of ADDERm is the output signal of module 002.

4. The CTDSM circuit capable of compensating for any periodic overshoot loop delay as claimed in claim 1, wherein: The loop filter adopts a cascade integrator CIFB with feedback or a cascade integrator CIFF with feedforward.

5. The CTDSM circuit capable of compensating for any periodic overshoot loop delay as claimed in claim 1, wherein: The multiplexer MCS is composed of m multiplexers MUX connected in parallel.

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