Address allocation method and device, electronic equipment and storage medium

Abstract

One or more embodiments of the invention provide an address allocation method and device, electronic equipment and a storage medium, and relates to the technical field of battery management systems. The method is applied to a battery management system, the battery management system comprises a plurality of control units which are sequentially cascaded through a communication bus, each control unit comprises a switch, the switch of each control unit is arranged on the communication bus and used for controlling connection and disconnection of the communication bus, the first control unit is used for being connected with a main controller, and the second control unit is used for being connected with a second controller. The address allocation method comprises the following steps: under the condition that a main controller sends a normal working instruction, each control unit is in a normal state; under the condition that the main controller sends an address self-adaption instruction, each control unit turns off the switch of the control unit according to the address self-adaption instruction; and the main controller allocates addresses to the control units according to the cascading sequence of the control units. Through the arrangement of the switch on the communication bus, the existing communication bus is multiplexed, so that the self-adaptive allocation of the address can be realized.

Description

Technical Field

[0001] The present application relates to the technical field of battery management systems, and in particular to an address allocation method, device, electronic device and storage medium. Background Art

[0002] In the field of energy storage systems, the battery management system (BMS) component of the battery subsystem plays a vital role. It is usually composed of a battery array unit (BAU), a battery cluster unit (BCU) and a battery module unit (BMU), with a typical ratio of 1:10:80. In this sophisticated architecture, each controller needs to communicate data with other controllers through a unique address code to ensure accurate information transmission and efficient operation of the system.

[0003] However, in the actual project deployment process, address allocation for BMS controllers has become a tedious and critical task, especially for a large number of battery cluster management system controllers and battery pack management unit controllers. The traditional manual addressing method is not only labor-intensive, time-consuming and labor-intensive, but also prone to errors due to human factors, which in turn affects the stability and reliability of the entire system. Summary of the invention

[0004] In view of this, one or more embodiments of the present application provide an address allocation method, apparatus, electronic device, and storage medium to at least partially improve the above-mentioned problem.

[0005] In order to achieve the above objectives, the technical solutions adopted by one or more embodiments of the present application are as follows: In a first aspect, one or more embodiments of the present application provide an address allocation method, which is applied to a battery management system, wherein the battery management system includes a plurality of control units cascaded in sequence through a communication bus, each of the control units includes a switch, and the switch of each control unit is arranged on the communication bus to control the connection and disconnection of the communication bus, and the first control unit is used to connect to a main controller, and the method includes: When the main controller issues a normal working instruction, each of the control units is in a normal state; the normal state indicates that each of the switches is in a closed state, and each of the control units can communicate normally; When the main controller issues an address adaptation instruction, each control unit disconnects its own switch according to the address adaptation instruction; and the main controller allocates addresses to each control unit according to the cascade sequence of each control unit.

[0006] Optionally, each of the control units disconnects its own switch according to the address adaptation instruction; and the main controller allocates addresses to each of the control units according to the cascade sequence of the control units, including: Each of the control units replies an address adaptation response to the main controller according to the address adaptation instruction, and turns off its own switch, marking its own state as an unassigned address; The main controller sends an address allocation instruction to each control unit according to the cascade sequence of each control unit according to the address adaptive response, and after completing the address allocation to each control unit, sends the normal working instruction to each control unit; Each of the control units receives the normal working instruction and returns to the normal state.

[0007] Optionally, the main controller sends an address allocation instruction to each control unit according to the cascade order of each control unit according to the address adaptive response, completes the address allocation to each control unit, and sends the normal working instruction to each control unit, including: The main controller sends an address allocation preparation instruction; The control unit in the state of unallocated address replies an address allocation preparation response to the main controller; Whether the main controller receives only one address allocation preparation response from the target control unit within a first preset time period; If not, the main controller sends the normal working instruction to each of the control units; If so, the main controller sends an address allocation assignment instruction to the target control unit; The target control unit performs address assignment according to the address assignment instruction, closes its own switch, marks its own state as assigned address, and replies an address assignment response to the main controller; Whether the main controller receives an address allocation response from the target control unit within a second preset time period; If not, the main controller sends the normal working instruction to each of the control units; If so, the main controller determines whether the number of control units in the state of being allocated is a preset number; If so, the main controller sends the normal working instruction to each of the control units; If not, the main controller sends the address allocation preparation instruction again until the state is that the number of allocated control units is the preset number.

[0008] Optionally, the method further comprises: If each of the control units does not receive the address allocation instruction sent by the main controller within a third preset time period, each of the control units returns to the normal state.

[0009] Optionally, the third preset duration is the sum of the first preset duration and the second preset duration multiplied by the preset number.

[0010] Optionally, each of the control units further includes an anti-interference unit, and the method further includes: When the switches of the control units are disconnected, the normally open ends of the switches are connected to the anti-interference unit.

[0011] Optionally, the communication bus is a CAN bus, and the anti-interference unit is a resistor of a preset size.

[0012] In a second aspect, one or more embodiments of the present application provide an address allocation device, which is applied to a battery management system, wherein the battery management system includes a plurality of control units cascaded in sequence through a communication bus, each of the control units includes a switch, and the switch of each control unit is arranged on the communication bus to control the connection and disconnection of the communication bus, and the first control unit is used to connect to a main controller, and the device includes: A normal working instruction processing module, used for, when the main controller issues a normal working instruction, each of the control units is in a normal state; the normal state indicates that each of the switches is in a closed state, and each of the control units can communicate normally; The address allocation module is used for each control unit to disconnect its own switch according to the address adaptation instruction issued by the main controller when the main controller issues the address adaptation instruction; the main controller allocates addresses to each control unit according to the cascade sequence of each control unit.

[0013] In a third aspect, one or more embodiments of the present application provide an electronic device, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor implements any of the methods described above when executing the program.

[0014] In a fourth aspect, one or more embodiments of the present application provide a storage medium having a computer program stored thereon, wherein the computer program implements any of the methods described above when executed by a processor.

[0015] One or more embodiments of the present application provide an address allocation method, device, electronic device and storage medium. By setting a switch on the communication bus of the cascaded control unit, the existing communication bus is reused to achieve efficient and convenient address allocation, which can eliminate the dedicated address allocation harness and simplify the wiring structure. In the process of address adaptation, if an abnormal situation occurs, the switch can quickly locate the address error in an intuitive physical manner, greatly improving the efficiency of troubleshooting. By connecting a preset resistor when the switch is disconnected, electrical interference can be reduced, the stability and reliability of the system can be improved, and the service life of the equipment can be extended.

[0016] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic structural block diagram of an electronic device provided in an embodiment of the present application; Figure 2 A schematic structural block diagram of a battery management system provided in an embodiment of the present application; Figure 3 A flowchart of an address allocation method provided in an embodiment of the present application; Figure 4 A schematic diagram of a process of step S222 provided in an embodiment of the present application; Figure 5 A connection diagram of a CAN bus provided in an embodiment of the present application; Figure 6 Another flowchart of an address allocation method provided in an embodiment of the present application; Figure 7 A schematic structural block diagram of an address allocation device provided in an embodiment of the present application.

[0019] Icon: 100 - electronic device; 101 - memory; 102 - communication interface; 103 - processor; 104 - bus; 300 - battery management system; 310 - main controller; 320 - control unit; 400 - address allocation device; 410 - normal working instruction processing module; 420 - address allocation module. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0022] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0023] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0024] As mentioned in the background technology, in the field of energy storage systems, the BMS component of the battery subsystem plays a vital role, usually consisting of a battery stack management system controller, a battery cluster management system controller, and a battery pack management unit controller. In this sophisticated architecture, each controller needs to communicate data with other controllers through a unique address code to ensure accurate information transmission and efficient operation of the system.

[0025] However, in the actual project deployment process, address allocation for BMS controllers has become a tedious and critical task, especially for a large number of BCUs and BMUs. The traditional manual addressing method is not only labor-intensive, time-consuming and labor-intensive, but also prone to errors due to human factors, which in turn affects the stability and reliability of the entire system.

[0026] In the prior art, the mainstream method of achieving address adaptation is mainly to use a dedicated address allocation line combined with sophisticated software logic for data interaction based on a communication harness.

[0027] Based on the above situation, the embodiments of the present application provide an address allocation method, device, electronic device and storage medium. By setting a switch on the communication bus of the cascaded control unit, the existing communication bus is reused to achieve efficient and convenient address allocation, which can eliminate the dedicated address allocation harness, simplify the wiring structure, and reuse the existing communication bus, so that adaptive address allocation can be achieved.

[0028] To implement the process steps and functions of each example in this application, please refer to Figure 1 , Figure 1 A schematic structural block diagram of an electronic device provided in an embodiment of the present application. The electronic device 100 includes a memory 101 and a processor 103, and the memory 101 and the processor 103 are electrically connected to each other directly or indirectly to realize data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses 104 or signal lines. The memory 101 can be used to store software programs and modules, and the processor 103 executes the software programs and modules stored in the memory 101 to perform various functional applications and data processing.

[0029] The electronic device 100 may be, but is not limited to, a personal computer (PC), a server, a distributed computer, etc. It is understandable that the electronic device 100 is not limited to a physical server, but may also be a virtual machine on a physical server, a virtual machine built on a cloud platform, etc., which can provide the same functions as the server or virtual machine. The operating system of the electronic device 100 may be, but is not limited to, a Windows system, a Linux system, etc.

[0030] Among them, the memory 101 can be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable read-only memory (EEPROM), etc.

[0031] The communication connection between the electronic device 100 and an external device is achieved through at least one communication interface 102 (which can be wired or wireless).

[0032] The processor 103 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of one or more embodiments of the present application can be completed by the hardware integrated logic circuit in the processor 103 or the instructions in the form of software. The processor 103 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.

[0033] Understandably, Figure 1 The structure shown is for illustration only. The electronic device 100 may also include Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown. Figure 1 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0034] The following is an exemplary description of the address allocation method provided in one or more embodiments of the present application. Figure 2 , Figure 2A schematic structural block diagram of a battery management system provided in an embodiment of the present application, the address allocation method is applied to the battery management system 300, the battery management system 300 includes a plurality of control units 320 cascaded in sequence through a communication bus, each control unit includes a switch, and the switch of each control unit is arranged on the communication bus for controlling the connection and disconnection of the communication bus, and the first control unit is used to connect to the main controller 310.

[0035] For example, in the three-level architecture of the BMS, if the BCU is the control unit 320 , the BAU is the main controller 310 ; if the BMU is the control unit 320 , the BCU is the main controller 310 .

[0036] Among them, the communication bus can be a variety of communication buses such as CAN, RS485, RS232, SPI, UART, ETH, etc. For example, the physical layer of the CAN bus uses two wires to connect each unit. Therefore, when using the CAN bus, the switch of each control unit is a pair of switches, that is, a switch is set on both wires.

[0037] See also Figure 3 , Figure 3 A flowchart of an address allocation method provided in an embodiment of the present application, the method comprising: Figure 3 The following steps are shown: S210: When the main controller issues a normal working instruction, each control unit is in a normal state; wherein the normal state indicates that each switch is in a closed state and each control unit can communicate normally.

[0038] When the battery management system is working normally, without address allocation, all switches are in a closed state, which means that the circuit is connected and the current can flow normally, thereby allowing all controllers to perform normal data communication on the communication bus.

[0039] S220: When the main controller issues an address adaptation instruction, each control unit disconnects its own switch according to the address adaptation instruction; the main controller allocates addresses to each control unit according to the cascade sequence of each control unit.

[0040] When the main controller issues an address adaptation instruction, it is necessary to assign addresses to each control unit, and each control unit will first disconnect its own switch. The main controller assigns addresses to each control unit in turn according to the cascade order (i.e., the physical connection order) of each control unit. The cascade order refers to the order in which the control units are arranged in the system, which is determined by the order in which they are connected in the physical line. For example, suppose there are three control units in the system, namely A, B, and C, and they are connected in sequence. The main controller will assign an address to A first, then B, and finally C.

[0041] The method sets a switch on the communication bus cascade control unit, and then when address adaptation is required, each control unit will disconnect its own switch, and the main controller will allocate addresses to each control unit according to the cascade order of each control unit. In this way, the existing communication bus can be reused to achieve efficient and convenient address allocation, and the dedicated address allocation harness can be omitted, that is, adaptive address allocation can be achieved.

[0042] In a possible implementation, in order to make the address allocation process more simple and quick, the above step S220 may include the following steps: S221: Each control unit replies an address adaptation response to the main controller according to the address adaptation instruction, and turns off its own switch, marking its own state as unassigned address.

[0043] After receiving the address adaptation instruction from the main controller, each control unit will immediately send a confirmation response to the main controller, indicating that they have received the instruction. This response tells the main controller that these control units are ready for address allocation. After sending the response, each control unit will turn off its own switch. At this time, the first control unit on the communication bus will obtain exclusive communication rights with the main controller. The main controller will then start to allocate addresses to the first control unit.

[0044] When the control unit turns off the switch, it will mark its internal state as "unassigned address". This means that they have not yet obtained a formal address and are waiting for the main controller to assign an address.

[0045] S222: The main controller sends an address allocation instruction to each control unit according to the cascade sequence of each control unit based on the address adaptive response, and after completing the address allocation to each control unit, sends a normal working instruction to each control unit.

[0046] The main controller receives the address adaptation response from each control unit and confirms that each control unit is ready for address assignment. The main controller sends address assignment instructions to each control unit in the cascade order of each control unit. For example, if there are three control units connected in sequence, A, B, and C, the main controller will first assign an address to A, then B, and finally C. After each control unit receives the address assignment instruction, it will store it internally and update its own status from "unassigned address" to "assigned address". Once all control units have successfully received and stored their respective addresses, the main controller will issue normal working instructions to all control units.

[0047] S223: Each control unit receives a normal working instruction and returns to a normal state.

[0048] After receiving the normal working instruction, each control unit will close its own switch again. This makes the circuit reconnected, the current and signal can flow and transmit normally, and the communication link between the control units is reestablished, and they can start to exchange data and information normally.

[0049] In a possible implementation, in order to ensure that the multi-control unit system can efficiently and orderly complete the address configuration in a complex network environment, and thus achieve stable data communication, see Figure 4 , the above step S222 may include the following steps: S2221: The main controller sends an address allocation preparation instruction.

[0050] The main controller first sends an address allocation preparation instruction and waits for a response to confirm that there is a control unit with normal communication.

[0051] S2222: The control unit in the unallocated address state replies to the main controller with an address allocation preparation response.

[0052] Only the control unit that can communicate with the main controller and whose state is unassigned address will reply the address assignment preparation response to the main controller. The control unit that has been assigned an address will enter the silent state and will no longer reply the address assignment response.

[0053] S2223: Whether the main controller receives only one address allocation preparation response from the target control unit within the first preset time period. If not, execute step S2224; if so, execute step S2225.

[0054] The main controller sets a first preset time length, receives the response of the control unit within the first preset time length, and determines how many responses are received within the first preset time length. If only one is received, the address can be allocated normally. If more than one is received, the main controller sends a normal working instruction to each control unit to end the allocation.

[0055] S2224: The main controller sends normal working instructions to each control unit.

[0056] S2225: The main controller sends an address allocation assignment instruction to the target control unit.

[0057] After confirming that there is only one control unit that responds to the address allocation preparation instruction, the main controller sends an address allocation assignment instruction to the control unit to assign an address to the control unit.

[0058] S2226: The target control unit performs address assignment according to the address assignment instruction, closes its own switch, marks its own state as assigned address, and replies an address assignment response to the main controller.

[0059] The control unit modifies its own address according to the address in the address allocation assignment instruction. After the modification is completed, it closes its own switch, marks its own state as the allocated address, and replies the address allocation assignment response to the main controller, and the control enters the silent state.

[0060] S2227: Whether the main controller receives the address assignment response from the target control unit within the second preset time period. If not, execute step S2224; if so, execute step S2228.

[0061] It is determined whether an address allocation response is received from the target control unit within the second preset time. If not, it indicates that a problem occurs in the allocation. The main controller then sends a normal working instruction to each control unit to end the allocation.

[0062] S2228: The main controller determines whether the number of control units in the allocated state is the preset number. If yes, execute step S2224; if no, execute step S2221.

[0063] For example, if one BCU needs to assign addresses to 10 BMUs, the preset number is 10. If the number of control units that have been assigned addresses is 10, it means that the address allocation of 10 BMUs is completed, and the allocation is ended. If 10 units are not assigned, the main controller resends the address allocation preparation instruction.

[0064] Optionally, as the number of address adaptive controllers increases, in order to ensure that the stability of the communication system is not affected, each control unit further includes an anti-interference unit, and the method may further include: S230: When the switches of the control units are disconnected, the normally open ends of the switches are connected to the anti-interference unit.

[0065] When the main controller issues an address adaptation instruction, each control unit will disconnect its own switch, which means that the switch changes from a closed state to an open state, cutting off the normal circuit connection. When the switch is disconnected, the normally open end of the switch (i.e., the default connection end when disconnected) will be connected to the anti-interference unit. The anti-interference unit can be a circuit component that reduces or eliminates electromagnetic interference and other noise.

[0066] Optionally, the communication bus is a CAN bus, and the anti-interference unit is a resistor of a preset value, and the value of the resistor may be 120 ohms.

[0067] Reference Figure 5, when the communication bus is a CAN bus and the anti-interference unit is a resistor of a preset size (for example, 120 ohms), in order to improve the anti-interference ability and signal integrity of the CAN bus, the CAN bus standard stipulates that in order to reduce signal reflection and improve signal integrity, there should be a 120 ohm terminal resistor at both ends of the bus. Therefore, when the switch is disconnected, a 120 ohm resistor is connected. The role of these resistors is to match the characteristic impedance of the bus with the terminal resistor, thereby reducing signal reflection and improving communication reliability.

[0068] Optionally, in order to solve the problem that some control units may not be able to successfully receive the address allocation end signal from the main controller under abnormal conditions, the method may further include the following steps: S240: If each control unit does not receive an address allocation instruction sent by the main controller within a third preset time period, each control unit returns to a normal state.

[0069] Under abnormal conditions, some control units may not be able to successfully receive the address allocation completion signal from the main controller. In view of this, in the above process, each controller is configured with a third preset time window mechanism. If no further instructions related to address adaptation are received within this time window, the control unit will automatically exit the address adaptation mode and perform the switch closing operation at the same time. This ensures that even when the system encounters abnormal conditions, each control unit can still maintain data communication capabilities with each other.

[0070] The third preset duration may be the sum of the first preset duration and the second preset duration multiplied by a preset number.

[0071] For example, one BCU needs to assign addresses to 10 BMUs. The first preset duration is 100ms, which means that after the main controller issues an address assignment preparation instruction, it takes 100ms to wait for the control unit to respond. The second preset duration is 100ms, which means that after the main controller issues an address assignment instruction, it takes 100ms to wait for the control unit to respond. The preset number is the number of BMUs that need to be assigned addresses, which is 10. Therefore, the third preset duration is (100ms+100ms)*10=2000ms. That is, if each control unit does not receive further instructions related to address adaptation within 2000ms, it will close its own switch. The following is an example to further illustrate the address allocation method. Figure 6, the main controller sends an address adaptation instruction to start address adaptation. Each control unit replies with an address adaptation response and disconnects its own switch, marking its own state as unassigned address. At this time, the first control unit on the communication bus will obtain exclusive communication rights with the main controller. The main controller sends an address allocation preparation instruction. The control unit in the unassigned address state replies with a response. At this time, it is the first control unit. Whether the main control receives only one response within 100ms, no response is received, or more responses are received, it means that a problem has occurred. The main controller sends a normal working instruction, and each control unit returns to normal state. If only one response is received, the first control unit performs address assignment. The main controller sends an address assignment instruction, and the first control unit assigns values ​​according to the address assignment. Instruction, change address, turn off the switch, mark as allocated address, reply address allocation assignment response, the main controller receives the reply from the control unit within 100ms, and then determines whether the number of allocated addresses is 10, that is, all 10 BMUs have allocated addresses. If so, the main controller sends a normal working instruction, and each control unit returns to normal status. If not, the main controller sends the address allocation preparation instruction again. Currently, the switch of the first control unit is turned off, and the first control unit and the second control unit can communicate with the main controller. Since the first control unit has been allocated an address and the status is allocated address, the first control unit will not reply to the response. The second control unit replies to the response and performs address allocation. By analogy, all 10 BMUs can be allocated addresses.

[0072] Furthermore, one or more embodiments of the present application further provide an address allocation device, which is applied to a battery management system. The battery management system includes a plurality of control units cascaded in sequence through a communication bus, each control unit includes a switch, and the switch of each control unit is arranged on the communication bus to control the connection and disconnection of the communication bus. The first control unit is used to connect to the main controller, and the battery management system includes a plurality of control units cascaded in sequence through a communication bus, each control unit includes a switch, and the switch of each control unit is arranged on the communication bus to control the connection and disconnection of the communication bus. Figure 7 , the address allocation device 400 comprises: The normal working instruction processing module 410 is used to ensure that each control unit is in a normal state when the main controller issues a normal working instruction; wherein the normal state indicates that each switch is in a closed state and each control unit can communicate normally.

[0073] The address allocation module 420 is used for each control unit to disconnect its own switch according to the address adaptation instruction issued by the main controller; the main controller allocates addresses to each control unit according to the cascade sequence of each control unit.

[0074] In summary, one or more embodiments of the present application provide an address allocation method, device, electronic device and storage medium, which reuse the communication lines between control units through the setting of switches, avoid the use of dedicated address allocation lines, thereby simplifying the wiring structure of the entire system and reducing wiring costs and complexity. In the process of address adaptation, if an abnormal situation occurs, the switch can quickly locate the address error in an intuitive physical way, greatly improving the efficiency of troubleshooting; by connecting a preset resistor when the switch is disconnected, electrical interference can be reduced, the stability and reliability of the system can be improved, and the service life of the equipment can be extended; the address allocation process is made faster and smoother, and the overall response speed of the system and user experience are improved.

[0075] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and a part of the module, program segment or code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0076] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0077] If the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a computer-readable storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, and other media that can store program codes.

[0078] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0079] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. An address allocation method, characterized in that: Applied to a battery management system, the battery management system includes a plurality of control units cascaded in sequence through a communication bus, each of the control units includes a switch, and the switch of each control unit is arranged on the communication bus to control the connection and disconnection of the communication bus, the first control unit is used to connect to a main controller, and the method includes: When the main controller issues a normal working instruction, each of the control units is in a normal state; the normal state indicates that each of the switches is in a closed state, and each of the control units can communicate normally; When the main controller issues an address adaptation instruction, each control unit disconnects its own switch according to the address adaptation instruction; and the main controller allocates addresses to each control unit according to the cascade sequence of each control unit.

2. The method according to claim 1, characterized in that: Each of the control units disconnects its own switch according to the address adaptation instruction; The main controller allocates addresses to the control units according to the cascade sequence of the control units, including: Each of the control units replies an address adaptation response to the main controller according to the address adaptation instruction, and turns off its own switch, marking its own state as an unassigned address; The main controller sends an address allocation instruction to each control unit according to the cascade sequence of each control unit according to the address adaptive response, and after completing the address allocation to each control unit, sends the normal working instruction to each control unit; Each of the control units receives the normal working instruction and returns to the normal state.

3. The method according to claim 2, characterized in that The main controller sends an address allocation instruction to each control unit according to the cascade order of each control unit according to the address adaptive response, completes the address allocation to each control unit, and sends the normal working instruction to each control unit, including: The main controller sends an address allocation preparation instruction; The control unit in the state of unallocated address replies an address allocation preparation response to the main controller; Whether the main controller receives only one address allocation preparation response from the target control unit within a first preset time period; If not, the main controller sends the normal working instruction to each of the control units; If so, the main controller sends an address allocation assignment instruction to the target control unit; The target control unit performs address assignment according to the address assignment instruction, closes its own switch, marks its own state as assigned address, and replies an address assignment response to the main controller; Whether the main controller receives an address allocation response from the target control unit within a second preset time period; If not, the main controller sends the normal working instruction to each of the control units; If so, the main controller determines whether the number of control units in the state of being allocated is a preset number; If so, the main controller sends the normal working instruction to each of the control units; If not, the main controller sends the address allocation preparation instruction again until the state is that the number of allocated control units is the preset number.

4. The method according to claim 3, characterized in that The method further comprises: If each of the control units does not receive the address allocation instruction sent by the main controller within a third preset time period, each of the control units returns to the normal state.

5. The method according to claim 4, characterized in that The third preset duration is the sum of the first preset duration and the second preset duration multiplied by the preset number.

6. The method according to claim 1, characterized in that Each of the control units further includes an anti-interference unit, and the method further includes: When the switches of the control units are disconnected, the normally open ends of the switches are connected to the anti-interference unit.

7. The method according to claim 6, characterized in that The communication bus is a CAN bus, and the anti-interference unit is a resistor of a preset value.

8. An address allocation device, characterized in that: Applied to a battery management system, the battery management system includes a plurality of control units cascaded in sequence through a communication bus, each of the control units includes a switch, and the switch of each control unit is arranged on the communication bus to control the connection and disconnection of the communication bus, the first control unit is used to connect to a main controller, and the device includes: A normal working instruction processing module, used for, when the main controller issues a normal working instruction, each of the control units is in a normal state; the normal state indicates that each of the switches is in a closed state, and each of the control units can communicate normally; The address allocation module is used for each control unit to disconnect its own switch according to the address adaptation instruction issued by the main controller; the main controller allocates addresses to each control unit according to the cascade sequence of each control unit.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the program, the method according to any one of claims 1 to 7 is implemented.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

Images