Video decoding core, video decoding method, electronic device and storage medium

Abstract

The present disclosure relates to the field of computer technology, and in particular to a video decoding kernel and a video decoding method, an electronic device and a storage medium, wherein the video decoding kernel comprises: a reconstructor, a multi-core controller, wherein the reconstructor comprises a plurality of reconstruction kernels; the multi-core controller is used to control each reconstruction kernel in the reconstructor, and read the corresponding row parsing information of the target Tile from the corresponding storage space in the target DDR corresponding to the video decoding kernel, wherein the target Tile is an image block to be decoded in a video frame in a video decoding task; the multi-core controller is used to control the plurality of reconstruction kernels in the reconstructor, and perform reconstruction processing in parallel on the corresponding row parsing information of the read target Tile, and obtain the reconstruction result of the target Tile. The embodiments of the present disclosure effectively improve the decoding performance of the video decoding kernel.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a video decoding kernel and a video decoding method, an electronic device and a storage medium. Background Art

[0002] With the rapid development of artificial intelligence (AI) video generation technology, the number of high-resolution, high-frame-rate video rendering scenarios is increasing, and the processing power of single-core video decoding can no longer meet the demand. The demand for multi-core video decoding is increasing. However, the current common multi-core video decoding is to schedule multiple single-core video decoding cores through software. The software scheduling process takes a long time to calculate, consumes a lot of time, and the scheduling process is complex. The system central processing unit (CPU) occupancy rate is high, and the performance of multiple reconstruction cores cannot be brought into play, resulting in no improvement in video decoding performance. Summary of the invention

[0003] The present disclosure proposes a technical solution of a video decoding core and a video decoding method, an electronic device and a storage medium.

[0004] According to one aspect of the present disclosure, a video decoding core is provided, comprising: a reconstructor and a multi-core controller, wherein the reconstructor comprises a plurality of reconstruction cores; the multi-core controller is used to control each reconstruction core in the reconstructor to read corresponding row parsing information of a target block from a corresponding storage space in a target DDR corresponding to the video decoding core, wherein the target block is an image block to be decoded in a video frame in a video decoding task; the multi-core controller is used to control the plurality of reconstruction cores in the reconstructor to perform reconstruction processing in parallel on the corresponding row parsing information of the read target block to obtain a reconstruction result of the target block.

[0005] In one possible implementation, the video decoding core includes: a parser and a decoding controller; the decoding controller is used to receive the video decoding task and control the parser to perform parsing processing on each block in the i-th video frame in the video decoding task, wherein i is a positive integer; the decoding controller is used to control the reconstructor to perform reconstruction processing on each block in the j-th video frame in the video decoding task, wherein the j-th video frame has been parsed and j is a positive integer.

[0006] In one possible implementation, the video decoding core includes: a parser and a decoding controller; the decoding controller is used to receive the video decoding task and control the parser to perform parsing processing on the nth block in the mth video frame in the video decoding task, wherein m and n are positive integers; the decoding controller is used to control the reconstructor to perform reconstruction processing on the pth block in the mth video frame, wherein the pth block has been parsed and p is a positive integer.

[0007] In one possible implementation, each block in the video decoding task includes multiple decoding processing unit rows; the video decoding core includes: a parser and a decoding controller; the decoding controller is used to determine, for each block in the video decoding task, the corresponding storage space of each decoding processing unit row of the block in the target DDR; the parser is used to parse each decoding processing unit row of the block in turn, and store the row parsing information obtained by parsing each decoding processing unit row in the corresponding storage space of the decoding processing unit row in the target DDR.

[0008] In one possible implementation, each block in the video decoding task includes multiple decoding processing unit rows; the video decoding core includes: a parser and a decoding controller; the reconstructor includes two reconstruction cores; the decoding controller is used to determine, for each block in the video decoding task, a first storage space corresponding to the odd-numbered row decoding processing unit rows of the block in the target DDR, and to determine a second storage space corresponding to the even-numbered row decoding processing unit rows of the block in the target DDR; the parser is used to parse each decoding processing unit row of the block in turn, and store the odd-numbered row parsing information obtained by parsing the odd-numbered row decoding processing unit rows of the block in the first storage space, and store the even-numbered row parsing information obtained by parsing the even-numbered row decoding processing unit rows of the block in the second storage space.

[0009] In one possible implementation, the multi-core controller is used to control a reconstruction core within the reconstructor to read the odd-row parsing information of the target block from the first storage space, and perform reconstruction processing on the odd-row parsing information to obtain the odd-row reconstruction result of the target block; the multi-core controller is used to control another reconstruction core within the reconstructor to read the even-row parsing information of the target block from the second storage space, and perform reconstruction processing on the even-row parsing information to obtain the even-row reconstruction result of the target block.

[0010] In one possible implementation, the target block includes N decoding processing unit rows, where N is a positive integer; the reconstructor includes two reconstruction kernels: a first reconstruction kernel and a second reconstruction kernel; the multi-core controller is used to control the first reconstruction kernel to sequentially perform reconstruction processing on the odd-numbered decoding processing unit rows included in the target block; the multi-core controller is used to control the second reconstruction kernel to sequentially perform reconstruction processing on the even-numbered decoding processing unit rows included in the target block.

[0011] In one possible implementation, N is an even number; the multi-core controller is used to determine that the first reconstruction kernel completes the reconstruction processing of the N-1th decoding processing unit row included in the target block, and determines that after the second reconstruction kernel completes the reconstruction processing of the Nth decoding processing unit row included in the target block, it starts the reconstruction processing of the next block after the target block.

[0012] In one possible implementation, N is an odd number; the multi-core controller is used to determine that after the second reconstruction kernel completes the reconstruction processing of the N-1th decoding processing unit row included in the target block, it starts the reconstruction processing of the next block after the target block.

[0013] In one possible implementation, the target block includes multiple decoding processing unit rows, each decoding processing unit row includes multiple decoding processing units; the multi-core controller is used to control another reconstruction core in the reconstructor that is in an idle state to start reconstruction processing on the m+1th decoding processing unit row of the target block when it is determined that a reconstruction core in the reconstructor has completed reconstruction processing on the first decoding processing unit in the mth decoding processing unit row of the target block, and when it is determined that there is another reconstruction core in an idle state in the reconstructor, where m is a positive integer.

[0014] In one possible implementation, for any reconstruction kernel, after the reconstruction kernel performs reconstruction processing on a decoding processing unit, the reference data corresponding to the decoding processing unit is determined according to the reconstruction result, and the reference data corresponding to the decoding processing unit is stored in a preset storage space.

[0015] In a possible implementation manner, the preset storage space is located in the internal memory of the video decoding core, or the preset storage space is located in the target DDR.

[0016] According to one aspect of the present disclosure, a video decoding method is provided, the method being applied to a video decoding core, the video decoding core comprising: a reconstructor, a multi-core controller, wherein the reconstructor comprises a plurality of reconstruction cores; the method comprising: based on the multi-core controller, controlling each reconstruction core in the reconstructor to read corresponding row parsing information of a target block from a corresponding storage space in a target DDR corresponding to the video decoding core, wherein the target block is an image block to be decoded in a video frame in a video decoding task; based on the multi-core controller, controlling the plurality of reconstruction cores in the reconstructor to perform reconstruction processing in parallel on the corresponding row parsing information of the read target block to obtain a reconstruction result of the target block.

[0017] According to one aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0018] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor.

[0019] In the disclosed embodiment, a hardware multi-core video decoding core is designed so that one video decoding core includes: a reconstructor composed of multiple reconstruction cores and a multi-core controller; based on the multi-core controller, each reconstruction core in the reconstructor is controlled to read the corresponding row parsing information of the target block from the corresponding storage space in the target DDR corresponding to the video decoding core; further, based on the multi-core controller, the multiple reconstruction cores in the reconstructor are controlled to perform reconstruction processing in parallel on the corresponding row parsing information of the read target block to obtain the reconstruction result of the target block; at the hardware level, through the scheduling of the multi-core controller, the multiple reconstruction cores in the reconstructor can be effectively controlled to decode in parallel, giving full play to the decoding performance of the multiple reconstruction cores, thereby effectively improving the decoding performance of the video decoding core.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0022] Figure 1 A schematic diagram showing software scheduling of two single-core video decoding cores in the related art.

[0023] Figure 2 A block diagram of a video decoding core according to an embodiment of the present disclosure is shown.

[0024] Figure 3 A schematic diagram showing a decoding controller determining a storage space of each decoding processing unit row of a Tile according to an embodiment of the present disclosure.

[0025] Figure 4 A schematic diagram showing a decoding controller according to an embodiment of the present disclosure determining storage space of odd-numbered rows and even-numbered rows of decoding processing unit rows of a Tile.

[0026] Figure 5 A schematic diagram of a video decoding system according to an embodiment of the present disclosure is shown.

[0027] Figure 6 A schematic diagram showing a reconstruction process performed on a target block by a reconstructor according to an embodiment of the present disclosure.

[0028] Figure 7 A schematic diagram showing a reconstruction process performed on block 1 and block 2 by a reconstructor according to an embodiment of the present disclosure.

[0029] Figure 8 A flowchart of a video decoding method according to an embodiment of the present disclosure is shown.

[0030] Fig. 9 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0031] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0032] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0033] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0034] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0035] Currently, the most common multi-core video decoding is to schedule multiple single-core video decoding cores through software. Figure 1 FIG. 1 is a schematic diagram showing software scheduling of two single-core video decoding cores in the related art. Figure 1 As shown in the figure, the hardware side includes two single-core video decoding cores: video decoding core 1 and video decoding core 2. A single-core video decoding core refers to a video decoding core that only includes one reconstruction core. The software side is responsible for task scheduling and parameter space calculation. Figure 1 As shown, first, the software side configures the parameters of the first frame of video to the video decoding kernel 1. After the configuration is completed, the software side starts the configuration of the second frame of video, and the video decoding kernel 1 on the hardware side starts decoding the first frame of video; the software side configures the parameters of the second frame of video to the video decoding kernel 2. After the configuration is completed, the software side starts the configuration of the third frame of video, and the video decoding kernel 2 on the hardware side starts decoding the second frame of video; the software side configures the parameters of the third frame of video to the video decoding kernel 1. After the configuration is completed, the software side starts the configuration of the fourth frame of video, and the video decoding kernel 1 on the hardware side starts decoding the third frame of video; the software side configures the parameters of the fourth frame of video to the video decoding kernel 2. After the configuration is completed, the software side starts the configuration of the fifth frame of video, and the video decoding kernel 2 on the hardware side starts decoding the fourth frame of video; and so on. The software scheduling process has a long calculation time, consumes a lot of time, is complex in the scheduling process, has a high system CPU occupancy rate, and cannot give full play to the performance of multiple reconstruction kernels, resulting in no improvement in video decoding performance. In addition, scheduling multiple single-core video decoding kernels by software will result in additional storage resources and bandwidth pressure.

[0036] In order to solve the above technical problems, the embodiment of the present disclosure provides a multi-core video decoding kernel, including: a reconstructor composed of multiple reconstruction kernels, and a multi-core controller. At the hardware level, through the scheduling of the multi-core controller, the parallel decoding of multiple reconstruction kernels in the reconstructor can be effectively controlled, and the decoding performance of the multiple reconstruction kernels is fully utilized, thereby effectively improving the decoding performance of the video decoding kernel. The video decoding kernel provided by the embodiment of the present disclosure is described in detail below.

[0037] Figure 2 FIG. 1 is a block diagram of a video decoding core according to an embodiment of the present disclosure. Figure 2As shown, the video decoding core includes: a reconstructor and a multi-core controller, wherein the reconstructor includes multiple reconstruction cores; the multi-core controller is used to control each reconstruction core in the reconstructor to read the corresponding row parsing information of the target block (i.e., target Tile) from the corresponding storage space in the target double data rate memory (Double Data Rate, DDR) corresponding to the video decoding core, wherein the target Tile is an image block to be decoded in a video frame in the video decoding task; the multi-core controller is used to control the multiple reconstruction cores in the reconstructor to perform reconstruction processing in parallel on the corresponding row parsing information of the read target Tile to obtain the reconstruction result of the target Tile.

[0038] The entire decoding process of the target Tile is divided into a parsing process and a reconstruction process. In the parsing process of the target Tile, the row parsing information obtained after the target Tile is parsed is stored in the corresponding storage space in the target DDR. Therefore, in the reconstruction process of the target Tile, the multi-core controller can flexibly schedule multiple reconstruction cores in the reconstructor to perform reconstruction processing on the target Tile in parallel: the multi-core controller controls each reconstruction core in the reconstructor to read the corresponding row parsing information of the target Tile from the corresponding storage space in the target DDR; the multi-core controller controls multiple reconstruction cores in the reconstructor to perform reconstruction processing in parallel on the row parsing information of the read target Tile to obtain the reconstruction result of the target Tile.

[0039] The parsing process refers to parsing the syntax elements according to the video standard protocol, completing entropy decoding and motion information calculation, and obtaining parsing information. The reconstruction process refers to performing pixel reconstruction calculations based on the parsing information (e.g., residual data, motion information). The reconstruction process is divided into inverse quantization, inverse transformation, prediction calculation, motion compensation, and reconstruction calculation processes. The specific execution steps of the parsing process and the reconstruction process can refer to the video decoding related process, and the present disclosure does not make specific limitations on this.

[0040] In the disclosed embodiment, a hardware multi-core video decoding core is designed so that one video decoding core includes: a reconstructor composed of multiple reconstruction cores and a multi-core controller; based on the multi-core controller, each reconstruction core in the reconstructor is controlled to read the corresponding row parsing information of the target Tile from the corresponding storage space in the target DDR corresponding to the video decoding core; further, based on the multi-core controller, the multiple reconstruction cores in the reconstructor are controlled to perform reconstruction processing in parallel on the corresponding row parsing information of the read target Tile to obtain the reconstruction result of the target Tile; at the hardware level, through the scheduling of the multi-core controller, the multiple reconstruction cores in the reconstructor can be effectively controlled to decode in parallel, giving full play to the decoding performance of the multiple reconstruction cores, thereby effectively improving the decoding performance of the video decoding core.

[0041] By implementing parallel reconstruction processing of multiple reconstruction cores in the reconstructor at the hardware level, compared with the software scheduling method in the related technology, the time required for software scheduling can be reduced, the occupation of system CPU resources can be reduced, and the video decoding capability can be improved.

[0042] In one possible implementation, each Tile in a video decoding task includes multiple decoding processing unit rows; the video decoding core includes: a parser and a decoding controller; the decoding controller is used to determine, for each Tile in the video decoding task, the corresponding storage space of each decoding processing unit row of the Tile in the target DDR; the parser is used to parse each decoding processing unit row of the Tile in turn, and store the row parsing information obtained by parsing each decoding processing unit row in the corresponding storage space of the decoding processing unit row in the target DDR.

[0043] In a video coding scenario, for example, under the HEVC video coding standard, a video frame can be divided into several tiles, that is, a video frame image is divided into several rectangular areas in the horizontal and vertical directions. These rectangular areas are called tiles.

[0044] In the video decoding scenario, the video decoding task includes multiple video frames, each video frame includes multiple tiles, and each tile includes multiple decoding processing unit rows. The software side configures the video decoding task to the multi-core video decoding kernel on the hardware side.

[0045] For any Tile in the video decoding task, the decoding controller included in the multi-core video decoding core determines the corresponding storage space of each decoding processing unit row of the Tile in the target DDR, so that after the parser parses each decoding processing unit row of the Tile in turn, the row parsing information obtained by parsing each decoding processing unit row can be stored in the corresponding storage space of the decoding processing unit row in the target DDR, preparing for the subsequent multiple reconstruction cores to perform reconstruction processing on the Tile in parallel.

[0046] By dividing the target DDR into the storage space corresponding to each reconstruction core, parallel reconstruction processing of multiple reconstruction cores in a multi-core video decoding core can be achieved. The multi-core video decoding core of the embodiment of the present disclosure can achieve multiple video decoding performance while maintaining the same bandwidth and DDR memory resources as the single-core video decoding core in the related technology, without occupying additional DDR memory resources and without bringing additional bandwidth pressure to the video decoding system.

[0047] Figure 3 FIG. 2 is a schematic diagram showing a decoding controller according to an embodiment of the present disclosure determining the storage space of each decoding processing unit row of a Tile. Figure 3As shown, a video frame in a video decoding task includes 4 tiles: tile 1, tile 2, tile 3, and tile 4. Assuming that the reconstructor in the multi-core video decoding kernel includes 4 reconstruction kernels: reconstruction kernel 0 to reconstruction kernel 3, the target DDR corresponding to the multi-core video decoding kernel can be divided into 4 storage spaces: storage space 0 to storage space 3. The relationship between the reconstruction kernel h and the storage space w is determined based on the modulus operation: w=h mod 4. For example, the reconstruction kernel h=0 corresponds to the storage space w=0 mod 4=0, the reconstruction kernel h=1 corresponds to the storage space w=1 mod 4=1, and so on, which will not be repeated.

[0048] by Figure 3 Taking Tile3 in Tile3 as an example, the decoding controller determines the corresponding storage space of each decoding processing unit row of Tile3 in the target DDR: the 1st decoding processing unit row, the 5th decoding processing unit row, the 9th decoding processing unit row, ..., correspond to storage space 1 in the target DDR; the 2nd decoding processing unit row, the 6th decoding processing unit row, the 10th decoding processing unit row, ..., correspond to storage space 2 in the target DDR; the 3rd decoding processing unit row, the 7th decoding processing unit row, the 11th decoding processing unit row, ..., correspond to storage space 3 in the target DDR; the 4th decoding processing unit row, the 8th decoding processing unit row, the 12th decoding processing unit row, ..., correspond to storage space 4 in the target DDR.

[0049] In one possible implementation, each Tile in a video decoding task includes multiple decoding processing unit rows; the video decoding core includes: a parser and a decoding controller; the decoding controller is used to determine, for each Tile in the video decoding task, that the odd-numbered rows of decoding processing unit rows of the Tile correspond to the first storage space in the target DDR, and to determine that the even-numbered rows of decoding processing unit rows of the Tile correspond to the second storage space in the target DDR; the parser is used to parse each decoding processing unit row of the Tile in turn, and store the odd-numbered row parsing information obtained by parsing the odd-numbered rows of decoding processing unit rows of the Tile in the first storage space, and store the even-numbered row parsing information obtained by parsing the even-numbered rows of decoding processing unit rows of the Tile in the second storage space.

[0050] Assuming that the reconstructor in the multi-core video decoding core includes two reconstruction cores, the target DDR can be divided into two storage spaces: the first storage space and the second storage space. For any Tile in the video decoding task, the decoding controller included in the multi-core video decoding core determines that the odd-numbered decoding processing unit rows of the Tile correspond to the first storage space, and determines that the even-numbered decoding processing unit rows of the Tile correspond to the second storage space, so as to prepare for the subsequent two reconstruction cores to perform reconstruction processing on the Tile in parallel.

[0051] By dividing the target DDR into a first storage space and a second storage space, parallel reconstruction processing of the two reconstruction cores in the multi-core video decoding core is achieved. When the multi-core video decoding core of the disclosed embodiment includes two reconstruction cores, double the video decoding performance can be achieved while maintaining the same bandwidth and DDR memory resources as the single-core video decoding core in the related technology, without occupying additional DDR memory resources and without bringing additional bandwidth pressure to the video decoding system.

[0052] Figure 4 FIG. 1 is a schematic diagram showing a decoding controller according to an embodiment of the present disclosure determining storage space of odd-numbered rows and even-numbered rows of decoding processing units of a Tile. Figure 4 As shown, a video frame in a video decoding task includes 4 tiles: tile 1 (Tile1), tile 2 (Tile2), tile 3 (Tile3), and tile 4 (Tile4). Taking Tile3 as an example, the decoding controller determines that each odd-numbered decoding processing unit row in Tile3 (the first decoding processing unit row, the third decoding processing unit row, the fifth decoding processing unit row...) corresponds to the first storage space in the target DDR, and determines that each even-numbered decoding processing unit row in Tile3 (decoding processing unit row 2, decoding processing unit row 4, decoding processing unit row 6...) corresponds to the second storage space in the target DDR.

[0053] After the decoding controller determines the storage space corresponding to the odd and even decoding processing unit rows of Tile3, the decoding controller starts the parser to perform parsing processing (entropy decoding, motion information calculation, etc.) on Tile3. Specifically: the parser sequentially parses each decoding processing unit row of Tile3, and stores the parsing information obtained by parsing each odd decoding processing unit row of Tile3 in the first storage space, and stores the parsing information obtained by parsing the even decoding processing unit rows of the Tile in the second storage space.

[0054] For example, the parser starts parsing the decoding processing unit row 1 of Tile3, and stores the parsing information of the decoding processing unit row 1 obtained by the parsing into the corresponding storage position in the first storage space in the target DDR; the parser starts parsing the decoding processing unit row 2 of Tile3, and stores the parsing information of the decoding processing unit row 2 obtained by the parsing into the corresponding storage position in the second storage space in the target DDR; the parser starts parsing the decoding processing unit row 3 of Tile3, and stores the parsing information of the decoding processing unit row 3 obtained by the parsing into the corresponding storage position in the first storage space in the target DDR; and so on, until the parsing of Tile3 is completed.

[0055] During the parsing process of the parser, the decoding controller continuously monitors the parser's parsing position information of the current Tile and records the storage space status of the first storage space and the second storage space. When the parser completes the parsing process of the current Tile and the storage space status of the first storage space and / or the second storage space is that there is remaining storage space, the parser starts parsing the odd-numbered decoding processing unit rows and / or the even-numbered decoding processing unit rows of the next Tile.

[0056] In one possible implementation, the reconstructor includes two reconstruction cores; a multi-core controller is used to control one reconstruction core in the reconstructor to read the odd-row parsing information of the target tile from a first storage space, and perform reconstruction processing on the odd-row parsing information to obtain the odd-row reconstruction result of the target tile; the multi-core controller is used to control another reconstruction core in the reconstructor to read the even-row parsing information of the target tile from a second storage space, and perform reconstruction processing on the even-row parsing information to obtain the even-row reconstruction result of the target tile.

[0057] During the parsing process of the target Tile, the odd-row parsing information obtained after the target Tile is parsed is stored in the first storage space in the target DDR, and the even-row parsing information is stored in the second storage space in the target DDR. Therefore, during the reconstruction process of the target Tile, the multi-core controller can flexibly schedule the two reconstruction cores in the reconstructor to perform reconstruction processing on the target Tile in parallel: the multi-core controller controls one reconstruction core in the reconstructor to read the odd-row parsing information of the target Tile from the first storage space in the target DDR, and perform reconstruction processing on the odd-row parsing information to obtain the reconstruction result of the odd-row of the target Tile; the multi-core controller controls another reconstruction core in the reconstructor to read the even-row parsing information of the target Tile from the second storage space in the target DDR, and perform reconstruction processing on the even-row parsing information to obtain the reconstruction result of the even-row of the target Tile.

[0058] Figure 5FIG. 2 is a schematic diagram of a video decoding system according to an embodiment of the present disclosure. Figure 5 As shown, the video decoding system includes: system software on the software side, a multi-core video decoding kernel on the hardware side, and a target DDR. The system software on the software side configures the video decoding task to the multi-core video decoding kernel on the hardware side.

[0059] The software side sends down the video decoding task and allocates storage space for the video decoding task. For example, storage space for motion parameters, residual coefficients, reconstructed pixels, reference pixels and other parameters is allocated according to the bit stream information. The specific process can be flexibly adjusted according to the actual video decoding scenario, and the present disclosure does not make specific limitations on this.

[0060] like Figure 5 As shown, the multi-core video decoding core includes: a decoding controller. The decoding controller receives a video decoding task, and determines the storage space of the odd-numbered rows and even-numbered rows of decoding processing unit rows of the video decoding task in the target DDR. For any Tile in any video frame in the video decoding task, the decoding controller determines that the odd-numbered rows of decoding processing unit rows of the Tile correspond to the first storage space in the target DDR, and determines that the even-numbered rows of decoding processing unit rows of the Tile correspond to the second storage space in the target DDR.

[0061] like Figure 5 As shown, the multi-core video decoding kernel includes: a parser. The parser sequentially parses each decoding processing unit row of any Tile, and stores the odd-numbered row parsing information obtained by parsing the odd-numbered row decoding processing unit rows of the Tile in the first storage space, and stores the even-numbered row parsing information obtained by parsing the even-numbered row decoding processing unit rows of the Tile in the second storage space.

[0062] For any Tile in any video frame in the video decoding task, when the decoding controller determines that the parser has completed the parsing processing of the Tile, and the odd-row parsing information of the Tile has been stored in the first storage space in the target DDR, and the even-row parsing information has been stored in the second storage space in the target DDR, the decoding controller can start the reconstructor to reconstruct the Tile.

[0063] In one possible implementation, the video decoding core includes: a parser and a decoding controller; the decoding controller is used to receive a video decoding task and control the parser to perform parsing processing on each Tile in the i-th video frame in the video decoding task, where i is a positive integer; the decoding controller is used to control the reconstructor to perform reconstruction processing on each Tile in the j-th video frame in the video decoding task, where the j-th video frame has been parsed and j is a positive integer.

[0064] The parser and reconstructor can work on different video frames in the video decoding task, reducing the impact of different bitstream parsing speeds on the reconstructor's calculation process, and processing the parsing and reconstruction processes in parallel, thereby improving the decoding performance of the entire multi-core video decoding kernel.

[0065] In one example, the parser and the reconstructor may have an offset of P frames in the video decoding task, where P is a positive integer. For example, when the reconstructor performs reconstruction processing on the jth video frame in the video decoding task, the parser performs parsing processing on the i=j+Pth video frame in the video decoding task. The specific value of P can be flexibly configured according to user needs, and this disclosure does not specifically limit this.

[0066] In one possible implementation, the video decoding core includes: a parser and a decoding controller; the decoding controller is used to receive a video decoding task and control the parser to perform parsing processing on the nth Tile in the mth video frame in the video decoding task, where m and n are positive integers; the decoding controller is used to control the reconstructor to perform reconstruction processing on the kth Tile in the mth video frame, where the kth Tile has been parsed and k is a positive integer.

[0067] The parser and reconstructor can work on different tiles within the same video frame in the video decoding task, reducing the impact of different bitstream parsing speeds on the reconstructor's calculation process, and processing the parsing and reconstruction processes in parallel, thereby improving the decoding performance of the entire multi-core video decoding core.

[0068] In one example, the parser and the reconstructor may have an offset of X tiles in the same video frame in a video decoding task, where X is a positive integer. For example, when the reconstructor performs reconstruction processing on the kth tile in the mth video frame in the video decoding task, the parser performs parsing processing on the n=k+Xth video frame in the mth video frame. The specific value of X can be flexibly configured according to user needs, and this disclosure does not specifically limit this.

[0069] In one possible implementation, the target Tile includes N rows of decoding processing units, where N is a positive integer; the reconstructor includes two reconstruction kernels: a first reconstruction kernel and a second reconstruction kernel; a multi-core controller is used to control the first reconstruction kernel to sequentially perform reconstruction processing on the odd-numbered rows of decoding processing units included in the target Tile; and the multi-core controller is used to control the second reconstruction kernel to sequentially perform reconstruction processing on the even-numbered rows of decoding processing units included in the target Tile.

[0070] like Figure 5 As shown, the multi-core video decoding kernel includes: a first reconstruction kernel and a second reconstruction kernel.

[0071] For the target Tile that currently needs to be reconstructed, since the parsing information of the odd-numbered decoding processing unit rows included in the target Tile is stored in the first storage space in the target DDR, and the parsing information of the even-numbered decoding processing unit rows is stored in the second storage space in the target DDR, the multi-core controller can control the two reconstruction cores in the reconstructor to perform reconstruction processing on the target Tile in parallel, specifically: the first reconstruction core performs reconstruction processing on the odd-numbered decoding processing unit rows included in the target Tile in turn; the second reconstruction core performs reconstruction processing on the even-numbered decoding processing unit rows included in the target Tile in turn.

[0072] In one possible implementation, the target Tile includes multiple decoding processing unit rows, each decoding processing unit row includes multiple decoding processing units; the multi-core controller is used to control a reconstruction kernel in the reconstructor that is in an idle state to start reconstruction processing on the p+1th decoding processing unit row of the target Tile when it is determined that a reconstruction kernel in the reconstructor has completed reconstruction processing on the first decoding processing unit in the pth decoding processing unit row of the target Tile, and when it is determined that there is at least one reconstruction kernel in an idle state in the reconstructor, where p is a positive integer.

[0073] For any Tile, the Tile includes multiple decoding processing unit rows, and each decoding processing unit row includes multiple decoding processing units. Figure 3 or Figure 4 As shown, decoding processing unit row 1 includes Q decoding processing units: decoding processing unit 1 to decoding processing unit Q. The specific value of Q depends on the tile division size in the actual video decoding task, and the present disclosure does not make any specific limitation on this.

[0074] During the reconstruction process, the reconstruction process of the lower decoding processing unit needs to rely on the upper decoding processing unit and the left decoding processing unit. Therefore, after determining that a reconstruction kernel in the reconstructor has completed the reconstruction process on the first decoding processing unit of the p-th decoding processing unit row of the target Tile, the reconstruction result of the first decoding processing unit of the p-th decoding processing unit row can provide the reference data required for the reconstruction process for the first decoding processing unit of the p+1-th decoding processing unit row. At this time, if there is at least one idle reconstruction kernel in the reconstructor, a reconstruction kernel in the idle state in the reconstructor can be started to perform reconstruction processing on the p+1-th decoding processing unit row of the target Tile.

[0075] In one possible implementation, for any reconstruction kernel, after the reconstruction kernel performs reconstruction processing on a decoding processing unit, the reference data corresponding to the decoding processing unit is determined according to the reconstruction result, and the reference data corresponding to the decoding processing unit is stored in a preset storage space.

[0076] Since the reconstruction processing of the lower decoding processing unit needs to rely on the upper decoding processing unit and the left decoding processing unit, for any reconstruction kernel, after the reconstruction kernel completes the reconstruction processing on a decoding processing unit, the reference data corresponding to the decoding processing unit is determined according to the reconstruction result, and the reference data corresponding to the decoding processing unit is stored in a preset storage space to provide reference data for subsequent reconstruction processing by other decoding processing units.

[0077] In a possible implementation, the preset storage space is located in an internal memory of a video decoding core, or the preset storage space is located in a target DDR.

[0078] In the case of system bandwidth restrictions, the preset storage space can be set in the internal memory of the video decoding core; in the case of chip area restrictions, the preset storage space can be set in the target DDR. According to user needs, the system bandwidth and chip area can be flexibly switched to set the preset storage space, and this disclosure does not make specific restrictions on this. Figure 5 As shown, the preset storage space is the internal memory of the video decoding core.

[0079] In one example, the reconstructor in the video decoding core includes two reconstruction cores: a first reconstruction core and a second reconstruction core, the target Tile includes N decoding processing unit rows, the first reconstruction core sequentially performs reconstruction processing on the odd-numbered decoding processing unit rows included in the target Tile; the second reconstruction core sequentially performs reconstruction processing on the even-numbered decoding processing unit rows included in the target Tile. Figure 6 A schematic diagram showing a reconstruction process performed on a target block by a reconstructor according to an embodiment of the present disclosure. Figure 7 FIG. 2 is a schematic diagram showing a reconstruction process performed on block 1 and block 2 by a reconstructor according to an embodiment of the present disclosure. Figure 7 In the example, Tile 1 is the target tile and Tile 2 is the next tile after the target tile. Figure 6 and Figure 7 As shown, the process of performing reconstruction processing on the target block (target Tile) is as follows:

[0080] After the multi-core controller detects that the parsing information corresponding to the first decoding processing unit row of the target Tile is ready (storage is completed), the multi-core controller controls the first reconstruction core to start the reconstruction processing of the first decoding processing unit row of the target Tile: the first reconstruction core reads the parsing information of the first decoding processing unit row of the target Tile from the first storage space of the target DDR, and then performs reconstruction processing on each decoding processing unit of the first decoding processing unit row in turn according to the parsing information of the first decoding processing unit row. A reconstruction process is performed on the first decoding processing unit of the first decoding processing unit row to obtain a reconstruction result of the first decoding processing unit of the first decoding processing unit row, and reference data corresponding to the first decoding processing unit of the first decoding processing unit row is determined based on the reconstruction result of the first decoding processing unit of the first decoding processing unit row, and the reference data is used to perform reconstruction processing on the second decoding processing unit of the first decoding processing unit row and the first decoding processing unit of the second decoding processing unit row, so the reference data corresponding to the first decoding processing unit of the first decoding processing unit row is stored in a preset storage space; a reconstruction process is performed on the second decoding processing unit of the first decoding processing unit row Reconstruction processing is performed to obtain a reconstruction result of the second decoding processing unit in the first decoding processing unit row, and according to the reconstruction result of the second decoding processing unit in the first decoding processing unit row, reference data corresponding to the second decoding processing unit in the first decoding processing unit row is determined, and the reference data is used to perform reconstruction processing on the third decoding processing unit in the first decoding processing unit row and the second decoding processing unit in the second decoding processing unit row, therefore, the reference data corresponding to the second decoding processing unit in the first decoding processing unit row is stored in a preset storage space; and so on, until the first reconstruction kernel completes the reconstruction processing of each decoding processing unit in the first decoding processing unit row of the target Tile.

[0081] After the multi-core controller detects that the first reconstruction core has completed the reconstruction processing of the first decoding processing unit of the first decoding processing unit row of the target Tile, and the parsing information and reference data corresponding to the first decoding processing unit of the second decoding processing unit row are ready (storage completed), the multi-core controller controls the second reconstruction core to start the reconstruction processing of the second decoding processing unit row of the target Tile: the second reconstruction core reads the parsing information of the second decoding processing unit row of the target Tile from the first storage space of the target DDR, and then performs reconstruction processing on each decoding processing unit of the second decoding processing unit row in turn according to the parsing information of the second decoding processing unit row. A reconstruction process is performed on the first decoding processing unit of the second decoding processing unit row to obtain a reconstruction result of the first decoding processing unit of the second decoding processing unit row, and reference data corresponding to the first decoding processing unit of the second decoding processing unit row is determined based on the reconstruction result of the first decoding processing unit of the second decoding processing unit row, and the reference data is used to perform reconstruction processing on the second decoding processing unit of the second decoding processing unit row and the first decoding processing unit of the third decoding processing unit row, therefore, the reference data corresponding to the first decoding processing unit of the second decoding processing unit row is stored in a preset storage space; a reconstruction process is performed on the second decoding processing unit of the second decoding processing unit row Reconstruction processing is performed to obtain a reconstruction result of the second decoding processing unit of the second decoding processing unit row, and according to the reconstruction result of the second decoding processing unit of the second decoding processing unit row, reference data corresponding to the second decoding processing unit of the second decoding processing unit row is determined, and the reference data is used to perform reconstruction processing on the third decoding processing unit of the second decoding processing unit row and the second decoding processing unit of the third decoding processing unit row, therefore, the reference data corresponding to the second decoding processing unit of the second decoding processing unit row is stored in a preset storage space; and so on, until the first reconstruction kernel completes the reconstruction processing of each decoding processing unit in the second decoding processing unit row of the target Tile.

[0082] For any decoding processing unit, the reconstruction processing of the decoding processing unit can be started only after the parsing information and reference data required for the decoding processing unit to perform the reconstruction processing are prepared.

[0083] After the multi-core controller detects that the first reconstruction kernel has completed the reconstruction process of each decoding processing unit in the first decoding processing unit row of the target Tile, and the parsing information and reference data required for the first decoding processing unit in the third decoding processing unit row to perform the reconstruction process are ready (storage completed), the multi-core controller controls the first reconstruction kernel to start the reconstruction process of the third decoding processing unit row of the target Tile. After the multi-core controller detects that the first reconstruction kernel has completed the reconstruction process of each decoding processing unit in the third decoding processing unit row of the target Tile, and the parsing information and reference data required for the first decoding processing unit in the fifth decoding processing unit row to perform the reconstruction process are ready (storage completed), the multi-core controller controls the first reconstruction kernel to start the reconstruction process of the fifth decoding processing unit row of the target Tile. And so on, until the reconstruction process of each odd-numbered decoding processing unit row in the target Tile is completed.

[0084] After the multi-core controller detects that the second reconstruction kernel has completed the reconstruction process of each decoding processing unit in the second decoding processing unit row of the target Tile, and the parsing information and reference data required for the first decoding processing unit in the fourth decoding processing unit row to perform the reconstruction process are ready (storage completed), the multi-core controller controls the second reconstruction kernel to start the reconstruction process of the fourth decoding processing unit row of the target Tile. After the multi-core controller detects that the second reconstruction kernel has completed the reconstruction process of each decoding processing unit in the fourth decoding processing unit row of the target Tile, and the parsing information and reference data required for the first decoding processing unit in the sixth decoding processing unit row to perform the reconstruction process are ready (storage completed), the multi-core controller controls the second reconstruction kernel to start the reconstruction process of the sixth decoding processing unit row of the target Tile. And so on, until the reconstruction process of each even-numbered decoding processing unit row in the target Tile is completed.

[0085] After completing the reconstruction process of each decoding processing unit row of the target Tile, the reconstruction process of the next Tile is started.

[0086] In one possible implementation, N is an even number; the multi-core controller is used to determine that after the first reconstruction kernel completes the reconstruction processing of the N-1th decoding processing unit row included in the target Tile, and after determining that the second reconstruction kernel completes the reconstruction processing of the Nth decoding processing unit row included in the target Tile, it starts the reconstruction processing of the next Tile after the target Tile.

[0087] When the target Tile includes N rows of decoding processing unit rows, and N is an even number, since the number of odd-numbered decoding processing unit rows and even-numbered decoding processing unit rows in the target Tile is average, after the first reconstruction kernel and the second reconstruction kernel complete the reconstruction processing on the target Tile in parallel, they start the reconstruction processing on the next Tile after the target Tile.

[0088] like Figure 6 As shown, the target Tile includes N=6 decoding processing unit rows. When the first reconstruction kernel performs reconstruction processing on the jth decoding processing unit in the i-th decoding processing unit row, the second reconstruction kernel performs reconstruction processing on the j-1th decoding processing unit block in the i+1th decoding processing unit row in parallel.

[0089] In a possible implementation, N is an odd number; the multi-core controller is used to determine that after the second reconstruction core completes the reconstruction process on the N-1th decoding processing unit row included in the target Tile, it starts the reconstruction process on the next Tile after the target Tile.

[0090] When the target Tile includes N rows of decoding processing unit rows and N is an odd number, since the number of odd-numbered decoding processing unit rows in the target Tile is greater than the number of even-numbered decoding processing unit rows, the second reconstruction kernel prioritizes completing the reconstruction of the even-numbered decoding processing unit rows. In order to improve the reconstruction efficiency, the multi-core controller controls the second reconstruction kernel to start the reconstruction of the next Tile after the target Tile, thereby realizing the cross-Tile reconstruction of the first reconstruction kernel and the second reconstruction kernel.

[0091] like Figure 7 As shown, the target Tile (Tile1) includes N=5 decoding processing unit rows. During the process of performing reconstruction processing on the first 4 decoding processing unit rows of Tile1, when the first reconstruction kernel performs reconstruction processing on the j-th decoding processing unit of the i-th (i is 1 or 3) decoding processing unit row of Tile1, the second reconstruction kernel performs reconstruction processing on the j-1-th decoding processing unit block of the i+1-th decoding processing unit row of Tile1 in parallel.

[0092] When the second reconstruction kernel executes the reconstruction process of the last decoding processing unit of the 4th decoding processing unit row of Tile1, the first reconstruction kernel executes the reconstruction process of the 1st decoding processing unit of the 5th decoding processing unit row of Tile1 in parallel. Therefore, after the second reconstruction kernel completes the reconstruction process of the 4th decoding processing unit row of Tile1, the first reconstruction kernel starts to execute the reconstruction process of the 2nd decoding processing unit of the 5th decoding processing unit row of Tile1. In the case where the number of decoding processing units included in each decoding processing unit row is large, if the second reconstruction kernel waits for the first reconstruction kernel to complete the reconstruction process of the 5th decoding processing unit row of Tile1 before starting the reconstruction process of the next Tile (Tile2), the second reconstruction kernel will be idle for a long time, resulting in low reconstruction efficiency.

[0093] Therefore, if Figure 7 As shown, after the second reconstruction core completes the reconstruction process of the 4th decoding processing unit row of Tile1, the multi-core controller controls the second reconstruction core to start the reconstruction process of the 1st decoding processing unit row of Tile2. At this time, the first reconstruction core works in Tile1, and the second reconstruction core works in Tile2, which effectively realizes the cross-Tile reconstruction process and improves the reconstruction efficiency.

[0094] After the first reconstruction core completes the reconstruction process of the 5th decoding processing unit row of Tile1, the multi-core controller can start the reconstruction process of the 2nd decoding processing unit row of Tile2 by the first reconstruction core. At this time, the first reconstruction core and the second reconstruction core work in Tile2 at the same time. Since cross-tile switching is implemented, in Tile2, the second reconstruction core performs reconstruction processing on the odd-numbered decoding processing unit rows of Tile2, and the first reconstruction core performs reconstruction processing on the even-numbered decoding processing unit rows of Tile2.

[0095] If the number of decoding processing unit rows included in Tile2 is even, there is no need to perform cross-Tile switching. After the second reconstruction core completes the reconstruction of the last odd-numbered decoding processing unit row included in Tile2, and the first reconstruction core completes the reconstruction of the last even-numbered decoding processing unit row included in Tile2, the reconstruction of the next Tile (Tile3) is started. In Tile3, the second reconstruction core can still perform the reconstruction of the odd-numbered decoding processing unit rows of Tile3, and the first reconstruction core can perform the reconstruction of the even-numbered decoding processing unit rows of Tile3.

[0096] If the number of decoding processing unit rows included in Tile2 is odd, it is necessary to perform cross-Tile switching again. After the first reconstruction kernel completes the reconstruction processing of the last even-numbered decoding processing unit row included in Tile2, the multi-core controller performs cross-Tile switching and controls the first reconstruction kernel to start the reconstruction processing of the first decoding processing unit row included in Tile3. At this time, the first reconstruction kernel works in Tile3, and the second reconstruction kernel works in Tile2, which effectively realizes the cross-Tile reconstruction processing and improves the reconstruction efficiency. In Tile3, the first reconstruction kernel performs reconstruction processing on the odd-numbered decoding processing unit rows of Tile3, and the second reconstruction kernel performs reconstruction processing on the even-numbered decoding processing unit rows of Tile3.

[0097] According to the above method, the reconstruction process of each Tile in each video frame in the video decoding task is completed in sequence, and the decoding of the video decoding task is completed.

[0098] In the disclosed embodiment, a hardware multi-core video decoding core is designed so that one video decoding core includes a reconstructor and a multi-core controller consisting of two reconstruction cores; based on the multi-core controller, one reconstruction core in the reconstructor is controlled to read the odd-row parsing information of the target tile from the first storage space in the target DDR corresponding to the video decoding core, and to perform reconstruction processing on the odd-row parsing information to obtain the odd-row reconstruction result of the target tile; at the same time, based on the multi-core controller, another reconstruction core in the reconstructor is controlled to read the even-row parsing information of the target tile from the second storage space in the target DDR, and to perform reconstruction processing on the even-row parsing information to obtain the even-row reconstruction result of the target tile; at the hardware level, through the scheduling of the multi-core controller, the two reconstruction cores in the reconstructor can be effectively controlled to decode in parallel, giving full play to the decoding performance of the two reconstruction cores, thereby effectively improving the decoding performance of the video decoding core.

[0099] Figure 8 A flowchart of a video decoding method according to an embodiment of the present disclosure is shown. The method is applied to Figure 1 The video decoding core shown in FIG. 1 includes a reconstructor and a multi-core controller, wherein the reconstructor includes multiple reconstruction cores. Figure 8 As shown, the method includes:

[0100] In step S81, based on the multi-core controller, each reconstruction core in the reconstructor is controlled to read the corresponding row parsing information of the target block (Tile) from the corresponding storage space in the target DDR corresponding to the video decoding core, wherein the target block (Tile) is an image block to be decoded in a video frame in the video decoding task.

[0101] In step S82, based on the multi-core controller, multiple reconstruction cores in the reconstructor are controlled to parse the corresponding row information of the read target tile (Tile), and perform reconstruction processing in parallel to obtain the reconstruction result of the target tile (Tile).

[0102] Apply the above Figure 2 For the specific process of video decoding performed by the video decoding core of the embodiment shown in the figure, please refer to the above Figures 2 to 7 The detailed description of the related embodiments shown is not repeated here.

[0103] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.

[0104] In addition, the present disclosure also provides electronic devices, computer-readable storage media, and programs, all of which can be used to implement any method provided by the present disclosure. The corresponding technical solutions and descriptions are referred to the corresponding records in the method part and will not be repeated here.

[0105] This method has a specific technical connection with the internal structure of the computer system, and can solve the technical problem of how to improve the hardware computing efficiency or execution effect (including reducing the amount of data storage, reducing the amount of data transmission, increasing the hardware processing speed, etc.), thereby obtaining the technical effect of improving the internal performance of the computer system in accordance with the laws of nature.

[0106] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0107] The embodiment of the present disclosure also provides a computer-readable storage medium on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0108] An embodiment of the present disclosure further proposes an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0109] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0110] The electronic device may be provided as a terminal, a server, or a device in other forms.

[0111] Fig. 9 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. Fig. 9 , the electronic device 1900 can be provided as a server or a terminal device. Fig. 9 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0112] The electronic device 1900 may also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958. The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as a Microsoft Server operating system (Windows Server 2003). TM ), Apple's graphical user interface operating system (Mac OS X TM ), a multi-user, multi-process computer operating system (Unix TM ), a free and open source Unix-like operating system (Linux TM ), an open source Unix-like operating system (FreeBSD TM ) or similar.

[0113] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0114] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0115] Computer-readable storage media can be a tangible device that can hold and store instructions used by an instruction execution device. Computer-readable storage media can be, for example, (but not limited to) an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive lists) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a convex structure in a groove on which instructions are stored, and any suitable combination thereof. The computer-readable storage media used here is not interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (for example, a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0116] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0117] The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect through the Internet). In some embodiments, by using the state information of the computer-readable program instructions to personalize an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit may execute the computer-readable program instructions, thereby implementing various aspects of the present disclosure.

[0118] Various aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of boxes in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0119] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0120] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0121] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0122] The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK) and the like.

[0123] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

[0124] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0125] If the technical solution of this application involves personal information, the product using the technical solution of this application has clearly informed the personal information processing rules and obtained the individual's voluntary consent before processing the personal information. If the technical solution of this application involves sensitive personal information, the product using the technical solution of this application has obtained the individual's separate consent before processing the sensitive personal information, and at the same time meets the "explicit consent" requirement. For example, on personal information collection devices such as cameras, clear and prominent signs are set to inform that the personal information collection scope has been entered and personal information will be collected. If the individual voluntarily enters the collection scope, it is deemed that he or she agrees to the collection of his or her personal information; or on the device that processes personal information, the personal information processing rules are notified by obvious signs / information, and the individual's authorization is obtained through pop-up information or by asking the individual to upload his or her personal information; among them, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed.

[0126] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A video decoding kernel, characterized in that: include: A reconstructor, a multi-core controller, wherein the reconstructor includes a plurality of reconstruction cores; The multi-core controller is used to control each reconstruction core in the reconstructor to read corresponding row parsing information of a target block from a corresponding storage space in a target DDR corresponding to the video decoding core, wherein the target block is an image block to be decoded in a video frame in a video decoding task, and the target block is a target Tile; The multi-core controller is used to control the multiple reconstruction cores in the reconstructor to read the corresponding row parsing information of the target block, perform reconstruction processing in parallel, and obtain the reconstruction result of the target block; The multi-core controller is further configured to start executing the reconstruction process of the next Tile after determining that the reconstruction process of the target Tile is completed.

2. The video decoding core according to claim 1, characterized in that The video decoding core includes: a parser and a decoding controller; The decoding controller is used to receive the video decoding task and control the parser to perform parsing processing on each block in the i-th video frame in the video decoding task, where i is a positive integer; The decoding controller is used to control the reconstructor to perform reconstruction processing on each block in the j-th video frame in the video decoding task, wherein the j-th video frame has been parsed and j is a positive integer.

3. The video decoding core according to claim 1, characterized in that: The video decoding core includes: a parser and a decoding controller; The decoding controller is used to receive the video decoding task and control the parser to perform parsing processing on the nth block in the mth video frame in the video decoding task, where m and n are positive integers; The decoding controller is used to control the reconstructor to perform reconstruction processing on the k-th block in the m-th video frame, wherein the k-th block has been parsed and k is a positive integer.

4. The video decoding core according to claim 1, characterized in that: Each block in the video decoding task includes a plurality of decoding processing unit rows; the video decoding core includes: a parser, a decoding controller; The decoding controller is used to determine, for each block in the video decoding task, a corresponding storage space of each decoding processing unit row of the block in the target DDR; The parser is used to parse each decoding processing unit row of the block in turn, and store the row parsing information obtained by parsing each decoding processing unit row in the corresponding storage space of the decoding processing unit row in the target DDR.

5. The video decoding core according to claim 1, characterized in that: Each block in the video decoding task includes a plurality of decoding processing unit rows; the video decoding core includes: a parser, a decoding controller; the reconstructor includes two reconstruction cores; The decoding controller is used to determine, for each block in the video decoding task, that the odd-numbered decoding processing unit rows of the block correspond to the first storage space in the target DDR, and to determine that the even-numbered decoding processing unit rows of the block correspond to the second storage space in the target DDR; The parser is used to parse each decoding processing unit row of the block in turn, and store the odd row parsing information obtained by parsing the odd row decoding processing unit rows of the block in the first storage space, and store the even row parsing information obtained by parsing the even row decoding processing unit rows of the block in the second storage space.

6. The video decoding core according to claim 5, characterized in that: The multi-core controller is used to control a reconstruction core in the reconstructor to read the odd-numbered row parsing information of the target block from the first storage space, and perform reconstruction processing on the odd-numbered row parsing information to obtain the odd-numbered row reconstruction result of the target block; The multi-core controller is used to control another reconstruction core in the reconstructor to read the even-row parsing information of the target block from the second storage space, and perform reconstruction processing on the even-row parsing information to obtain the even-row reconstruction result of the target block.

7. The video decoding core according to claim 1, characterized in that: The target block includes N decoding processing unit rows, where N is a positive integer; the reconstructor includes two reconstruction kernels: a first reconstruction kernel and a second reconstruction kernel; The multi-core controller is used to control the first reconstruction core to sequentially perform reconstruction processing on odd-numbered decoding processing unit rows included in the target block; The multi-core controller is used to control the second reconstruction core to sequentially perform reconstruction processing on even-numbered decoding processing unit rows included in the target block.

8. The video decoding core according to claim 7, characterized in that: N is an even number; The multi-core controller is used to determine that after the first reconstruction kernel completes the reconstruction processing of the N-1th decoding processing unit row included in the target block, and determines that after the second reconstruction kernel completes the reconstruction processing of the Nth decoding processing unit row included in the target block, it starts the reconstruction processing of the next block after the target block.

9. The video decoding core according to claim 7, characterized in that: N is an odd number; The multi-core controller is used to determine that after the second reconstruction core completes the reconstruction process on the N-1th decoding processing unit row included in the target block, the reconstruction process on the next block after the target block is started.

10. The video decoding core according to claim 1, characterized in that: The target block includes a plurality of decoding processing unit rows, each decoding processing unit row includes a plurality of decoding processing units; The multi-core controller is used to control a reconstruction core in the reconstructor that is in an idle state to start performing reconstruction processing on the p+1th decoding processing unit row of the target block when it is determined that a reconstruction core in the reconstructor has completed reconstruction processing on the first decoding processing unit in the pth decoding processing unit row of the target block, and when it is determined that there is at least one reconstruction core in an idle state in the reconstructor, where p is a positive integer.

11. The video decoding core according to claim 10, characterized in that: For any reconstruction kernel, after the reconstruction kernel performs reconstruction processing on a decoding processing unit, reference data corresponding to the decoding processing unit is determined according to the reconstruction result, and the reference data corresponding to the decoding processing unit is stored in a preset storage space.

12. The video decoding core according to claim 11, characterized in that: The preset storage space is located in the internal memory of the video decoding core, or the preset storage space is located in the target DDR.

13. A video decoding method, characterized in that: The method is applied to a video decoding core, the video decoding core includes: a reconstructor, a multi-core controller, wherein the reconstructor includes a plurality of reconstruction cores; the method includes: Based on the multi-core controller, each reconstruction core in the reconstructor is controlled to read corresponding row parsing information of a target block from a corresponding storage space in a target DDR corresponding to the video decoding core, wherein the target block is an image block to be decoded in a video frame in a video decoding task, and the target block is a target Tile; Based on the multi-core controller, control the multiple reconstruction cores in the reconstructor to read the corresponding row parsing information of the target block, perform reconstruction processing in parallel, and obtain the reconstruction result of the target block; The method further comprises: After determining that the reconstruction process of the target Tile is completed, based on the multi-core controller, the reconstruction process of the next Tile after the target Tile is started.

14. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; Wherein, the processor is configured to call the instructions stored in the memory to execute the method of claim 13.

15. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method of claim 13 is implemented.

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