A video processing system and control method based on single-port SDRAM pseudo ping-pong read-write

Abstract

This application discloses a video processing system and control method based on pseudo-ping-pong read / write of single-port SDRAM. The system includes a data stream input device, a software layer, a hardware layer, a video output display device, and an infrared remote control device. The control method includes: acquiring the video to be played and control parameters; performing read / write data preprocessing on the video to be played based on pseudo-ping-pong operation of the single-port SDRAM controller and in combination with the control parameters, and outputting the preprocessed video for playback; adjusting the display on the video output display device to display the preprocessed video for playback. The embodiments of this application can continuously process video frame data and complete high-quality video processing within a small storage space. This application can be widely applied in the field of digital image processing technology.

Description

Technical Field

[0001] This application relates to the field of digital image processing technology, and in particular to a video processing system and control method based on single-port SDRAM pseudo ping-pong read / write. Background Technology

[0002] With the rapid development of multimedia devices, video processing systems are playing an increasingly important role in various electronic products. Modern video processing systems typically need to process large amounts of data, which places higher demands on the system's memory bandwidth, data transfer efficiency, and processor computing power. In the field of video processing, the use of System-on-Chip (SoC) has become the mainstream trend. SoC integrates a processor, memory controller, I / O interfaces, and other functional modules, providing not only high-performance computing capabilities but also effectively reducing system power consumption and cost.

[0003] In relevant video processing architectures, video data processing and management typically rely on a computer system (PC). The computer acts as the host computer, undertaking the main computational tasks and transmitting the processed data to the display device. However, this approach requires high-performance computer hardware, increasing system complexity and cost, and is unsuitable for embedded devices or resource-constrained environments.

[0004] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0005] The main objective of this application is to propose a video processing system and control method based on single-port SDRAM pseudo-ping-pong read / write, which can continuously process video frame data and complete high-quality video processing in a small storage space.

[0006] To achieve the above objectives, one aspect of this application proposes a video processing system based on single-port SDRAM pseudo-ping-pong read / write. The system includes a data stream input device, a software layer, a hardware layer, a video output display device, and an infrared remote control device. The output terminal of the data stream input device is connected to a first input terminal of the hardware layer, the output terminal of the hardware layer is connected to the input terminal of the video output display device, the first output terminal of the software layer is connected to the input terminal of the data stream input device, the second output terminal of the software layer is connected to a second input terminal of the hardware layer, and the third output terminal of the software layer is connected to the input terminal of the infrared remote control device, wherein:

[0007] The data stream input device is used to provide the video to be played.

[0008] The software layer is used to generate control parameters;

[0009] The hardware layer is used for pseudo-ping-pong operation based on a single-port SDRAM controller, and combines the control parameters to perform read and write data preprocessing on the video to be played, and outputs the preprocessed video for playback.

[0010] The video output display device is used to display the preprocessed playback video;

[0011] The infrared remote control device is used to adjust the display of the video output display device.

[0012] In some embodiments, the software layer includes an ARM processor debugging module, an AHB bus, an input / output module, an image processing algorithm module, an instruction bus, a data bus, an AHB-APB conversion module, a serial communication module, and a host computer module. The ARM processor debugging module bridges the input / output module, the image processing algorithm module, the instruction bus, the data bus, and the AHB-APB conversion module via the AHB bus. The AHB-APB conversion module is connected to the host computer module via the serial communication module. The host computer module has a feedback connection with the ARM processor debugging module.

[0013] In some embodiments, the hardware layer includes a processing unit, a single-port SDRAM controller, and a VGA module. The output of the processing unit is connected to the input of the single-port SDRAM controller, and the output of the single-port SDRAM controller is connected to the input of the VGA module.

[0014] The processing unit is used to perform image data preprocessing on the video to be played, so as to obtain a pre-processed video for playback.

[0015] The single-port SDRAM controller is used to perform read / write pseudo-ping-pong operations on the pre-processed playback video and output the pre-processed playback video.

[0016] The VGA module is used to transmit the preprocessed playback video to the video output display device.

[0017] In some embodiments, the single-port SDRAM controller includes an input FIFO port, an SDRAM arbitration module, an SDRAM initialization module, an SDRAM write module, an SDRAM read module, an SDRAM refresh module, and an output FIFO port. The input FIFO port is interconnected with the SDRAM arbitration module. The SDRAM arbitration module is interconnected with the SDRAM initialization module, the SDRAM write module, the SDRAM read module, and the SDRAM refresh module, respectively. The output terminal of the SDRAM data exchange module is connected to the input terminal of the output FIFO port. The output FIFO port is interconnected with the SDRAM arbitration module.

[0018] The input FIFO port is used to characterize the current data volume of the single-port SDRAM controller to prevent the writing of invalid data;

[0019] The output FIFO port is used to characterize the current number of available positions of the single-port SDRAM controller to prevent data loss.

[0020] The SDRAM initialization module is used to initialize the single-port SDRAM controller;

[0021] The SDRAM write module is used to control the single-port SDRAM controller to perform data write operations;

[0022] The SDRAM read module is used to control the single-port SDRAM controller to perform data read operations;

[0023] The SDRAM refresh module is used to refresh the internal storage data of the single-port SDRAM controller.

[0024] The SDRAM arbitration module is used to determine the priority order of operations performed by the single-port SDRAM controller.

[0025] To achieve the above objectives, another aspect of this application proposes a control method for a video processing system based on single-port SDRAM pseudo-ping-pong read / write, the control method comprising the following steps:

[0026] Obtain the video to be played and control parameters;

[0027] Based on the pseudo-ping-pong operation of the single-port SDRAM controller, and combined with the control parameters, the video to be played is preprocessed for reading and writing data, and the preprocessed video is output.

[0028] Adjust the display settings of the video output display device to display the preprocessed video.

[0029] In some embodiments, the pseudo-ping-pong operation based on a single-port SDRAM controller, combined with the control parameters, performs read / write data preprocessing on the video to be played, and outputs the preprocessed playback video, including:

[0030] The video to be played is preprocessed according to the control parameters to obtain a pre-processed video for playback.

[0031] Based on a single-port SDRAM controller, the pre-processed playback video is processed by read / write pseudo-ping-pong operation, and the pre-processed playback video is output.

[0032] The preprocessed playback video is transmitted to the video output display device.

[0033] In some embodiments, the step of performing read / write pseudo-ping-pong operation processing on the pre-processed playback video based on a single-port SDRAM controller and outputting the pre-processed playback video includes:

[0034] The single-port SDRAM controller is initialized to obtain a single-port SDRAM controller that enters a standby state.

[0035] Based on burst transmission mode, the standby single-port SDRAM controller performs read / write pseudo-ping-pong operations on the pre-processed playback video and outputs the pre-processed playback video.

[0036] In some embodiments, initializing the single-port SDRAM controller to obtain a single-port SDRAM controller entering a standby state includes:

[0037] The single-port SDRAM controller is initialized to obtain the initialized single-port SDRAM controller.

[0038] The initialized single-port SDRAM controller is precharged to obtain a precharged single-port SDRAM controller.

[0039] The pre-charged single-port SDRAM controller is then automatically refreshed and enters execution mode sequentially to obtain the single-port SDRAM controller that has entered the standby state.

[0040] In some embodiments, the read / write pseudo-ping-pong operation processing includes simultaneously performing read / write request operations, read request operations, and write request operations, wherein:

[0041] For the read / write request operation, the single-port SDRAM controller prioritizes the write request operation, and then executes the read request operation when the pointer of the write request operation reaches the bottom of the bank.

[0042] For the read request operation, the single-port SDRAM controller determines whether the read pointer has reached the bottom of the bank. If the read pointer has reached the bottom of the bank but the write pointer has not, the single-port SDRAM controller will repeatedly read the current frame data. If both the read pointer and the write pointer have reached the bottom of the bank, the single-port SDRAM controller will perform a bank switching operation and execute the read request operation to read the next frame image data.

[0043] For the write request operation, the single-port SDRAM controller determines whether the write pointer has reached the bottom of the bank. If the write pointer has reached the bottom of the bank but the read pointer has not, the single-port SDRAM controller sends an interrupt command to pause data writing. If both the read pointer and the write pointer have reached the bottom of the bank, the single-port SDRAM controller will perform a bank switching operation and execute the write request operation to write the next frame of image data.

[0044] In some embodiments, the method further includes setting a priority order for data read and write operations, wherein automatic refresh is processed with the first priority, write request operations are processed with the second priority, and read request operations are processed with the third priority.

[0045] The embodiments of this application include at least the following beneficial effects: This application provides a video processing system and control method based on single-port SDRAM pseudo ping-pong read / write. This scheme obtains the video to be played and control parameters, further performs read / write data preprocessing on the video to be played based on the pseudo ping-pong operation of the single-port SDRAM controller, and combines the control parameters. The video processing is fully implemented on the FPGA without the need for a host computer. The efficient ping-pong operation is achieved through the single-port SDRAM controller, ensuring that the processor can continuously process video frame data. This reduces the circuit complexity and cost of the design while avoiding image tearing and video frame loss. Through the efficient use of single-port SDRAM and the optimized pseudo ping-pong operation, the maximum utilization of storage resources is achieved, enabling high-quality video processing to be completed in a small storage space. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the structure of a video processing system based on single-port SDRAM pseudo-ping-pong read / write provided in an embodiment of this application;

[0047] Figure 2 This is a flowchart illustrating the steps of a control method for a video processing system based on single-port SDRAM pseudo-ping-pong read / write provided in an embodiment of this application.

[0048] Figure 3This is a schematic diagram of the structure of a single-port SDRAM controller provided in an embodiment of this application;

[0049] Figure 4 This is a schematic diagram of the memory strategy of a single-port SDRAM controller provided in an embodiment of this application. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of systems and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0051] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0052] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0054] Reference Figure 1 , Figure 1 A structural diagram of a video processing system based on single-port SDRAM pseudo-ping-pong read / write provided in an embodiment of the present invention is shown below. Figure 1The system includes a data stream input device, a software layer, a hardware layer, a video output display device, and an infrared remote control device. The output terminal of the data stream input device is connected to the first input terminal of the hardware layer, the output terminal of the hardware layer is connected to the input terminal of the video output display device, the first output terminal of the software layer is connected to the input terminal of the data stream input device, the second output terminal of the software layer is connected to the second input terminal of the hardware layer, and the third output terminal of the software layer is connected to the input terminal of the infrared remote control device.

[0055] The data stream input device is used to provide the video to be played;

[0056] In this embodiment, an SD card is used to store the video to be played in order to simulate data stream input; in other embodiments, other data stream input methods may be used.

[0057] The software layer is used to generate control parameters;

[0058] Specifically, the software layer includes an ARM processor debugging module, an AHB bus, an input / output module, an image processing algorithm module, an instruction bus, a data bus, an AHB-APB conversion module, a serial communication module, and a host computer module. The ARM processor debugging module bridges the input / output module, the image processing algorithm module, the instruction bus, the data bus, and the AHB-APB conversion module via the AHB bus. The AHB-APB conversion module is connected to the host computer module via the serial communication module, and the host computer module has a feedback connection with the ARM processor debugging module.

[0059] In this embodiment, the software layer system is based on the ARM Cortex-M0 soft core and bridges various peripheral modules such as GPIO (GPIO, ISP, image processing algorithm module), DTCM (data bus), and ITCM (instruction bus) via the AHB bus. GPIO connects to a running LED, and software programs written and generated using the KeikkVision tool control the running LED, enabling online real-time debugging of the software program running on the SoC to confirm correct program execution. ISP connects to the video data processing module, performing white balance, sharpening, saturation adjustment, filtering, and noise reduction on video data to restore a more realistic and user-relevant video scene. ITCM is the instruction transmission bus in the Cortex core, and DTCM is the data transmission bus in the Cortex core. The AHB bus bridges to the APB, and the APB bus transmits data to the PC via a UART serial communication interface. It is important to note that the PC is only used during debugging and troubleshooting; after the device is debugged, the overall execution flow does not require PC intervention.

[0060] The hardware layer is used for pseudo-ping-pong operation based on a single-port SDRAM controller, and combines control parameters to perform read and write data preprocessing on the video to be played, and outputs the preprocessed video to be played.

[0061] Specifically, the hardware layer includes a processing unit, a single-port SDRAM controller, and a VGA module. The output of the processing unit is connected to the input of the single-port SDRAM controller, and the output of the single-port SDRAM controller is connected to the input of the VGA module. The processing unit is used to preprocess the image data of the video to be played, obtaining a preliminary preprocessed video for playback. The single-port SDRAM controller is used to perform read / write pseudo-ping-pong operations on the preliminary preprocessed video for playback and output the preprocessed video for playback. The VGA module is used to transmit the preprocessed video for playback to a video output display device.

[0062] Furthermore, such as Figure 3 As shown, the single-port SDRAM controller includes an input FIFO port, an SDRAM arbitration module, an SDRAM initialization module, an SDRAM write module, an SDRAM read module, an SDRAM refresh module, and an output FIFO port. The input FIFO port is interconnected with the SDRAM arbitration module. The SDRAM arbitration module is interconnected with the SDRAM initialization module, the SDRAM write module, the SDRAM read module, and the SDRAM refresh module, respectively. The output terminal of the SDRAM data exchange module is connected to the input terminal of the output FIFO port, and the output FIFO port is interconnected with the SDRAM arbitration module.

[0063] The input FIFO port is used to characterize the current data volume of the single-port SDRAM controller to prevent the writing of invalid data.

[0064] Specifically, the input FIFO port is placed between the SD card and the SDRAM controller as a buffer for cross-clock domain transmission. At the same time, a Kmost_empty_fK ag is provided to indicate whether the current data volume of the FIFO is greater than 256. If it is greater, it is pulled low, allowing the SDRAM controller to request data to write into the single-port SDRAM, effectively preventing the writing of invalid data.

[0065] The output FIFO port is used to indicate the current number of available positions of the single-port SDRAM controller to prevent data loss;

[0066] Specifically, the output FIFO port is placed between the SDRAM controller and VGA as a buffer for cross-clock domain transmission. At the same time, it provides a Kmost_fu K K_f Kag to indicate whether the number of currently free positions in the FIFO is greater than 256. If it is greater, it is pulled low, allowing the SDRAM controller to output the data stored in the single-port SDRAM to the VGA for display. This effectively prevents the output data from being lost due to insufficient FIFO capacity and ensures data validity.

[0067] The SDRAM initialization module is used to initialize the single-port SDRAM controller;

[0068] Specifically, the SDRAM initialization module is responsible for configuring some register parameters inside the SDRAM, and completing the power-on and pre-charge operations to prepare for the next step.

[0069] The SDRAM write module is used to control the single-port SDRAM controller to perform data write operations.

[0070] Specifically, the read operation of the single-port SDRAM is initiated, using burst transmission mode to read 256 data items at a time.

[0071] The SDRAM read module is used to control the single-port SDRAM controller to perform data read operations;

[0072] Specifically, the read operation of the single-port SDRAM is initiated, using burst transmission mode, writing 256 data entries at a time.

[0073] The SDRAM refresh module is used to refresh the internal storage data of a single-port SDRAM controller.

[0074] Specifically, because SDRAM requires periodic refreshes to maintain data validity, the controller must effectively arbitrate between read / write operations and data refresh. According to the official SDRAM manual, the refresh rate must be at least 4096 times / 64ms. The refresh module is responsible for refreshing the SDRAM, updating the current data according to the stored high and low bits, maintaining the data unchanged, and ensuring the correctness of the data stored in the SDRAM.

[0075] The SDRAM arbitration module is used to determine the priority order of operations performed by a single-port SDRAM controller.

[0076] Specifically, this module ensures timely data refresh. Based on time counting, it sets refresh commands to the highest priority, prioritizing the 4096 refreshes / 64ms refresh rate requirement of a single-port SDRAM. Only after the refresh operation is completed will the system allow other read and write operations. This design effectively prevents data loss due to power failure. When processing multiple requests, the arbitration module selects according to a predetermined priority rule. If refresh, read, and write requests are issued simultaneously, the arbitration module will process them in the order of refresh > write > read. This priority setting ensures data integrity and validity: refresh operations are performed first to protect the data, then write operations are performed to update the stored content, and finally read operations are performed to ensure the accuracy of the system output.

[0077] These modules work together to ensure that a single-port SDRAM can perform data storage and retrieval operations stably and efficiently.

[0078] In this embodiment, the hardware layer includes a complete DMA (Direct Memory Access) path. All data processing is implemented in the hardware layer without going through the processor, saving processor resources and improving data processing efficiency. This includes a series of ISP modules, which connect to the ISP configuration module in the software layer to obtain specific parameters. Data processing is completed in the Processing Module in the hardware layer, implementing rich ISP functions such as white balance, sharpening, saturation adjustment, filtering, and noise reduction. The hardware layer uses single-port SDRAM to implement pseudo-ping-pong operation to prevent image tearing and video frame dropping. A FIFO is placed before and after the single-port SDRAM as a cross-clock domain data processing buffer unit to ensure data validity.

[0079] The video output display device is used to display the pre-processed video for playback;

[0080] In this embodiment, a VGA screen is used to output and display the processed video. In other embodiments, other data display devices may be used.

[0081] The infrared remote control device is used to adjust the display of the video output display device.

[0082] In this embodiment, the infrared remote control device is connected to the LCD screen, providing the user with a screen to display debugging input parameter information, making the user's operation more flexible and convenient.

[0083] Please see Figure 2 This application also provides a control method for a video processing system based on single-port SDRAM pseudo ping-pong read / write, which can realize the above-mentioned video processing system based on single-port SDRAM pseudo ping-pong read / write. The control method includes:

[0084] S100: Obtain the video to be played and control parameters;

[0085] S200, based on the pseudo-ping-pong operation of a single-port SDRAM controller, and combined with control parameters, performs read and write data preprocessing on the video to be played, and outputs the preprocessed video for playback;

[0086] It should be noted that in some embodiments, step S200 may include: S210, performing image data preprocessing on the video to be played according to control parameters to obtain a preliminary preprocessed video; S220, performing read / write pseudo-ping-pong operation processing on the preliminary preprocessed video based on a single-port SDRAM controller, and outputting the preprocessed video; S230, transmitting the preprocessed video to a video output display device.

[0087] In some specific embodiments, the single-port SDRAM controller is initialized to obtain a single-port SDRAM controller in standby mode; based on burst transmission mode, the standby single-port SDRAM controller performs read and write pseudo ping-pong operation processing on the pre-processed playback video and outputs the pre-processed playback video.

[0088] The initialization process involves: initializing the single-port SDRAM controller to obtain an initialized single-port SDRAM controller; precharging the initialized single-port SDRAM controller to obtain a precharged single-port SDRAM controller; and then performing automatic refresh and execution mode entry processes on the precharged single-port SDRAM controller to obtain a single-port SDRAM controller in standby mode.

[0089] In this embodiment, upon system startup, the SDRAM controller first enters an initialization state machine and executes a series of configuration operations, including timing parameter settings and mode register configuration. The initialization process is fundamental for subsequent operations, ensuring the SDRAM is in a stable operating state. After initialization, the controller performs a pre-charge operation to release the charge in all banks, ensuring all SDRAM memory cells are in a unified state, preparing for subsequent operations. After pre-charging, the SDRAM controller performs two automatic refresh operations. Due to its DRAM characteristics, SDRAM requires periodic refreshes to maintain the validity of stored data. The automatic refresh operation refreshes all memory cells according to a predetermined refresh cycle to prevent data loss due to charge leakage. During subsequent read / write operations, the SDRAM still needs to refresh the already stored data to prevent data loss. After refresh, the controller enters a standby state, waiting for external read / write commands. At this time, the SDRAM is ready to receive and execute data read / write operations. Simultaneously, if the automatic refresh module issues a refresh request, the execution mode determines whether to execute it.

[0090] Furthermore, upon receiving a read or write command, the single-port SDRAM controller executes the corresponding operation based on the command type. Since single-port SDRAM uses a shared data line, read and write operations cannot be performed simultaneously. The controller selects the appropriate operating mode and executes data transmission based on the current command type. Specifically, single-port SDRAM read and write operations both employ burst transmission mode, which significantly improves transmission efficiency. Specifically, after sending an address once, the single-port SDRAM continuously transmits data to 256 addresses, thereby reducing latency caused by command sending and response. Once the transmission operation is complete, the single-port SDRAM controller stops using the data line and waits for the next command (read, write, or refresh). At this point, the controller re-enters standby mode or performs other operations as needed.

[0091] In summary, the overall working logic of SDRAM is as follows: initialization, precharge, automatic refresh, execution mode (waiting for read / write commands), read or write (shared data line, cannot be performed simultaneously), and transmission stop. Since SDRAM needs to be refreshed periodically to maintain data validity, an arbitration module is required between read, write, and refresh operations to ensure the validity of periodic data refreshes. The refresh rate is at least 4096 times / 64ms. Therefore, the arbitration module is set to prioritize refresh commands based on time counting. Read and write operations can only be performed after the refresh command is satisfied, preventing data loss due to power failure. Simultaneously, if refresh, read, and write requests are issued simultaneously, the priority is: refresh > write > read, preventing data loss. Furthermore, a significant portion of the limitation in SDRAM read / write speed comes from the repeated sending and responding of commands. Therefore, this design uses burst transmission for both SDRAM read and write operations, greatly improving transmission efficiency. After issuing an address to SDRAM, 256 consecutive addresses in the SDRAM are read or written using burst transmission, avoiding the latency issues caused by repeated command sending and responses. To enable burst transfer for reading and writing, this design introduces two FIFOs as buffers for reading and writing, respectively. Since a burst transfer requires transmitting 256 data bits at a time, FIFOs are needed to prevent data loss. Specifically, the `a Kmost_empty_f Kag` for writing to the FIFO and the `a Kmost_fu K K_f Kag` for reading from the FIFO serve as control signals for burst transfers. A burst transfer can only be used to transfer 256 data bits to SDRAM when there are at least 256 data bits in the FIFO; conversely, a burst transfer can only be used to read 256 data bits from SDRAM to the FIFO when there are at least 256 empty data bits in the FIFO, thus ensuring data validity.

[0092] Furthermore, it should be noted that the biggest problem with single-port SDRAM is that simultaneous reading and writing are impossible due to the shared read and write port. The common solution is to use dual-port devices, separating the read and write ports for control, allowing for simultaneous read and write operations. However, this increases circuit design complexity, cost, and power consumption. This invention implements pseudo-ping-pong operation using single-port SDRAM by employing dual pointers and dividing the memory into two blocks (one for reading and one for writing). This method not only reduces cost but also decreases the need for large-capacity storage, a common requirement in many modern systems. By using single-port SDRAM and an efficient control strategy, this design significantly reduces cost and storage space usage while maintaining performance.

[0093] Single-port SDRAM read / write operations pose a significant challenge for VGA video reading because VGA needs to continuously read data at a certain frequency. This means that if SDRAM is in a write state for an extended period, VGA will not be able to read data, leading to black screens and image tearing. To meet read speed requirements, this design executes read / write requests line by line. That is, after a burst of reading or writing one line (256 data points), the next SDRAM read / write request is initiated, thus satisfying the VGA's video data reading needs. Another issue arises because VGA read speeds are faster than SD card read speeds. When the video display module's data read / write speed requirement exceeds the data stream input module's capacity, VGA needs to repeatedly read the same frame to prevent image tearing until the next frame is loaded. Therefore, an arbitration module is needed to determine SDRAM memory usage, i.e., when to read or write.

[0094] Specifically, it should be noted that, such as Figure 4 As shown, the read / write pseudo-ping-pong operation processing includes operations that simultaneously perform read / write request operations, read request operations, and write request operations.

[0095] For read and write request operations, the single-port SDRAM controller prioritizes write request operations. When the pointer of the write request operation reaches the bottom of the bank, the read request operation is then executed.

[0096] Specifically, when read and write requests occur simultaneously, the system prioritizes write requests. After a write operation is completed, read requests are processed immediately. This prioritization ensures that new image data is written promptly, preventing blank displays in subsequent frames. When both the read and write pointers reach the bottom of their respective banks, the system immediately switches banks to continue the next round of read and write operations. If the write pointer reaches the bottom before the read pointer, the write operation is temporarily interrupted, prioritizing the reading of the current frame to prevent the VGA monitor from reading incomplete image data. Conversely, if the read pointer reaches the bottom before the write pointer, the system repeatedly reads the current frame until the write operation is complete. This design ensures that image display is not interrupted or malfunctions even if the write operation is not yet complete.

[0097] For read request operations, the single-port SDRAM controller determines whether the read pointer has reached the bottom of the bank. If the read pointer has reached the bottom of the bank but the write pointer has not, the single-port SDRAM controller will repeatedly read the current frame data. If both the read pointer and the write pointer have reached the bottom of the bank, the single-port SDRAM controller will perform a bank switching operation and execute a read request operation to read the next frame image data.

[0098] Specifically, in the case of read requests only, when the system receives only a read request, it first checks if the read pointer has reached the last line of the bank. If the read pointer has reached the bottom but the write pointer has not, the system will repeatedly read the current frame data. This is to meet the continuity requirements of VGA displays and avoid image tearing or flickering. If the write pointer has also reached the bottom at this time, the system will perform a bank switching operation and then continue reading the next frame of image data. If the read pointer has not yet reached the last line, the system continues to read data line by line until the read pointer reaches the bottom.

[0099] For write request operations, the single-port SDRAM controller determines whether the write pointer has reached the bottom of the bank. If the write pointer has reached the bottom of the bank but the read pointer has not, the single-port SDRAM controller sends an interrupt command to pause data writing. If both the read pointer and the write pointer have reached the bottom of the bank, the single-port SDRAM controller will perform a bank switching operation and execute the write request operation to write the next frame of image data.

[0100] Specifically, in the case of write requests only, the system's focus is on ensuring that write operations do not overwrite data that has not yet been read. The system first checks if the write pointer has reached the last row of the bank. If the write pointer has reached the bottom, the system further checks the position of the read pointer. If the read pointer has also reached the bottom, the system performs a bank switching operation to allow simultaneous read and write operations. However, if the read pointer has not yet reached the bottom, it means there is still unread data, and continuing to write at this point could overwrite the data. To prevent this, the system sends an interrupt command to the SD card, pausing data writing until the read operation is complete. If the write pointer has not yet reached the bottom, the system continues normal read and write operations until the switching condition is met.

[0101] In summary, a single-port SDRAM was used, divided into two separate banks for reading and writing, with each bank serving as an independent storage unit to implement pseudo-ping-pong operation. The core purpose of this operation is to efficiently and stably process and output video data even when read and write operations cannot occur simultaneously, thus avoiding instability, tearing, and dropped frames in image display. The specific pseudo-ping-pong operation method for single-port SDRAM is as follows: two banks form the read and write storage units, respectively, used to store a complete frame of image data. The key to the entire storage structure design is how to read previously stored data while writing new data without causing data conflicts or loss. To avoid reading empty frames, the system writes two frames of data in the initial stage. This ensures that at any given time, at least one complete image frame can be read and output to the VGA monitor, with two pointers pointing to the row numbers of the banks currently being read and written, respectively. This dual-pointer strategy allows the system to efficiently switch between different banks, thus achieving alternating read and write operations. The system only triggers bank switching when both pointers simultaneously reach the bottom of their respective banks. The advantage of this design is that, in most cases, read and write conflicts can be avoided, thereby improving the overall efficiency of the system. It should be noted that the dual-pointer mechanism requires extremely fine-grained control. Therefore, this invention adopts a line-by-line read and write operation. That is, after each line of data (256×32 bits = 8192 bits) is read or written to a single-port SDRAM, the pointer status is checked to meet the speed requirements of VGA reading and displaying video.

[0102] Therefore, the pseudo-ping-pong operation method for single-port SDRAM adopted in this embodiment of the invention can overcome the technical limitations of single-port SDRAM, which cannot be read and written simultaneously, leading to image tearing and video frame dropping. It utilizes a dual-pointer mechanism to flexibly arrange the memory of the single-port SDRAM, enabling the VGA to display video images normally and smoothly, approximating the ping-pong process of conventional dual-port SDRAM. Simultaneously, this embodiment of the invention requires minimal memory, only needing enough space to store two frames of images to complete the pseudo-ping-pong operation. Furthermore, the introduction of the burst transmission method in this invention not only reduces the number of instruction interactions between the controller and SDRAM but also significantly reduces communication latency, ensuring system stability and response speed under high data throughput conditions.

[0103] S300: Adjust the display of the video output display device to display the pre-processed playback video.

[0104] In summary, this invention innovatively employs single-port SDRAM (Synchronous Dynamic Random-Access Memory) to implement storage operations in video processing. Although single-port SDRAM can only perform read or write operations at a time, through reasonable architectural design and dual-pointer management, the embodiments of this invention can still achieve performance comparable to dual-port RAM. The SDRAM is divided into two independent banks, one for data reading and the other for data writing. The system uses two pointers to point to the current read / write position respectively, ensuring smooth video data processing without increasing storage hardware complexity. This design not only reduces the system's hardware cost but also reduces circuit complexity.

[0105] The SoC system of this invention employs a highly integrated FPGA design, which is significantly different from traditional video processing architectures that require computer systems. Our system can independently complete the tasks of reading, processing, and displaying video data without relying on any host computer's computing or storage resources. This not only simplifies the system design but also further reduces the overall cost and improves the system's reliability and stability.

[0106] In terms of system control, this invention employs infrared remote control technology, further enhancing the user experience. Infrared remote control is widely used in consumer electronics due to its low cost, ease of operation, strong anti-interference capabilities, and low energy consumption. However, traditional video processing systems typically rely on computers or other complex input devices for control, rarely using infrared remote controls. This gives our design a significant advantage in terms of ease of operation and user experience. Infrared remote control is not only easy to use but also offers good privacy because infrared signals can only be transmitted within line-of-sight, reducing the possibility of accidental interference.

[0107] Meanwhile, the system also ensures stable data transmission between different modules by designing an effective cross-clock domain transmission mechanism, thereby improving the system's reliability and performance.

[0108] The embodiments of the present invention differ from related technologies in the following ways and have the following beneficial effects:

[0109] 1) Video processing is implemented entirely on the FPGA without the need for a host computer. This design differs significantly from traditional computer systems: it adopts a highly integrated SoC architecture, integrating the processor, memory controller, video display controller, and other functional modules into a single chip, enabling it to independently complete the tasks of reading, processing, and displaying video data, thus reducing dependence on external hardware.

[0110] 2) In terms of storage management, a single-port SDRAM (Synchronous Dynamic Random-Access Memory) is used to achieve low-cost video data storage. Traditional video processing systems typically use dual-port RAM or more complex multi-port memory architectures to achieve efficient ping-pong operation, ensuring that the processor can continuously process video frame data.

[0111] 3) While memory offers superior performance, its high cost makes it difficult to apply in low-cost embedded systems. This invention addresses this issue by implementing hardware and software co-control of the ARM core, tailored to the requirements of a VGA display system, to achieve efficient management of a single-port SDRAM. Specifically, the single-port SDRAM is divided into two independent banks (slices), one for data reading and the other for data writing. Dual pointer operations are used to point to the currently read / written memory address, ensuring the continuity and synchronization of video data during read / write operations. This design not only effectively avoids image tearing and frame dropping issues in video processing but also strictly meets the timing requirements of VGA displays, while simultaneously reducing design costs.

[0112] 4) In this embodiment of the invention, the FPGA undertakes all video processing tasks, ensuring the real-time performance of data processing and the stability of the system. Compared with traditional video processing methods that require the participation of a computer system, the design of the SoC system significantly reduces hardware costs and system complexity, while improving integration and reliability.

[0113] 5) Furthermore, by designing an effective cross-clock domain transmission mechanism, the synchronization problem during data transmission between different modules was solved, ensuring data integrity and transmission efficiency. Simultaneously, the integrated infrared remote control system further enhances the system's usability, enabling remote control of the video processing system.

[0114] In summary, the embodiments of the present invention provide a high-performance, low-cost video processing solution that does not require the intervention of a host computer by using single-port SDRAM as memory in the SoC system, combined with ARM core hardware and software collaborative control, cross-clock domain data transmission mechanism and infrared remote control system, which has broad application prospects.

[0115] It is understood that the content of the above method embodiments is applicable to this system embodiment. The specific functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0116] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A video processing system based on single-port SDRAM pseudo-ping-pong read / write, characterized in that, The system includes a data stream input device, a software layer, a hardware layer, a video output display device, and an infrared remote control device. The output terminal of the data stream input device is connected to the first input terminal of the hardware layer, the output terminal of the hardware layer is connected to the input terminal of the video output display device, the first output terminal of the software layer is connected to the input terminal of the data stream input device, the second output terminal of the software layer is connected to the second input terminal of the hardware layer, and the third output terminal of the software layer is connected to the input terminal of the infrared remote control device, wherein: The data stream input device is used to provide the video to be played. The software layer is used to generate control parameters; The hardware layer is used for pseudo-ping-pong operation based on a single-port SDRAM controller, and combines the control parameters to perform read and write data preprocessing on the video to be played, and outputs the preprocessed video for playback. The video output display device is used to display the preprocessed playback video; The infrared remote control device is used to adjust the display of the video output display device; The pseudo-ping-pong operation is a read-write pseudo-ping-pong operation, which includes operations that simultaneously perform read-write request operations, read request operations, and write request operations. For simultaneous read and write request operations, the single-port SDRAM controller prioritizes the write request operation, and executes the read request operation only when the pointer of the write request operation reaches the bottom of the bank. For the read request operation, the single-port SDRAM controller determines whether the read pointer has reached the bottom of the bank. If the read pointer has reached the bottom of the bank but the write pointer has not, the single-port SDRAM controller will repeatedly read the current frame data. If both the read pointer and the write pointer have reached the bottom of the bank, the single-port SDRAM controller will perform a bank switching operation and execute the read request operation to read the next frame image data. For the write request operation, the single-port SDRAM controller determines whether the write pointer has reached the bottom of the bank. If the write pointer has reached the bottom of the bank but the read pointer has not, the single-port SDRAM controller sends an interrupt command to pause data writing. If both the read pointer and the write pointer have reached the bottom of the bank, the single-port SDRAM controller will perform a bank switching operation and execute the write request operation to write the next frame of image data.

2. The system according to claim 1, characterized in that, The software layer includes an ARM processor debugging module, an AHB bus, an input / output module, an image processing algorithm module, an instruction bus, a data bus, an AHB-APB conversion module, a serial communication module, and a host computer module. The ARM processor debugging module bridges the input / output module, the image processing algorithm module, the instruction bus, the data bus, and the AHB-APB conversion module via the AHB bus. The AHB-APB conversion module is connected to the host computer module via the serial communication module. The host computer module has a feedback connection with the ARM processor debugging module.

3. The system according to claim 1, characterized in that, The hardware layer includes a processing unit, a single-port SDRAM controller, and a VGA module. The output of the processing unit is connected to the input of the single-port SDRAM controller, and the output of the single-port SDRAM controller is connected to the input of the VGA module. The processing unit is used to perform image data preprocessing on the video to be played, so as to obtain a pre-processed video for playback. The single-port SDRAM controller is used to perform read / write pseudo-ping-pong operations on the pre-processed playback video and output the pre-processed playback video. The VGA module is used to transmit the preprocessed playback video to the video output display device.

4. The system according to claim 3, characterized in that, The single-port SDRAM controller includes an input FIFO port, an SDRAM arbitration module, an SDRAM initialization module, an SDRAM write module, an SDRAM read module, an SDRAM refresh module, and an output FIFO port. The input FIFO port is interconnected with the SDRAM arbitration module. The SDRAM arbitration module is interconnected with the SDRAM initialization module, the SDRAM write module, the SDRAM read module, and the SDRAM refresh module, respectively. The output terminal of the SDRAM data exchange module is connected to the input terminal of the output FIFO port, and the output FIFO port is interconnected with the SDRAM arbitration module. The input FIFO port is used to characterize the current data volume of the single-port SDRAM controller to prevent the writing of invalid data; The output FIFO port is used to represent the current number of available positions of the single-port SDRAM controller to prevent data loss. The SDRAM initialization module is used to initialize the single-port SDRAM controller; The SDRAM write module is used to control the single-port SDRAM controller to perform data write operations; The SDRAM read module is used to control the single-port SDRAM controller to perform data read operations; The SDRAM refresh module is used to refresh the internal storage data of the single-port SDRAM controller. The SDRAM arbitration module is used to determine the priority order of operations performed by the single-port SDRAM controller.

5. A control method for a video processing system based on single-port SDRAM pseudo-ping-pong read / write, characterized in that, The control method includes the following steps: Obtain the video to be played and control parameters; Based on the pseudo-ping-pong operation of the single-port SDRAM controller, and combined with the control parameters, the video to be played is preprocessed for reading and writing data, and the preprocessed video is output. Adjust the display of the video output display device to display the preprocessed playback video; The pseudo-ping-pong operation is a read-write pseudo-ping-pong operation, which includes operations that simultaneously perform read-write request operations, read request operations, and write request operations. For simultaneous read and write request operations, the single-port SDRAM controller prioritizes the write request operation, and executes the read request operation only when the pointer of the write request operation reaches the bottom of the bank. For the read request operation, the single-port SDRAM controller determines whether the read pointer has reached the bottom of the bank. If the read pointer has reached the bottom of the bank but the write pointer has not, the single-port SDRAM controller will repeatedly read the current frame data. If both the read pointer and the write pointer have reached the bottom of the bank, the single-port SDRAM controller will perform a bank switching operation and execute the read request operation to read the next frame image data. For the write request operation, the single-port SDRAM controller determines whether the write pointer has reached the bottom of the bank. If the write pointer has reached the bottom of the bank but the read pointer has not, the single-port SDRAM controller sends an interrupt command to pause data writing. If both the read pointer and the write pointer have reached the bottom of the bank, the single-port SDRAM controller will perform a bank switching operation and execute the write request operation to write the next frame of image data.

6. The method according to claim 5, characterized in that, The pseudo-ping-pong operation based on the single-port SDRAM controller, combined with the control parameters, performs read / write data preprocessing on the video to be played, and outputs the preprocessed playback video, including: The video to be played is preprocessed according to the control parameters to obtain a pre-processed video for playback. Based on a single-port SDRAM controller, the pre-processed playback video is processed by read / write pseudo-ping-pong operation, and the pre-processed playback video is output. The preprocessed playback video is transmitted to the video output display device.

7. The method according to claim 6, characterized in that, The single-port SDRAM controller performs read / write pseudo-ping-pong operations on the pre-processed playback video and outputs the pre-processed playback video, including: The single-port SDRAM controller is initialized to obtain a single-port SDRAM controller that enters a standby state. Based on burst transmission mode, the standby single-port SDRAM controller performs read / write pseudo-ping-pong operations on the pre-processed playback video and outputs the pre-processed playback video.

8. The method according to claim 7, characterized in that, The initialization of the single-port SDRAM controller to obtain a single-port SDRAM controller in standby mode includes: The single-port SDRAM controller is initialized to obtain the initialized single-port SDRAM controller. The initialized single-port SDRAM controller is precharged to obtain a precharged single-port SDRAM controller. The pre-charged single-port SDRAM controller is then automatically refreshed and enters execution mode sequentially to obtain the single-port SDRAM controller that has entered the standby state.

9. The method according to claim 8, characterized in that, It also includes setting a priority order for data read and write operations, wherein automatic refresh is processed with the first priority, write request operations are processed with the second priority, and read request operations are processed with the third priority.

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