Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor structure and a method for manufacturing the same. The method includes: providing a substrate structure having an array region and a peripheral region, and having a first dielectric layer with a contact plug therein; forming a second dielectric layer on the first dielectric layer; etching the second dielectric layer in the array region and the peripheral region to a preset depth to form a first trench corresponding to covering the contact plug, the preset depth being less than a height of the second dielectric layer; forming a first spin-on layer in the first trench; etching the first spin-on layer in the first trench in the peripheral region to form a second trench, and exposing the second dielectric layer at a bottom of the first trench; etching the second dielectric layer in the second trench to expose the contact plug to form a filling hole; removing the remaining first spin-on layer to form a diffusion barrier layer conformally in the first trench and the filling hole, the diffusion barrier layer being connected with the contact plug; and forming a metal layer on the diffusion barrier layer. The method of the present disclosure can improve the electrical performance and yield of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor manufacturing, and particularly relates to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] In the back-end-of-line of a DRAM (Dynamic Random Access Memory), a trench for filling a metal interconnection line is formed in a peripheral region, and then a spin-on layer with a certain thickness is formed in an active region and the peripheral region. The spin-on layer fills the trench, and the spin-on layer in the active region can act as a mask to form another shallow trench in the active region.

[0003] However, due to the large aspect ratio of the trench in the peripheral region, the spin-on layer at the bottom of the trench will be left over when the spin-on layer is removed. Thus, the metal interconnection line formed in the trench cannot be electrically connected to the underlying conductive member such as a plug, which affects the electrical performance of the semiconductor structure and reduces the yield.

[0004] The above information disclosed in the background section is only for the purpose of enhancing the understanding of the background of the present disclosure, and therefore it can include information that does not constitute the prior art known to those of ordinary skill in the art. SUMMARY

[0005] Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which can completely remove the first spin-on layer, the metal layer can be connected to the contact plug, and the electrical performance and yield of the semiconductor structure are improved.

[0006] Embodiments of the present disclosure provide a manufacturing method of a semiconductor structure, which comprises: providing a base structure, the base structure having an array region and a peripheral region, the base structure having a first dielectric layer, the first dielectric layer having a contact plug therein; forming a second dielectric layer on the first dielectric layer located in the array region and the peripheral region; etching the second dielectric layer located in the array region and the peripheral region to a preset depth to form a first trench, the first trench corresponding to covering at least part of the contact plug in a vertical direction, and the preset depth being less than the height of the second dielectric layer in the vertical direction; forming a first spin-on layer on the remaining second dielectric layer and in the first trench; etching the first spin-on layer located in the peripheral region and in the first trench to form a second trench, and exposing the second dielectric layer at the bottom of the first trench; etching the second dielectric layer in the second trench to expose the contact plug to form a filling hole; removing the remaining first spin-on layer to form a diffusion barrier layer conformally in the first trench located in the array region and the peripheral region and in the filling hole located in the peripheral region, the diffusion barrier layer being connected to the contact plug, and forming a metal layer on the diffusion barrier layer.

[0007] In some embodiments of the present disclosure, after etching the first spin-on layer located in the peripheral region and in the first trench to expose the second dielectric layer located at the bottom of the first trench, the method further comprises: forming a protective layer on the sidewall of the second trench formed by the first spin-on layer and the bottom wall of the second trench formed by the exposed second dielectric layer, the material of the protective layer being different from the material of the first spin-on layer; etching the second dielectric layer in the second trench to expose the contact plug to form a filling hole, comprising: etching to remove the protective layer, and etching the second dielectric layer to expose the contact plug to form the filling hole.

[0008] In some embodiments of the present disclosure, the filling hole is located in the middle of the first trench in the horizontal direction; and / or, the size of the second trench in the horizontal direction is smaller than the size of the first trench in the horizontal direction.

[0009] In some embodiments of the present disclosure, the size of the first trench located in the peripheral region in the horizontal direction is greater than the size of the first trench located in the array region in the horizontal direction.

[0010] In some embodiments of the present disclosure, forming a second dielectric layer on the first dielectric layer located in the array region and the peripheral region comprises: forming an isolation layer on the first dielectric layer located in the array region and the peripheral region; forming the second dielectric layer on the isolation layer; etching the second dielectric layer in the second trench to expose the contact plug to form a filling hole, comprising: etching the second dielectric layer and the isolation layer in the second trench to expose the contact plug to form the filling hole.

[0011] In some embodiments of the present disclosure, before etching the second dielectric layer located in the array region and the peripheral region to a preset depth to form a first trench, the method further comprises: forming an etching stop layer on the second dielectric layer; forming an initial spin-on layer on the etching stop layer; forming an initial mask layer on the initial spin-on layer; forming an initial photoresist layer on the initial mask layer.

[0012] In some embodiments of the present disclosure, etching the second dielectric layer located in the array region and the peripheral region to a preset depth to form a first trench comprises: forming a first trench pattern in the initial photoresist layer; sequentially transferring the first trench pattern to the initial mask layer, the initial spin-on layer, the etching stop layer and the second dielectric layer; removing the remaining initial photoresist layer, initial mask layer, initial spin-on layer and etching stop layer to form the first trench in the second dielectric layer.

[0013] In some embodiments of the present disclosure, before etching the first spin-on layer located in the peripheral region and in the first trench to form a second trench and expose the second dielectric layer located at the bottom of the first trench, the method further comprises: forming a first mask layer on the first spin-on layer; forming a first photoresist layer on the first mask layer; etching the first spin-on layer located in the peripheral region and in the first trench to form a second trench and expose the second dielectric layer located at the bottom of the first trench, comprising: forming a second trench pattern in the first photoresist layer; transferring the second trench pattern to the first mask layer; etching the first spin-on layer located in the peripheral region and in the first trench according to the second trench pattern in the first mask layer to form the second trench.

[0014] In some embodiments of the present disclosure, forming a metal layer on the diffusion barrier layer comprises: filling the metal layer in the first trench and the filling hole formed with the diffusion barrier layer; and polishing the metal layer and the diffusion barrier layer located on the second dielectric layer by using a chemical mechanical polishing process to make the surfaces of the second dielectric layer, the metal layer and the diffusion barrier layer flush.

[0015] The present disclosure also provides a semiconductor structure, comprising: a base structure having an array region and a peripheral region, the base structure having a first dielectric layer with a contact plug therein; a second dielectric layer located on the first dielectric layer in the array region and the peripheral region; in the array region and the peripheral region, the second dielectric layer has a first trench with a preset depth, the preset depth being less than the height of the second dielectric layer in the vertical direction, and in the peripheral region, the second dielectric layer located below the first trench is provided with a filling hole communicating the contact plug and the first trench; a diffusion barrier layer located in the first trench and the filling hole; and a metal layer located in the first trench and the filling hole with the diffusion barrier layer.

[0016] The above technical solutions show that the preparation method of the semiconductor structure of the embodiments of the present disclosure has at least one of the following advantages and positive effects:

[0017] In the embodiments of the present disclosure, the second dielectric layer located in the array region and the peripheral region is etched to a preset depth to form a first trench, and the preset depth is less than the height of the second dielectric layer in the vertical direction, so that the aspect ratio of the first trench located in the peripheral region is reduced, and the aspect ratio of the first spin-on layer located in the first trench is reduced, and the first spin-on layer can be completely removed in subsequent processes, thereby avoiding residual. In addition, the first spin-on layer located in the peripheral region and in the first trench is etched to form a second trench, and the second dielectric layer located at the bottom of the first trench is exposed. The second dielectric layer in the second trench is etched to expose the contact plug to form a filling hole. Since there is no first spin-on layer in the filling hole, and the first spin-on layer in the first trench can be completely removed in subsequent processes, the diffusion barrier layer and the metal layer formed in the first trench and the filling hole can be completely connected with the contact plug, thereby improving the electrical performance and yield of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0018] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0019] Figure 1 A schematic diagram of a semiconductor structure with a spin-on layer residual in a trench in the related art;

[0020] Figure 2 A schematic diagram of a metal interconnection line formed in the related art and unable to be connected with a lower plug due to a spin-on layer residual;

[0021] Figure 3 A flowchart of a preparation method of a semiconductor structure according to some embodiments of the present disclosure;

[0022] Figure 4 A schematic diagram of forming a second dielectric layer, an etching stop layer, an initial spin-on layer, an initial mask layer and an initial photoresist layer on a base structure according to some embodiments of the present disclosure;

[0023] Figure 5 A schematic diagram of transferring a first trench pattern of the initial photoresist to the initial spin-on layer according to some embodiments of the present disclosure;

[0024] Figure 6 A schematic diagram of forming a first trench in the second dielectric layer according to some embodiments of the present disclosure;

[0025] Figure 7 A schematic diagram of forming a first spin-on layer in the second dielectric layer and the first trench according to some embodiments of the present disclosure;

[0026] Figure 8 A schematic diagram of etching the first spin-on layer located in the first trench to form a second trench according to some embodiments of the present disclosure;

[0027] Figure 9 A schematic diagram illustrating forming a protection layer for some embodiments of the present disclosure;

[0028] Figure 10 A schematic diagram illustrating etching a second dielectric layer in a second trench to form a filling hole for some embodiments of the present disclosure;

[0029] Figure 11 A schematic diagram illustrating removing a first spin-on layer for some embodiments of the present disclosure;

[0030] Figure 12 A schematic diagram illustrating forming a diffusion barrier layer and a metal seed layer in a first trench and a filling hole for some embodiments of the present disclosure;

[0031] Figure 13 A schematic diagram illustrating forming a metal layer for some embodiments of the present disclosure;

[0032] Figure 14 A schematic diagram illustrating polishing a metal layer by a chemical mechanical polishing process for some embodiments of the present disclosure.

[0033] Explanation of reference signs:

[0034] 1', metal interconnection line; 2', trench; 3', plug; 4', spin-on layer;

[0035] 1, base structure; 101, first dielectric layer; 102, contact plug; 2, isolation layer; 3, second dielectric layer; 4, etching stop layer; 5, initial spin-on layer; 6, initial mask layer; 7, initial photoresist layer; 8, first trench; 9, first spin-on layer; 10, first mask layer; 11, first photoresist layer; 12, second trench; 13, protection layer; 14, filling hole; 15, diffusion barrier layer; 16', metal seed layer; 16, metal layer; A, array region; P, peripheral region; X, horizontal direction; Y, vertical direction. DETAILED DESCRIPTION

[0036] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and description of the same or like elements can be omitted.

[0037] In the following description of various example embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration various example structures in which aspects of the present disclosure can be implemented. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps can be utilized and structural and functional modifications can be made without departing from the scope of the present disclosure. Also, while the terms "over," "between," "inside," "on," and the like can be used in the present description and claims to describe one aspect or element of a structure as overlying, between, inside, on, and / or the like relative to another, it is understood that the structure can be oriented in any direction and the terms "over," "between," "inside," "on," and the like are used herein merely to facilitate the description of the structures. The terms "over," "under," "between," and the like are not intended to exclude the various alternative orientations of a structure described herein. For example, structural elements can be oriented in any direction and the terms "over," "under," "between," and the like are used herein merely to facilitate the description of the structures. Nothing in this specification should be construed as requiring a specific three dimensional orientation of structures.

[0038] The flow charts shown in the drawings are merely illustrative examples and do not necessarily include all of the content and operations / steps, nor are they necessarily performed in the order described. For example, some operations / steps can be further broken down, while some operations / steps can be combined or partially combined, so the actual order of execution can be changed according to actual conditions.

[0039] In addition, in the description of the present disclosure, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise explicitly specifically limited.

[0040] In the back-end-of-line process of the DRAM, it is necessary to form a metal interconnect line 1', which is electrically connected to the semiconductor devices (such as capacitors, transistors, etc.) formed in the front-end-of-line process. In the process of preparing the metal interconnect line 1', as shown in Figure 1 It is necessary to first form a trench 2' in the peripheral region P to be filled with the metal interconnect line 1', with the plug 3' in the lower layer of dielectric layer exposed at the bottom of the trench 2', and then form a spin-on layer 4' with a certain thickness in the array region A and the peripheral region P, which fills the trench 2'. The spin-on layer 4' in the array region A can act as a mask layer, so that another shallower trench is formed in the array region A for forming the metal interconnect line 1' of the active region.

[0041] Continuing to refer to Figure 1 Because the value of the aspect ratio of the trench 2' in the peripheral region P is large, when the spin-on layer 4' in the trench 2' in the peripheral region P is removed by etching process, the spin-on layer 4' at the bottom of the trench 2' will have a residue. Referring to Figure 2 After the metal interconnect line 1' is formed in the trench 2', due to the influence of the residue of the spin-on layer 4', the metal interconnect line 1' cannot be electrically connected to the underlying conductive member such as the plug 3', thereby affecting the electrical performance of the semiconductor structure and reducing the yield.

[0042] Based on this, the embodiment of the present disclosure provides a preparation method of a semiconductor structure, which can avoid the generation of spin coating layer residues, so that the metal layer can be connected with the contact plug, and the electrical performance and yield of the semiconductor structure are improved.

[0043] As shown in Figure 3 The preparation method of the semiconductor structure provided by the embodiment of the present disclosure comprises the following steps S110-S170.

[0044] S110: providing a substrate structure 1, the substrate structure 1 has an array area A and a peripheral area P, the substrate structure 1 has a first dielectric layer 101, and the first dielectric layer 101 has a contact plug 102.

[0045] S120: forming a second dielectric layer 3 on the first dielectric layer 101 located in the array area A and the peripheral area P.

[0046] S130: etching the second dielectric layer 3 located in the array area A and the peripheral area P to a preset depth to form a first groove 8, the first groove 8 corresponds to covering at least part of the contact plug 102 in the vertical direction Y, and the preset depth is smaller than the height of the second dielectric layer 3 in the vertical direction Y.

[0047] S140: forming a first spin coating layer 9 on the remaining second dielectric layer 3 and in the first groove 8.

[0048] S150: etching the first spin coating layer 9 located in the peripheral area P and in the first groove 8 to form a second groove 12, and exposing the second dielectric layer 3 at the bottom of the first groove 8.

[0049] S160: etching the second dielectric layer 3 in the second groove 12 to expose the contact plug 102 to form a filling hole 14.

[0050] S170: removing the remaining first spin coating layer 9, conformally forming a diffusion barrier layer 15 in the first groove 8 located in the array area A and the peripheral area P and in the filling hole 14 located in the peripheral area P, the diffusion barrier layer 15 is connected with the contact plug 102, and a metal layer 16 is formed on the diffusion barrier layer 15.

[0051] In the embodiments of the present disclosure, the second dielectric layer 3 located in the array region A and the peripheral region P is etched to a preset depth to form a first trench 8, the preset depth being smaller than the height of the second dielectric layer 3 in the vertical direction Y, so that the aspect ratio of the first trench 8 located in the peripheral region P is reduced, and then the aspect ratio of the first spin-on layer 9 located in the first trench 8 is reduced, and the first spin-on layer 9 can be completely removed in subsequent processes to avoid residue. In addition, the first spin-on layer 9 located in the peripheral region P and in the first trench 8 is etched to form a second trench 12, and the second dielectric layer 3 located at the bottom of the first trench 8 is exposed. The second dielectric layer 3 in the second trench 12 is etched to expose the contact plug 102 to form a filling hole 14. Since there is no first spin-on layer 9 in the filling hole 14, and the first spin-on layer 9 in the first trench 8 can be completely removed in subsequent processes, the diffusion barrier layer 15 and the metal layer 16 formed in the first trench 8 and the filling hole 14 can be completely connected with the contact plug 102, thereby improving the electrical performance and yield of the semiconductor structure.

[0052] The preparation method of the semiconductor structure in the embodiments of the present disclosure will be described in detail below.

[0053] S110: providing a base structure 1, the base structure 1 having an array region A and a peripheral region P, and the base structure 1 having a first dielectric layer 101, the first dielectric layer 101 having a contact plug 102.

[0054] As shown in FIG. 1, the base structure 1 can include a substrate and devices (not shown in the figure) located on or in the substrate. Shallow trench isolations are formed in the substrate, and active regions are provided between the shallow trench isolations. The substrate also has word line structures (not shown in the figure) and bit line structures, the word line structures and the bit line structures being provided at different heights of the substrate, and the word line structures and the bit line structures being connected with the active regions. Figure 4 In addition, the substrate includes the array region A and the peripheral region P, and devices (not shown in the figure) such as transistor structures and capacitor structures can be provided in the array region A of the substrate, and peripheral circuits are formed in the peripheral region P. The base structure 1 also has the first dielectric layer 101, the first dielectric layer 101 being used for insulation and isolation between devices, and the first dielectric layer 101 having the contact plug 102 and conductive leads to realize electrical connection between devices.

[0055] In some embodiments, the material of the substrate can be silicon, silicon carbide, silicon-on-insulator, stacked silicon-on-insulator, stacked germanosilicon-on-insulator, stacked germanium-on-insulator, or the like. The substrate can also be doped with certain dopant particles according to design requirements to change electrical parameters.

[0056] The base structure 1 is a structure prepared in a front-end-of-line process of a semiconductor process, and the specific structure and preparation process will not be described here.

[0057] ​

[0058] S120: A second dielectric layer 3 is formed on the first dielectric layer 101 located in the array region A and the peripheral region P.

[0059] like Figure 4 As shown, a second dielectric layer 3 can be formed on the first dielectric layer 101 using a deposition process. The material of the second dielectric layer 3 can be silicon oxide or a low-k dielectric material.

[0060] In some embodiments, such as Figure 4 As shown, a second dielectric layer 3 is formed on a first dielectric layer 101 located in array region A and peripheral region P, including: forming an isolation layer 2 on the first dielectric layer 101 located in array region A and peripheral region P; and forming a second dielectric layer 3 on the isolation layer 2.

[0061] An isolation layer 2 can be deposited on the surface of the first dielectric layer 101 using a deposition process. The material of the isolation layer 2 may include silicon nitride, which has good isolation performance and can reduce parasitic capacitance. The thickness of the isolation layer 2 is less than the thickness of the second dielectric layer 3, which facilitates subsequent processes while achieving its isolation performance.

[0062] S130: Etch the second dielectric layer 3 located in the array region A and the peripheral region P to a preset depth to form a first trench 8. The first trench 8 covers at least part of the contact plug 102 in the vertical direction Y. The preset depth is less than the height of the second dielectric layer 3 in the vertical direction Y.

[0063] like Figure 4 As shown, before etching the second dielectric layer 3 located in the array region A and the peripheral region P to a preset depth to form the first trench 8, the process further includes: forming an etch stop layer 4 on the second dielectric layer 3; forming an initial spin coating layer 5 on the etch stop layer 4; forming an initial mask layer 6 on the initial spin coating layer 5; and forming an initial photoresist layer 7 on the initial mask layer 6.

[0064] A second dielectric layer 3 can be deposited on the isolation layer 2 using a deposition process. An etch stop layer 4 is then formed on the second dielectric layer 3; the material of the etch stop layer 4 can be silicon oxynitride. An initial spin-coating layer 5 is formed on the etch stop layer 4 using a spin-coating process. The material of the initial spin-coating layer 5 can be spin-on carbon (SOC) or spin-on hard mask (SOH). An initial mask layer 6 and an initial photoresist layer 7 are sequentially formed on the initial spin-coating layer 5 using a deposition process. The material of the initial mask layer 6 can include silicon oxynitride.

[0065] The second dielectric layer 3 located in the array region A and the peripheral region P is etched to a predetermined depth to form a first trench 8, including the following contents A1 to A3.

[0066] A1: Forming a first trench pattern in the initial photoresist layer 7.

[0067] As shown in Figure 4 , a first trench pattern can be formed in the initial photoresist located in the array region A and the peripheral region P by using a photolithography process.

[0068] A2: Sequentially transferring the first trench pattern to the initial mask layer 6, the initial spin-on layer 5, the etch stop layer 4 and the second dielectric layer 3.

[0069] The first trench pattern in the initial photoresist layer 7 can be transferred to the initial mask layer 6 by using a dry etching process, and the silicon oxynitride material in the initial mask layer 6 can act as an antireflection film in the photolithography process to prevent the photolithography process from damaging the initial spin-on layer 5, thereby ensuring that the first trench pattern can be accurately transferred. As shown in Figure 5 , the first trench pattern is transferred from the initial mask layer 6 to the initial spin-on layer 5, and the etching stops at the etch stop layer 4. As shown in Figure 6 , the first trench pattern can then be transferred from the etch stop layer 4 to the second dielectric layer 3 by using a dry etching process, so that a first trench 8 is formed in the second dielectric layer 3 located in the array region A and the peripheral region P.

[0070] A3: Removing the remaining initial photoresist layer 7, initial mask layer 6, initial spin-on layer 5 and etch stop layer 4 to form the first trench 8 in the second dielectric layer 3.

[0071] As shown in Figure 5 , the initial photoresist layer 7 and the initial mask layer 6 can be removed after the first trench pattern is transferred to the initial spin-on layer 5, as shown in Figure 6 , the initial spin-on layer 5 and the etch stop layer 4 can be removed after the first trench 8 is formed in the second dielectric layer 3.

[0072] As shown in Figure 6 , the first trench 8 corresponds to at least partially covering the contact plug 102 in the vertical direction Y, and the preset depth is less than the height of the second dielectric layer 3 in the vertical direction Y. That is, the projection of the first trench 8 on the substrate structure 1 along the vertical direction Y covers at least part of the contact plug 102, so that the filling hole 14 formed in the subsequent process can expose the contact plug 102, so that the metal layer 16 formed subsequently can be connected with the contact plug 102.

[0073] Continuing to refer to Figure 6 , the preset depth can be understood as the depth of the first trench 8, which is less than the height of the second dielectric layer 3 in the vertical direction Y, that is, the first trench 8 does not penetrate the second dielectric layer 3, so that the aspect ratio of the first trench 8 can be reduced.

[0074] In some embodiments, the dimension of the first trench 8 located in the peripheral region P in the horizontal direction X is larger than the dimension of the first trench 8 located in the array region A in the horizontal direction X. That is, the key dimension of the first trench 8 in the peripheral region P is increased. At the same time, since the depth of the first trench 8 is less than the height of the second dielectric layer 3, the aspect ratio of the first trench 8 located in the peripheral region P can be further reduced, so that the first spin coating 9 formed in the first trench 8 can be completely removed subsequently, avoiding the formation of residues.

[0075] It should be noted that, in this embodiment, "vertical direction Y" refers to the direction perpendicular to the surface of the substrate structure 1, and can also be understood as the stacking direction of the second dielectric layer 3, the etch stop layer 4, and the initial spin coating layer 5. "Horizontal direction X" refers to the direction parallel to the surface of the substrate structure 1, and the horizontal direction X is perpendicular to the vertical direction Y. The terms "vertical direction Y" and "horizontal direction X" are merely for descriptive purposes and are not intended to be limiting.

[0076] S140: A first spin coating 9 is formed on the remaining second dielectric layer 3 and in the first trench 8.

[0077] like Figure 7 As shown, a first spin coating layer 9 is formed on the second dielectric layer 3 and in the first trench 8 using a spin coating process. The first spin coating layer 9 fills the first trench 8 located in the array region A and the peripheral region P, and is higher than the surface of the second dielectric layer 3. The material of the first spin coating layer 9 may include spin-coated organic carbon or spin-coated hard mask.

[0078] S150: Etch the first spin coating 9 located in the peripheral region P and in the first trench 8 to form the second trench 12, exposing the second dielectric layer 3 located at the bottom of the first trench 8.

[0079] Continue to refer to Figure 7 Before performing S150, the method further includes: forming a first mask layer 10 on the first spin coating layer 9; and forming a first photoresist layer 11 on the first mask layer 10.

[0080] The material of the first mask layer 10 may include silicon oxynitride. During the subsequent photolithography process of the first photoresist to form the second trench pattern, the first mask layer 10 can act as an anti-reflective film during the photolithography process, preventing damage to the first spin-coating layer 9. Additionally, it can transfer the second trench pattern into the first mask layer 10, allowing the first mask layer 10 to continue transferring the second trench pattern downwards.

[0081] It should be noted that the terms "upper" and "lower" in the embodiments of this disclosure are technical terms indicating orientation. For example, the direction from the first dielectric layer 101 to the second dielectric layer 3 is upward, and vice versa, such as when the second dielectric layer 3 is located below the etch stop layer 4. These terms are used merely for ease of description and are not intended to be limiting.

[0082] In some embodiments, S150 may include the following contents B1 to B3.

[0083] B1: A second trench pattern is formed in the first photoresist layer 11.

[0084] For example, a mask layer with a second trench pattern can be formed above the first photoresist layer 11, and the second trench pattern can be formed in the first photoresist layer 11 using photolithography and development techniques. Figure 7 As shown, the second groove pattern is formed only in the outer region P, and the second groove pattern corresponds to the first groove 8 in the vertical direction Y.

[0085] B2: Transfer the second trench pattern to the first mask layer 10.

[0086] The second trench pattern in the first photoresist layer 11 can be transferred to the first mask layer 10 using an etching process, so that the first mask layer 10 can continue to transfer the second trench pattern downward as a mask.

[0087] B3: According to the second trench pattern in the first mask layer 10, the first spin coating layer 9 located in the peripheral region P and in the first trench 8 is etched to form the second trench 12.

[0088] like Figure 8 As shown, in some embodiments, the dimension of the second trench 12 along the horizontal direction X is smaller than the dimension of the first trench 8 along the horizontal direction X, that is, the critical dimension of the second trench 12 is smaller than the critical dimension of the first trench 8, and the sidewall of the second trench 12 is formed by the first spin coating 9. After etching the second dielectric layer 3 to form the filling hole 14 in the subsequent process, the critical dimension of the filling hole 14 can be smaller than the critical dimension of the first trench 8. Since the critical dimension of the first trench 8 is larger, the aspect ratio of the first trench 8 is reduced, making it easier to completely remove the first spin coating 9 located in the first trench 8. And since there is no first spin coating 9 in the filling hole 14, there will be no residue of the first spin coating 9 in the final formed first trench 8 and filling hole 14. Moreover, the fact that the critical dimension of the filling hole 14 is smaller than the critical dimension of the first trench 8 can also meet the requirements of high density and further improve the electrical performance of the semiconductor structure.

[0089] In addition, the critical dimension of the second trench 12 is smaller than that of the first trench 8. The sidewall of the second trench 12 is the first spin coating 9. In the subsequent process of etching the second dielectric layer 3 to form the filling hole 14, the sidewall of the second trench 12 (the first spin coating 9) can protect the sidewall of the first trench 8 (the second dielectric layer 3) and prevent the sidewall of the first trench 8 from being damaged.

[0090] In some embodiments, such as Figure 9As shown, after etching the first spin coating 9 located in the peripheral region P and within the first trench 8 to form the second trench 12 and expose the second dielectric layer 3 located at the bottom of the first trench 8, the process further includes forming a protective layer 13 on the sidewalls of the second trench 12 formed by the first spin coating 9 and the bottom wall of the second trench 12 formed by the exposed second dielectric layer 3. The material of the protective layer 13 is different from the material of the first spin coating 9. The material of the protective layer 13 can be the same as the material of the second dielectric layer 3.

[0091] Since the second dielectric layer 3 exposed in the second trench 12 needs to be etched in subsequent processes to form the filling hole 14, the protective layer 13 can protect the sidewalls of the second trench 12, preventing damage to the sidewalls of the second trench 12 during etching. The material of the protective layer 13 is different from that of the first spin coating layer 9. The material of the protective layer 13 can be silicon oxide or a low-k dielectric material, and the protective layer 13 can be formed using atomic layer deposition. The first spin coating layer 9 can protect the sidewalls of the first trench 8. Since the materials of the protective layer 13 and the first spin coating layer 9 are different, the impact on the first spin coating layer 9 is small when the protective layer 13 is etched, thus protecting the sidewalls of the second trench 12. At the same time, since the materials of the protective layer 13 and the second dielectric layer 3 are the same, the first spin coating layer 9 can prevent the etching gas from etching the sidewalls of the first trench 8 when the protective layer 13 is etched, avoiding an increase in the critical dimensions of the first trench 8, or even the complete etching of the sidewalls of the first trench 8 leading to the connection of the two first trenches 8.

[0092] S160: Etch the second dielectric layer 3 in the second trench 12 until the contact plug 102 is exposed to form a filling hole 14.

[0093] In some embodiments, S160 may include etching to remove the protective layer 13 and etching the second dielectric layer 3 to expose the contact plug 102, forming a filling hole 14.

[0094] like Figure 10 As shown, during the etching process to form the filling hole 14, the protective layer 13 can be removed simultaneously. During the etching process, the etching rate of the protective layer 13 and the second dielectric layer 3 located on the bottom wall of the second trench 12 is greater than the etching rate of the protective layer 13 located on the side wall of the second trench 12. Therefore, while forming the contact hole, the protective layer 13 on the side wall can also be removed, exposing the side wall of the second trench 12.

[0095] In some other embodiments, instead of forming a protective layer 13, the exposed second dielectric layer 3 can be directly etched into the second trench 12 to form a filling hole 14.

[0096] In some embodiments, since an isolation layer 2 is formed between the second dielectric layer 3 and the first dielectric layer 101, etching the second dielectric layer 3 in the second trench 12 to expose the contact plug 102 and forming a filling hole 14 includes etching the second dielectric layer 3 and the isolation layer 2 in the second trench 12 to expose the contact plug 102 and forming a filling hole 14.

[0097] In some embodiments, such as Figure 11 As shown, the filling hole 14 is located in the middle of the first trench 8 in the horizontal direction X. Aligning the filling hole 14 with the middle of the first trench 8 ensures that the contact plug 102 can be fully exposed in the filling hole 14 and avoids the subsequent formation of the metal layer 16 from being misaligned.

[0098] S170: Remove the remaining first spin coating 9, and conformally form a diffusion barrier layer 15 in the first trench 8 located in the array region A and the peripheral region P and the filling hole 14 located in the peripheral region P. The diffusion barrier layer 15 is connected to the contact plug 102, and a metal layer 16 is formed on the diffusion barrier layer 15.

[0099] like Figure 11 As shown, the remaining first swirl coating 9 can be removed using a wet etching process. Because the first trench 8 has a small aspect ratio and the critical dimensions of the first trench 8 located in the peripheral region P are larger, the first swirl coating 9 can be completely removed. Figure 11 As shown, there is no residue of the first spin coating 9 in the first groove 8 and the filling hole 14.

[0100] like Figure 12 As shown, a diffusion barrier layer 15 can be conformally formed in the first trench 8 of the array region A and the peripheral region P and in the filling hole 14 located in the peripheral region P using a deposition process. The diffusion barrier layer 15 can be made of titanium nitride to block the diffusion of the subsequently formed metal layer 16, ensuring the stability of the electrical performance of the semiconductor structure. The diffusion barrier layer 15 is connected to the contact plug 102 to ensure that the metal layer 16 can be electrically connected to the contact plug 102.

[0101] In some embodiments, forming a metal layer 16 on the diffusion barrier layer 15 includes: filling the metal layer 16 into the first trench 8 and the filling hole 14 where the diffusion barrier layer 15 is formed; and grinding the metal layer 16 and the diffusion barrier layer 15 located on the second dielectric layer 3 using a chemical mechanical polishing process, so that the surfaces of the second dielectric layer 3, the metal layer 16 and the diffusion barrier layer 15 are flush.

[0102] like Figure 12 As shown, a metal seed layer 16' can be conformally formed on the diffusion barrier layer 15 using atomic layer deposition (ALD) technology, such as... Figure 13As shown, the metal layer 16 can be formed using an electroplating process. The metal seed layer 16' and the metal layer 16 are made of the same material to facilitate the formation of a uniform metal layer 16. In some embodiments, the materials of the metal seed layer 16' and the metal layer 16 may include copper or tungsten.

[0103] like Figure 14 As shown, after the metal layer 16 is formed, the metal layer 16 and the diffusion barrier layer 15 located on the second dielectric layer 3 can be polished using a chemical mechanical polishing process, so that the surfaces of the second dielectric layer 3, the metal layer 16 and the diffusion barrier layer 15 are flush, which facilitates subsequent processes.

[0104] In embodiments of this disclosure, the deposition process may be at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0105] In summary, the method of this disclosure reduces the aspect ratio of the first trench 8, thereby reducing the aspect ratio of the first swirl coating 9 located in the first trench 8. This allows for complete removal of the first swirl coating 9 in subsequent processes, preventing residue buildup. Furthermore, since the filling hole 14 does not contain the first swirl coating 9, the diffusion barrier layer 15 and the metal layer 16 formed in the first trench 8 and the filling hole 14 can be fully connected to the contact plug 102, improving the electrical performance and yield of the semiconductor structure.

[0106] This disclosure also provides a semiconductor structure, such as... Figure 14 As shown, the semiconductor structure includes a substrate structure 1, a second dielectric layer 3, a diffusion barrier layer 15, and a metal layer 16.

[0107] like Figure 14 As shown, the substrate structure 1 has an array region A and a peripheral region P. The substrate structure 1 has a first dielectric layer 101, in which contact plugs 102 are provided. The substrate structure 1 may include a substrate and devices (not shown) located on or within the substrate. The substrate also includes the first dielectric layer 101, in which contact plugs 102 are provided for electrical connection to the respective devices. The substrate structure 1 is the same as in the method embodiment, and will not be described again here.

[0108] Continue to refer to Figure 14 The second dielectric layer 3 is located on the first dielectric layer 101 of the array region A and the peripheral region P; in the array region A and the peripheral region P, the second dielectric layer 3 has a first trench 8 with a predetermined depth (reference). Figure 11 The preset depth is less than the height of the second dielectric layer 3 in the vertical direction Y, that is, the first trench 8 does not penetrate the second dielectric layer 3. In the peripheral area P, the second dielectric layer 3 located below the first trench 8 is provided with a filling hole 14 that connects the contact plug 102 and the first trench 8.

[0109] In some embodiments, the critical dimension of the filling via 14 is smaller than the critical dimension of the first trench 8, wherein the critical dimension of the first trench 8 is its dimension along the horizontal direction X. The smaller critical dimension of the filling via 14 compared to the critical dimension of the first trench 8 satisfies the high-density requirements of the semiconductor structure and improves its electrical performance. Simultaneously, the portion of the metal layer 16 located within the first trench 8 increases the conductive area of ​​the metal layer 16, further enhancing its electrical performance.

[0110] In some embodiments, the filling hole 14 is located in the middle of the first trench 8 in the horizontal direction X. That is, the filling hole 14 is connected to the middle position of the bottom of the first trench 8, which can ensure that the metal layer 16 in the filling hole 14 can be connected to the plug in the first dielectric layer 101, thus ensuring the stability of electrical performance.

[0111] like Figure 14 As shown, a diffusion barrier layer 15 is located in the first trench 8 of the array region A and the peripheral region P, and in the first filling hole 14 of the peripheral region P, to prevent the diffusion of metal in the metal layer 16. The metal layer 16 is located in the first trench 8 and the filling hole 14 having the diffusion barrier layer 15. In some embodiments, the material of the metal layer 16 may include at least one of copper and tungsten.

[0112] In some embodiments, such as Figure 14 As shown, the top surfaces of the second dielectric layer 3, the diffusion barrier layer 15, and the metal layer 16 are flush to facilitate other semiconductor processes on this semiconductor structure.

[0113] In summary, the semiconductor structure of this embodiment has no spin coating residue between the metal layer 16 and the contact plug 102, which allows the metal layer 16 to make full contact with the contact plug 102, thereby improving the electrical performance and yield of the semiconductor structure.

[0114] It should be understood that this disclosure is not limited to the detailed structure and arrangement of the components presented in this specification. This disclosure is capable of other embodiments and can be implemented and performed in various ways. The foregoing variations and modifications fall within the scope of this disclosure. It should be understood that this disclosure, as disclosed and defined in this specification, extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or drawings. All these different combinations constitute multiple alternative aspects of this disclosure. The embodiments described in this specification illustrate the best known mode for implementing this disclosure and will enable those skilled in the art to adopt this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, comprising: providing a substrate structure having an array region and a peripheral region, the substrate structure having a first dielectric layer with a contact plug therein; forming a second dielectric layer on the first dielectric layer in the array region and the peripheral region; etching the second dielectric layer in the array region and the peripheral region to a preset depth to form a first trench, the first trench vertically corresponding to covering at least part of the contact plug, the preset depth being less than a height of the second dielectric layer in the vertical direction; forming a first spin-on layer on the remaining second dielectric layer and in the first trench; etching the first spin-on layer in the peripheral region and in the first trench to form a second trench, exposing the second dielectric layer at a bottom of the first trench; etching the second dielectric layer in the second trench to expose the contact plug to form a fill hole; removing the remaining first spin-on layer to form a diffusion barrier layer conformally in the first trench in the array region and the peripheral region and in the fill hole in the peripheral region, the diffusion barrier layer being connected with the contact plug, and forming a metal layer on the diffusion barrier layer; etching the first spin-on layer in the peripheral region and in the first trench to form a second trench, exposing the second dielectric layer at a bottom of the first trench, further comprising: forming a protection layer on a sidewall of the second trench formed by the first spin-on layer and a bottom wall of the second trench formed by the exposed second dielectric layer; and a size of the first trench in the peripheral region in a horizontal direction being greater than a size of the first trench in the array region in the horizontal direction. 2.The method of claim 1, wherein: a material of the protection layer is different from a material of the first spin-on layer; and etching the second dielectric layer in the second trench to expose the contact plug to form a fill hole comprises: etching to remove the protection layer and etching the second dielectric layer to expose the contact plug to form the fill hole. 3.The method of claim 1, wherein: the fill hole is located in a middle of the first trench in a horizontal direction; and / or a size of the second trench in a horizontal direction is less than a size of the first trench in the horizontal direction. 4.The method of claim 1, wherein: forming a second dielectric layer on the first dielectric layer in the array region and the peripheral region comprises: forming an isolation layer on the first dielectric layer in the array region and the peripheral region; and forming the second dielectric layer on the isolation layer; and etching the second dielectric layer in the second trench to expose the contact plug to form a fill hole comprises: etching the second dielectric layer and the isolation layer in the second trench to expose the contact plug to form the fill hole. 5.The method of claim 1, wherein: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ etching the second dielectric layer in the array region and the peripheral region to a preset depth to form a first trench, further comprising: forming an etching stop layer on the second dielectric layer; forming an initial spin-on layer on the etching stop layer; forming an initial mask layer on the initial spin-on layer; forming an initial photoresist layer on the initial mask layer.

6. The method of claim 5, wherein, etching the second dielectric layer in the array region and the peripheral region to a preset depth to form a first trench, comprises: forming a first trench pattern in the initial photoresist layer; transferring the first trench pattern to the initial mask layer, the initial spin-on layer, the etching stop layer and the second dielectric layer in sequence; removing the remaining initial photoresist layer, the initial mask layer, the initial spin-on layer and the etching stop layer to form the first trench in the second dielectric layer.

7. The method of claim 1, wherein, before etching the first spin-on layer in the peripheral region and in the first trench to form a second trench to expose the second dielectric layer at the bottom of the first trench, further comprising: forming a first mask layer on the first spin-on layer; forming a first photoresist layer on the first mask layer; before etching the first spin-on layer in the peripheral region and in the first trench to form a second trench to expose the second dielectric layer at the bottom of the first trench, comprising: forming a second trench pattern in the first photoresist layer; transferring the second trench pattern to the first mask layer; etching the first spin-on layer in the peripheral region and in the first trench according to the second trench pattern in the first mask layer to form the second trench.

8. The method of any one of claims 1-7, wherein, forming a metal layer on the diffusion barrier layer, comprises: filling the metal layer in the first trench and the filling hole formed with the diffusion barrier layer; polishing the metal layer and the diffusion barrier layer on the second dielectric layer by a chemical mechanical polishing process to make the surfaces of the second dielectric layer, the metal layer and the diffusion barrier layer flush.

9. A semiconductor structure prepared by the method of any one of claims 1-8, comprising: a base structure having an array region and a peripheral region, the base structure having a first dielectric layer with a contact plug therein; a second dielectric layer on the first dielectric layer in the array region and the peripheral region; a first trench in the second dielectric layer in the array region and the peripheral region to a preset depth, the preset depth being less than the height of the second dielectric layer in the vertical direction, in the peripheral region, the second dielectric layer under the first trench being provided with a filling hole communicating the contact plug and the first trench; a diffusion barrier layer in the first trench and the filling hole; a metal layer in the first trench and the filling hole with the diffusion barrier layer. ​

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