Semiconductor device including buried gate structure

Abstract

The invention relates to a semiconductor device including a buried gate structure. A semiconductor device includes: a first buried gate configured to extend in a first direction; a bit line contact disposed on one side of the first buried gate and located outside the first buried gate; a storage node contact disposed on the other side of the first buried gate in a diagonal direction of the bit line contact, and located outside the first buried gate; and a plurality of active regions repeatedly arranged, spaced apart from each other by a predetermined distance in the first direction, and overlapping the first buried gate. Each of the plurality of active regions includes: a first extension region configured to extend in a second direction perpendicular to the first direction and overlap with the bit line contact; a second extension region configured to extend in a second direction and overlap the storage node contact; and a third extension region configured to extend in the diagonal direction and overlap the first buried gate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2023-0096398, filed on Jul. 24, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The techniques and implementations disclosed in the present disclosure generally relate to a semiconductor device, and more particularly to a semiconductor device including a plurality of active regions. Background Art

[0004] A semiconductor device with a memory from among a variety of semiconductor devices as a device that can be used to store information can include an array, and the array includes individual memory cells with transistors. The semiconductor device with a memory can include, for example, a dynamic random access memory (DRAM). The DRAM can include bit lines and word lines that can cross each other in a vertical direction. The bit lines and word lines can extend through the array including the memory cells. The bit lines and word lines can be used to access the individual memory cells.

[0005] Memory performance, cell stability and reliability, power efficiency, ease of processing, cost, etc. can vary depending on how individual memory cells are designed and placed, so research into cell array design and cell array manufacturing processes for memory devices is actively underway. Summary of the invention

[0006] Various embodiments of the disclosed technology are directed to a structure in which the shape and arrangement of memory cells are effectively designed to improve the performance of a semiconductor device.

[0007] According to an embodiment of the disclosed technology, a semiconductor device may include: a first buried gate configured to extend in a first direction; a bit line contact disposed on one side of the first buried gate and located outside the first buried gate; a storage node contact disposed on the other side of the first buried gate along a diagonal direction of the bit line contact and located outside the first buried gate; and a plurality of active regions repeatedly arranged, which are spaced apart from each other by a predetermined distance in the first direction and overlap with the first buried gate. Each of the plurality of active regions may include: a first extension region configured to extend in a second direction perpendicular to the first direction and overlap with the bit line contact; a second extension region configured to extend in the second direction and overlap with the storage node contact; and a third extension region configured to extend in a diagonal direction and overlap with the first buried gate.

[0008] In some implementations, the semiconductor device may further include: a second buried gate configured to extend in the first direction and to be spaced apart from the first extension region in the second direction.

[0009] In some implementations, the first buried gate may overlap a portion of the first extension region and a portion of the third extension region.

[0010] In some implementations, the width of the first extended region in the first direction can be greater than the width of the second extended region in the first direction.

[0011] In some implementations, the third extension regions included in active regions adjacent to each other in a diagonal direction among the plurality of active regions may be repeatedly arranged to be spaced apart from each other by a predetermined distance.

[0012] In some implementations, the semiconductor device may further include: a bit line configured to extend in the second direction and overlap with the bit line contact; and a first bit line spacer and a second bit line spacer, each of which contacts the bit line on both sides of the bit line, is configured not to overlap with the second extension region, and is formed to extend in the second direction.

[0013] In some implementations, the first bit line spacer and the second extension region can contact each other.

[0014] In some implementations, the first bit line spacer and the second extension region can be spaced apart from each other.

[0015] In some implementations, the bit line may be disposed on a substrate including a semiconductor layer having a first buried gate disposed therein.

[0016] In some implementations, the bit line may be disposed to be buried in a substrate including a semiconductor layer in which a first buried gate is disposed.

[0017] According to another embodiment of the disclosed technology, a semiconductor device may include: a bit line configured to extend in a first direction; a first extension region configured to extend in the first direction and overlap with the bit line; a second extension region spaced apart from the bit line and formed to extend in the first direction; a third extension region, one end of which contacts a side of the first extension region arranged in the first direction and extends in a second direction at an obtuse angle to the first direction, and the other end of which contacts a side of the second extension region arranged in the first direction; a first buried gate overlapping at least a portion of the third extension region and extending in a third direction perpendicular to the first direction within the semiconductor layer; a bit line contact disposed in the first extension region; and a storage node contact disposed in the third extension region.

[0018] In some implementations, the semiconductor device may further include a second buried gate spaced apart from the first extension region in the first direction and formed to extend in a third direction.

[0019] In some implementations, the first buried gate may overlap a portion of the second extension region, and the second buried gate overlaps a portion of the first extension region.

[0020] In some implementations, the width of the first extended region in the third direction can be equal to the width of the third extended region in the second direction.

[0021] In some implementations, the width of the third extended region in the second direction can be greater than the width of the first extended region in the second direction.

[0022] In some implementations, the semiconductor device may further include: a first bit line spacer and a second bit line spacer, each of which contacts the bit line at both sides of the bit line, is arranged not to overlap the first extension region, and is formed to extend in the first direction.

[0023] In some implementations, the first bit line spacer and the second extension region can be spaced apart from each other.

[0024] In some implementations, the first bit line spacer and the second extension region can contact each other.

[0025] In some implementations, the bit lines can be disposed outside the semiconductor layer.

[0026] In some implementations, the bit lines may be arranged buried in the semiconductor layer.

[0027] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are illustrative and descriptive and are intended to provide further description of embodiments of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other features and advantageous aspects of the disclosed technology will become readily apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0029] Figure 1 is a plan view showing a cell array of a memory device that may be included in a semiconductor device based on some implementations of the disclosed technology.

[0030] Figure 2 is a plan view showing a cell array of a memory device based on some other implementations of the disclosed technology.

[0031] Figure 3 is a plan view showing a cell array of a memory device based on some other implementations of the disclosed technology.

[0032] Figure 4 is a plan view showing a cell array of a memory device based on some other implementations of the disclosed technology.

[0033] Figure 5 is a plan view showing a cell array of a memory device based on some other implementations of the disclosed technology.

[0034] Figure 6 is a diagram showing some implementations of memory devices based on the disclosed technology. Figure 1 A cross-sectional view taken along line II'.

[0035] Figure 7 is a diagram showing some implementations of memory devices based on the disclosed technology. Figure 1 A cross-sectional view taken along line II-II'.

[0036] Figure 8 is a diagram showing some implementations of memory devices based on the disclosed technology. Figure 1 A cross-sectional view taken along line III-III'.

[0037] Fig. 9 is a diagram showing some implementations of memory devices based on the disclosed technology. Figure 1 A cross-sectional view taken along line IV-IV'.

[0038] Fig.10 is a diagram showing some implementations of memory devices based on the disclosed technology. Figure 1 A cross-sectional view taken along line V-V'. DETAILED DESCRIPTION

[0039] The present disclosure provides implementations and examples of semiconductor devices including multiple active regions that can be used for configuration to substantially solve one or more technical or engineering problems and alleviate limitations or disadvantages encountered in some other semiconductor device designs. Some implementations of the disclosed technology relate to a structure in which the shape and arrangement of memory cells are effectively designed to improve the performance of the semiconductor device. Acknowledging the above problems, the disclosed technology provides a semiconductor device that can facilitate the manufacturing process of bit line contacts and storage node contacts and can ensure the contact area, thereby ensuring the necessary resistance. In addition, the disclosed technology can provide a storage semiconductor device in which a large fin area is ensured by the shape of the active region, and the capacitance is ensured by the arrangement of the active regions regularly spaced apart from each other.

[0040] Reference will now be made in detail to the embodiments of the disclosed technology shown in the accompanying drawings. Where possible, the same reference numerals will be used throughout the figures to refer to the same or similar parts. Although the present disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof are shown in the form of drawings. However, the present disclosure should not be construed as being limited to the embodiments presented herein. In addition, in the following description of the embodiments of the disclosed technology, detailed descriptions of known functions and configurations incorporated herein will be omitted to avoid confusing the subject matter of the embodiments.

[0041] Hereinafter, various embodiments will be described with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to specific embodiments, but includes various modifications, equivalents and / or alternatives of the embodiments. The embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized by the disclosed technology.

[0042] When describing the components of the embodiments of the disclosed technology, various terms such as first, second, etc. may be used only for the purpose of distinguishing one component from another component, but the nature, order, and sequence of the components are not limited to these terms. Unless otherwise defined, all terms (including technical and scientific terms) used in the disclosed technology may have the same meaning as those commonly understood by people with ordinary skills in the field involved in the disclosed technology. It should be further understood that terms (such as those defined in commonly used dictionaries) can be interpreted as having a meaning consistent with their meaning in the context of the relevant field and the disclosed technology, and should not be idealized or overly formalized unless clearly defined in this article.

[0043] Figure 1 is a plan view showing a cell array of a memory device 1 that may be included in a semiconductor device based on some implementations of the disclosed technology.

[0044] refer to Figure 1 , based on some implementations of the disclosed technology, the memory device 1 may be part of a semiconductor device that may be used as a data storage device that may be included in a variety of electronic devices such as computers. A semiconductor device including the memory device 1 may use a central processing unit (CPU) of an electronic device and the memory device 1 to store data or provide stored data. In some implementations, the semiconductor device may be a volatile memory device (e.g., a dynamic random access memory (DRAM)). In some other implementations, the semiconductor device may be a non-volatile memory device (e.g., a NAND memory).

[0045] For example, the memory device 1 may include first to fourth bit lines (101-104), first to eighth bit line spacers (111-118), first to fourth buried gates (401-404), first to sixteenth active regions (1001A-1016A), and a deactivation region 20. The number of bit lines, bit line spacers, buried gates, and active regions included in the memory device 1 is disclosed only for illustrative purposes, and the scope of the disclosed technology is not limited thereto. Figure 1 is a plan view showing an example of 16 active regions arranged in a (4×4) matrix, but the scope of the disclosed technology is not limited thereto. That is, the memory device 1 may include at least one active region arranged in an (M×N) matrix, where each of M and N is an integer of 1 or greater, and the memory device 1 may include a bit line, a bit line spacer, a buried gate, and a deactivation region corresponding to the at least one active region. Each unit cell in the cell array of the memory device 1 may include one active region.

[0046] The first to fourth bit lines (101-104) may be arranged parallel to each other at a predetermined interval (i.e., at intervals of a predetermined distance) and may extend in a first direction D1. The predetermined interval may be spaced apart from each other by a predetermined distance. Specifically, the predetermined interval may be spaced apart from each other in a second direction D2 perpendicular to the first direction D1. Each of the first to fourth bit lines (101-104) may be used to read data from a capacitor (i.e., from the first to sixteenth capacitor) electrically connected to the first to sixteenth active regions (1001A-1016A), respectively, or may be used to write data in a capacitor. The operation of writing data in a capacitor electrically connected to the first to sixteenth active regions (1001A-1016A) may include an operation of applying a voltage signal to an active region (1001A-1016A) connected to a capacitor arranged to store desired data. Here, the operation of applying a voltage signal to the active regions (1001A-1016A) can be performed by the first to fourth bit lines (101-104) electrically connected to the first to sixteenth active regions (1001A-1016A). For example, the operation of writing data in the capacitor electrically connected to the first active region 1001A can be performed by applying a voltage signal to the first bit line 101.

[0047] The first to eighth bit line spacers (111-118) may be arranged to contact both sides of the first to fourth bit lines (101-104) arranged in parallel with each other at intervals of a predetermined distance. Figure 1In the embodiment, for the convenience of explanation, the pattern corresponding to the first to eighth bit line spacers (111-118) is omitted from the portion where the first to eighth bit line spacers (111-118) overlap with the first to fourth buried gates (401-404), but may have a structure extending continuously in the first direction D1. In one example, the first bit line spacer 111 may extend in the first direction D1 and contact one side surface of the first bit line 101, and the second bit line spacer 112 may extend in the first direction D1 and contact the other side surface of the first bit line 101. The first bit line spacer and the second bit line spacer (111, 112) may prevent electrical interaction that may occur between the first bit line 101 and the second bit line 102 adjacent to the first bit line 101. When electrical interaction occurs between two adjacent bit lines (101, 102), interference may occur in an operation of reading or writing data, thereby causing unexpected errors in an operation of processing such data. The first to eighth bit line spacers (111-118) may be disposed to contact the first to fourth bit lines (101-104) to electrically isolate the first to fourth bit lines (101-104) from each other. As a result, leakage current may be prevented and an interference phenomenon may also be prevented.

[0048] The first to fourth buried gates (401-404) may be arranged in parallel with each other at a predetermined interval (i.e., at intervals of a predetermined distance) and may extend in the second direction D2. The predetermined interval may be spaced apart from each other by a predetermined distance. Specifically, the predetermined interval may be arranged to be spaced apart from each other in the first direction D1. The first to fourth buried gates (401-404) may be used to read data from a capacitor electrically connected to the first to fourth bit lines (101-104) and the first to sixteenth active regions (1001A-1016A), or may be used to write data in the capacitor. Each of the first to fourth buried gates (401-404) may be arranged to cross vertically with the first to fourth bit lines (101-104), and may be used as a word line for selecting one of the active regions (1001A-1016A) to read or write data. For example, when the first bit line 101 and the first buried gate 401 are selected, the first active region 1001A may be selected. More specifically, when a voltage is applied to first bit line 101 and a voltage equal to or greater than a threshold voltage is applied to first buried gate 401, charges from first bit line 101 may move to second extension region 1200 through third extension region 1300 disposed to overlap first buried gate 401 after passing through first extension region 1100. Then, the charges moved to second extension region 1200 may move to a capacitor electrically connected to second extension region 1200.

[0049] A portion of the first to sixteenth active regions (1001A to 1016A) (e.g., the first extension region 1100) may overlap with the first to fourth bit lines (101 to 104), and another portion of the first to sixteenth active regions (1001A to 1016A) (e.g., the third extension region 1300) may overlap with the first to fourth buried gates (401 to 404). The first to sixteenth active regions (1001A to 1016A) may have the same shape. Each of the first to sixteenth active regions (1001A to 1016A) may include a first extension region 1100, a second extension region 1200, and a third extension region 1300. Although in Figure 1 1001A, the first to third extension regions (1100, 1200, 1300) are shown only in the first memory cell 1001A, but the first to third extension regions (1100, 1200, 1300) can also be commonly applied to the second to sixteenth memory cells (1002A-1016A), but for the convenience of description, the first to third extension regions (1100, 1200, 1300) are shown in the first memory cell 1001A. For the convenience of description, the following example in which the first to third extension regions (1100, 1200, 1300) are applied to the first active region 1001 will be described below.

[0050] The first active region 1001A may refer to a region in which charges from the first bit line 101 to which a voltage for reading or writing data is applied move. When a voltage is applied to the first bit line 101 and the first buried gate 401 is selected, charges may be stored in a capacitor electrically connected to the first active region 1001A. The first active region 1001A may contact a bit line contact (not shown) and a storage node contact (not shown). Reference will be made later to Figure 6 The accompanying drawings describe bit line contacts and storage node contacts.

[0051] The first extension region 1100 may refer to a region that does not overlap with the first buried gate 401 and extends in the first direction D1 from a portion formed to overlap with the first bit line 101 on one side of the first buried gate 401. The first extension region 1100 may extend until overlapping with another buried gate (not shown) that may be located below the first buried gate 401. A bit line contact may be disposed in the first extension region 1100. When the first extension region 1100 is formed to extend to an adjacent buried gate, the size of the bit line contact disposed in the first extension region 1100 may be substantially increased. When the bit line contact is enlarged, resistance against the flow of current according to a voltage received from the first bit line 101 may be reduced. When the resistance of the bit line contact is reduced, the difference between the voltage applied to the first bit line 101 and the voltage applied to the first extension region 1100 may be reduced, thereby reducing power consumption.

[0052] The second extension region 1200 may be disposed between the second bit line spacer 112 and the third bit line spacer 113. In addition, the second extension region 1200 may extend from the other side surface of the first buried gate 401 in the first direction D1 without overlapping the first buried gate 401. The second extension region 1200 may extend until overlapping the second buried gate 402. A storage node contact may be disposed in the second extension region 1200. When both sides of the second extension region 1200 are disposed to contact the second bit line spacer 112 and the third bit line spacer 113, a larger area may be ensured compared to a case in which the second extension region 1200 is spaced apart from each of the second bit line spacer 112 and the third bit line spacer 113. As a result, a storage node contact that may be disposed in the second extension region 1200 may be more enlarged, and resistance against the flow of current in response to a voltage received from the first bit line 101 may be reduced. When the resistance of the storage node contact decreases, the access speed to data in the capacitor of the first active region 1001A may be increased, so that the data transmission rate may be increased, and the memory device 1 may improve power efficiency by reducing voltage loss.

[0053] The third extension region 1300 may contact the first extension region 1100 at a first line segment (e.g., line segment P1-P2 where the first extension region 1100 contacts the first buried gate 401), and may also contact the second extension region 1200 at a second line segment (e.g., line segment P3-P4 where the second extension region 1200 contacts the first buried gate 401). The third extension region 1300 may overlap the first buried gate 401. More specifically, the third extension region 1300 may be a region extending from the first line segment (e.g., line segment P1-P2) in the third direction D3 and extending to the second line segment (e.g., line segment P3-P4). The third direction D3 may form an acute angle with the first direction D1 or the second direction D2. In some embodiments, the acute angle may range from 30 degrees to 60 degrees. The width W1 of the third extension region 1300 may be constant. The width L2 of the third extension region 1300 in the second direction D2 may be equal to the width L1 of the first extension region 1100 in the second direction D2.

[0054] The first point P1 may be located at a position equivalent to the fifth to seventh points (A1, A2, A3). The first point P1 may be any one of the points that contact any one of the first to fourth buried gates (401-404), contact any one of the first to fourth bit lines (101-104), and constitute the boundaries of the first to sixteenth active regions (1001A-1016A). In more detail, the first point P1 may be any one of the points that contact any one of the first to fourth buried gates (401-404), contact any one of the first to fourth bit lines (101-104), and constitute the boundaries of the first to sixteenth active regions (1001A-1016A). Figure 1The example structure has a point corresponding to any one of the vertices of the range of 180 degrees of internal angle. The second point P2 can be located at a position equivalent to the eighth to tenth points (B1, B2, B3). The second point P2 can be any one of the points that contact any one of the first to fourth buried gates (401-404), contact any one of the first to fourth bit lines (101-104), and constitute the boundaries of the first to sixteenth active regions (1001A-1016A). In more detail, the second point P2 can be ... Figure 1 The example structure has a 180 degree interior angle range for any one of the vertices corresponding to the point.

[0055] The active regions belonging to the same column as the first active region 1001A may be arranged to be spaced apart from each other by a first distance (i.e., a first interval) in the first direction D1. For example, the second active region 1002A may be arranged to be spaced apart from the first active region 1001A by a first distance in the first direction D1, and the third active region 1003A may be arranged to be spaced apart from the second active region 1002A by a first distance in the first direction D1. The first distance may be equal to the sum of the width (toward the first direction D1) of the buried gates (401-404) and the distance between the first buried gate 401 and the second buried gate 402.

[0056] The active regions belonging to the same row as the first active region 1001A may be arranged to be spaced apart from each other by a second distance (i.e., a first interval) in the second direction D2. The second distance may be equal to the sum of the width of the first bit line 101 extending in the second direction D2 and the distance between the first bit line 101 and the second bit line 102. For example, the fifth active region 1005A may be spaced apart from the first active region 1001A by the second distance, and the ninth active region 1009A may be spaced apart from the fifth active region 1005A by the second distance.

[0057] According to the arrangement structure in which the plurality of active regions are spaced apart from each other in the column direction and the row direction, the sixth, eleventh, and sixteenth active regions (1006A, 1011A, 1016A) may be sequentially spaced apart from each other by a predetermined distance in the third direction D3.

[0058] The fifth to seventh points (A1, A2, A3) may be points located on a virtual straight line called straight line A (i.e., LA). The eighth to tenth points (B1, B2, B3) may also be points located on a virtual straight line called straight line B (i.e., LB). The distance between straight line A and straight line B may be equal to the distance W1 between the third line segment (e.g., line segment P1-P3) and the fourth line segment (e.g., line segment P2-P4) of the third extension region 1300. The third extension region 1300 may be disposed in an area where the first to fourth buried gates (401-404) and the area between straight lines A and B overlap with each other. Straight line A and straight line B are virtual straight lines, Figure 1 Only the case where the straight lines A and B pass through the second active region 1002A, the seventh active region 1007A, and the twelfth active region 1012A is shown, and other embodiments are possible, and it should be noted that the straight lines A and B can also be equally applied to multiple active regions arranged in the third direction D3. The positional relationship between the A straight line (LA) and the A straight line (LB) of the fifth to tenth points (A1-A3 and B1-B3) can correspond to an embodiment of the disclosed technology, but the scope of the disclosed technology is not limited thereto.

[0059] The deactivation region 20 may refer to a remaining region obtained when the first to sixteenth active regions (1001A to 1016A) are subtracted from the cell array of the memory device 1. Because it is difficult to show the remaining region other than the first to sixteenth active regions (1001A to 1016A) in the figure, the deactivation region 20 is shown in the figure as a portion of the space between the second bit line spacer 112 and the third bit line spacer 113. Other embodiments are also possible, and it should be noted that the remaining region may be a region corresponding to the remaining region other than the first to sixteenth active regions (1001A to 1016A) in the cell array of the memory device 1. In one embodiment, the first to fourth buried gates (401 to 404) may be disposed in a substrate region including a semiconductor layer (see Figure 6 610 in the figure), and the first to sixteenth active regions (1001A to 1016A) may be regions included in the substrate region. The first to fourth bit lines (101 to 104) and the first to eighth bit line spacers (111 to 118) may be disposed in an interconnection region disposed on the substrate region (see Figure 6 The deactivation region 20 may be disposed in the remaining substrate region where the first to sixteenth active regions (1001A to 1016A) are not disposed in the substrate region. The deactivation region 20 may be disposed in a fourth direction D4 perpendicular to all of the first to third directions D1 to D3 from the top surface of the substrate region (see Figure 610a) in the deactivation region 20 is recessed and can be set to a predetermined depth. The deactivation region 20 can prevent electrical interaction between adjacent active regions 1001A to 1016A in the active region by a structure in which an insulating material is arranged at a great depth along the fourth direction D4, and can also prevent damage to data stored in a capacitor in the active region of the memory device 1. For example, the fin space 20F disposed between the first active region 1001A and the fifth active region 1005A can correspond to a portion of the deactivation region 20. When a voltage is applied from the first bit line 101 to the first active region 1001A, charges can be moved to the second extension region 1200 along a charge transfer path through the first extension region 1100 formed to overlap the first bit line 101, and the charge transfer path can be formed at the lower portion of the first buried gate 401 overlapping the third extension region 1300. The charges moved to the second extension region 1200 through the charge transfer path can be moved to the capacitor of the first active region 1001A through a storage node contact that can be disposed in the second extension region 1200, and can be stored in the capacitor. The deactivation region 20 including the fin region 20F may have a structure that is disposed deeper than the first buried gate 401. Due to the depth difference, the deactivation region 20 including the fin region 20F may prevent charge from leaking into the fifth active region 1005A during a series of charge transfer processes, the active region 1005A being one of the active regions adjacent to the first active region 1001A. For convenience, the fin region 20F is shown only between the first active region 1001A and the fifth active region 1005A. The deactivation region 20 disposed between the active regions spaced apart from each other along the second direction D2 may be referred to as the fin region 20F. For a plurality of active regions spaced apart from each other along the first direction D1 or the third direction D3, a portion of the deactivation region 20 disposed between the active regions (1001A to 1016A) is formed as an insulating structure deeper than each buried gate (401 to 404), thereby preventing charge movement between the active regions (1001A to 1016A). Since the deactivation region 20 blocks charge movement between the active regions (1001A-1016A), the number of errors in operations of reading, writing or storing data in the capacitor of each active region (1001A-1016A) can be reduced and the reliability of the memory device 1 can be improved.

[0060] Figure 2 is a plan view showing a cell array of a memory device based on some other implementations of the disclosed technology.

[0061] Will focus on Figure 2 and Figure 1 To describe the difference between Figure 2 structure to avoid redundant descriptions.

[0062] refer to Figure 1 and Figure 2 , Figure 2 Each of the first to sixteenth active regions (1001A-1016A) may include a first extension region 1100, a second extension region 1200, and a third extension region 1300. Figure 1 A cell array of a memory device 1 according to an embodiment of the present invention Figure 2 A difference between the cell arrays of the memory device 1 of the embodiment may be an arrangement range of the first extension region 1100 and the second extension region 1200 .

[0063] In the description of the first active region 1001A, the first extension region 1100 may extend to a range in which the first extension region 1100 is arranged to be separated from an adjacent buried gate (not shown) arranged in a downward direction, and the second extension region 1200 may extend to a range in which the second extension region 1200 does not contact the second buried gate 402 (serving as an adjacent buried gate arranged in an upward direction). The memory device 1 having a cell array in which each of the first and second extension regions (1100, 1200) is arranged to extend only to a range in which each of the first extension region 1100 and the second extension region 1200 is spaced apart from its adjacent gate can be designed to prevent electrical interaction between an adjacent gate and the first extension region 1100 or the second extension region 1200, so that data reliability can be improved.

[0064] Figure 3 is a plan view showing a cell array of a memory device based on some other implementations of the disclosed technology.

[0065] Will focus on Figure 3 and Figure 1 To describe the difference between Figure 3 structure to avoid redundant descriptions.

[0066] Reference Figure 1 and Figure 3 , Figure 3 The active regions (1001A-1016A) can be similar in shape and repeated arrangement structure. Figure 1 The active regions (1001A to 1016A) of the MOSFET are substantially the same. Figure 3 The buried gates (401-404) shown in FIG. Figure 1 The buried gates ( 401 ˜ 404 ) are arranged at different positions. In addition, the bit line contact may be disposed not only in the first extension region 1100 , but also in a portion 1301 of the third extension region 1300 overlapping with the first bit line 101 .

[0067] For the convenience of description, the following description will be based on the second active region 1002A. Figure 3 The first to third buried gates (401-403) can be arranged in the following manner Figure 3 In the structure of: the first extension region 1100 of the second active region 1002A partially overlaps with the first buried gate 401 used as an adjacent buried gate, the second extension region 1200 partially overlaps with the buried gate 402, and the second extension region 1200 is spaced apart from the third buried gate 403 used as an adjacent buried gate. The distance between the first buried gate 401 and the second buried gate 402 may be the same as the distance between the second buried gate 402 and the third buried gate 403. Figure 3 In the illustrated embodiment, the region in which the bit line contact may be disposed may be expanded, thereby reducing resistance to a voltage received from the first bit line 101. In addition, the storage node contact may cause electrical interference to the third buried gate 403 serving as an adjacent gate to which a voltage may be applied, and a structure in which the second extension region 1200 in which the storage node contact may be disposed is spaced apart from the third buried gate 403 may block the electrical interference.

[0068] Figure 4 is a plan view showing a cell array of a memory device based on some other implementations of the disclosed technology.

[0069] Will focus on Figure 4 and Figure 1 To describe the difference between Figure 4 structure to avoid redundant descriptions.

[0070] Reference Figure 1 and Figure 4 , Figure 4 The third extension regions 1300D of the first to sixteenth active regions (1001B-1016B) may be different in structure from Figure 1 The third extension region 1300 of the first to sixteenth active regions (1001A~1016A).

[0071] Figure 4 The virtual straight line A(LA) and virtual straight line B(LB) can be equivalent to Figure 1 The virtual straight line A(LA) and the virtual straight line B(LB) are virtual straight lines. The virtual straight line A'(LA') may be a virtual straight line extending from one end of the third extension area 1300D in the third direction D3, and the virtual straight line B'(LB') may be a virtual straight line extending from the other end of the third extension area 1300D in the third direction D3. When the distance between the virtual straight line A(LA) and the virtual straight line B(LB) is W1 and the distance between the virtual straight line A'(LA') and the virtual straight line B'(LB') is W2, W2 may have a value greater than W1. W2 may refer to the width of the third extension area 1300D extending in the third direction D3, and Figure 4 The width W2 of the third extension region 1300D may be greater than Figure 1When the width W2 of the third extension region 1300D in the third direction D3 increases and a voltage for writing data is applied to the first bit line 101 formed to overlap the first extension region 1100, a charge transfer path in a lower portion (arranged along the direction D4) of the first buried gate 401 that may be formed in the third extension region 1300D may be extended, thereby improving a data transfer rate.

[0072] The width of the third extension region 1300D in the second direction D2 may be greater than the width of the first extension region 1100 in the second direction D2. Figure 4 The width of the third extension region 1300D in the second direction D2 is greater than Figure 1 The width L2 of the third extension region 1300 can also be applied to Figure 2 and Figure 3 Each one of them.

[0073] Figure 5 is a plan view showing a cell array of a memory device based on some other implementations of the disclosed technology.

[0074] Will focus on Figure 5 and Figure 1 To describe the difference between Figure 5 structure to avoid redundant descriptions.

[0075] Reference Figure 1 and Figure 5 , Figure 5 The second extension regions 1200D of the first to sixteenth active regions (1001C-1016C) may be different in structure from Figure 1 The second extension region 1200 of the first to sixteenth active regions (1001A~1016A).

[0076] and Figure 1 Differently, referring to the first active region 1001C, the second extension region 1200D may be disposed to be spaced apart from each of the second and third bit line spacers (112, 113) without contacting the second and third bit line spacers 112 and 113. A gap space 50 may be formed between the second extension region 1200D and the second bit line spacer 112, and the gap space 50 may be formed between the second extension region 1200D and the third bit line spacer 113. The gap space 50 may contain a material having a low dielectric constant (e.g., air).

[0077] The gap space 50 is formed between the second extension region 1200D and each of the second bit line spacer 112 and the third bit line spacer 113. The gap space 50 can reduce parasitic capacitance that may occur in each of the second bit line spacer 112 and the third bit line spacer 113. In the arrangement of the gap space 50, Figure 5 The distance between the first bit line 101 and the second bit line 102 may be greater than Figure 1 The distance between the first bit line 101 and the second bit line 102 is . Figure 5 The gap space of 50 can also be applied to Figures 1 to 4 Each embodiment of .

[0078] In the following, reference will be made to Figure 1 The cutting line is cut Figures 6 to 10 For the sake of brevity, the cross-sectional view of Figures 6 to 10 The description of the same constituent elements is repeated to avoid redundant description thereof.

[0079] Figure 6 is a diagram showing an example of a memory device 1 based on some implementations of the disclosed technology. Figure 1 600 is a cross-sectional view taken along line II′.

[0080] Reference Figure 1 and Figure 6 , along Figure 1 The first cross section 600 of the cell array of the memory device 1 taken along the line II′ shown may be an example of a cross-sectional view of the cell array taken along the line II′. Figure 1 The cross-section is taken along line II' shown, but the scope of the disclosed technology is not limited to this, and it should be noted that a cross-sectional view of another portion of the cell array of the storage device 1 corresponding to line II' (for example, a line alternately passing through the first extension region 1100 and the second extension region 1200) may also have a structure substantially the same as the first cross-section 600.

[0081] A first cross section 600 of a cell array of the memory device 1 may include a substrate region 610 and an interconnection region 620 disposed on the substrate region 610. The substrate region 610 may include a semiconductor layer 10, at least one deactivation region 20, at least one first extension region 1100, and at least one second extension region 1200.

[0082] The semiconductor layer 10 may refer to the remaining area except for the activation area 20 recessed from the top surface 10a of the substrate area 610 into the substrate area 610. That is, the semiconductor layer 10 may include the first extension area 1100, the second extension area 1200, the deactivation area 20, and an area disposed below the lower end of each of the first extension area 1100 and the second extension area (1100, 1200). Although the semiconductor layer 10 is shown as being separated from each of the first extension area 1100 and the second extension area 1200, as shown in FIG. Figure 6 However, this diagram can be used to indicate Figure 1 The semiconductor layer 10 may include a portion corresponding to each of the first extension region 1100 and the second extension region 1200, and it should be noted that the first extension region 1100 and the second extension region 1200 may be a portion of the semiconductor layer 10. The semiconductor layer 10 may include silicon (Si).

[0083] The deactivation region 20 may be arranged to be recessed from the top surface 10a into the substrate region 610. The deactivation region 20 may include a plurality of deactivation regions 20 spaced apart from each other by a predetermined distance along the top surface 10a. The first extension region 1100 and the second extension region 1200 may fill the space between adjacent deactivation regions 20 in an alternating manner. The deactivation region 20 may include an insulating material. For example, the deactivation region 20 may include at least one of silicon oxide or oxynitride. The deactivation region 20 may prevent the movement of charges between the first extension region and the second extension region (1100, 1200) that may be located in the space between the deactivation regions 20.

[0084] The first extension region 1100 and the second extension region 1200 may be alternately arranged between the deactivation regions 20 spaced apart from each other by a predetermined distance. For example, the deactivation region 20, then the first extension region 1100, then another deactivation region 20, and then the second extension region 1200 may be sequentially arranged along the top surface 10a, and the pattern may be repeated multiple times as needed. Each of the first extension region 1100 and the second extension region 1200 may include silicon (Si). The first extension region 1100 and the second extension region 1200 may include the same material as the semiconductor layer 10. Each of the first extension region 1100 and the second extension region 1200 may include a region doped with an ion material. For example, when the first extension region 1100 and the second extension region 1200 are doped with positive (+) ions (i.e., cations), the positive ions may reduce the energy loss required for charge movement, thereby realizing a memory device 1 with less power consumption.

[0085] The interconnection region 620 may include fifth to eighth bit line spacers ( 115 ˜ 118 ), third and fourth bit lines ( 103 , 104 ), at least one bit line contact 120 , at least one barrier metal layer 130 , at least one nitride pattern layer 140 , and at least one storage node contact 300 .

[0086] The fifth to eighth bit line spacers (115-118) may be disposed on the deactivation region 20 spaced a predetermined distance apart from each other. Each of the fifth to eighth bit line spacers (115-118) may completely overlap a corresponding one of the deactivation regions 20. The width of each of the fifth to eighth bit line spacers (115-118) may be equal to the width of each of the deactivation regions 20.

[0087] Each bit line contact 120 may be disposed above each first extension region 1100. The bit line contact 120 may provide an electrical connection between the first extension region 1100 and the third bit line 103, or provide an electrical connection between the first extension region 1100 and the fourth bit line 104. For example, data may be read from or written in the eleventh active region 1011A. The bit line contact 120 may include a metal material (e.g., aluminum (Al) or copper (Cu)).

[0088] The barrier metal layer 130 may be disposed at Figure 6 The left bit line contact 120 of the two bit line contacts 120 shown and the third bit line contact 103, and can be arranged between the right bit line contact 120 and the fourth bit line 104. The barrier metal layer 130 can be arranged between the bit line contact 120 and the bit line (e.g., the third bit line 103) to reduce the electrical contact resistance and to reduce unnecessary signal noise. The barrier metal layer 130 may include a metal material. For example, the barrier metal layer 130 may include a material containing titanium (Ti) (e.g., TiN).

[0089] The nitride pattern layer 140 may be disposed over the third bit line 103 and the fourth bit line 104. The nitride pattern layer 140 may prevent the third bit line 103 and the fourth bit line 104 from being contaminated by external substances and may electrically insulate upper portions of the third bit line 103 and the fourth bit line 104. The nitride pattern layer 140 may include a nitride (e.g., oxynitride).

[0090] The storage node contact 300 may be disposed on the second extension region 1200. The left storage node contact 300 may connect the tenth active region 1010A (see Figure 1 ) is electrically connected to the second extension region 1200, and the right storage node contact 300 can connect the fourteenth active region 1014A (see Figure 1) is electrically connected to the second extension region 1200. The storage node contact 300 may include a metal material. For example, the storage node contact 300 may include at least one of titanium, titanium carbide, and titanium nickel.

[0091] Figure 7 is an example of a memory device 1 based on some implementations of the disclosed technology. Figure 1 A cross-sectional view taken along line II-II'.

[0092] Reference Figure 1 and Figure 7 , the cell array of the memory device 1 is along Figure 1 The second cross section 700 taken along the line II-II' shown may be an example of a cross-sectional view of the cell array taken along the line II-II'. Figure 1 The cross-section shown is taken along line II-II', but the scope of the disclosed technology is not limited to this, and it should be noted that a cross-sectional view of another portion of the cell array of the memory device 1 corresponding to line II-II' (e.g., a line passing through an active area) may also have a structure substantially the same as the second cross-section 700.

[0093] The second cross section 700 may include a substrate region 710 and an interconnection region 720 disposed on the substrate region 710. The substrate region 710 may include a first buried gate metal layer 411, a first buried gate insulating layer 421, a first buried gate nitride layer 431, a first buried gate oxide layer 441, a semiconductor layer 10, a first extension region 1100, a second extension region 1200, and a third extension region 1300.

[0094] The first buried gate oxide layer 441 may be disposed at an inner wall of a trench recessed from the top surface 10a. The first buried gate oxide layer 441 may prevent electrical interaction between the third extension region 1300 and the first buried gate metal layer 411. The first buried gate oxide layer 441 may include an insulating material (eg, silicon oxide).

[0095] The first buried gate metal layer 411 may be disposed on the first buried gate oxide layer 441. The first buried gate metal layer 411 may be used to select and access the ninth active region 1009A. The first buried gate metal layer 411 may be used to apply a voltage to the ninth active region 1009A. The first buried gate metal layer 411 may include a metal material.

[0096] The first buried gate insulating layer 421 may be disposed on the first buried gate metal layer 411. The first buried gate insulating layer 421 may adjust resistance of the first buried gate 401 including the first buried gate insulating layer 421 and the first buried gate metal layer 411. The first buried gate insulating layer 421 may include an insulating material (eg, polysilicon).

[0097] The first buried gate nitride layer 431 may be disposed to extend from the first buried gate insulating layer 421 to the top surface 10a. The first buried gate nitride layer 431 may prevent current caused by a voltage applied to the first buried gate metal layer 411 from leaking toward the top surface 10a. The first buried gate nitride layer 431 may include an insulating material (e.g., oxynitride, silicon nitride, etc.).

[0098] The third extension region 1300 may be disposed below the stack structure of the first buried gate oxide layer 441, the first buried gate metal layer 411, the first buried gate insulating layer 421, and the first buried gate nitride layer 431 (hereinafter referred to as the stack structure of the first buried gate 401). The third extension region 1300 may be disposed between the first extension region 1100 and the second extension region 1200. The third extension region 1300 may be included in the semiconductor layer 10. Although the semiconductor layer 10 is shown as being separated from the first extension region 1100 and the second extension region 1200, as shown in FIG. Figure 7 However, the scope of the disclosed technology is not limited thereto. Such a diagram may be used to indicate the second cross section 700. Figure 1 The third extension region 1300 may be a portion corresponding to each extension region (1100, 1200, 1300), and it should be noted that the third extension region 1300 may also be a region included in the semiconductor layer 10 like the first extension region 1100 and the second extension region 1200. The third extension region 1300 may provide a channel (or passage) 80 (e.g., a portion of the channel 80) through which charges may move between the first extension region 1100 and the second extension region 1200. The third extension region 1300 may include the same material as the semiconductor layer 10. For example, the third extension region 1300 may include silicon (Si). The third extension region 1300 may include a region doped with ions. When the third extension region 1300 includes a region doped with positive (+) ions, the doped positive ions may increase the carrier mobility of the channel 80, which represents the channel through which the charges move. As the carrier mobility of the channel 80 increases, the data transmission rate may also increase.

[0099] The interconnection region 720 may include a bit line contact 120 , a barrier metal layer 130 , a nitride pattern layer 140 , a third bit line 103 , a sixth bit line spacer 116 , a contact insulating layer 450 , and a storage node contact 300 .

[0100] The bit line contact 120 may be disposed on the first extension region 1100. The barrier metal layer 130 may be disposed on the bit line contact 120. The third bit line 103 may be disposed on the barrier metal layer 130. The third bit line 103 may be disposed longer than the barrier metal layer 130. The nitride pattern layer 140 may be disposed on the third bit line 103. The storage node contact 300 may be disposed on the second extension region 1200. The sixth bit line spacer 116 may be disposed on the stack structure of the first buried gate 401 and may be disposed to have a smaller width than the stack structure of the first buried gate 401. A portion of one side surface of the sixth bit line spacer 116 may contact the third bit line 103 and the nitride pattern layer 140. The remaining portion of one side surface of the sixth bit line spacer 116 and the other side surface of the sixth bit line spacer 116 may contact the contact insulating layer 450.

[0101] The contact insulating layer 450 may be disposed on the stacked structure of the first buried gate 401 where the sixth bit line spacer 116 is not disposed. Of the two contact insulating layers 450 shown in the second cross section 700, the left contact insulating layer 450 may be disposed between the third bit line 103 and the top surface 10a of the substrate region 710, and the right contact insulating layer 450 may be disposed between the sixth bit line spacer 116 and the storage node contact 300 disposed on the second extension region 1200. The contact insulating layer 450 may be in contact at its bottom surface with the top surface of the first buried gate nitride layer 431 and the top surface of the first buried gate oxide layer 441 at the same level as the top surface 10a of the substrate region 710. The contact insulating layer 450 may prevent electrical interaction between the third bit line 103, the bit line contact 120, the first buried gate metal layer 411, and the storage node contact 300. The contact insulating layer 450 may include at least one of an oxide or an oxynitride.

[0102] When voltage is applied to the third bit line 103 in the ninth active region 1009A, the channel 80 may be used as a charge transfer path extending from a portion of the first extension region 1100 in contact with the bit line contact 120 to another portion of the second extension region 1200 in contact with the storage node contact 300 along the third extension region 1300 disposed under the stack structure of the first buried gate 401. When voltage is applied to the third bit line 103, charges may move from the third bit line 103 to the first extension region 1100 through the barrier metal layer 130 and the bit line contact 120. Charges that have reached the first extension region 1100 may move to the storage node contact 300 after passing through the third extension region 1300 and the second extension region 1200 through the channel 80, so that the resulting charges may move to a capacitor electrically connected to the storage node contact 300.

[0103] Figure 8is an example of a memory device based on some implementations of the disclosed technology. Figure 1 A cross-sectional view taken along line III-III'.

[0104] Reference Figure 1 and Figure 8 , the cell array of the memory device 1 is along Figure 1 The third cross section 800 taken along line III-III' may be an example of a cross-sectional view of the cell array taken along line III-III'. Figure 1 The cross-section is taken along line III-III' shown in the figure, but the scope of the disclosed technology is not limited to this, and it should be noted that a cross-sectional view of another portion of the cell array of the memory device 1 corresponding to line III-III' (for example, a line formed to pass through the buried gate in the second direction D2) may also have a structure substantially the same as the third cross-section 800.

[0105] The third cross section 800 may include a substrate region 810 and an interconnection region 820. The substrate region 810 may include a second buried gate metal layer 412, a second buried gate insulation layer 422, a second buried gate nitride layer 432, a second buried gate oxide layer 442, a semiconductor layer 10, a third extension region 1300, and a deactivation region 20.

[0106] The second buried gate nitride layer 432 may be disposed in the substrate region 810 along the top surface 10a of the substrate region 810. The second buried gate nitride layer 432 may prevent a current caused by a voltage applied to the second buried gate metal layer 412 from leaking toward the top surface 10a. The second buried gate nitride layer 432 may include an insulating material (e.g., oxynitride, silicon nitride, etc.).

[0107] The second buried gate insulating layer 422 may be disposed under the second buried gate nitride layer 432. The second buried gate insulating layer 422 may adjust the resistance of the second buried gate 402 including the second buried gate insulating layer 422 and the second buried gate metal layer 412. The second buried gate insulating layer 422 may include an insulating material (eg, polysilicon).

[0108] The second buried gate metal layer 412 may be disposed below the second buried gate insulating layer 422. The second buried gate metal layer 412 formed at a portion adjacent to the deactivation region 20 in a direction perpendicular to the top surface 10a may have a greater thickness than the second buried gate metal layer 412 formed at a portion adjacent to the third extension region 1300 in a direction perpendicular to the top surface 10a. The second buried gate metal layer 412 may be used to provide a second buried gate metal layer 412 to an active region (e.g., Figure 8The second buried gate metal layer 412 may include a metal material.

[0109] The second buried gate oxide layer 442 may be disposed under the second buried gate metal layer 412. The second buried gate oxide layer 442 may adjust electrical interaction between the second buried gate metal layer 412 and the third extension region 1300. The second buried gate oxide layer 442 may include an insulating material (eg, silicon oxide).

[0110] Each of the deactivation regions 20 may be disposed adjacent to a region where the second buried gate metal layer 412 having a greater thickness is disposed in a direction perpendicular to the top surface 10 a , and may contact the second buried gate oxide layer 442 .

[0111] The third extension regions 1300 may be respectively disposed in the spaces between the deactivation regions 20. Corresponding to the structure in which the second buried gate metal layer 412 is not disposed too thick, the third extension regions 1300 may be disposed thicker than the deactivation regions 20. The semiconductor layer 10 may be disposed at a deeper depth within the substrate region 810 than in the region in which the deactivation regions 20 and the third extension regions 1300 are disposed in the substrate region 810.

[0112] The interconnection region 820 may include fifth to eighth bit line spacers (115-118), third and fourth bit lines (103, 104), at least one nitride pattern layer 140, and at least one contact insulating layer 450.

[0113] The fifth to eighth bit line spacers (115118) may be spaced a predetermined distance apart from each other on the top surface 10a of the substrate region 810. Each of the sixth and eighth bit line spacers 116 may be aligned and disposed on the top surface 10a of the region where the third extension region 1300 is disposed.

[0114] The third bit line 103 may be disposed between the fifth bit line spacer 115 and the sixth bit line spacer 116. The third bit line 103 may be disposed on the contact insulating layer 450.

[0115] The fourth bit line 104 may be disposed between the seventh bit line spacer 117 and the eighth bit line spacer 118. The fourth bit line 104 may be disposed on the contact insulating layer 450.

[0116] The nitride pattern layers 140 may be disposed on the third bit lines 103 and the fourth bit lines 104 , respectively.

[0117] The contact insulating layer 450 may be disposed respectively under the third bit line 103 and the fourth bit line 104. Each contact insulating layer 450 may also be disposed between the sixth bit line spacer 116 and the seventh bit line spacer 117. The contact insulating layer 450 may also be disposed on the right side of the eighth bit line spacer 118. The contact insulating layer 450 may be disposed in a gap space where no bit line is disposed among the spaces between the bit line spacers.

[0118] Fig. 9 is a diagram showing some implementations of memory devices based on the disclosed technology. Figure 1 A cross-sectional view taken along line IV-IV'.

[0119] Reference Figure 1 and Fig. 9 , the cell array of the memory device 1 is along Figure 1 The fourth cross section 900 taken along the line IV-IV' shown in FIG. 1 shows a cross-sectional view of the cell array taken along the line IV-IV'. Figure 1 The cross-section shown is taken along line IV-IV', but the scope of the disclosed technology is not limited to this, and it should be noted that a cross-sectional view of another portion of the cell array of the memory device 1 corresponding to line IV-IV' (for example, a line formed to cross the bit line in the first direction D1) may also have a structure substantially the same as that of the fourth cross-section 900.

[0120] The fourth cross section 900 may include a substrate region 910 and an interconnection region 920 disposed over the substrate region 910 .

[0121] The substrate region 910 may include a third buried gate metal layer 413, a third buried gate insulation layer 423, a third buried gate nitride layer 433, a third buried gate oxide layer 443, a fourth buried gate metal layer 414, a fourth buried gate insulation layer 424, a fourth buried gate nitride layer 434, a fourth buried gate oxide layer 444, a semiconductor layer 10, at least one first extension region 1100, at least one third extension region 1300 and at least one deactivation region 20.

[0122] The third buried gate oxide layer 443 may be disposed along an inner wall of a predetermined area recessed from a portion of the top surface 10a into the substrate area 910. The first extension area 1100 may be disposed on both sides of the third buried gate oxide layer 443, respectively. The third extension area 1300 and the deactivation area 20 may be disposed below the third buried gate oxide layer 443. The third buried gate oxide layer 443 may be disposed at a deeper depth in an area where the third buried gate oxide layer 443 is adjacent to the deactivation area 20 than in another area where the third buried gate oxide layer 443 is adjacent to the third extension area 1300. The third buried gate oxide layer 443 may prevent electrical interaction between the third buried gate metal layer 413 and the first extension area 1100, and may also prevent electrical interaction between the third buried gate metal layer 413 and the third extension area 1300. The third buried gate oxide layer 443 may include an insulating material (e.g., silicon oxide).

[0123] The third buried gate metal layer 413 may be disposed on the third buried gate oxide layer 443. The top surface of the third buried gate metal layer 413 may be formed to be flat. The third buried gate metal layer 413 may be used to apply a voltage to an active region connected to the third buried gate 403. The third buried gate metal layer 413 may include a metal material.

[0124] The third buried gate insulating layer 423 may be disposed on the third buried gate metal layer 413. The third buried gate insulating layer 423 may adjust resistance of the third buried gate 403 including the third buried gate insulating layer 423 and the third buried gate metal layer 413. The third buried gate insulating layer 423 may include an insulating material (eg, polysilicon).

[0125] The third buried gate nitride layer 433 may be formed to extend from the top surface of the third buried gate insulating layer 423 to the top surface 10a. The third buried gate nitride layer 433 may prevent current caused by a voltage applied to the third buried gate metal layer 413 from leaking toward the top surface 10a. The third buried gate nitride layer 433 may include an insulating material (e.g., oxynitride, silicon nitride, etc.).

[0126] The fourth buried gate oxide layer 444 may be disposed along an inner wall of a predetermined area recessed from another portion of the top surface 10a into the substrate area 910. The first extension area 1100 may be disposed on a side surface of the fourth buried gate oxide layer 444. The third extension area 1300 and the deactivation area 20 may be disposed below the fourth buried gate oxide layer 444. The fourth buried gate oxide layer 444 may be disposed at a deeper depth in an area where the fourth buried gate oxide layer 444 is adjacent to the deactivation area 20 than in another area where the fourth buried gate oxide layer 444 is adjacent to the third extension area 1300. The fourth buried gate oxide layer 444 may prevent electrical interaction between the fourth buried gate metal layer 414 and the first extension area 1100, and may also prevent electrical interaction between the fourth buried gate metal layer 414 and the third extension area 1300.

[0127] The fourth buried gate metal layer 414 may be disposed on the fourth buried gate oxide layer 444, but an upper portion of the fourth buried gate oxide layer 444 may be exposed. The fourth buried gate metal layer 414 is added to a level lower than a top surface of the fourth buried gate oxide layer 444. A top surface of the fourth buried gate metal layer 414 may be formed to be flat and may be at a level lower than a top surface of the fourth buried gate oxide layer 444. The fourth buried gate metal layer 414 may be used to apply a voltage to an active region connected to the fourth buried gate 404. The fourth buried gate metal layer 414 may include a metal material.

[0128] The fourth buried gate insulating layer 424 may be disposed on the fourth buried gate metal layer 414. The fourth buried gate insulating layer 424 may adjust resistance of the fourth buried gate 404 including the fourth buried gate insulating layer 424 and the fourth buried gate metal layer 414. The fourth buried gate insulating layer 424 may include an insulating material (eg, polysilicon).

[0129] The fourth buried gate nitride layer 434 may be formed to extend from the top surface of the fourth buried gate insulating layer 424 to the top surface 10a. The fourth buried gate nitride layer 434 may prevent a current caused by a voltage applied to the fourth buried gate metal layer 414 from leaking toward the top surface 10a. The fourth buried gate nitride layer 434 may include an insulating material (e.g., oxynitride, silicon nitride, etc.).

[0130] Among the two first extension regions 1100, the left first extension region 1100 may contact the left side of the third buried gate oxide layer 443, and may be disposed inside the substrate region 910 from the top surface 10a. Among the two first extension regions 1100, the right first extension region 1100 may contact the right side of the third buried gate oxide layer 443, may contact the left side of the fourth buried gate oxide layer 444, and may be disposed inside the substrate region 910 from the top surface 10a.

[0131] Among the two third extension regions 1300, the left third extension region 1300 may contact a portion of the right side of the left first extension region 1100 and may be disposed under the third buried gate oxide layer 443. The left third extension region 1300 may contact the left side of the left first deactivation region 20. Among the two third extension regions 1300, the right third extension region 1300 may contact a portion of the right side of the right first extension region 1100 and may be disposed under the fourth buried gate oxide layer 444. The right third extension region 1300 may contact the left side of the right deactivation region 20.

[0132] Among the two deactivation regions 20, the left deactivation region 20 may be disposed under the third buried gate oxide layer 443 located under the portion of the third buried gate metal layer 413 provided with a larger thickness. The third extension region 1300 may be disposed on the left side of the left deactivation region 20, and the first extension region 1100 may be disposed on the right side of the left deactivation region 20. Among the two deactivation regions 20, the right deactivation region 20 may be disposed under the fourth buried gate oxide layer 444 located under the portion of the fourth buried gate metal layer 414 provided with a larger thickness. The third extension region 1300 may be disposed on the left side of the right deactivation region 20. For example, the left deactivation region 20 may prevent electrical interaction between a predetermined channel that may be formed in the left first extension region 1100 and the left third extension region 1300 and another predetermined channel that may be formed in the right first extension region 1100 and the right third extension region 1300.

[0133] The semiconductor layer 10 may be disposed under the first extension region 1100 , the third extension region 1300 , and the deactivation region 20 .

[0134] The interconnection region 920 may include at least one bit line contact 120 , at least one barrier metal layer 130 , at least one contact insulating layer 450 , a first bit line 101 , and a nitride pattern layer 140 .

[0135] The bit line contacts 120 may be disposed on the first extension regions 1100 , respectively.

[0136] Barrier metal layers 130 may be disposed on the bit line contacts 120 , respectively.

[0137] Each contact insulating layer 450 may be disposed on the top surface 10a in a region where the bit line contact 120 is not disposed. The contact insulating layer 450 may be formed to extend to a lower portion of the first bit line 101.

[0138] The first bit line 101 may be disposed flat on the barrier metal layer 130 and the contact insulating layer 450 and have a constant thickness thereon.

[0139] The nitride pattern layer 140 may be disposed on the first bit line 101 .

[0140] Fig.10 is a diagram showing some implementations of memory devices based on the disclosed technology. Figure 1 A cross-sectional view taken along line V-V'.

[0141] Reference Figure 1 and Fig.10 , the cell array of memory device 1 is along Figure 1 The fifth cross section 1000 taken along the line VV′ is a cross-sectional view of the cell array taken along the line VV′. Figure 1 The cross-section shown is taken along the line V-V', but the scope of the disclosed technology is not limited to this, and it should be noted that a cross-sectional view of another portion of the cell array of the memory device 1 corresponding to the line V-V' (for example, a line formed to pass through the second extension region 1200 and extend in the first direction D1) may also have a structure substantially the same as the fifth cross-section 1000.

[0142] The fifth cross section 1000 may include a substrate region 1010 and an interconnection region 1020 .

[0143] The substrate region 1010 may include a third buried gate metal layer 413, a third buried gate insulation layer 423, a third buried gate nitride layer 433, a third buried gate oxide layer 443, a fourth buried gate metal layer 414, a fourth buried gate insulation layer 424, a fourth buried gate nitride layer 434, a fourth buried gate oxide layer 444, a semiconductor layer 10, at least one second extension region 1200, at least one third extension region 1300 and at least one deactivation region 20.

[0144] The third buried gate oxide layer 443 may be disposed along an inner wall of a predetermined area recessed from a portion of the top surface 10a into the substrate area 1010. The second extension area 1200 may be disposed on both sides of the third buried gate oxide layer 443, respectively. The third extension area 1300 and the deactivation area 20 may be disposed below the third buried gate oxide layer 443. The third buried gate oxide layer 443 may be disposed at a deeper depth in an area where the third buried gate oxide layer 443 is adjacent to the deactivation area 20 than in another area where the third buried gate oxide layer 443 is adjacent to the third extension area 1300. The third buried gate oxide layer 443 may prevent electrical interaction between the third buried gate metal layer 413 and the second extension area 1200, and may also prevent electrical interaction between the third buried gate metal layer 413 and the third extension area 1300. The third buried gate oxide layer 443 may include an insulating material (e.g., silicon oxide).

[0145] The third buried gate metal layer 413 may be disposed on the third buried gate oxide layer 443. The top surface of the third buried gate metal layer 413 may be formed to be flat. The third buried gate metal layer 413 may be used to apply a voltage to an active region connected to the third buried gate 403. The third buried gate metal layer 413 may include a metal material.

[0146] The third buried gate insulating layer 423 may be disposed on the third buried gate metal layer 413. The third buried gate insulating layer 423 may adjust resistance of the third buried gate 403 including the third buried gate insulating layer 423 and the third buried gate metal layer 413. The third buried gate insulating layer 423 may include an insulating material (eg, polysilicon).

[0147] The third buried gate nitride layer 433 may be formed to extend from the top surface of the third buried gate insulating layer 423 to the top surface 10a. The third buried gate nitride layer 433 may prevent current caused by a voltage applied to the third buried gate metal layer 413 from leaking toward the top surface 10a. The third buried gate nitride layer 433 may include an insulating material (e.g., oxynitride, silicon nitride, etc.).

[0148] The fourth buried gate oxide layer 444 may be disposed along an inner wall of a predetermined area recessed from another portion of the top surface 10a into the substrate region 1010. The second extension region 1200 may be disposed on a side surface of the fourth buried gate oxide layer 444. The third extension region 1300 and the deactivation region 20 may be disposed below the fourth buried gate oxide layer 444. The fourth buried gate oxide layer 444 may be disposed at a deeper depth in an area where the fourth buried gate oxide layer 444 is adjacent to the deactivation region 20 than in another area where the fourth buried gate oxide layer 444 is adjacent to the third extension region 1300. The fourth buried gate oxide layer 444 may prevent electrical interaction between the fourth buried gate metal layer 414 and the second extension region 1200, and may also prevent electrical interaction between the fourth buried gate metal layer 414 and the third extension region 1300. The fourth buried gate oxide layer 444 may include an insulating material (e.g., silicon oxide).

[0149] The fourth buried gate metal layer 414 may be disposed on the fourth buried gate oxide layer 444. A top surface of the fourth buried gate metal layer 414 may be formed to be flat. The fourth buried gate metal layer 414 may be used to apply a voltage to an active region connected to the fourth buried gate 404. The fourth buried gate metal layer 414 may include a metal material.

[0150] The fourth buried gate insulating layer 424 may be disposed on the fourth buried gate metal layer 414. The fourth buried gate insulating layer 424 may adjust resistance of the fourth buried gate 404 including the fourth buried gate insulating layer 424 and the fourth buried gate metal layer 414. The fourth buried gate insulating layer 424 may include an insulating material (eg, polysilicon).

[0151] The fourth buried gate nitride layer 434 may be formed to extend from the top surface of the fourth buried gate insulating layer 424 to the top surface 10a. The fourth buried gate nitride layer 434 may prevent a current caused by a voltage applied to the fourth buried gate metal layer 414 from leaking toward the top surface 10a. The fourth buried gate nitride layer 434 may include an insulating material (e.g., oxynitride, silicon nitride, etc.).

[0152] Among the two second extension regions 1200, the left second extension region 1200 may contact the right side of the third buried gate oxide layer 443, may contact the left side of the fourth buried gate oxide layer 444, and may be disposed in the substrate region 1010 and extend from the top surface 10a. Among the two second extension regions 1200, the right second extension region 1200 may contact the right side of the fourth buried gate oxide layer 444, and may be disposed in the substrate region 1010 and extend from the top surface 10a.

[0153] Among the two third extension regions 1300, the left third extension region 1300 may contact a portion of the left side of the left second extension region 1200, and may be disposed under the third buried gate oxide layer 443. The left third extension region 1300 may contact the right side of the left deactivation region 20 of the two deactivation regions 20. Among the two third extension regions 1300, the right third extension region 1300 may contact the right side of the left deactivation region 20, may contact a portion of the left side of the right second extension region 1200, and may be disposed under the fourth buried gate oxide layer 444.

[0154] The left deactivation region 20 may be disposed under the third buried gate oxide layer 443 located under the portion where the third buried gate metal layer 413 having a larger thickness is disposed. The third extension region 1300 may be disposed on the right side of the left deactivation region 20. Among the two deactivation regions 20, the right deactivation region 20 may be disposed under the fourth buried gate oxide layer 444 located under the portion where the fourth buried gate metal layer 414 having a larger thickness is disposed. The second extension region 1200 may be disposed on the left side of the right deactivation region 20, and the third extension region 1300 may be disposed on the right side of the right deactivation region 20. For example, the right deactivation region 20 may prevent electrical interaction between a predetermined channel that may be formed in the left second extension region 1200 and the left third extension region 1300 and another predetermined channel that may be formed in the right second extension region 1200 and the right third extension region 1300.

[0155] The semiconductor layer 10 may be disposed under the second extension region 1200 , the third extension region 1300 , and the deactivation region 20 .

[0156] The interconnection region 1020 may include at least one storage node contact 300 and at least one contact insulating layer 450 .

[0157] The storage node contacts 300 may be disposed on the second extension regions 1200 , respectively.

[0158] The contact insulating layer 450 may be disposed on the top surface 10a in a region where the storage node contacts 300 are not disposed. The contact insulating layer 450 may prevent electrical interaction between the storage node contacts 300, and may also prevent electrical interaction between each of the storage node contacts 300 and each of the third buried gate 403 and the fourth buried gate 404.

[0159] Referring to the above embodiments according to the present disclosure Figures 6 to 10 A cross-sectional view of Figures 2 to 5 The cross section can be easily modified by a technician in the field to which the disclosed technology belongs.

[0160] also, Figures 6 to 9 A cross-sectional view of a memory device in which a bit line contact 120 is disposed on a top surface 10 a of substrate regions 610 , 710 , 810 , and 910 is shown. Figure 1 The modified embodiment may include a bit line contact 120 and first to fourth bit lines (101-104) disposed to be buried in substrate regions 610, 710, 810, and 910. Figures 6 to 9 Compared with the embodiment of the present invention, in the modified embodiment, the first to fourth buried gates (401-404) can be disposed at a deeper depth. When the first to fourth bit lines (101-104) are buried, parasitic capacitance that may be formed in the first to eighth bit line spacers (111-118) can be reduced.

[0161] As is apparent from the above description, a semiconductor device based on some implementations of the disclosed technology can facilitate the manufacturing process of a bit line contact and a storage node contact, and can ensure a contact area, thereby ensuring necessary resistance. In addition, the disclosed technology can provide a storage semiconductor device in which a large fin area is ensured by the shape of the active area, and capacitance is ensured by the arrangement in which the active areas are regularly spaced apart from each other.

[0162] Embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized through the above-described embodiments of the present disclosure.

[0163] Those skilled in the art will appreciate that the disclosed technology can be implemented in other specific ways different from the ways set forth herein. In addition, claims that are not explicitly proposed in the appended claims can be proposed as embodiments in combination through subsequent amendments after the application is submitted, or included as new claims.

[0164] Although a number of exemplary embodiments have been described, it should be understood that modifications and / or improvements to the disclosed embodiments and other embodiments may be designed based on the content described and / or shown in the present disclosure. In addition, these embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: a first buried gate extending in a first direction; A bit line contact, which is disposed on one side of the first buried gate and is located outside the first buried gate; a storage node contact, which is arranged on the other side of the first buried gate along the diagonal direction of the bit line contact and is located outside the first buried gate; as well as a plurality of repeatedly arranged active regions which are spaced apart from each other by a predetermined distance in the first direction and overlap with the first buried gate, Wherein, each of the plurality of active regions comprises: a first extension region extending in a second direction perpendicular to the first direction and overlapping the bit line contact; a second extension region extending in the second direction and overlapping the storage node contact; and A third extension region extends in a diagonal direction and overlaps the first buried gate.

2. The semiconductor device according to claim 1, further comprising: A second buried gate extends in the first direction and is spaced apart from the first extension region in the second direction.

3. The semiconductor device according to claim 1, wherein The first buried gate overlaps a portion of the first extension region and a portion of the third extension region.

4. The semiconductor device according to claim 1, wherein A width of the first extension region in the first direction is greater than a width of the second extension region in the first direction.

5. The semiconductor device according to claim 1, wherein The third extension regions included in active regions adjacent to each other in the diagonal direction among the plurality of active regions are repeatedly arranged to be spaced apart from each other by a predetermined distance.

6. The semiconductor device according to claim 1, further comprising: a bit line extending in the second direction and overlapping the bit line contact; as well as A first bit line spacer and a second bit line spacer, each of which contacts the bit line at both sides of the bit line, are disposed not to overlap the second extension region, and are formed to extend in the second direction.

7. The semiconductor device according to claim 6, wherein The first bit line spacer and the second extension region contact each other.

8. The semiconductor device according to claim 6, wherein The first bit line spacer and the second extension region are spaced apart from each other.

9. The semiconductor device according to claim 1, wherein The bit line is disposed on a substrate including a semiconductor layer, and the first buried gate is disposed in the semiconductor layer.

10. The semiconductor device according to claim 1, wherein The bit line is disposed to be buried in a substrate including a semiconductor layer, and the first buried gate is disposed in the semiconductor layer.

11. A semiconductor device comprising: a bit line extending in a first direction; a first extension region extending in the first direction and overlapping the bit line; a second extension region spaced apart from the bit line and formed to extend in the first direction; a third extension region, one end of which contacts the one side of the first extension region arranged in the first direction and extends in a second direction forming an obtuse angle with the first direction, and the other end of which contacts the one side of the second extension region arranged in the first direction; a first buried gate overlapping at least a portion of the third extension region and extending in the semiconductor layer along a third direction perpendicular to the first direction; A bit line contact disposed in the first extension region; as well as A storage node contact is disposed in the third extension region.

12. The semiconductor device according to claim 11, further comprising: A second buried gate is spaced apart from the first extension region in the first direction and is formed to extend in a third direction.

13. The semiconductor device according to claim 12, wherein The first buried gate overlaps a portion of the second extension region; and The second buried gate overlaps a portion of the first extension region.

14. The semiconductor device according to claim 11, wherein The width of the first extension region in the third direction is equal to the width of the third extension region in the second direction.

15. The semiconductor device according to claim 11, wherein The width of the third extension region in the third direction is greater than the width of the first extension region in the third direction.

16. The semiconductor device according to claim 11, further comprising: A first bit line spacer and a second bit line spacer, each of which contacts the bit line at both sides of the bit line, are disposed not to overlap the first extension region, and are formed to extend in the first direction.

17. The semiconductor device according to claim 16, wherein The first bit line spacer and the second extension region are spaced apart from each other.

18. The semiconductor device according to claim 16, wherein The first bit line spacer and the second extension region contact each other.

19. The semiconductor device according to claim 11, wherein The bit line is disposed outside the semiconductor layer.

20. The semiconductor device according to claim 11, wherein The bit line is configured to be buried in the semiconductor layer.

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