Memory and its manufacturing method

Abstract

This disclosure belongs to the field of semiconductor technology, specifically relating to a memory and its manufacturing method. The manufacturing method includes the following steps: providing a semiconductor substrate; fabricating at least one memory cell on the semiconductor substrate, the memory cell including at least one transistor, each transistor including a gate, a gate dielectric, a semiconductor channel, an upper electrode, and a lower electrode, the semiconductor channel at least surrounding the outer periphery of the gate, the gate dielectric being formed between the semiconductor channel and the gate, the upper electrode and the lower electrode being located outside the semiconductor channel and in contact with the semiconductor channel, the lower electrode being insulated and disposed below the upper electrode; oxidizing the region to be oxidized in the effective semiconductor channel of at least one transistor in the memory cell to form an oxide channel. This solution can improve the gate's control over the semiconductor channel while reducing the contact resistance between the source / drain and the semiconductor channel.

Description

Technical Field

[0001] This disclosure belongs to the field of semiconductor technology, and specifically relates to a memory and its manufacturing method. Background Technology

[0002] With the miniaturization of technology nodes, capacitor-free memory has become a research hotspot. Currently, the structure of capacitor-free memory tends to be three-dimensional. When using oxidation treatment to improve defects in the channel of three-dimensional capacitor-free memory, it is easy to cause the entire channel to be oxidized, which will increase the overall resistance of the channel and is not conducive to improving electrical performance. Summary of the Invention

[0003] This disclosure provides a memory and a method for manufacturing the same, which can improve the gate's control over the semiconductor channel while reducing the contact resistance between the source / drain and the semiconductor channel.

[0004] The first aspect of this disclosure provides a method for manufacturing a memory, which includes the following steps:

[0005] Provide a semiconductor substrate;

[0006] At least one memory cell is fabricated on the semiconductor substrate. The memory cell includes at least one transistor. Each transistor includes a gate, a gate dielectric, a semiconductor channel, an upper electrode, and a lower electrode. The semiconductor channel surrounds at least the outer periphery of the gate. The gate dielectric is formed between the semiconductor channel and the gate. The upper electrode and the lower electrode are both located outside the semiconductor channel and in contact with the semiconductor channel. The lower electrode is insulated and disposed below the upper electrode. One of the upper electrode and the lower electrode is a source electrode, and the other is a drain electrode.

[0007] The region to be oxidized in the effective semiconductor channel of at least one transistor in the memory cell is oxidized to form an oxide channel, wherein the region to be oxidized is at least a portion of the effective semiconductor channel, and neither the upper electrode nor the lower electrode is in contact with the oxide channel; wherein the effective semiconductor channel is the portion of the semiconductor channel located between the upper electrode and the lower electrode.

[0008] A second aspect of this disclosure provides a memory comprising:

[0009] Semiconductor substrate; and

[0010] At least one memory cell is formed on the semiconductor substrate. The memory cell includes at least one transistor. Each transistor includes a gate, a gate dielectric, a semiconductor channel, an upper electrode, and a lower electrode. The semiconductor channel surrounds at least the outer periphery of the gate. The gate dielectric is formed between the semiconductor channel and the gate. The upper electrode and the lower electrode are both located outside the semiconductor channel and in contact with the semiconductor channel. The lower electrode is insulated and disposed below the upper electrode. One of the upper electrode and the lower electrode is a source and the other is a drain.

[0011] In the memory cell: at least one of the transistors has a portion of its effective semiconductor channel oxidized to form an oxide channel, the effective semiconductor channel being the portion of the semiconductor channel located between the upper electrode and the lower electrode, and neither the upper electrode nor the lower electrode being in contact with the oxide channel.

[0012] The technical solutions provided in this disclosure have at least the following advantages:

[0013] By oxidizing only the effective semiconductor channel located between the source and drain in the semiconductor channel, the gate's control over the semiconductor channel is improved, and the conduction current is increased. At the same time, since the area in the semiconductor channel that contacts the source and drain is not oxidized, the contact resistance between the source / drain and the semiconductor channel is also reduced. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0015] Figure 1 A schematic diagram of the structure formed in step S100 of the memory manufacturing method described in this embodiment is shown.

[0016] Figure 2 A schematic diagram of the structure formed in step S102 of the memory manufacturing method described in this embodiment is shown.

[0017] Figure 3 A schematic diagram of the structure formed in step S104 of the memory manufacturing method described in this embodiment is shown.

[0018] Figure 4 This diagram illustrates the structure after the gas channel is formed in the memory manufacturing method described in this embodiment.

[0019] Figure 5 This diagram illustrates the structure of the memory manufacturing method described in this embodiment after an oxidizing gas is introduced into a gas channel to form an oxidation channel.

[0020] Figure 6 This diagram illustrates the structure after the gas channel is partially filled to form a filler in the memory manufacturing method described in this embodiment of the present disclosure.

[0021] Figure 7 A schematic diagram of the structure of a memory cell in an embodiment of the present disclosure, including a read transistor and a write transistor, is shown.

[0022] Figure 8 This diagram illustrates the structure after only the region to be oxidized of the read transistor is oxidized to form an oxide channel in the memory manufacturing method described in this embodiment of the present disclosure.

[0023] Figure 9 This diagram illustrates the structure after only the write transistor's region to be oxidized is oxidized to form an oxide channel in the memory manufacturing method described in this embodiment of the present disclosure.

[0024] Figure 10 This diagram illustrates the structure after the regions of the read transistor and write transistor to be oxidized are oxidized to form an oxide channel in the memory manufacturing method described in this embodiment of the present disclosure.

[0025] Figure 11 This diagram illustrates the structure after the gas channel is formed in the memory manufacturing method described in Embodiment 1 of this disclosure.

[0026] Figure 12 The diagram shows a schematic of the structure formed by simultaneously forming a first oxidation channel and a second oxidation channel in the memory manufacturing method described in Embodiment 1 of this disclosure, by introducing an oxidizing gas into a gas channel.

[0027] Figure 13 This diagram illustrates the structure after the gas channel is fully filled to form a filler in the method for manufacturing the memory according to Embodiment 1 of this disclosure.

[0028] Figure 14 This diagram illustrates the structure after the gas channel is partially filled to form a filler in the method for manufacturing the memory according to Embodiment 1 of this disclosure.

[0029] Figure 15 A schematic diagram of the structure formed in step S200 of the memory manufacturing method described in this embodiment is shown.

[0030] Figure 16 and Figure 17 The diagrams show the structure formed in step S200 of the memory manufacturing method described in this embodiment from different perspectives.

[0031] Figure 18 A schematic diagram of the structure formed in step S202 of the memory manufacturing method described in this embodiment is shown.

[0032] Figure 19 A schematic diagram of the structure corresponding to the formation of the read transistor in the memory manufacturing method described in this embodiment is shown.

[0033] Figure 20 This illustration shows a structural diagram of step S2041 in the memory manufacturing method described in this embodiment.

[0034] Figure 21 This illustration shows another structural diagram formed in step S2041 of the memory manufacturing method described in this embodiment.

[0035] Figure 22 This illustration shows another structural diagram formed in step S2041 of the memory manufacturing method described in this embodiment of the present disclosure.

[0036] Figure 23 This illustration shows a structural diagram of step S206 in the memory manufacturing method described in this embodiment of the present disclosure.

[0037] Figure 24 This illustration shows another structural diagram formed in step S206 of the memory manufacturing method described in this embodiment.

[0038] Figure 25 A schematic diagram of the structure formed in step S208 of the memory manufacturing method described in this embodiment is shown.

[0039] Figure 26 and Figure 27 The diagrams show the structure formed in step S208 of the memory manufacturing method described in the embodiments of this disclosure from different perspectives.

[0040] Figure 28 A schematic diagram of the structure formed in step S210 of the memory manufacturing method described in this embodiment is shown.

[0041] Figure 29 A schematic diagram of the structure corresponding to the formation of a write transistor in the memory manufacturing method described in this embodiment is shown.

[0042] Figure 30 This illustration shows a structural diagram of step S2121 in the memory manufacturing method described in this embodiment of the present disclosure.

[0043] Figure 31 This illustration shows another structural diagram formed in step S2121 of the memory manufacturing method described in this embodiment.

[0044] Figure 32 This illustration shows a structural diagram of step S2131 in the memory manufacturing method described in this embodiment of the present disclosure.

[0045] Figure 33 and Figure 34 The diagrams show the structure formed in step S2132 of the memory manufacturing method described in the embodiments of this disclosure from different perspectives.

[0046] Figure 35 A schematic diagram of the structure formed in step S2133 of the memory manufacturing method described in this embodiment is shown.

[0047] Figure 36 This illustration shows a structural diagram of step S214 in the memory manufacturing method described in this embodiment of the present disclosure.

[0048] Figure 37 This illustration shows another structural diagram formed in step S214 of the memory manufacturing method described in this embodiment.

[0049] Figure 38 A schematic diagram of the arrangement of the storage cells and the second part of the gas channel in the memory described in this embodiment of the present disclosure is shown on a horizontal plane.

[0050] Figure 39 This illustration shows a structural diagram of step S216 in the memory manufacturing method described in this embodiment.

[0051] Figure 40 This diagram illustrates the structure after the second gas channel is formed in the memory manufacturing method according to Embodiment 2 of this disclosure.

[0052] Figure 41 This diagram illustrates the structure after the first gas channel is formed in the memory manufacturing method according to Embodiment 2 of this disclosure.

[0053] Figure 42 This diagram illustrates the structure after the second oxide channel is formed in the memory manufacturing method according to Embodiment 2 of this disclosure.

[0054] Figure 43 This diagram illustrates the structure after the second filler body is formed in the memory manufacturing method according to Embodiment 2 of this disclosure.

[0055] Figure 44 This diagram illustrates the structure after the first oxide channel is formed in the memory manufacturing method according to Embodiment 2 of this disclosure.

[0056] Figure 45 This diagram illustrates the structure after the first filler body is formed in the memory manufacturing method according to Embodiment 2 of this disclosure.

[0057] Figure 46 A schematic diagram of the structure formed in step S308 of the memory manufacturing method described in this embodiment is shown.

[0058] Figure 47 This diagram illustrates the structure after the second gas channel is partially filled to form a second filler in the memory manufacturing method described in Embodiment 2 of this disclosure.

[0059] Figure 48 This illustration shows a structural diagram of step S406 in the memory manufacturing method described in this embodiment of the present disclosure.

[0060] Figure 49 This illustration shows another structural diagram formed in step S406 of the memory manufacturing method described in this embodiment of the present disclosure.

[0061] Figure 50 A schematic diagram of the structure formed in step S408 of the memory manufacturing method described in this embodiment is shown.

[0062] Figure 51 This diagram illustrates the structure after the first gas channel is partially filled to form the first filler in the memory manufacturing method described in Embodiment 2 of this disclosure.

[0063] Explanation of reference numerals in the attached figures:

[0064] 10. Semiconductor substrate;

[0065] 11. Transistor; 110. Gate; 111. Gate dielectric; 112. Semiconductor channel; 1120. Oxide channel; 113. Upper electrode; 114. Lower electrode;

[0066] 11W, Write transistor; 110W, First gate; 111W, First gate dielectric; 112W, First semiconductor channel; 1120W, First oxide channel; 113W, First upper electrode; 114W, First lower electrode; 115W, Upper conductive filler;

[0067] 11R, read transistor; 110R, second gate; 111R, second gate dielectric; 112R, second semiconductor channel; 1120R, second oxide channel; 113R, second upper electrode; 114R, second lower electrode; 115R, lower conductive filler;

[0068] 12. Gas passage; 12W. First gas passage; 12R. Second gas passage; 120. First section; 120W. Upper first section; 120R. Lower first section; 121. Second section;

[0069] 13. Filler; 13W, First Filler; 13R, Second Filler;

[0070] 141R, Lower sacrificial insulating film layer; 142R, Lower isolation insulating film layer; 143R, First lower interlayer dielectric layer; 144R, Second lower interlayer dielectric layer; 145R, Second lower signal line; 146R, Second lower isolation insulating portion; 147R, Second upper signal line; 148R, Second upper isolation insulating portion; 149R, Lower through-hole;

[0071] 151R, lower semiconductor thin film layer; 152R, lower gate dielectric thin film layer; 153R, lower gate thin film layer; 154R, lower conductive filler thin film layer;

[0072] 16. Intermediate insulating film layer; 160. Intermediate via;

[0073] 171W, Upper sacrificial insulating film layer; 172W, Upper insulating film layer; 173W, First upper interlayer dielectric layer; 174W, Second upper interlayer dielectric layer; 175W, Write line; 176W, First lower insulating portion; 177W, Upper through-hole; 178W, Filler insulating portion; 179W, Write line;

[0074] 180W, First upper insulating film layer; 180W, First upper insulating part;

[0075] 181W, upper semiconductor thin film layer; 182W, upper gate dielectric thin film layer; 183W, upper gate thin film layer; 184W, upper conductive filler thin film layer;

[0076] 19. Cover with insulating layer;

[0077] C, storage unit; X, first horizontal direction; Y, second horizontal direction; Z, vertical direction. Detailed Implementation

[0078] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0079] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0080] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0081] This disclosure provides a method for manufacturing a memory, which may include steps S100, S102 and S104.

[0082] In step S100: a semiconductor substrate 10 is provided, with reference to... Figure 1 As shown; for example, the semiconductor substrate 10 may be a silicon (Si) substrate, but is not limited to this, and may also be a germanium (Ge) substrate, etc., depending on the specific circumstances.

[0083] In step S102: At least one memory cell is fabricated on the semiconductor substrate 10. The memory cell may include at least one transistor 11, as referenced. Figure 2 As shown, transistor 11 can be a three-dimensional structure. Specifically, each transistor 11 may include a gate 110, a gate dielectric 111, a semiconductor channel 112, an upper electrode 113, and a lower electrode 114. The semiconductor channel 112 is at least surrounding the outer periphery of the gate 110, and the gate dielectric 111 is formed between the semiconductor channel 112 and the gate 110 to avoid direct contact between the semiconductor channel 112 and the gate 110. The upper electrode 113 and the lower electrode 114 are both located outside the semiconductor channel 112 and are in contact with the semiconductor channel 112.

[0084] The lower electrode 114 is insulated and disposed below the upper electrode 113, that is, the lower electrode 114 is closer to the semiconductor substrate 10 than the upper electrode 113. It should be noted that one of the upper electrode 113 and the lower electrode 114 is the source and the other is the drain. In the semiconductor channel 112, the portion located between the upper electrode 113 and the lower electrode 114 can be defined as the effective semiconductor channel.

[0085] For example, the number of memory cells can be multiple, and they can be arranged in a horizontal plane to form a memory array structure. The memory array structure can have one layer or multiple layers stacked in a vertical direction. It should be understood that the horizontal plane mentioned in this embodiment refers to a plane that is parallel or approximately parallel to the semiconductor substrate 10, and the vertical direction refers to a direction that is perpendicular or approximately perpendicular to the semiconductor substrate 10.

[0086] In step S104: the region to be oxidized in the effective semiconductor channel of at least one transistor 11 in the memory cell is oxidized to form an oxide channel 1120, referring to... Figure 3 As shown; wherein, the region to be oxidized is at least a portion of the effective semiconductor channel, and neither the upper electrode 113 nor the lower electrode 114 is in contact with the oxidation channel 1120.

[0087] In this embodiment, by oxidizing only the effective semiconductor channel between the source and drain in the semiconductor channel 112, an oxide channel 1120 with oxygen vacancies is formed in the region between the source and drain in the semiconductor channel 112. This improves the control capability of the gate 110 over the semiconductor channel 112 and increases the conduction current. At the same time, since the region in the semiconductor channel 112 that is in contact with the source and drain is not oxidized, the contact resistance between the source and drain and the semiconductor channel 112 can also be reduced.

[0088] It should be noted that step S104 in this embodiment may be a sub-step of step S102, but is not limited thereto. Step S104 may also be a step performed after the entire memory cell is prepared in step S102. The specific details can be explained later according to the actual preparation situation, and will not be elaborated here.

[0089] Prior to oxidizing the region to be oxidized in the semiconductor channel 112, the manufacturing method of this embodiment may further include preparing a gas channel 12, as described above. Figure 4 As shown, the gas channel 12 may include a first portion 120 surrounding the outer periphery of the region to be oxidized, and a second portion 121 communicating with the first portion 120 and extending vertically upward. After the gas channel 12 is formed, oxidizing gas can be introduced from above the second portion 121 to act on the region to be oxidized. That is, when oxidizing the region to be oxidized in the semiconductor channel 112, as... Figure 5 As shown, an oxidizing gas can be introduced from the upper opening of the second part 121. This oxidizing gas flows sequentially through the second part 121 and the first part 120 and acts on the area to be oxidized to oxidize the area into an oxidation channel 1120. Figure 5 The bold dashed line with arrows in the gas channel 12 indicates the flow path of the oxidizing gas.

[0090] In this embodiment, by forming an oxide channel 1120 in the effective semiconductor channel of the semiconductor channel 112, the electrical performance of the transistor 11 can be improved, so as to design a threshold voltage that meets the requirements to control the semiconductor channel 112. For example, the oxidizing gas in this embodiment may include at least oxygen.

[0091] Since the first part 120 of the gas channel 12 is arranged around the outer periphery of the region to be oxidized, the oxidation channel 1120 formed in this embodiment can also be arranged in a ring shape, specifically around the gate 110 of the transistor 11.

[0092] In an alternative embodiment, after forming the gas channel 12 and before introducing the target gas from above the second portion 121, the manufacturing method of this embodiment may further include: introducing a repair agent from above the second portion 121 to act on the area to be oxidized, so as to repair the surface of the area to be oxidized.

[0093] For example, when the semiconductor channel 112 is made of a metal oxide semiconductor material such as IGZO (Indium Gallium Zinc Oxide), the repair agent may include at least hydrogen, but is not limited to this, and other types of repair agents may also be used, depending on the actual situation.

[0094] In this embodiment, after the oxidation channel 1120 is formed, the manufacturing method may further include filling the gas channel 12 with an insulating material to avoid the subsequent processing affecting the oxidation channel 1120.

[0095] In some embodiments, the step of filling the gas channel 12 with an insulating material may include: completely filling the gas channel 12 with an insulating material to form a filler 13 within the gas channel 12, referencing Figure 3 As shown; it should be understood that, since the gas channel 12 is completely filled, both the first part 120 and the second part 121 of the gas channel 12 are filled with insulating material, which ensures structural stability. The upper surface of the filler 13 is flush with the upper surface of the gas channel 12 to ensure the flatness of the upper surface of the structure, facilitating the formation of other structural layers on top.

[0096] It should be understood that the upper surface mentioned in this disclosure refers to the surface of the object away from the semiconductor substrate 10, and will not be repeated hereafter.

[0097] In some other embodiments, the step of filling the gas channel 12 with an insulating material may include: partially or completely filling the second portion 121 of the gas channel 12 with an insulating material to form a filler 13 within the second portion 121, as shown in the reference. Figure 6 As shown, the upper surface of the filler 13 is flush with the upper surface of the gas channel 12 to ensure the flatness of the upper surface of the structure, which is conducive to the formation of other structural layers on top of it.

[0098] refer to Figure 6 As shown, the gas channel 12 is empty except for the area filled by the filler 13. For example, if the filler 13 only fills a portion of the second part 121, then the first part 120 of the gas channel 12 and the unfilled portion of the second part 121 in the gas channel 12 are both empty areas. If the filler 13 completely fills the second part 121, then the first part 120 of the gas channel 12 is an empty area. That is to say, while using insulating material to partially or completely fill the second part 121 of the gas channel 12 to avoid subsequent processing affecting the oxidation channel, the first part 120 of the gas channel 12 can be formed as an empty area. That is, there is a gap between the upper electrode 113 and the lower electrode 114 of the transistor 11. (Refer to...) Figure 6 As shown, this reduces the parasitic capacitance between the upper electrode 113 and the lower electrode 114 in transistor 11.

[0099] It should be noted that if insulating material is used to partially fill the second part 121 of the gas channel 12, the filled area should be the upper part of the second part 121, as shown in the reference. Figure 6 As shown, this makes the upper surface of the filler 13 flush with the upper surface of the gas channel 12. Specifically, the filler 13 can be formed by quickly sealing with insulating material. The filler 13 is formed in the upper part of the second part 121, while the lower part of the second part 121 and the first part 120 are both void areas.

[0100] The manufacturing method of the memory will be described in detail below with reference to the accompanying drawings and the specific structure of the memory cell. In the embodiments of this disclosure, the memory cell may be a 2TOC structure, that is: the memory cell includes two transistors 11 and has no storage capacitor; wherein, of the two transistors 11 in each memory cell, one is a read transistor 11R and the other is a write transistor 11W.

[0101] For ease of subsequent description, in this embodiment of the present disclosure, the gate 110, gate dielectric 111, semiconductor channel 112, upper electrode 113, and lower electrode 114 of the write transistor 11W are respectively defined as the first gate 110W, the first gate dielectric 111W, the first semiconductor channel 112W, the first upper electrode 113W, and the first lower electrode 114W; and the gate 110, gate dielectric 111, semiconductor channel 112, upper electrode 113, and lower electrode 114 of the read transistor 11R are respectively defined as the second gate 110R, the second gate dielectric 111R, the second semiconductor channel 112R, the second upper electrode 113R, and the second lower electrode 114R.

[0102] refer to Figure 7 As shown, in the memory cell: the write transistor 11W is located above the read transistor 11R, and the first lower electrode 114W of the write transistor 11W and the second gate 110R of the read transistor 11R are electrically connected.

[0103] Specifically, the oxidation process mentioned in step S104 of the above-mentioned process of oxidizing the region to be oxidized in the effective semiconductor channel of at least one transistor 11 in the memory cell to form an oxide channel may include: oxidizing the region to be oxidized in the effective semiconductor channel of at least one of the write transistor 11W and the read transistor 11R, that is, the effective semiconductor channel of at least one of the write transistor 11W and the read transistor 11R includes an oxide channel 1120.

[0104] In some embodiments, the method for manufacturing the memory disclosed herein may include: oxidizing the region to be oxidized in the effective semiconductor channel of one of the write transistor 11W and the read transistor 11R to form an oxide channel 1120; wherein the gas channel 12 is fabricated after the transistor 11 corresponding to the region to be oxidized is fabricated, so that the inner side of the semiconductor channel 112 is protected by structures such as the gate dielectric 111 and the gate 110, thereby reducing damage to the semiconductor channel 112 during the fabrication of the gas channel 12.

[0105] For example, refer to Figure 8 As shown, the step of oxidizing the region to be oxidized in the transistor 11 in the memory cell in this embodiment may include: oxidizing only the region to be oxidized in the read transistor 11R in the memory cell so that the effective semiconductor channel of the read transistor 11R includes an oxide channel 1120, wherein the gas channel 12 is prepared after the read transistor 11R is prepared and the gas channel 12 is filled before the write transistor 11W is prepared.

[0106] Or, refer to Figure 9As shown, the step of oxidizing the region to be oxidized in the transistor 11 in the memory cell in this embodiment may include: oxidizing only the region to be oxidized in the write transistor 11W in the memory cell so that the effective semiconductor channel of the write transistor 11W includes an oxide channel 1120, wherein the gas channel 12 is prepared after the write transistor 11W is prepared.

[0107] In some other embodiments, the manufacturing method of this disclosure may include: oxidizing the regions to be oxidized in the effective semiconductor channels of the write transistor 11W and the read transistor 11R, so that the regions to be oxidized in the write transistor 11W and the read transistor 11R are both formed as oxide channels 1120.

[0108] For ease of description later, the effective semiconductor channel of the first semiconductor channel 112W in the write transistor 11W can be defined as the first effective semiconductor channel, the region to be oxidized in the first effective semiconductor channel of the write transistor 11W can be defined as the first region to be oxidized, the effective semiconductor channel of the second semiconductor channel 112R in the read transistor 11R can be defined as the second effective semiconductor channel, and the region to be oxidized in the second effective semiconductor channel of the read transistor 11R can be defined as the second region to be oxidized.

[0109] Specifically, refer to Figure 10 As shown, the aforementioned step of oxidizing the active semiconductor channels in both the write transistor 11W and the read transistor 11R to form oxide channels 1120 may include: oxidizing the first active semiconductor channel in the write transistor 11W to form a first oxide channel 1120W; and oxidizing the second active semiconductor channel in the read transistor 11R to form a second oxide channel 1120R. By oxidizing the active semiconductor channels in both the write transistor 11W and the read transistor 11R, oxide channels 1120 are formed in both the write transistor 11W and the read transistor 11R, thereby improving the electrical performance of the read transistor 11R and the write transistor 11W and thus improving the storage performance of the memory cell.

[0110] In this embodiment, the oxidation treatment of the effective semiconductor channel regions in both the write transistor 11W and the read transistor 11R can include the following implementation methods:

[0111] Implementation Method 1

[0112] In this embodiment of the present disclosure, the first oxide channel 1120W of the write transistor 11W and the second oxide channel 1120R of the read transistor 11R can be formed simultaneously. That is, the first oxide channel 1120W and the second oxide channel 1120R can be formed in the same preparation step, which can improve the preparation efficiency and reduce the preparation cost.

[0113] If the first oxide channel 1120W and the second oxide channel 1120R need to be formed simultaneously, the gas channel 12 can be fabricated after the write transistor 11W is fabricated. In this embodiment, refer to... Figure 11 As shown, the first portion 120 of the fabricated gas channel 12 may include an upper first portion 120W and a lower first portion 120R. The upper first portion 120W refers to the upper portion of the first portion 120 that is away from the semiconductor substrate 10, and the upper first portion 120W surrounds the outer periphery of the first region to be oxidized. The lower first portion 120R refers to the lower portion of the first portion 120 that is close to the semiconductor substrate 10, and the lower first portion 120R surrounds the outer periphery of the second region to be oxidized.

[0114] It should be understood that, reference Figure 11 As shown, in this embodiment, the upper first portion 120W and the lower first portion 120R of the gas channel 12 are spaced apart in the vertical direction Z and connected by the second portion 121. Specifically, the second portion 121 extends vertically upward to the upper surface of the storage unit and connects the upper first portion 120W and the lower first portion 120R, so that the oxidizing gas introduced from above the second portion 121 can simultaneously act on the first and second areas to be oxidized for oxidation treatment, that is: (Refer to...) Figure 12 As shown, the oxidizing gas can enter the second part 121 through the inlet, and a portion of the oxidizing gas can be diverted to the upper first part 120W to act on the first area to be oxidized for oxidation treatment, while the other portion of the oxidizing gas can be diverted to the lower first part 120R to act on the second area to be oxidized for oxidation treatment, thereby forming the first oxidation channel 1120W and the second oxidation channel 1120R simultaneously. It should be noted that... Figure 12 The bold dashed line with an arrow indicates the flow path of the oxidizing gas.

[0115] For example, after the first oxide channel 1120W and the second oxide channel 1120R are formed simultaneously, refer to Figure 13As shown, the gas channel 12 can be completely filled with insulating material to form a filler 13 within the gas channel 12. In other words, the upper first part 120W, the lower first part 120R, and the second part 121 of the gas channel 12 are all filled with the filler 13 made of insulating material to ensure the structural stability of the storage cell. The upper surface of the filler 13 can be flush with the upper surface of the storage cell to ensure that the upper surface of the storage array structure is flat, which is beneficial to the fabrication of subsequent structural layers.

[0116] It should be understood that after the first oxide channel 1120W and the second oxide channel 1120R are formed simultaneously, the gas channel 12 is not limited to being filled using the aforementioned fully filled method. It can also be filled using an incomplete filling method. For example, the second part 121 can be divided into an upper trunk region and a lower connecting region along the vertical direction Z. The upper trunk region extends from the upper surface of the storage cell to the upper first part 120W and is connected to it. The lower connecting region connects the upper first part 120W and the lower first part 120R. A quick sealing method can be used to fill the upper trunk region with insulating material to form a filler 13 in the upper trunk region of the second part 121. (Refer to...) Figure 14 As shown, the filler 13 is flush with the upper surface of the storage cell. It should be noted that the filler 13 can completely fill the upper trunk area of ​​the second part 121 or fill the upper half of the upper trunk area.

[0117] If the gas channel 12 is filled using the aforementioned incomplete filling method, then refer to Figure 14 As shown, the upper first part 120W and the lower first part 120R are both void regions that are not filled by the filler 13. That is, there are gaps between the first upper electrode 113W and the first lower electrode 114W, as well as between the second upper electrode 113R and the second lower electrode 114R. This can reduce the parasitic capacitance between the first upper electrode 113W and the first lower electrode 114W, as well as between the second upper electrode 113R and the second lower electrode 114R.

[0118] In a specific embodiment of the present disclosure, a method for manufacturing a gas channel 12 including an upper first portion 120W, a lower first portion 120R, and a second portion 121 may include at least steps S200, S202, S204, S206, S208, S210, S212, S214, and S216.

[0119] In step S200: a lower stacked film layer is formed on the semiconductor substrate 10, with reference to... Figure 15As shown, the lower stacked film layer includes at least a second lower electrode 114R, a lower sacrificial insulating film layer 141R, a second upper electrode 113R, and a lower isolation insulating film layer 142R stacked sequentially along the vertical direction Z. The material of the lower isolation insulating film layer 142R may be different from the materials of the lower sacrificial insulating film layer 141R and the subsequent upper sacrificial insulating film layer to avoid the risk of removing the lower isolation insulating film layer 142R in the subsequent removal steps of the upper and lower sacrificial insulating film layers 141R.

[0120] In some embodiments, reference Figure 15 As shown, the lower stacked film layer may further include a first lower interlayer dielectric layer 143R and a second lower interlayer dielectric layer 144R. The first lower interlayer dielectric layer 143R is formed between the second upper electrode 113R and the lower sacrificial insulating film layer 141R, and the second lower interlayer dielectric layer 144R is formed between the second lower electrode 114R and the lower sacrificial insulating film layer 141R.

[0121] The materials of the first lower interlayer dielectric layer 143R and the second lower interlayer dielectric layer 144R are different from the materials of the lower sacrificial insulating film layer 141R, so as to avoid the risk of removing the first lower interlayer dielectric layer 143R and the second lower interlayer dielectric layer 144R in the subsequent removal step of the lower sacrificial insulating film layer 141R. Thus, the first lower interlayer dielectric layer 143R and the second lower interlayer dielectric layer 144R can be used to protect the second upper electrode 113R and the second lower electrode 114R.

[0122] For example, the insulating materials of the first lower interlayer dielectric layer 143R, the second lower interlayer dielectric layer 144R, and the lower insulating film layer 142R can be the same, for example, silicon oxide. The insulating material of the lower sacrificial insulating film layer 141R can be silicon nitride, silicon oxynitride, or silicon carbonitride, etc., but is not limited to these. The specific material can be determined according to the actual situation.

[0123] In some embodiments of this disclosure, step S200 may specifically include steps S2001, S2002, S2003 and S2004.

[0124] In step S2001: a plurality of second lower signal lines 145R are formed on the semiconductor substrate 10, spaced apart in the first horizontal direction X and extending in the second horizontal direction Y, and a second lower isolation insulating portion 146R is formed between adjacent second lower signal lines 145R, combined with Figure 16 and Figure 17As shown; in this embodiment, the second lower isolation insulating portion 146R can insulate adjacent second lower signal lines 145R from each other; wherein, the second lower signal lines 145R can be formed on the semiconductor substrate 10 before the second lower isolation insulating portion 146R, but it is not limited to this, the second lower isolation insulating portion 146R can be formed first, and then multiple lower second lower signal lines 145R can be formed.

[0125] It should be noted that the first horizontal direction X and the second horizontal direction Y mentioned anywhere in this disclosure are defined as directions that are parallel or approximately parallel to the semiconductor substrate 10, wherein the first horizontal direction X intersects the second horizontal direction Y; furthermore, the first horizontal direction X and the second horizontal direction Y are perpendicular or approximately perpendicular to each other, in order to reduce design difficulty and save space.

[0126] In step S2002: A second lower interlayer dielectric layer 144R, a lower sacrificial insulating film layer 141R, and a first lower interlayer dielectric layer 143R are formed on the upper surface (i.e., the surface away from the semiconductor substrate 10) of the second lower signal line 145R and the second lower isolation insulating portion 146R, stacked sequentially in the vertical direction Z, and combined with Figure 16 and Figure 17 As shown.

[0127] In step S2003: a plurality of second upper signal lines 147R are formed on the first lower interlayer dielectric layer 143R, spaced apart in the second horizontal direction Y and extending in the first horizontal direction X, and a second upper isolation insulating portion 148R is formed between adjacent second upper signal lines 147R, combined with Figure 16 and Figure 17 As shown; in this embodiment, the second upper isolation insulating portion 148R can insulate adjacent second upper signal lines 147R from each other; wherein, the second upper signal lines 147R can be formed on the first lower interlayer dielectric layer 143R before the second upper isolation insulating portion 148R, but it is not limited to this, the second upper isolation insulating portion 148R can be formed first, and then multiple lower second upper signal lines 147R can be formed.

[0128] In this embodiment of the disclosure, one of the second upper signal line 147R and the second lower signal line 145R is a read bit line, and the other is a read word line; combined with Figure 16 and Figure 17 As shown, the orthogonal projections of the second upper signal line 147R and the second lower signal line 145R on the semiconductor substrate 10 have an overlapping region. The part of the second upper signal line 147R corresponding to the overlapping region can be defined as the second upper electrode 113R, and the part of the second lower signal line 145R corresponding to the overlapping region can be defined as the second lower electrode 114R.

[0129] For example, the second upper signal line 147R and the second lower signal line 145R may include one or more conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), ITO (indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), and polycrystalline silicon, but are not limited to these. Other conductive materials may also be used, as long as the performance of the second upper signal line 147R and the second lower signal line 145R can be guaranteed.

[0130] In step S2004: A lower insulating film layer 142R is formed that fully covers the second upper signal line 147R and the second upper insulating portion 148R, and is then combined with... Figure 16 and Figure 17 As shown.

[0131] It should be noted that the lower insulating film layer 142R can be integrally formed with the second upper insulating part 148R, but it is not limited to this. It can also be made separately, depending on the specific situation.

[0132] In some other embodiments, the lower stacked film layer may also not include, for example, Figures 15 to 17 The first lower interlayer dielectric layer 143R and the second lower interlayer dielectric layer 144R shown may vary depending on the specific circumstances.

[0133] In step S202: A lower via 149R is formed that penetrates at least the lower insulating film layer 142R, the second upper electrode 113R, and the lower sacrificial insulating film layer 141R, as referenced. Figure 18 As shown, the second lower electrode 114R is exposed by the lower through hole 149R. It should be understood that since the second upper electrode 113R is located in the overlapping area of ​​the second upper signal line 147R and the second lower signal line 145R, and the second lower electrode 114R is located in the overlapping area of ​​the second lower signal line 145R and the second upper signal line 147R, it can be understood that the lower through hole 149R in this embodiment is opened in the overlapping area of ​​the second upper signal line 147R and the second lower signal line 145R.

[0134] Where the lower stacked film layers also include a first lower interlayer dielectric layer 143R and a second lower interlayer dielectric layer 144R, the lower via 149R can also penetrate the first lower interlayer dielectric layer 143R and the second lower interlayer dielectric layer 144R, as shown in the reference. Figure 18 As shown.

[0135] For example, the lower surface of the lower through-hole 149R may extend into the second lower electrode 114R, as shown in the reference. Figure 18As shown, this allows for a larger exposed area of ​​the second lower electrode 114R, increasing the subsequent contact area with the semiconductor channel 112. Furthermore, while ensuring the exposure of the second lower electrode 114R, the etching precision can be reduced, thereby lowering the etching cost. However, it should be understood that the lower surface of the lower via 149R is not limited to extending into the second lower electrode 114R, but may also extend just to the upper surface of the second lower electrode 114R, or the lower via 149R may penetrate the second lower electrode 114R (i.e., the lower surface of the lower via 149R is flush with or lower than the lower surface of the second lower electrode 114R), etc.

[0136] In step S204: a second semiconductor channel 112R, a second gate dielectric 111R, and a second gate 110R are formed at the lower via 149R to form a read transistor 11R, for reference. Figure 19 As shown, the second region to be oxidized in the second semiconductor channel 112R corresponds to the lower sacrificial insulating film layer 141R, that is, the second region to be oxidized in the second semiconductor channel 112R is located in a position surrounded by the lower sacrificial insulating film layer 141R.

[0137] It should be noted that when the lower stacked film layers include a first lower interlayer dielectric layer 143R and a second lower interlayer dielectric layer 144R, after step S204 is executed, both the first lower interlayer dielectric layer 143R and the second lower interlayer dielectric layer 144R can be disposed around the second effective semiconductor channel. Specifically, the first lower interlayer dielectric layer 143R can surround the region in the second effective semiconductor channel located above the second region to be oxidized, and the second lower interlayer dielectric layer 144R can surround the region in the second effective semiconductor channel located below the second region to be oxidized.

[0138] In some embodiments of this disclosure, step S204 may include at least steps S2041 and S2042.

[0139] In step S2041: After forming the lower via 149R, a lower semiconductor thin film layer 151R, a lower gate dielectric thin film layer 152R, and a lower gate thin film layer 153R are sequentially deposited on the lower stacked film layers, with reference to... Figure 20 As shown, the lower semiconductor thin film layer 151R, the lower gate dielectric thin film layer 152R, and the lower gate thin film layer 153R all completely cover the lower stacked film layers. That is, the lower semiconductor thin film layer 151R, the lower gate dielectric thin film layer 152R, and the lower gate thin film layer 153R can be deposited on the upper surface of the lower isolation insulating film layer 142R and deposited within the lower via 149R. The portions of the lower semiconductor thin film layer 151R and the lower gate dielectric thin film layer 152R located within the lower via 149R can be U-shaped, and the portion of the lower gate thin film layer 153R located within the lower via 149R can also be U-shaped. (Refer to...) Figure 20As shown; or the lower gate thin film layer 153R can also fill the lower via 149R, see reference. Figure 21 As shown.

[0140] For example, the material of the lower semiconductor thin film layer 151R can be a semiconductor material such as IGZO, but is not limited to it, and can also be other semiconductor materials; the material of the lower gate dielectric thin film layer 152R can be a high dielectric insulating material such as silicon oxide, but is not limited to it, and can also be a low dielectric material, etc.; the material of the lower gate thin film layer 153R can be a conductive material with good gate control capability such as ZnO (zinc oxide), ITO (indium tin oxide), IZO (indium zinc oxide), but is not limited to it, and can also be other conductive materials.

[0141] It should be noted that the portion of the lower gate thin film layer 153R located within the lower via 149R is as follows: Figure 20 When the U-shape is shown, step S2041 may further include: after depositing the lower gate thin film layer 153R, depositing a lower conductive fill thin film layer 154R that covers the entire surface of the lower gate thin film layer 153R, as shown in the reference. Figure 22 As shown, the portion of the lower conductive filling thin film layer 154R located within the lower via 149R completely fills the lower via 149R. In this embodiment, the lower conductive filling thin film layer 154R can be selected from conductive materials with good conductivity and lower cost than the lower gate thin film layer 153R.

[0142] In step S2042: the portions of the lower semiconductor thin film layer 151R, the lower gate dielectric thin film layer 152R, and the lower gate thin film layer 153R that extend beyond the target distance value of the hole boundary of the lower via 149R are etched away to form a second semiconductor channel 112R, a second gate dielectric 111R, and a second gate 110R at the lower via 149R, thereby forming a read transistor 11R, as shown below. Figure 19 As shown.

[0143] In step S2042, the target distance value can be 0, meaning that the portions of the lower semiconductor thin film layer 151R, lower gate dielectric thin film layer 152R, and lower gate thin film layer 153R that extend beyond the boundary of the lower via 149R are etched away. However, this is not the only possibility; the target distance value mentioned in step S2042 can also be greater than 0, but it must still be less than half the distance between adjacent lower vias 149R. Thus, the second semiconductor channel 112R, second gate dielectric 111R, and second gate 110R, in addition to the portions located within the lower via 149R, also have portions extending away from the via axis and resting on the upper surface of the lower insulating film layer 142R. (Refer to...) Figure 19 As shown, this reduces the etching difficulty and ensures product quality when forming multiple arrays of read transistors 11R.

[0144] It should be understood that if step S2041 includes a lower conductive filling thin film layer 154R that fully covers the lower gate thin film layer 153R, then in step S2042, during the process of etching away the portion of the lower semiconductor thin film layer 151R, the lower gate dielectric thin film layer 152R, and the lower gate thin film layer 153R that exceeds the target distance value of the hole boundary, the process also includes etching away the portion of the lower conductive filling thin film layer 154R that exceeds the target distance value of the hole boundary. The remaining unetched portion in the lower conductive filling thin film layer 154R is defined as the lower conductive filling portion 115R. The lower conductive filling portion 115R may be included in the read transistor 11R. A portion of the lower conductive filling portion 115R fills the lower via 149R and contacts the second gate 110R, while another portion overlaps the upper surface of the second gate 110R. It should be noted that the upper surface of the second gate 110 mentioned in this disclosure refers to the surface of the second gate 110 that is farthest from the semiconductor substrate 10.

[0145] In step S206: An intermediate insulating film layer 16 is formed on the lower stacked film layer, as referenced. Figure 23 As shown, the intermediate isolation insulating film layer 16 at least covers the area on the upper surface of the lower isolation insulating film layer 142R that is not covered by the read transistor 11R, and at least a portion of the second gate 110R does not overlap with the orthographic projection of the intermediate isolation insulating film layer 16 on the semiconductor substrate 10. That is, at least a portion of the second gate 110R is not blocked by the intermediate isolation insulating film layer 16, so as to connect with the first lower electrode 114W of the subsequently formed write transistor 11W.

[0146] Among them, reference Figure 23 As shown, if the portion of the second gate 110R located within the lower via 149R is U-shaped, and the lower via 149R is completely filled by the lower conductive fill portion 115R, the upper surface of the intermediate insulating film layer 16 can be higher than the upper surface of the lower conductive fill portion 115R. The intermediate insulating film layer 16 has a plurality of intermediate vias 160 corresponding one-to-one with the lower conductive fill portion 115R, and the intermediate vias 160 expose at least a portion of the upper surface of the lower conductive fill portion 115R. (Reference) Figure 24 As shown, if the second gate 110R fills the lower via 149R, the upper surface of the intermediate isolation insulating film layer 16 can be higher than the upper surface of the second gate 110R, and the intermediate isolation insulating film layer 16 has a plurality of intermediate vias 160 corresponding one-to-one with the second gate 110R of the read transistor 11R, and the intermediate vias 160 expose at least a portion of the upper surface of the second gate 110R.

[0147] In step S208: the upper stacked film layer is formed, referenced Figure 25As shown, the upper stacked film layer includes at least a first lower electrode 114W, an upper sacrificial insulating film layer 171W, a first upper electrode 113W, and an upper isolation insulating film layer 172W stacked sequentially along the vertical direction Z. The first lower electrode 114W is connected to the second gate 110R, and the upper surface of the first lower electrode 114W is flush with the upper surface of the intermediate isolation insulating film layer 16.

[0148] For example, the material of the upper insulating layer 172W is different from the materials of the upper sacrificial insulating layer 171W and the lower sacrificial insulating layer 141R, in order to avoid the risk of removing the upper insulating layer 172W in the subsequent removal steps of the upper sacrificial insulating layer 171W and the lower sacrificial insulating layer 141R.

[0149] In some embodiments, reference Figure 25 As shown, the upper stacked film layer may further include a first upper interlayer dielectric layer 173W and a second upper interlayer dielectric layer 174W. The first upper interlayer dielectric layer 173W is formed between the first upper electrode 113W and the upper sacrificial insulating film layer 171W, and the second upper interlayer dielectric layer 174W is formed between the intermediate insulating film layer 16 and the upper sacrificial insulating film layer 171W.

[0150] For example, the materials of the first upper interlayer dielectric layer 173W and the second upper interlayer dielectric layer 174W are different from the materials of the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R, so as to avoid the risk of removing the first upper interlayer dielectric layer 173W and the second upper interlayer dielectric layer 174W in the subsequent removal steps of the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R, thereby protecting the first upper electrode 113W and the first lower electrode 114W using the first upper interlayer dielectric layer 173W and the second upper interlayer dielectric layer 174W.

[0151] For example, the insulating materials of the first upper interlayer dielectric layer 173W, the second upper interlayer dielectric layer 174W, the upper insulating film layer 172W, the middle insulating film layer 16, and the lower insulating film layer 142R can be the same, for example, silicon oxide. The insulating materials of the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R can be the same, for example, silicon nitride, silicon oxynitride, or silicon carbonitride, etc. It should be understood that the insulating materials of each interlayer dielectric layer, insulating film layer, and sacrificial insulating film layer are not limited to the materials mentioned above, and can also be other insulating materials, depending on the specific circumstances.

[0152] In some embodiments of this disclosure, step S208 may specifically include steps S2081, S2082 and S2083.

[0153] In step S2081: a plurality of first lower electrodes 114W are formed arranged in an array along the first horizontal direction X and the second horizontal direction Y. Each first lower electrode 114W corresponds to a via 160 in the middle. That is, each first lower electrode 114W is connected to a second gate 110R. Figure 26 and Figure 27 As shown.

[0154] It should be understood that if the second gate 110R fills the lower via 149R, the lower surface of the first lower electrode 114W will directly contact the upper surface of the second gate 110R to achieve a direct connection between the first lower electrode 114W and the second gate 110R. The first lower electrode 114W and the second gate 110R can be integrally formed, but are not limited to this. Alternatively, the second gate 110R and the first lower electrode 114W can be fabricated separately, i.e., the second gate 110R can be fabricated first, followed by the first lower electrode 114W. Furthermore, the first lower electrode 114W and the second gate 110R can be fabricated using the same conductive material, but are not limited to this. They can also be fabricated using different conductive materials, depending on the specific circumstances.

[0155] If the portion of the second gate 110R located within the lower via 149R is U-shaped, and the lower via 149R is filled with the lower conductive filling portion 115R, the lower surface of the first lower electrode 114W directly contacts the upper surface of the lower conductive filling portion 115R, thereby achieving indirect connection with the second electrode through the lower conductive filling portion 115R. The first lower electrode 114W can be integrally formed with the lower conductive filling portion 115R, but is not limited to this; the lower conductive filling portion 115R and the first lower electrode 114W can also be fabricated separately, i.e., the lower conductive filling portion 115R is fabricated first, and then the first lower electrode 114W is fabricated. Furthermore, the first lower electrode 114W and the lower conductive filling portion 115R can be fabricated using the same conductive material, but is not limited to this; they can also be fabricated using different conductive materials, depending on the specific circumstances.

[0156] For example, if the first lower electrode 114W is integrally formed with the second gate 110R or the first lower electrode 114W is integrally formed with the lower conductive filling portion 115R, the intermediate isolation insulating film layer 16 can be selected as an integrally formed whole layer structure. For example, after the first lower electrode 114W is integrally formed with the second gate 110R or with the lower conductive filling portion 115R, step S206 can specifically include: first forming an intermediate isolation insulating film that covers the entire surface of the lower isolation insulating film layer 142R, the second gate 110R (or the lower conductive filling portion 115R) and the first lower electrode 114W, and then removing the portion of the intermediate isolation insulating film that is higher than the upper surface of the first lower electrode 114W to form the intermediate isolation insulating film layer 16, the upper surface of which is flush with the upper surface of the first lower electrode 114W.

[0157] It should be understood that if the first lower electrode 114W is separately prepared from the second gate 110R or separately prepared from the lower conductive fill portion 115R, the intermediate insulating film layer 16 can also be an integrally formed whole structure. For example, after the second gate 110R or the lower conductive fill portion 115R is formed, and before the first lower electrode 114W is formed, step S206 may specifically include: first forming an intermediate insulating film that covers the entire surface of the lower insulating film layer 142R and the second gate 110R (or the lower conductive fill portion 115R); then removing the portion of the intermediate insulating film that is connected to the second gate 110R (or the lower conductive fill portion 115R) to form an intermediate insulating film layer 16 including an intermediate via 160; then, step S2081 is executed; but not limited to this, if the first lower electrode 114W is separately prepared from the second gate 110R or separately prepared from the lower conductive fill portion 115R, the intermediate insulating film... Layer 16 can also be fabricated in two layers. For example, after the second gate 110R or the lower conductive fill portion 115R is formed, a first intermediate insulating film can be formed to cover the entire surface of the lower isolation insulating film layer 142R and the second gate 110R (or the lower conductive fill portion 115R). Then, the portion of the first intermediate insulating film that is higher than the upper surface of the second gate 110R (or the lower conductive fill portion 115R) is completely removed to form the first intermediate insulating film layer. This first intermediate insulating film layer covers the area on the upper surface of the lower isolation insulating film layer 142R that is not covered by the read transistor 11R. Then, a second intermediate insulating film is formed to cover the entire surface of the second intermediate insulating film layer and the second gate 110R (or the lower conductive fill portion 115R). Then, the second intermediate insulating film is subjected to an opening process to form a second intermediate insulating film layer including an intermediate via. This second intermediate insulating film layer and the first intermediate insulating film layer constitute the intermediate isolation insulating film layer 16.

[0158] It should be noted that the preparation step of the second intermediate insulating film layer can be performed after the preparation step of the first lower electrode 114W, or before the preparation step of the first lower electrode 114W, depending on the specific situation, which will not be elaborated on here.

[0159] In step S2082: A second upper interlayer dielectric layer 174W, an upper sacrificial insulating layer 171W, and a first upper interlayer dielectric layer 173W are sequentially stacked on the upper surface of the intermediate insulating film layer 16 and the first lower electrode 114W, in combination with... Figure 26 and Figure 27 As shown.

[0160] In step S2083: a plurality of write bit lines 175W are formed on the first upper interlayer dielectric layer 173W, spaced apart in the second horizontal direction Y and extending in the first horizontal direction X, and a first lower isolation insulating portion 176W is formed between adjacent write bit lines 175W, combined with Figure 26 and Figure 27 As shown, in this embodiment, the first lower isolation insulating portion 176W can insulate adjacent write bit lines 175W from each other; wherein, the write bit lines 175W can be formed on the first upper interlayer dielectric layer 173W before the first lower isolation insulating portion 176W, but it is not limited to this, the first lower isolation insulating portion 176W can be formed first, and then multiple write bit lines 175W can be formed.

[0161] In this embodiment of the disclosure, the write bit line 175W may include a first upper electrode 113, and the first upper electrode 113 and the first lower electrode 114W have an overlapping region on the semiconductor substrate 10.

[0162] In step S2084: an upper insulating film layer 172W is formed that fully covers the write bit line 175W and the first lower insulating portion 176W, and is then combined with... Figure 26 and Figure 27 As shown.

[0163] In some other embodiments, the upper stacked film layers may also exclude the first upper interlayer dielectric layer 173W and the second upper interlayer dielectric layer 174W, depending on the specific circumstances.

[0164] In step S210: an upper through-hole 177W is formed that penetrates at least the upper insulating film layer 172W, the first upper electrode 113W, and the upper sacrificial insulating film layer 171W, as referenced. Figure 28 As shown, the first lower electrode 114W is exposed by the upper through hole 177W, that is, the upper through hole 177W can be opened in the area where the first upper electrode 113W and the first lower electrode 114W overlap.

[0165] For example, the orthographic projections of the upper via 177W and the lower via 149R on the semiconductor substrate 10 can coincide, so that the write transistor 11W and the read transistor 11R of the memory cell coincide as much as possible in the vertical direction Z. While ensuring the performance of the memory cell, the horizontal area occupied by the memory cell can be reduced, thereby enabling more memory cells to be arranged in a unit area to improve the storage density of the memory.

[0166] In some embodiments, when the upper stacked film layers further include a first upper interlayer dielectric layer 173W and a second upper interlayer dielectric layer 174W, the upper via 177W can also penetrate the first upper interlayer dielectric layer 173W and the second upper interlayer dielectric layer 174W, as shown in the reference. Figure 28 As shown.

[0167] For example, refer to Figure 28 As shown, the orthographic projection of the upper via 177W on the semiconductor substrate 10 can completely cover the orthographic projection of the first lower electrode 114W on the semiconductor substrate 10. At this time, the lower surface of the upper via 177W can just extend to the upper surface of the first lower electrode 114W, so as to avoid the situation that subsequent etching is prone to poor due to the different materials of the first lower electrode 114W and the intermediate isolation insulating film layer 16.

[0168] It should be understood that the orthogonal projection of the upper via 177W onto the semiconductor substrate 10 may lie within the orthogonal projection of the first lower electrode 114W onto the semiconductor substrate 10. In this case, the lower surface of the upper via 177W may extend into the interior of the first lower electrode 114W, thereby increasing the exposed area of ​​the first lower electrode 114W and increasing the subsequent contact area with the semiconductor channel 112. In addition, while ensuring that the first lower electrode 114W is exposed, the etching precision can be reduced, thereby reducing the etching cost. However, it should be understood that the lower surface of the upper via 177W is not limited to extending into the first lower electrode 114W, but may also just extend to the upper surface of the first lower electrode 114W.

[0169] In step S212: a first semiconductor channel 112W, a first gate dielectric 111W, and a first gate 110W are sequentially formed at the upper via 177W to form a write transistor 11W, as shown in the reference. Figure 29 As shown; wherein, the first region to be oxidized of the first semiconductor channel 112W corresponds to the upper sacrificial insulating film layer 171W, that is: the first region to be oxidized of the first semiconductor channel 112W is located in a position surrounded by the upper sacrificial insulating film layer 171W.

[0170] It should be noted that when the stacked film layers include a first interlayer dielectric layer 173W and a second interlayer dielectric layer 174W, after performing step S212, refer to Figure 29 As shown, both the first upper interlayer dielectric layer 173W and the second upper interlayer dielectric layer 174W can be disposed around the first effective semiconductor channel. Specifically, the first upper interlayer dielectric layer 173W can surround the region of the first effective semiconductor channel located above the first region to be oxidized, and the second upper interlayer dielectric layer 174W can surround the region of the first effective semiconductor channel located below the first region to be oxidized.

[0171] In some embodiments of this disclosure, step S212 may include at least steps S2121 and S2122.

[0172] In step S2121: After forming the upper via 177W, an upper semiconductor thin film layer 181W, an upper gate dielectric thin film layer 182W, and an upper gate thin film layer 183W are sequentially deposited on the upper stacked film layers, as referenced. Figure 30As shown, the upper semiconductor thin film layer 181W, the upper gate dielectric thin film layer 182W, and the upper gate thin film layer 183W all cover the stacked film layers on their entire surface. That is, the upper semiconductor thin film layer 181W, the upper gate dielectric thin film layer 182W, and the upper gate thin film layer 183W can be deposited on the upper surface of the upper isolation insulating film layer 172W and deposited in the upper via 177W.

[0173] Specifically, the portions of the upper semiconductor thin film layer 181W and the upper gate dielectric thin film layer 182W located within the upper via 177W can be U-shaped, and the portion of the upper gate thin film layer 183W located within the upper via 177W can be U-shaped. (Reference) Figure 31 As shown; or the upper gate thin film layer 183W can fill the upper via 177W, see reference. Figure 30 As shown.

[0174] For example, the material of the upper semiconductor thin film layer 181W can be a semiconductor material such as IGZO, but is not limited to it, and can also be other semiconductor materials; the material of the upper gate dielectric thin film layer 182W can be a high dielectric insulating material such as silicon oxide, but is not limited to it, and can also be a low dielectric material, etc.; the material of the upper gate thin film layer 183W can be a conductive material with good gate control capability such as ZnO (zinc oxide), ITO (indium tin oxide), IZO (indium zinc oxide), but is not limited to it, and can also be other conductive materials.

[0175] In step S2122: the portion of the upper semiconductor thin film layer 181W, the upper gate dielectric thin film layer 182W and the upper gate thin film layer 183W that exceeds the target distance value of the hole boundary of the upper via 177W is etched away, so as to form the first semiconductor channel 112W, the first gate dielectric 111W and the first gate 110W at the upper via 177W, thereby forming the write transistor 11W.

[0176] In the embodiments of this disclosure, the target distance value mentioned in step S2122 can be 0, meaning that the portions of the upper semiconductor thin film layer 181W, the upper gate dielectric thin film layer 182W, and the upper gate thin film layer 183W that extend beyond the boundary of the upper via 177W are etched away. However, this is not the only possibility; the target distance value in step S2122 can also be greater than 0, but it must still be less than half the distance between adjacent upper vias 177W. In this way, the first semiconductor channel 112W, the first gate dielectric 111W, and the first gate 110W, in addition to the portions located within the upper via 177W, also have portions extending away from the via axis and resting on the upper surface of the upper insulating film layer 172W. (Refer to...) Figure 29 As shown, this reduces the etching difficulty and ensures product quality when forming multiple arrays of write transistors 11W.

[0177] Wherein, when the portion of the first gate 110W located within the upper via 177W is U-shaped, reference Figure 29 As shown, the write transistor 11W in this embodiment may further include an upper conductive filling portion 115W that at least fills the upper via 177W. In this embodiment, the upper conductive filling portion 115W may be selected from a conductive material with good conductivity and lower cost than the first gate 110W.

[0178] For example, the upper conductive filling portion 115W in this embodiment can be cylindrical, and the upper surface of the cylindrical upper conductive filling portion 115W can be flush with the upper surface of the first gate 110W; however, it is not limited to this, the upper conductive filling portion 115W can also be T-shaped, see reference. Figure 29 As shown, the conductive filling portion 115W of the T-shape can fill the upper through hole 177W while also covering the upper surface of the first gate 110W. The upper surface of the first gate 110W can be the surface of the first gate 110W that is furthest from the semiconductor substrate 10.

[0179] In some embodiments, the method for manufacturing the upper conductive filling portion 115W may include: in step S2121: after depositing the upper gate thin film layer 183W, referring to Figure 31 As shown, an upper conductive filling thin film layer 184W is deposited to cover the entire surface of the upper gate thin film layer 183W. Then, in step S2112, during the etching process of removing the portions of the upper semiconductor thin film layer 181W, the upper gate dielectric thin film layer 182W, and the upper gate thin film layer 183W that exceed the target distance value of the hole boundary, the portions of the upper conductive filling thin film layer 184W that exceed the target distance value of the hole boundary are also etched away to form a T-shaped upper conductive filling portion. If a pillar-shaped upper conductive filling portion is to be formed, after step S2112, the portion of the T-shaped upper conductive filling portion that exceeds the upper surface of the first gate 110W can be removed to form a pillar-shaped upper conductive filling portion.

[0180] It should be noted that the cylindrical conductive filling portion is not limited to being prepared in the aforementioned manner, but can also be prepared in the following manner, for example, after performing step S2122 to form the first gate 110W, the first gate dielectric 111W and the first semiconductor channel 112W of the write transistor 11W: firstly, an upper conductive filling thin film layer 184W is deposited. This upper conductive filling thin film layer 184W not only covers the entire surface of the structural layer located below it, but also fills the upper via 177W; then, the upper conductive filling thin film layer 184W is patterned to form a filled cylindrical conductive filling portion in each upper via 177W.

[0181] In some embodiments of this disclosure, after the write transistor 11W is formed, step S212 may further include steps S2131, S2132 and S2133.

[0182] In step S2131: A filling insulating portion 178W is formed on the upper surface of the upper insulating film layer 172W, with reference to... Figure 32 As shown, the filling isolation insulating portion 178W can cover the upper surface of the upper isolation insulating film layer 172W that is not covered by the write transistor 11W. It should be noted that if the first gate 110W itself fills the upper via 177W or the prepared columnar upper conductive filling portion fills the upper via 177W, then the upper surface of the filling isolation insulating portion 178W formed here can be flush with the upper surface of the first gate 110W and the upper surface of the columnar upper conductive filling portion. If the prepared T-shaped upper conductive filling portion fills the upper via 177W, then the upper surface of the filling isolation insulating portion 178W formed here can be flush with the upper surface of the T-shaped upper conductive filling portion, so as to ensure that the subsequent write word lines are formed on the flush surface.

[0183] In step S2132: a plurality of writing lines 179W are formed, spaced apart in the first horizontal direction X and extending in the second horizontal direction Y; and a first upper insulating portion 180W is formed between adjacent writing lines 179W, combined with... Figure 33 and Figure 34 As shown.

[0184] The write line 179W can be connected to the first gate 110W of a plurality of write transistors 11W arranged at intervals in the second horizontal direction Y. If the first gate 110W fills the upper via 177W, the write line 179W can directly contact the first gate 110W to achieve a direct connection between the two. If the upper via 177W is filled with a T-shaped upper conductive filling portion, the write line 179W can directly contact the upper surface of the T-shaped upper conductive filling portion to achieve an indirect connection with the first gate 110W through the T-shaped upper conductive filling portion. If the upper via 177W is filled with a cylindrical upper conductive filling portion, the write line 179W can simultaneously directly contact the first gate 110W and the upper surface of the cylindrical upper conductive filling portion to achieve a connection between the three.

[0185] In step S2133: A full-coverage sealing insulation layer 19 is formed, which covers the writing line 179W and the filling isolation insulation portion 178W. (Refer to...) Figure 35 As shown, the upper surface of the sealing insulating layer 19 is a plane that is parallel or approximately parallel to the semiconductor substrate 10.

[0186] In this embodiment, adjacent writing lines 179W are insulated from each other by a first upper insulating portion 180W. Specifically, the writing lines 179W may be formed before the first upper insulating portion 180W, but it is not limited to this. Alternatively, the first upper insulating portion 180W may be formed first, and then multiple writing lines 179W may be formed.

[0187] In some embodiments, if the writing line 179W is formed first and then the first upper insulating portion 180W is formed: the first upper insulating portion 180W can be integrally formed with the cover insulating layer 19, but it is not limited thereto. The first upper insulating portion 180W can also be separately prepared from the cover insulating layer 19, that is: the first upper insulating portion 180W is formed first, and then the cover insulating layer 19 is prepared.

[0188] In other embodiments, if the first upper insulating portion 180W is formed first and the writing line 179W is formed later: the first upper insulating portion 180W can be integrally formed with the filling insulating portion 178W, but it is not limited to this. The first upper insulating portion 180W can also be separately prepared from the filling insulating portion 178W, that is: the filling insulating portion 178W is formed first, and then the first upper insulating portion 180W is prepared.

[0189] It should be understood that the write word line 179W in this disclosure is not limited to being formed after the first gate 110W or the upper conductive fill portion 115W, but may also be integrally formed with the first gate 110W or the upper conductive fill portion 115W, depending on the specific circumstances, which will not be elaborated further here. Furthermore, this disclosure is not limited to the write bit line 175W extending in the first horizontal direction X and the write word line 179W extending in the second horizontal direction Y; it is also possible for the write bit line 175W to extend in the second horizontal direction Y and the write word line 179W to extend in the first horizontal direction X, as long as the extension directions of the write word line 179W and the write bit line 175W intersect.

[0190] In step S214: After forming the write transistor 11W, a second portion 121 of the gas channel 12 is formed. The second portion 121 does not overlap with the orthographic projections of the lower via 149R and the upper via 177W onto the semiconductor substrate 10. (Refer to...) Figure 36 and Figure 37 As shown, the second portion 121 penetrates at least the upper insulating film layer 172W, the upper sacrificial insulating film layer 171W, the intermediate insulating film layer 16, and the lower insulating film layer 142R, and exposes the lower sacrificial insulating film layer 141R. The second portion 121 of the gas channel 12 can extend vertically in the Z direction into the interior of the lower sacrificial insulating film layer 141R. This reduces the difficulty of the process and increases the exposed area of ​​the lower sacrificial insulating film layer 141R, thereby accelerating the rate at which the lower sacrificial insulating film layer 141R is subsequently etched away. However, it is not limited to this. The second portion 121 of the gas channel 12 can also extend just to the upper surface of the lower sacrificial insulating film layer 141R or penetrate the lower sacrificial insulating film layer 141R.

[0191] In some embodiments, reference Figure 36As shown, the second part 121 of the gas channel 12 can be prepared after the capping insulating layer 19 is formed. At this time, the "upper surface of the memory cell" in the aforementioned "the second part 121 extends vertically upward to the upper surface of the memory cell" refers to the upper surface of the capping insulating layer 19. That is, after the capping insulating layer 19 is formed, the hole is etched vertically downward from the upper surface of the capping insulating layer 19 until the lower sacrificial insulating film layer 141R is etched. By preparing the second part 121 of the gas channel 12 after the capping insulating layer 19, the write transistor 11W and the write word line 179W can be protected by the capping insulating layer 19 to avoid damage to the write transistor 11W and the write word line 179W during subsequent hole etching.

[0192] In some other embodiments, the second portion 121 of the gas channel 12 may also be fabricated after the write transistor 11W (or before the formation of the conductive fill portion 115W) and before the formation of the write word line 179W. If protection of the write transistor 11W is achieved in this case, refer to... Figure 37 As shown, after forming the write transistor 11W (or forming the upper conductive filling portion 115W), a first upper isolation insulating film layer 180 covering the entire surface is formed. At this time, the "upper surface of the memory cell" in the aforementioned "second portion 121 extends vertically upward to the upper surface of the memory cell" refers to the upper surface of the first upper isolation insulating film layer 180. Then, hole etching is performed vertically downward from the upper surface of the first upper isolation insulating film layer 180 until the lower sacrificial insulating film layer 141R is etched. Then, subsequent steps are performed. After the first oxide channel 1120W and the second oxide channel 1120R are formed and the second portion 121 of the gas channel 12 is partially or completely filled with insulating material, the first upper isolation insulating film layer 180 is etched to form the first upper isolation insulating portion 180W. After that, the write word line 179W and the cover insulating layer 19 are formed, etc.

[0193] In some embodiments, reference Figure 36 and Figure 37 As shown, when the lower stacked film layer includes a first lower interlayer dielectric layer 143R and a second lower interlayer dielectric layer 144R, and the upper stacked film layer includes a first upper interlayer dielectric layer 173W and a second upper interlayer dielectric layer 174W, the second part 121 of the gas channel 12 can also penetrate the first upper interlayer dielectric layer 173W, the second upper interlayer dielectric layer 174W and the first lower interlayer dielectric layer 143R.

[0194] In some embodiments, reference Figure 38As shown, the second portion 121 of the gas channel 12 does not overlap with the orthographic projections of the write word line 179W, write bit line 175W, second lower signal line 145R, and second upper signal line 147R on the semiconductor substrate 10, thus ensuring the performance of the write word line 179W, write bit line 175W, second lower signal line 145R, and second upper signal line 147R. Since the second portion 121 of the gas channel 12 does not overlap with the orthographic projections of the write word line 179W, write bit line 175W, second lower signal line 145R, and second upper signal line 147R on the semiconductor substrate 10, the second portion 121 of the gas channel 12, in addition to penetrating the aforementioned film layer, can also penetrate the first upper isolation insulating portion 180W, the first lower isolation insulating portion 176W, and the second upper isolation insulating portion 148R. (Refer to...) Figure 36 As shown.

[0195] In some embodiments, reference Figure 38 As shown, multiple second portions 121 of the gas channel 12 can be provided, and multiple second portions 121 can surround the outer periphery of each storage cell C. This can not only accelerate the etching rate of the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R, but also ensure etching uniformity.

[0196] In step S216, an etchant is introduced into the second portion 121 to remove the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R, forming an upper first portion 120W surrounding the first region to be oxidized and a lower first portion 120R surrounding the second region to be oxidized. (Refer to...) Figure 39 As shown.

[0197] In the process of removing the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R using an etchant, the first lower interlayer dielectric layer 143R, the second lower interlayer dielectric layer 144R, the first upper interlayer dielectric layer 173W, and the second upper interlayer dielectric layer 174W are retained, that is, they are not etched by the etchant or are etched very little.

[0198] For example, the etchant in this embodiment can be a liquid, but is not limited to this, and can also be a gas. Wherein, the insulating material of the aforementioned interlayer dielectric layer, isolation insulating film layer, and isolation insulating part is silicon oxide, and the insulating material of the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R is silicon nitride, silicon oxynitride, or silicon carbonitride, etc., this embodiment can use chlorine gas or liquid phosphoric acid to completely etch the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R, but is not limited to this. This embodiment can also use other etchants to etch the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R, as long as it is ensured that the etchant can etch away the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R while having little or no impact on the aforementioned interlayer dielectric layer, isolation insulating film layer, and isolation insulating part, so as to retain the aforementioned interlayer dielectric layer, isolation insulating film layer, and isolation insulating part.

[0199] Implementation Method 2

[0200] In this embodiment of the present disclosure, the first oxide channel 1120W of the write transistor 11W and the second oxide channel 1120R of the read transistor 11R can be fabricated separately. Specifically, the second oxide channel 1120R of the read transistor 11R can be formed first, and then the first oxide channel 1120W of the write transistor 11W can be formed. This can ensure the quality of the first oxide channel 1120W and the second oxide channel 1120R.

[0201] When the first oxide channel 1120W of the write transistor 11W and the second oxide channel 1120R of the read transistor 11R are formed separately, the aforementioned gas channel 12 needs to include two channels manufactured sequentially, that is: the gas channel 12 may include, for example, Figure 41 The first gas channel 12W shown and as follows Figure 40 The second gas channel 12R shown is fabricated separately from the first gas channel 12W, and the second gas channel 12R is fabricated before the first gas channel 12W.

[0202] Among them, reference Figure 40 As shown, the second gas channel 12R includes a first portion 120 surrounding the second region to be oxidized, and a second portion 121 communicating with the first portion 120 and extending vertically upward to the upper surface of the read transistor 11R. (Refer to...) Figure 41 As shown, the first gas channel 12W includes a first portion 120 surrounding the first region to be oxidized, and a second portion 121 communicating with the first portion 120 of the first gas channel 12W and extending vertically upward to the upper surface of the storage cell.

[0203] Based on this, the manufacturing method of this embodiment includes: firstly, oxidizing the second region to be oxidized in the second effective semiconductor channel of the read transistor 11R to form a second oxide channel 1120R, referring to... Figure 42 As shown; after forming the second oxidation channel 1120R, the second gas channel 12R is filled with insulating material to form the second filler 13R, as shown in the reference. Figure 43 As shown, the upper surface of the second filler 13R can be flush with the upper surface of the second gas channel 12R to ensure the flatness of the upper surface of the structural layer, which is beneficial to the subsequent fabrication of the structural layer; then, the first region to be oxidized in the first effective semiconductor channel of the write transistor 11W is oxidized to form the first oxide channel 1120W, as shown in the reference. Figure 44 As shown; after forming the first oxidation channel 1120W, the first gas channel 12W is filled with insulating material to form the first filler 13, as shown in the reference. Figure 45 As shown, the upper surface of the first filler 13 is flush with the upper surface of the first gas channel 12W to ensure that the upper surface of the storage array structure is flat, which is beneficial to the fabrication of subsequent structural layers.

[0204] In a specific embodiment of this disclosure, the manufacturing method of the first gas channel 12W may include steps S300, S302, S304, S306, S308 and S310.

[0205] In particular, step S300 can be referred to the description in step S200 above, step S302 can be referred to the description in step S202 above, and step S304 can be referred to the description in step S204 above. The contents of steps S300, S302 and S304 will not be described in detail here.

[0206] In step S306: An intermediate isolation insulating film layer 16 is formed on the lower stacked film layer. The intermediate isolation insulating film layer 16 at least covers the area on the upper surface of the lower isolation insulating film layer 142R that is not covered by the read transistor 11R. The intermediate isolation insulating film layer 16 formed in step S306 can also completely cover the read transistor 11R to protect it. It should be understood that when a lower conductive filling portion 115R is formed at the read transistor 11, the intermediate isolation insulating film layer 16 formed in step S306 can also completely cover both the read transistor 11 and the lower conductive filling portion 115R to protect both the read transistor 11 and the lower conductive filling portion 115R. However, it is not limited to this. At least a portion of the second gate 110R or the lower conductive filling portion 115R may not be blocked by the intermediate isolation insulating film layer 16 to facilitate the subsequent direct connection, indirect connection, or integral molding of the first lower electrode 114W and the second gate 110R, depending on the actual situation.

[0207] In step S308: the second portion 121 of the second gas channel 12R is formed, as shown in the reference. Figure 46 As shown, the second portion 121 of the second gas channel 12R does not overlap with the orthographic projection of the lower via 149R on the semiconductor substrate 10, and the second portion 121 of the second gas channel 12R at least penetrates the intermediate isolation insulating film layer 16 and the lower isolation insulating film layer 142R, and exposes the lower sacrificial insulating film layer 141R.

[0208] In this case, the second portion 121 of the second gas channel 12R does not overlap with the orthographic projection of the read word line and read bit line on the semiconductor substrate 10, so as to ensure the performance of the read word line and read bit line. Since the second portion 121 of the second gas channel 12R does not overlap with the orthographic projection of the read word line and read bit line on the semiconductor substrate 10, the second portion 121 of the second gas channel 12R can penetrate the second upper isolation insulating portion 148R in addition to penetrating the aforementioned film layer. Furthermore, the lower stacked film layer includes a first lower interlayer dielectric layer 143R and a second lower interlayer dielectric layer 144R, and the second portion 121 of the second gas channel 12R can also penetrate the first lower interlayer dielectric layer 143R.

[0209] It should be noted that the second portion 121 of the aforementioned second gas channel 12R extends vertically upward to the upper surface of the read transistor 11R. Here, "the upper surface of the read transistor 11R" can be understood as the upper surface of the structural layer in which the read transistor 11R is located. The structural layer in which the read transistor 11R is located includes a lower stacked film layer and an intermediate isolation insulating film layer 16 located above the lower stacked film layer. Therefore, "the upper surface of the read transistor 11R" can be understood as the upper surface of the intermediate isolation insulating film layer 16. In other words, the second portion 121 of the second gas channel 12R can extend vertically downward from the upper surface of the intermediate isolation insulating film layer 16 to the lower sacrificial insulating film layer 141R. (Refer to...) Figure 41 As shown.

[0210] In some embodiments, the second portion 121 of the second gas channel 12R may extend vertically Z into the interior of the lower sacrificial insulating layer 141R. This reduces the processing difficulty while increasing the exposed area of ​​the lower sacrificial insulating layer 141R, thereby accelerating the subsequent etching rate of the lower sacrificial insulating layer 141R. However, this is not the only possibility; see reference [reference needed]. Figure 46 As shown, the second portion 121 of the second gas channel 12R may also extend just to the upper surface of the lower sacrificial insulating layer 141R, or penetrate through the lower sacrificial insulating layer 141R.

[0211] In some embodiments, multiple second portions 121 of the second gas channels 12R may be provided, and multiple second portions 121 of the second gas channels 12R may surround the outer periphery of each read transistor 11R. This can not only accelerate the etching rate of the lower sacrificial insulating film layer 141R, but also ensure etching uniformity.

[0212] In step S310, an etchant is introduced into the second portion 121 of the second gas channel 12R to remove the lower sacrificial insulating film layer 141R, forming the first portion 120 of the second gas channel 12R surrounding the second region to be oxidized. (Refer to...) Figure 42 As shown. The limitations regarding the etchant can be found in the aforementioned description, and will not be elaborated upon here.

[0213] In this process, after step S310 is completed, oxidizing gas is introduced through the second part 121 of the second gas channel 12R. The oxidizing gas then acts on the second region to be oxidized through the first part 120 of the second gas channel 12R to oxidize the region, forming a second oxidation channel 1120R. After the second oxidation channel 1120R is formed, insulating material is used to fill the second gas channel 12R to form a second filler 13R. (Refer to...) Figure 43 As shown, the upper surface of this second filler 13R can be flush with the upper surface of the intermediate insulating film layer 16 to facilitate the subsequent formation of the write transistor 11W and the structural layer thereon.

[0214] In some embodiments, when the second gas channel 12R is filled with insulating material, a complete filling method can be used, i.e.: Reference Figure 43 As shown, the formed second filler 13R can completely fill the first portion 120 and the second portion 121 of the second gas channel 12R to ensure structural stability. However, this is not the only possibility; in other embodiments, refer to... Figure 47 As shown, an insulating material can also be used to fill a portion of the second gas channel 12R, that is, the formed second filler 13R can partially or completely fill the second part 121 of the second gas channel 12R; for example, an insulating material can be filled into the second part 121 of the second gas channel 12R by a quick sealing method to form the second filler 13R in the second part 121 of the second gas channel 12R.

[0215] It should be understood that when the second filler 13R partially or completely fills the second portion 121 of the second gas channel 12R, the area of ​​the second gas channel 12R other than the area filled by the second filler 13R is a void area. Specifically, refer to... Figure 47As shown, at least the first portion 120 of the second gas channel 12R can be a void region not filled by the second filler 13R, which can reduce the parasitic capacitance between the second upper electrode 113R and the second lower electrode 114R in the read transistor 11R.

[0216] In a specific embodiment of this disclosure, the manufacturing method of the first gas channel 12W may include steps S400, S402, S404, S406 and S408.

[0217] In particular, step S400 can be referred to the description at step S208 above, step S402 can be referred to the description at step S210 above, and step S404 can be referred to the description at step S212 above. The contents of steps S400, S402 and S404 will not be described in detail here.

[0218] In step S406: After forming the write transistor 11W, the second portion 121 of the first gas channel 12W is formed, referencing... Figure 48 As shown, the second portion 121 of the first gas channel 12W does not overlap with the orthographic projection of the upper through hole 177W on the semiconductor substrate 10, and the second portion 121 of the first gas channel 12W at least penetrates the upper insulating film layer 172W and exposes the upper sacrificial insulating film layer 171W.

[0219] The second portion 121 of the first gas channel 12W can extend vertically Z into the interior of the upper sacrificial insulating film layer 171W. This reduces the processing difficulty while increasing the exposed area of ​​the upper sacrificial insulating film layer 171W, thereby accelerating the subsequent etching rate of the upper sacrificial insulating film layer 171W. However, this is not the only possibility; see reference [link / reference]. Figure 48 As shown, the second portion 121 of the first gas channel 12W may also extend just to the upper surface of the upper sacrificial insulating film, or penetrate the upper sacrificial insulating film.

[0220] In addition, multiple second portions 121 of the first gas channel 12W can be provided, and multiple second portions 121 of the first gas channel 12W can surround the outer periphery of each write transistor 11W. This can not only accelerate the etching rate of the upper sacrificial insulating film layer 171W, but also ensure the etching uniformity.

[0221] In some embodiments, the manufacturing method of the first gas channel 12W may further include steps S4051, S4052 and S4053. Step S4051 can be referred to the description at the aforementioned step S2131, step S4052 can be referred to the description at the aforementioned step S2132, and step S4053 can be referred to the description at the aforementioned step S2133. The contents of steps S4051, S4052 and S4053 will not be described in detail here.

[0222] Specifically, the second portion 121 of the first gas channel 12W and the orthogonal projections of the write word line 179W and the write bit line 175W on the semiconductor substrate 10 may not overlap, thus ensuring the performance of the write word line 179W and the write bit line 175W. Since the second portion 121 of the first gas channel 12W and the orthogonal projections of the write word line 179W and the write bit line 175W on the semiconductor substrate 10 do not overlap, the second portion 121 of the first gas channel 12W can penetrate not only the aforementioned film layer, but also the first upper isolation insulating portion 180W and the first lower isolation insulating portion 176W. Furthermore, the upper stacked film layer includes a first upper interlayer dielectric layer 173W and a second upper interlayer dielectric layer 174W, and the second portion 121 of the first gas channel 12W can also penetrate the first upper interlayer dielectric layer 173W.

[0223] It should be noted that the second part 121 of the first gas channel 12W mentioned above extends vertically upward to the upper surface of the storage cell. Here, "upper surface of the storage cell" can be understood as the upper surface of the capping insulating layer 19. That is to say, after the capping insulating layer 19 is formed, referring to... Figure 49 As shown, hole etching is performed vertically downwards from the upper surface of the capping insulating layer 19 until the upper sacrificial insulating film layer 171W is reached. By fabricating the second portion 121 of the first gas channel 12W after the capping insulating layer 19, the capping insulating layer 19 can protect the write transistor 11W and the write word line 179W, preventing damage to the write transistor 11W and the write word line 179W during subsequent hole etching. However, it is not limited to this. The second portion 121 of the first gas channel 12W can also be fabricated after the write transistor 11W (or the upper conductive filling portion 115W) is formed and before the write word line 179W is formed. If protection of the write transistor 11W is achieved in this case, the first upper insulating film layer 180 covering the entire surface can be formed after the write transistor 11W (or the upper conductive filling portion 115W) is formed. In this case, the "upper surface of the memory cell" mentioned above refers to the upper surface of the first upper insulating film layer 180. Then refer to Figure 48 As shown, hole etching is performed vertically downwards from the upper surface of the first upper insulating film layer 180 until the upper sacrificial insulating film layer 171W is etched; then subsequent steps are performed, wherein after the first oxide channel 1120W is formed and the first gas channel 12W is filled with insulating material, the first upper insulating film layer 180 is etched to form the first upper insulating portion 180W, and then the writing line 179W and the capping insulating layer 19 are formed, etc.

[0224] In step S408, an etchant is introduced into the second portion 121 of the first gas channel 12W to remove the upper sacrificial insulating film layer 171W, forming the first portion 120 of the first gas channel 12W surrounding the first region to be oxidized. (Refer to...) Figure 50 As shown; the limitations of the etchant can be found in the aforementioned description, and will not be elaborated upon here.

[0225] In this process, after step S408 is completed, oxidizing gas is introduced through the second part 121 of the first gas channel 12W. The oxidizing gas acts on the first area to be oxidized through the first part 120 of the first gas channel 12W to oxidize the area and form a first oxidation channel 1120W. After the first oxidation channel 1120W is formed, insulating material is used to fill the first gas channel 12W to form a first filler 13W. (Refer to...) Figure 51 As shown, the upper surface of this first filler 13W can be flush with the upper surface of the storage cell to facilitate the formation of subsequent structural layers. In some embodiments, when filling the first gas channel 12W with insulating material, a complete filling method can be adopted, that is, the formed first filler 13W can completely fill the first portion 120 and the second portion 121 of the first gas channel 12W, as shown in the figure. Figure 45 As shown, this is to ensure structural stability. However, it is not limited to this; in other embodiments, an insulating material may also be used to fill a portion of the first gas channel 12W, i.e., refer to... Figure 51 As shown, the first filler 13W formed can partially or completely fill the second part 121 of the first gas channel 12W; for example, an insulating material can be filled into the second part 121 of the first gas channel 12W by a quick sealing method to form the first filler 13W in the second part 121 of the first gas channel 12W.

[0226] It should be understood that when the first filler 13W partially or completely fills the second portion 121 of the first gas channel 12W, the area of ​​the first gas channel 12W other than the area filled by the first filler 13W is a void area. Specifically, refer to... Figure 51 As shown, at least the first portion 120 of the first gas channel 12W can be a void region not filled by the first filler 13W, which can reduce the parasitic capacitance between the first upper electrode 113W and the first lower electrode 114W in the write transistor 11W.

[0227] This disclosure also provides a memory, including a semiconductor substrate 10 and at least one memory cell. The memory cell is formed on the semiconductor substrate 10 and includes at least one transistor 11. Each transistor 11 includes a gate 110, a gate dielectric 111, a semiconductor channel 112, an upper electrode 113, and a lower electrode 114. The semiconductor channel 112 at least surrounds the outer periphery of the gate 110. The gate dielectric 111 is formed between the semiconductor channel 112 and the gate 110. The upper electrode 113 and the lower electrode 114 are both located outside the semiconductor channel 112 and in contact with the semiconductor channel 112. The lower electrode 114 is insulated and disposed below the upper electrode 113. One of the upper electrode 113 and the lower electrode 114 is the source, and the other is the drain.

[0228] In the memory cell: at least one transistor 11 has a portion of its effective semiconductor channel oxidized to form an oxide channel. The effective semiconductor channel is the portion of the semiconductor channel 112 located between the upper electrode 113 and the lower electrode 114. Neither the upper electrode 113 nor the lower electrode 114 is in contact with the oxide channel. Figure 8 , Figure 9 or Figure 10 As shown.

[0229] It should be understood that the memory of this embodiment can be manufactured using the manufacturing method described in any of the foregoing embodiments, and will not be repeated here; however, it is not limited thereto, and the memory of this embodiment can also be formed using other preparation methods.

[0230] In embodiments of this disclosure, there are multiple memory cells arranged in a horizontal plane to form a memory array structure. Each memory cell includes two transistors 11, namely a read transistor 11R and a write transistor 11W. The write transistor 11W includes a first gate 110W, a first gate dielectric 111W, a first semiconductor channel 112W, a first upper electrode 113W, and a first lower electrode 114W; the read transistor 11R includes a second gate 110R, a second gate dielectric 111R, a second semiconductor channel 112R, a second upper electrode 113R, and a second lower electrode 114R; the write transistor 11W is located above the read transistor 11R, and the first lower electrode 114W and the second gate 110R are electrically connected; wherein, a portion of the effective semiconductor channel 112 of at least one of the write transistor 11W and the read transistor 11R is oxidized to form an oxide channel 1120, as shown in the reference. Figure 8 , Figure 9 or Figure 10 As shown.

[0231] In a storage array structure: multiple storage cells are arranged in an array along a first horizontal direction X and a second horizontal direction Y, where the first horizontal direction X intersects the second horizontal direction Y. (Refer to...) Figure 38As shown. For example, the first horizontal direction X is perpendicular or approximately perpendicular to the second horizontal direction Y.

[0232] Combination Figure 26 , Figure 27 , Figure 33 , Figure 34 and Figure 38 As shown, the memory also includes a second lower signal line 145R, a second upper signal line 147R, a write word line 179W, and a write bit line 175W. The second lower signal line 145R extends in the second horizontal direction Y, and multiple second lower signal lines 145R are arranged at intervals in the first horizontal direction X. Each second lower signal line 145R is connected to the second lower electrode 114 of a row of read transistors 11R arranged in the second horizontal direction Y. The second upper signal line 147R extends in the first horizontal direction X, and multiple second lower signal lines 145R are arranged at intervals in the second horizontal direction Y. The second upper signal line 147R is located on the side of the second lower signal line 145R away from the semiconductor substrate 10, and each second upper signal line 147R is connected to the second lower electrode 114 of a row of read transistors 11R arranged in the first horizontal direction X. The electrode 113 is connected. One of the second upper signal line 147R and the second lower signal line 145R is a read word line and the other is a read bit line. The write bit line 175W is formed on the side of the second upper signal line 147R away from the semiconductor substrate 10. The write word line 179W is formed on the side of the write bit line 175W away from the semiconductor substrate 10. One of the write word line 179W and the write bit line 175W extends in the first horizontal direction X and is arranged in multiple intervals in the second horizontal direction Y. The other extends in the second horizontal direction Y and is arranged in multiple intervals in the first horizontal direction X. Each write bit line 175W is connected to the first upper electrode 113 of each write transistor 11W arranged in a row in its extension direction. Each write word line 179W is connected to the first gate 110W of each write transistor 11W arranged in a row in its extension direction.

[0233] In some embodiments, a portion of the first effective semiconductor channel 112 of the write transistor 11W is oxidized to form a first oxide channel 1120W, a first gap region is formed between the first upper electrode 113 and the first lower electrode 114, and the first gap region surrounds the first oxide channel 1120W. (Reference) Figure 14 and Figure 51 As shown.

[0234] Further, refer to Figure 14 and Figure 51As shown, a first upper interlayer dielectric layer 173W is formed between the first upper electrode 113 and the first gap region, and a second upper interlayer dielectric layer 174W is formed between the first lower electrode 114 and the first gap region. Both the first upper interlayer dielectric layer 173W and the second upper interlayer dielectric layer 174W are disposed around the first effective semiconductor channel 112 and do not contact the first oxide channel 1120W.

[0235] In some other embodiments, a portion of the first effective semiconductor channel 112 of the write transistor 11W is oxidized to form a first oxide channel 1120W. A first insulating layer is formed between the first upper electrode 113 and the first lower electrode 114. The first insulating layer surrounds the first oxide channel 1120W and is seamlessly connected to the lower surface of the first upper electrode 113 and the upper surface of the first lower electrode 114. (Refer to...) Figure 9 , Figure 10 , Figure 13 or Figure 45 As shown.

[0236] For example, the first insulating layer may be a composite film layer comprising a first upper interlayer dielectric layer 173W, a second upper interlayer dielectric layer 174W, and a first filler 13W.

[0237] In some embodiments, a portion of the second effective semiconductor channel 112 of the read transistor 11R is oxidized to form a second oxide channel 1120R, a second gap region is formed between the second upper electrode 113 and the second lower electrode 114, and the second gap region surrounds the second oxide channel 1120R. Figure 14 or Figures 47 to 51 As shown.

[0238] Furthermore, a first lower interlayer dielectric layer 143R is formed between the second upper electrode 113 and the second gap region, and a second lower interlayer dielectric layer 144R is formed between the second lower electrode 114 and the second gap region. The first lower interlayer dielectric layer 143R and the second lower interlayer dielectric layer 144R are both disposed around the second effective semiconductor channel 112 and do not contact the second oxide channel 1120R.

[0239] In other embodiments, a portion of the second effective semiconductor channel 112 of the read transistor 11R is oxidized to form a second oxide channel 1120R. A second insulating layer is formed between the second upper electrode 113 and the second lower electrode 114. The second insulating layer surrounds the second oxide channel 1120R and is seamlessly connected to the lower surface of the second upper electrode 113 and the upper surface of the second lower electrode 114. (Refer to...) Figure 8 , Figure 10 , Figure 13 or Figure 44 As shown.

[0240] For example, the second insulating layer may be a composite film layer comprising a first lower interlayer dielectric layer 143R, a second lower interlayer dielectric layer 144R, and a second filler 13R.

[0241] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0242] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0243] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A method for manufacturing a memory, characterized in that, Includes the following steps: Provide a semiconductor substrate; At least one memory cell is fabricated on the semiconductor substrate. The memory cell includes at least one transistor. Each transistor includes a gate, a gate dielectric, a semiconductor channel, an upper electrode, and a lower electrode. The semiconductor channel surrounds at least the outer periphery of the gate. The gate dielectric is formed between the semiconductor channel and the gate. The upper electrode and the lower electrode are both located outside the semiconductor channel and in contact with the semiconductor channel. The lower electrode is insulated and disposed below the upper electrode. One of the upper electrode and the lower electrode is a source electrode, and the other is a drain electrode. The region to be oxidized in the effective semiconductor channel of at least one transistor in the memory cell is oxidized to form an oxide channel, wherein the region to be oxidized is at least a portion of the effective semiconductor channel, and neither the upper electrode nor the lower electrode is in contact with the oxide channel; wherein the effective semiconductor channel is the portion of the semiconductor channel located between the upper electrode and the lower electrode.

2. The method for manufacturing a memory according to claim 1, characterized in that, After oxidizing the region to be oxidized, the method further includes: heat-treating the oxidized region; or The oxidation process also includes heat treatment of the region to be oxidized.

3. The method for manufacturing a memory according to claim 1 or 2, characterized in that, Before oxidizing the region to be oxidized, the manufacturing method further includes preparing a gas channel, the gas channel including a first portion surrounding the outer periphery of the region to be oxidized, and a second portion communicating with the first portion and extending vertically upward, so that oxidizing gas introduced from above the second portion acts on the region to be oxidized.

4. The method for manufacturing a memory according to claim 3, characterized in that, After forming the oxidation channel, the manufacturing method further includes filling the gas channel with an insulating material.

5. The method for manufacturing a memory according to claim 4, characterized in that, The step of filling the gas channel with insulating material includes: completely filling the gas channel with insulating material to form a filler body inside the gas channel, wherein the upper surface of the filler body is flush with the upper surface of the gas channel.

6. The method for manufacturing a memory according to claim 4, characterized in that, The step of filling the gas channel with insulating material includes: partially or completely filling the second part of the gas channel with insulating material to form a filler in the second part, wherein the upper surface of the filler is flush with the upper surface of the gas channel, and the gas channel is a void area except for the area filled by the filler.

7. The method for manufacturing a memory according to claim 4, characterized in that, The number of storage cells is multiple, and they are arranged in a horizontal plane to form a storage array structure. Each storage cell includes two transistors, namely a read transistor and a write transistor. The write transistor includes: a first gate, a first gate dielectric, a first semiconductor channel, a first upper electrode, and a first lower electrode; The read transistor includes: a second gate, a second gate dielectric, a second semiconductor channel, a second upper electrode, and a second lower electrode; The write transistor is located above the read transistor, and the first lower electrode and the second gate are electrically connected; The manufacturing method includes: oxidizing the region to be oxidized in the effective semiconductor channel of at least one of the write transistor and the read transistor.

8. The method for manufacturing a memory according to claim 7, characterized in that, The manufacturing method includes: oxidizing the region to be oxidized in the effective semiconductor channel of one of the write transistor and the read transistor to form an oxide channel; The gas channel is prepared after the transistor corresponding to the region to be oxidized is prepared.

9. The method for manufacturing a memory according to claim 7, characterized in that, The manufacturing method includes: The first region to be oxidized in the first effective semiconductor channel of the write transistor is oxidized to form a first oxide channel; and The second region to be oxidized in the second effective semiconductor channel of the read transistor is oxidized to form a second oxide channel.

10. The method for manufacturing a memory according to claim 9, characterized in that, The first oxide channel and the second oxide channel are formed simultaneously, and the gas channel is prepared after the write transistor is prepared; The gas channel includes an upper first portion surrounding the outer periphery of the first region to be oxidized and a lower first portion surrounding the outer periphery of the second region to be oxidized. The upper first portion and the lower first portion are spaced apart in the vertical direction. The second portion extends vertically upward to the upper surface of the storage unit and connects the upper first portion and the lower first portion, so that the oxidizing gas introduced from above the second portion can act on both the first region to be oxidized and the second region to be oxidized simultaneously for oxidation treatment.

11. The method for manufacturing a memory according to claim 10, characterized in that, The method for manufacturing the gas channel includes: A lower stacked film layer is formed on the semiconductor substrate, the lower stacked film layer comprising at least a second lower electrode, a lower sacrificial insulating film layer, a second upper electrode, and a lower isolation insulating film layer stacked sequentially in a vertical direction; A lower via is formed that penetrates at least the lower insulating film layer, the second upper electrode, and the lower sacrificial insulating film layer, wherein the second lower electrode is exposed by the lower via; The second semiconductor channel, the second gate dielectric, and the second gate are formed at the lower via to form the read transistor, wherein the second region to be oxidized in the second semiconductor channel is located at a position surrounded by the lower sacrificial insulating film layer; An intermediate isolation insulating film layer is formed on the lower stacked film layer. The intermediate isolation insulating film layer at least covers the area on the upper surface of the lower isolation insulating film layer that is not covered by the read transistor, and at least a portion of the second gate does not overlap with the orthographic projection of the intermediate isolation insulating film layer on the semiconductor substrate. An upper stacked film layer is formed, the upper stacked film layer including at least a first lower electrode, an upper sacrificial insulating film layer, a first upper electrode and an upper isolation insulating film layer stacked in sequence along the vertical direction, the first lower electrode being connected to the second gate, and the upper surface of the first lower electrode being flush with the upper surface of the intermediate isolation insulating film layer; An upper via is formed that penetrates at least the upper insulating film layer, the first upper electrode, and the upper sacrificial insulating film layer, wherein the first lower electrode is exposed by the upper via; The first semiconductor channel, the first gate dielectric, and the first gate are sequentially formed at the upper via to form the write transistor, wherein the first region to be oxidized in the first semiconductor channel is located at a position surrounded by the upper sacrificial insulating film layer; After the write transistor is formed, the second portion of the gas channel is formed, the second portion not overlapping the orthographic projections of the lower via and the upper via on the semiconductor substrate, and the second portion at least penetrates the upper isolation insulating film layer, the upper sacrificial insulating film layer, the intermediate isolation insulating film layer and the lower isolation insulating film layer, and exposes the lower sacrificial insulating film layer; An etchant is introduced into the second portion to remove the upper sacrificial insulating film layer and the lower sacrificial insulating film layer, forming an upper first portion surrounding the first region to be oxidized and a lower first portion surrounding the second region to be oxidized.

12. The method for manufacturing a memory according to claim 9, characterized in that, The gas channel includes a first gas channel and a second gas channel; the first gas channel includes a first portion surrounding the first region to be oxidized, and a second portion communicating with the first portion of the first gas channel and extending vertically upward to the upper surface of the memory cell; the second gas channel includes a first portion surrounding the second region to be oxidized, and a second portion communicating with the first portion of the second gas channel and extending vertically upward to the upper surface of the read transistor; wherein, the manufacturing method includes: First, the second region to be oxidized in the second effective semiconductor channel of the read transistor is oxidized to form a second oxide channel. After the second oxide channel is formed, the second gas channel is filled with an insulating material to form a second filler. The upper surface of the second filler is flush with the upper surface of the second gas channel. Then, the first region to be oxidized in the first effective semiconductor channel of the write transistor is oxidized to form a first oxide channel. After the first oxide channel is formed, the first gas channel is filled with an insulating material to form a first filler. The upper surface of the first filler is flush with the upper surface of the first gas channel.

13. The method for manufacturing a memory according to claim 12, characterized in that, The second filling material completely fills the first and second portions of the second gas channel; Alternatively, the second filler partially or completely fills the second portion of the second gas channel, wherein the area of ​​the second gas channel other than the area filled by the second filler is a void area.

14. The method for manufacturing a memory according to claim 12, characterized in that, The first filling material completely fills the first and second portions of the first gas channel; Alternatively, the first filler may partially or completely fill the second portion of the first gas channel, wherein the area of ​​the first gas channel other than the area filled by the first filler is a void area.

15. The method for manufacturing a memory according to claim 12, characterized in that, The method for manufacturing the first gas channel includes: A lower stacked film layer is formed on the semiconductor substrate, the lower stacked film layer comprising at least a second lower electrode, a lower sacrificial insulating film layer, a second upper electrode, and a lower isolation insulating film layer stacked sequentially; A lower via is formed that penetrates at least the lower insulating film layer, the second upper electrode, and the lower sacrificial insulating film layer, wherein the second lower electrode is exposed by the lower via; The second semiconductor channel, the second gate dielectric, and the second gate are formed at the lower via to form the read transistor, wherein the second region to be oxidized in the second semiconductor channel is located at a position surrounded by the lower sacrificial insulating film layer; An intermediate isolation insulating film layer is formed on the lower stacked film layer, the intermediate isolation insulating film layer at least covering the area on the upper surface of the lower isolation insulating film layer that is not covered by the read transistor; a second portion of a second gas channel is formed, the second portion of the second gas channel does not overlap with the orthographic projection of the lower via on the semiconductor substrate, and the second portion of the second gas channel at least penetrates the intermediate isolation insulating film layer and the lower isolation insulating film layer, and exposes the lower sacrificial insulating film layer; An etchant is introduced into the second portion of the second gas channel to remove the lower sacrificial insulating film layer, forming the first portion of the second gas channel surrounding the second region to be oxidized.

16. The method for manufacturing a memory according to claim 15, characterized in that, The method for manufacturing the first gas channel includes: An upper stacked film layer is formed, the upper stacked film layer including at least a first lower electrode, an upper sacrificial insulating film layer, a first upper electrode and an upper isolation insulating film layer stacked in sequence, the first lower electrode being connected to the second gate, and the upper surface of the first lower electrode being flush with the upper surface of the intermediate isolation insulating film layer; An upper via is formed that penetrates at least the upper insulating film layer, the first upper electrode, and the upper sacrificial insulating film layer, wherein the first lower electrode is exposed by the upper via; The first semiconductor channel, the first gate dielectric, and the first gate are sequentially formed at the upper via to form the write transistor, wherein the first region to be oxidized in the first semiconductor channel is located at a position surrounded by the upper sacrificial insulating film layer; After the write transistor is formed, a second portion of the first gas channel is formed, wherein the second portion of the first gas channel does not overlap with the orthographic projection of the upper via on the semiconductor substrate, and the second portion of the first gas channel at least penetrates the upper isolation insulating film layer, exposing the upper sacrificial insulating film layer; An etchant is introduced into the second portion of the first gas channel to remove the upper sacrificial insulating film layer, forming the first portion of the first gas channel surrounding the first region to be oxidized.

17. The manufacturing method according to claim 11 or 16, characterized in that, The lower stacked film layer further includes a first lower interlayer dielectric layer and a second lower interlayer dielectric layer, which are different from the material of the lower sacrificial insulating film layer. The first lower interlayer dielectric layer is formed between the second upper electrode and the lower sacrificial insulating film layer and is disposed around the second effective semiconductor channel. The second lower interlayer dielectric layer is formed between the second lower electrode and the lower sacrificial insulating film layer and is disposed around the second effective semiconductor channel. The upper stacked film layer further includes a first upper interlayer dielectric layer and a second upper interlayer dielectric layer, which are made of materials different from those of the upper sacrificial insulating film layer. The first upper interlayer dielectric layer is formed between the first upper electrode and the upper sacrificial insulating film layer and is disposed around the first effective semiconductor channel. The second upper interlayer dielectric layer is formed between the first lower electrode and the upper sacrificial insulating film layer and is disposed around the first effective semiconductor channel. During the process of removing the upper sacrificial insulating film layer and the lower sacrificial insulating film layer using the etchant, the first lower interlayer dielectric layer, the second lower interlayer dielectric layer, the first upper interlayer dielectric layer, and the second upper interlayer dielectric layer are retained.

18. A memory, characterized in that, include: Semiconductor substrate; as well as At least one memory cell is formed on the semiconductor substrate. The memory cell includes at least one transistor. Each transistor includes a gate, a gate dielectric, a semiconductor channel, an upper electrode, and a lower electrode. The semiconductor channel surrounds at least the outer periphery of the gate. The gate dielectric is formed between the semiconductor channel and the gate. The upper electrode and the lower electrode are both located outside the semiconductor channel and in contact with the semiconductor channel. The lower electrode is insulated and disposed below the upper electrode. One of the upper electrode and the lower electrode is a source and the other is a drain. In the memory cell: at least one of the transistors has a portion of its effective semiconductor channel oxidized to form an oxide channel, the effective semiconductor channel being the portion of the semiconductor channel located between the upper electrode and the lower electrode, and neither the upper electrode nor the lower electrode being in contact with the oxide channel.

19. The memory according to claim 18, characterized in that, The number of storage cells is multiple, and they are arranged in a horizontal plane to form a storage array structure. Each storage cell includes two transistors, namely a read transistor and a write transistor. The write transistor includes: a first gate, a first gate dielectric, a first semiconductor channel, a first upper electrode, and a first lower electrode; The read transistor includes: a second gate, a second gate dielectric, a second semiconductor channel, a second upper electrode, and a second lower electrode; The write transistor is located above the read transistor, and the first lower electrode and the second gate are electrically connected; In this embodiment, a portion of the effective semiconductor channel of at least one of the write transistor and the read transistor is formed into the oxide channel through an oxidation process.

20. The memory according to claim 19, characterized in that, In the storage array structure: a plurality of storage cells are arranged in an array in a first horizontal direction and a second horizontal direction, the first horizontal direction intersecting the second horizontal direction.

21. The memory according to claim 20, characterized in that, The memory also includes: Multiple second lower signal lines are spaced apart in a first horizontal direction and extend in a second horizontal direction, each of the second lower signal lines being connected to the second lower electrode of each of the read transistors arranged in a row in the second horizontal direction; Multiple second upper signal lines are spaced apart in a second horizontal direction and extend in a first horizontal direction. The second upper signal lines are located on the side of the second lower signal lines away from the semiconductor substrate. Each second upper signal line is connected to the second upper electrode of a row of read transistors arranged in the first horizontal direction. One of the second upper signal lines and the second lower signal line is a read word line, and the other is a read bit line. The system includes a write word line and a write bit line. The write bit line is formed on the side of the second upper signal line away from the semiconductor substrate. The write word line is formed on the side of the write bit line away from the semiconductor substrate. One of the write word line and the write bit line extends in a first horizontal direction and is arranged in multiple lines spaced apart in a second horizontal direction. The other extends in the second horizontal direction and is arranged in multiple lines spaced apart in the first horizontal direction. Each write bit line is connected to the first upper electrode of a row of write transistors arranged in its extending direction. Each write word line is connected to the first gate of a row of write transistors arranged in its extending direction.

22. The memory according to claim 19, characterized in that, A portion of the first effective semiconductor channel of the write transistor is oxidized to form a first oxide channel, and a first void region is formed between the first upper electrode and the first lower electrode. The first void region surrounds the first oxide channel. A portion of the second effective semiconductor channel of the read transistor is oxidized to form a second oxide channel, and a second void region is formed between the second upper electrode and the second lower electrode, the second void region surrounding the second oxide channel.

23. The memory according to claim 22, characterized in that, A first upper interlayer dielectric layer is formed between the first upper electrode and the first gap region, and a second upper interlayer dielectric layer is formed between the first lower electrode and the first gap region. Both the first upper interlayer dielectric layer and the second upper interlayer dielectric layer are disposed around the first effective semiconductor channel and do not contact the first oxide channel. A first lower interlayer dielectric layer is formed between the second upper electrode and the second gap region, and a second lower interlayer dielectric layer is formed between the second lower electrode and the second gap region. Both the first lower interlayer dielectric layer and the second lower interlayer dielectric layer are disposed around the second effective semiconductor channel and do not contact the second oxide channel.

24. The memory according to claim 19, characterized in that, A portion of the first effective semiconductor channel of the write transistor is oxidized to form a first oxide channel. A first insulating layer is formed between the first upper electrode and the first lower electrode. The first insulating layer surrounds the first oxide channel and is seamlessly connected to the lower surface of the first upper electrode and the upper surface of the first lower electrode. A portion of the second effective semiconductor channel of the read transistor is oxidized to form a second oxide channel. A second insulating layer is formed between the second upper electrode and the second lower electrode. The second insulating layer surrounds the second oxide channel and is seamlessly connected to the lower surface of the second upper electrode and the upper surface of the second lower electrode.

Images