Three-dimensional memory device and manufacturing method thereof

Abstract

Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a 3D NAND memory device includes a substrate, a layer stack, a memory cell, a semiconductor layer, a contact structure, and a gate slot structure. The substrate includes a doped region. A layer stack is formed over a substrate. A memory cell is formed over the substrate through the layer stack. A semiconductor layer is formed on the doped region and a side portion of the channel layer extending through the layer stack. The contact structure electrically contacts the doped region. And filling a dielectric material in the grid line gap structure. An air gap is formed through a dielectric material in the gate line gap structure.

Description

[0001] This application is a divisional application of the Chinese invention patent application with the application date of July 6, 2020, application number 202080001483.0, and application name “Three-dimensional memory device and manufacturing method thereof”. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular, to a three-dimensional (3D) memory device and a method for manufacturing the same. Background Art

[0003] NAND memory is a non-volatile type of memory that does not require power to maintain stored data. The growing demand for consumer electronics, cloud computing, and big data has brought about a continued need for NAND memory with larger capacity and better performance. As conventional two-dimensional (2D) NAND memory approaches its physical limits, three-dimensional (3D) NAND memory now plays an important role. 3D NAND memory uses multiple stacked layers in a single chip to achieve higher density, higher capacity, faster performance, lower power consumption, and better cost efficiency.

[0004] 3D NAND structure is built on a substrate (e.g., a silicon wafer). In the manufacturing process, many layers are formed on the substrate to form a layer stack. When multiple layers (e.g., silicon oxide layers, silicon nitride layers, polycrystalline silicon (polysilicon) layers, and / or tetraethyl orthosilicate (TEOS) layers) are stacked on top of each other, stress may accumulate in the wafer and cause the wafer to bend. Other manufacturing processes (e.g., etching, filling, and heat treatment) may further aggravate the stress and wafer bending problems. This may cause poor alignment of the underlying features. When the wafer bends beyond a certain limit, operational difficulties and yield problems may occur.

[0005] The disclosed methods and systems are directed to solving one or more of the problems set forth above and other problems. Summary of the invention

[0006] In one aspect of the present disclosure, a 3D NAND memory device includes a substrate having a doped region, a layer stack, a memory cell, a semiconductor layer, a contact structure, and a gate line gap structure. The layer stack is formed on the substrate. The memory cell is formed on the substrate through the layer stack. The semiconductor layer is formed on the doped region and the side portion of the channel layer extending through the layer stack. The contact structure electrically contacts the doped region. The gate line gap structure is formed through the layer stack to divide the memory cell into blocks. A dielectric material is filled in each of the gate line gap structures. One or more air gaps are formed in one or more of the gate line gaps through the dielectric material.

[0007] In another aspect of the present disclosure, a method for manufacturing a 3D NAND memory device includes: forming a layer stack over a doped region of a substrate, forming a memory cell through the layer stack over the doped region, forming a semiconductor layer on the doped region and a side portion of a channel layer extending through the layer stack, forming a contact structure electrically contacting the doped region, forming a gate line gap structure through the layer stack to divide the memory cell into blocks, and filling each of the gate line gap structures with a dielectric material. One or more air gaps are formed in one or more of the gate line gap structures through the dielectric material.

[0008] In another aspect of the present disclosure, a method for manufacturing a 3D NAND memory device includes: forming a layer stack on a first substrate, trimming the layer stack to form a stepped structure, forming a channel layer, forming a gate line gap structure, and filling the gate line gap structure with a filling material to form an air gap. The maximum width of the air gap is equal to or greater than a value obtained using a measurement result or an estimation result. The layer stack includes a first stack layer and a second stack layer stacked alternately. The first stack layer includes a first dielectric material, and the second stack layer includes a second dielectric material. The channel layer and the gate line gap structure extend through the layer stack in a direction approximately perpendicular to the first substrate.

[0009] Other aspects of the present disclosure may be understood by those skilled in the art based on the specification, claims and drawings of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 and Figure 2 schematically illustrates a cross-sectional view of a three-dimensional (3D) array device in an exemplary manufacturing process according to an embodiment of the present disclosure;

[0011] Figure 3 and Figure 4 Schematically shows the process after forming the channel hole according to an embodiment of the present disclosure. Figure 2 A top view and a cross-sectional view of the 3D array device shown in ;

[0012] Figure 5 and Figure 6 Schematically shows the process after forming the gate line gap according to an embodiment of the present disclosure. Figure 3 and Figure 4 A top view and a cross-sectional view of the 3D array device shown in ;

[0013] Figure 7 and Figure 8 Schematically illustrates an embodiment of the present disclosure after certain manufacturing steps. Figure 5 and Figure 6 A cross-sectional view of a 3D array device shown in;

[0014] Fig. 9A , Fig. 9B and Fig. 9C Schematically shows the embodiment of the present disclosure after forming the air gap Figure 8 A cross-sectional view of a 3D array device shown in;

[0015] Fig.10 and Fig.11 Schematically shows the process of forming certain contacts according to an embodiment of the present disclosure. Fig. 9A A cross-sectional view of a 3D array device shown in;

[0016] Figure 12-17 Schematically shows an embodiment of the present disclosure. Fig.11 A cross-sectional view of a 3D memory device after the 3D array device is bonded to a peripheral device;

[0017] Fig.18 A schematic flow chart showing the fabrication of a 3D memory device according to an embodiment of the present disclosure;

[0018] Fig.19 and Fig. 20 schematically shows a cross-sectional view of another 3D array device in an exemplary manufacturing process according to an embodiment of the present disclosure;

[0019] Fig.21 and Fig. 22 Schematically shows the process after forming the channel hole and the gate line gap according to an embodiment of the present disclosure. Fig.19 and Fig. 20 A top view and a cross-sectional view of the 3D array device shown in ;

[0020] Fig.23A , Fig. 23B and Fig.23C Schematically shows the embodiment of the present disclosure after forming the air gap Fig.21 and Fig. 22 A cross-sectional view of a 3D array device shown in;

[0021] Fig.24 Schematically shows the process of forming certain contacts according to an embodiment of the present disclosure. Fig.23A A cross-sectional view of a 3D array device shown in;

[0022] Fig.25 schematically shows a cross-sectional view of a peripheral device according to an embodiment of the present disclosure;

[0023] Fig.26 Schematically shows an embodiment of the present disclosure. Fig.24 The 3D array device shown is similar to Fig.25A cross-sectional view of another 3D memory device after peripheral device bonding is shown;

[0024] Fig. 27 and Fig.28 schematically shows a cross-sectional view of another 3D array device in an exemplary manufacturing process according to an embodiment of the present disclosure;

[0025] Fig.29 and Fig.30 Schematically shows the process after forming the channel hole and the gate line gap according to an embodiment of the present disclosure. Fig. 27 and Fig.28 A top view and a cross-sectional view of the 3D array device shown in ;

[0026] Fig.31A , Fig.31B and Fig. 31C Schematically shows the embodiment of the present disclosure after forming the air gap Fig.29 and Fig.30 A cross-sectional view of a 3D array device shown in;

[0027] Fig.32 Schematically shows the process of forming certain contacts according to an embodiment of the present disclosure. Fig.31A A cross-sectional view of a 3D array device shown in;

[0028] Fig.33 A cross-sectional view schematically illustrates another peripheral device according to an embodiment of the present disclosure; and

[0029] Fig.34 Schematically shows an embodiment of the present disclosure. Fig.32 The 3D array device shown is similar to Fig.33 A cross-sectional view of another 3D memory device after peripheral device bonding is shown. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present disclosure will be described below with reference to the accompanying drawings. Where possible, the same reference numerals will be used in all drawings to represent the same or similar components. Obviously, the embodiments described are only some embodiments of the present disclosure rather than all embodiments. The features in the various embodiments can be exchanged and / or combined. Other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative work will also fall within the scope of the present disclosure.

[0031] Figure 1-11 The manufacturing process of an exemplary 3D array device 100 according to an embodiment of the present disclosure is schematically shown. Figure 1-11 In , the cross-section view is in the YZ plane, and the top view is in the XY plane. Figure 1As shown, the 3D array device 100 includes a substrate 110 .

[0032] In some embodiments, the substrate 110 may include a single crystal silicon layer. In some other embodiments, the substrate 110 may include a semiconductor material, such as germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI), polycrystalline silicon, III-V compounds (e.g., gallium arsenide (GaAs) or indium phosphide (InP)), etc. In some other embodiments, the substrate 110 may include a non-conductive material, such as glass, a plastic material, or a ceramic material. As an example, the substrate 110 includes an undoped or lightly doped single crystal silicon layer. In some other embodiments, the substrate 110 may be doped differently with p-type or n-type dopants. When the substrate 110 includes glass, plastic, or ceramic material, the substrate 110 may also include a thin layer of polycrystalline silicon deposited on the glass, plastic, or ceramic material. In this case, the substrate 110 may be processed like a polycrystalline silicon substrate.

[0033] In some embodiments, the top portion of the substrate 110 may be doped with an n-type dopant via ion implantation and / or diffusion to form a doped region 111. For example, the dopant of the doped region 111 may include phosphorus (P), arsenic (As), and / or antimony (Sb). Figure 1 As shown, the capping layer 120 may be deposited on the doped region 111. The capping layer 120 may be a sacrificial layer and may include a single layer, a multilayer, or a suitable composite layer. For example, the capping layer 120 may include one or more of a silicon oxide layer and a silicon nitride layer. The capping layer 120 may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof. In some other embodiments, the capping layer 120 may include another material such as aluminum oxide.

[0034] On top of the capping layer 120, a sacrificial layer 130 may be deposited. The sacrificial layer 130 may include a dielectric material, a semiconductor material, or a conductive material. For example, the sacrificial layer 130 may be single crystal silicon or polycrystalline silicon, which may be deposited by a CVD and / or PVD process. An exemplary material for the sacrificial layer 130 is polycrystalline silicon.

[0035] After forming the polysilicon sacrificial layer 130, a layer stack 140 may be formed. The layer stack 140 includes a plurality of pairs of stacked layers 141 and 142, for example, the stacked layers 141 and 142 are alternately stacked with each other. For example, the layer stack may include 64 pairs, 128 pairs, or more than 128 pairs of stacked layers 141 and 142.

[0036] In some embodiments, stacked layers 141 and 142 may include a first dielectric material and a second dielectric material different from the first dielectric material, respectively. Alternating stacked layers 141 and 142 may be deposited via CVD, PVD, ALD, or a combination thereof. Exemplary materials for stacked layers 141 and 142 include silicon oxide and silicon nitride, respectively. The silicon oxide layer may be used as an isolation stacked layer, and the silicon nitride layer may be used as a sacrificial stacked layer. The sacrificial stacked layer may then be etched away and replaced with a conductor layer including a conductive material.

[0037] refer to Figure 2 , a step structure can be formed by a step forming process based on the layer stack 140. Any suitable etching process (including dry etching and / or wet etching process) can be used in the step forming process. The layer stack 140 can be trimmed by an etching process to form a step structure. For example, Figure 2 As shown, the height of the step structure of the layer stack 140 may increase in a stepwise manner along the Y direction. The dielectric layer 121 is formed to cover the step structure.

[0038] Figure 3 and Figure 4 Schematically shows a top view and a cross-sectional view of a 3D array device 100 after forming a channel hole 150 and then filling it with a layer structure according to an embodiment of the present disclosure. Figure 3 and Figure 4 The number, size, and arrangement of the channel holes 150 shown in the other figures are merely exemplary and used for descriptive purposes, although any suitable number, size, and arrangement may be used for the disclosed device 100 according to various embodiments of the present disclosure.

[0039] The channel holes 150 are configured to extend in the Z direction or in a direction approximately perpendicular to the substrate 110 and form an array of a predetermined pattern in the XY plane. Figure 4 The cross-sectional view shown in FIG. Figure 3 The line AA' is intercepted. Figure 4 Only the cross-sectional view in the YZ plane is shown. Figure 3 Some of the channel holes 150.

[0040] The channel hole 150 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes. Other manufacturing processes, such as patterning processes including photolithography, cleaning, and / or chemical mechanical polishing (CMP), may also be performed. The channel hole 150 may have a cylindrical or columnar shape extending through the layer stack 140, the sacrificial layer 130, the capping layer 120, and partially penetrating the doped region 111. After forming the channel hole 150, a functional layer 151 may be deposited on the sidewalls and bottom of the channel hole. The functional layer 151 may include a blocking layer 152 on the sidewalls and bottom of the channel hole to block the outflow of charges, a charge trapping layer 153 on the surface of the blocking layer 152 to store charges during the operation of the 3D array device 100, and a tunnel insulating layer 154 on the surface of the charge trapping layer 153. The blocking layer 152 may include one or more layers, which may include one or more materials. The material for the blocking layer 152 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, etc. The charge trapping layer 153 may include one or more layers, which may include one or more materials. The material for the charge trapping layer 153 may include polysilicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide bandgap material, etc. The tunnel insulating layer 154 may include one or more layers, which may include one or more materials. The material for the tunnel insulating layer 154 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, etc.

[0041] In some embodiments, the functional layer 151 may include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer 151 may have a structure different from the ONO configuration. For example, the functional layer 151 may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer.

[0042] like Figure 4 As shown, the blocking layer 152 may be, for example, a silicon oxide layer deposited on the sidewalls of the channel hole 150. The charge trapping layer 153 may be, for example, a silicon nitride layer deposited on the blocking layer 152. The tunnel insulating layer 154 may be, for example, another silicon oxide layer deposited on the charge trapping layer 153. The channel layer 155 (also referred to as a "semiconductor channel") may be, for example, a polysilicon layer deposited on the tunnel insulating layer 154. In some other embodiments, the channel layer 155 may include amorphous silicon. Similar to the channel hole, the channel layer 155 also extends through the layer stack 140 and into the doped region 111. As shown in FIG. Figure 4As shown, a portion of each functional layer 151 is disposed between a portion of one of the stacked layers 141 and 142 and a portion of one of the channel layers 155. The blocking layer 152, the charge trapping layer 153, the tunnel insulating layer 154, and the channel layer 155 may be deposited by, for example, CVD, PVD, ALD, or a combination of two or more of these processes. After the channel layer 155 is formed, the channel hole 150 may be filled with an oxide material 156.

[0043] In the above process, after the step structure is formed, the channel hole 150 is etched. In some other embodiments, the channel hole 150 may be formed before the step formation process. Figure 1 After manufacturing the layer structure 140 as shown, the channel hole 150 may be formed, and then the functional layer 151 and the channel layer 155 may be deposited. After filling the channel hole 150 with the oxide material 156, a step formation process may be performed to form a Figure 4 The stepped structure shown.

[0044] In some other embodiments, the layer stack 140 may be referred to as the first layer stack. After manufacturing the layer stack 140 (i.e., the first layer stack) in a stepped form and manufacturing the channel hole 150 having the functional layer 151 and the channel layer 155, the second layer stack (not shown) in a stepped form may be made on the layer stack 140. A channel hole aligned with the channel hole 150 may be formed, and the functional layer and the channel layer may be deposited in the second layer stack. Each channel layer of the second layer stack may be aligned with the corresponding channel layer 155 and electrically connected to the corresponding channel layer 155. In a similar manner, a third or more layer stack may be formed on the second layer stack. In this way, a multilayer stack may be formed and integrated on the substrate 110, and the storage capacity of the 3D array device 100 may be multiplied. In the following description, the layer stack 140 is used to illustrate the structure and manufacturing method of the device 100.

[0045] Figure 5 and Figure 6 Schematically illustrates a top view and a cross-sectional view of the 3D array device 100 after the gate line slits 160 are formed according to an embodiment of the present disclosure. Figure 6 The cross-sectional view shown in FIG. Figure 5 The 3D array device 100 may have a large number of NAND memory cells configured or residing in the layer stack 140. The layer stack 140 may be divided into a plurality of memory blocks. In some embodiments, the NAND memory cells belonging to the memory blocks may be reset together in a block erase operation. Figure 5The channel holes shown in the figure may form an exemplary memory block, which is separated from other memory block regions (not shown) by a gate line gap 160, which may also be referred to as a gate line gap structure 160. For example, Figure 5 and Figure 6 The pair of gate line slits 160 shown in FIG. 1 define a block therebetween. In some other embodiments, one or more additional gate line slits may be formed between the pair of gate line slits 160.

[0046] When the layer stack 140 is formed with multiple stacked layers 141 and 142 deposited on top of each other, stress is introduced, which causes the wafer to bend. The step formation process plus the filling process of the channel hole can cause the wafer to bend further. Since the bent wafer causes alignment problems and even yield problems, it is very desirable to reduce film stress and wafer bending.

[0047] During the manufacture of the 3D array device 100, the wafer bow can be measured, especially after the step structure is made and the channel hole 150 is formed. Optical methods can be used to directly detect the wafer bow. In some embodiments, the lowest and highest points of the 3D array device 100 can be optically detected, and the measurement results can be used to calculate the wafer bow. In some embodiments, after the wafer bow is quantified, the position, size, profile and filling of the gate line gap 160 in the YZ plane can be determined to reduce the wafer bow.

[0048] In some other embodiments, wafer bow is not directly measured during the manufacturing process. Instead, other data and previous records may be used to determine wafer bow. Other data may include materials used, processes performed, and measurement data other than measurement data for wafer bow detection. Previous records may include previously obtained measurement results and bow reduction solutions.

[0049] In some embodiments, the size and shape of the gate line gaps 160 can be the same or similar. In some other embodiments, the size and shape of the gate line gaps 160 can be arranged differently to reduce wafer bending. For example, the maximum gap width of one gap can be different from the maximum gap width of another gap along the Y direction.

[0050] The gate line gap 160 may be formed by, for example, a dry etching process or a combination of a dry etching process and a wet etching process. Figure 6As shown, the gate line gap 160 can extend through the layer stack 140 and reach or partially penetrate the sacrificial layer 130 in the Z direction or in a direction approximately perpendicular to the substrate 110. Therefore, at the bottom of the gate line gap 160, the sacrificial layer 130 is exposed. Then, a spacer layer (not shown) can be deposited on the sidewall and bottom of the gate line gap 160 by CVD, PVD, ALD, or a combination of two or more of these processes. The spacer layer is configured to protect the stacked layers 141 and 142, and can include, for example, silicon oxide and silicon nitride.

[0051] After the spacer layer is deposited, selective etching may be performed so that the portion of the spacer layer at the bottom of the gap is removed by dry etching or a combination of dry etching and wet etching. Thus, the sacrificial layer 130 is exposed again. Then, a selective etching process (e.g., a selective wet etching process) may be performed to remove the sacrificial layer 130. The removal of the sacrificial layer 130 creates a cavity and exposes the bottom of the capping layer 120 and the barrier layer 152 formed in the channel hole 150. Next, multiple selective etching processes (e.g., multiple selective wet etching processes) may be performed to successively remove the exposed portions of the barrier layer 152, the charge trapping layer 153, and the tunnel insulating layer 154, which exposes the bottom side portion of the channel layer 155.

[0052] In some embodiments, the capping layer 120 may be silicon oxide. Then, when the bottom portion of the functional layer 151 is etched away, the capping layer 120 may be removed. In some other embodiments, the capping layer 120 may include a material other than silicon oxide or silicon nitride. Then, the capping layer 120 may be removed by one or more additional selective etching processes. Removal of the capping layer 120 exposes the top surface of the doped region 111.

[0053] Therefore, after the above-mentioned etching process, the side portions of the doped region 111 and the channel layer 155 near the bottom of the channel hole 150 are exposed in the cavity left by etching away the sacrificial layer 130 and the capping layer 120. The cavity can be filled with a semiconductor material (e.g., polysilicon) to form a semiconductor layer 131, for example, by a CVD and / or PVD deposition process. The semiconductor layer 131 can be n-doped. The semiconductor layer 131 can be formed on the exposed surface of the doped region 111 and on the sidewall or side portion of the channel layer 155, and can be electrically connected to the doped region 111 and the channel layer 155.

[0054] In some other embodiments, selective epitaxial growth may be performed such that a single crystalline silicon layer is grown on the exposed surface of the doping region 111 and a polycrystalline silicon layer is grown on the exposed surface of the channel layer 155. In this way, the semiconductor layer 131 may include contiguous layers of single crystalline silicon and polycrystalline silicon.

[0055] When etching the bottom portion of the functional layer 151 and the capping layer 120, some of the spacer layer may be etched away, and the remaining spacer layer may remain on the sidewalls of the gate line gap 160 to protect the stacked layers 141 and 142. After forming the semiconductor layer 131, the remaining spacer layer may be removed in a selective etching process (e.g., a selective wet etching process). In some embodiments, the innermost spacer layer in contact with the sidewall is silicon nitride. Because the stacked layer 142 is also a silicon nitride layer, the innermost spacer layer and the silicon nitride layer 142 may be removed together during the etching process, leaving a cavity 143 between the stacked layers 141, as shown in FIG. Figure 7 shown.

[0056] Thereafter, a conductive material (e.g., tungsten (W)) may be grown to fill the cavity 143 left by removing the stacked layers 142, thereby forming a conductor layer 144 between the stacked layers 141. That is, the conductor layer 144 replaces the stacked layers 142, and the layer stack 140 now includes alternating dielectric stacked layers 141 and conductor layers 144, as shown in FIG. Figure 8 As shown. In some embodiments, before depositing metal W in cavity 143, a dielectric layer 145 of a high-k dielectric material (e.g., aluminum oxide) may be deposited, followed by a layer of a conductive material (e.g., titanium nitride) (not shown). Then, metal W may be deposited to form conductor layer 144. CVD, PVD, ALD, or a combination of two or more of these processes may be used in the deposition process. In some other embodiments, another conductive material (e.g., cobalt (Co), copper (Cu), aluminum (Al), doped silicon, or any combination thereof) may be used to form conductor layer 144.

[0057] A portion of each functional layer 151 in the channel hole 150 is between a portion of one of the conductor layers 144 and a portion of the channel layer 155 in the channel hole 150. Each conductor layer 144 is configured to electrically connect one or more rows of NAND memory cells along the Y direction or in the XY plane, and is configured as a word line of the 3D array device 100. The channel layer 155 formed in the channel hole 150 is configured to electrically connect columns or strings of NAND memory cells along the Z direction, and is configured as a bit line of the 3D array device 100. In this way, a portion of the functional layer 151 in the channel hole 150 (as a portion of the NAND memory cell) is arranged between the conductor layer 144 and the channel layer 155 in the XY plane, that is, between the word line and the bit line. The portion of the conductor layer 144 surrounding a portion of the channel hole 150 serves as a control gate or gate electrode of the NAND memory cell. Figure 8The 3D array device 100 depicted in FIG. 1 can be considered to include a 2D array of NAND cell strings (such strings are also referred to as "NAND strings"). Each NAND string contains a plurality of NAND memory cells and extends vertically toward a substrate 110. The NAND strings form a 3D array of NAND memory cells.

[0058] In some embodiments, after forming the conductor layer 144, the wafer bow of the 3D array device 100 can be measured, and the filling of the gate line gap 160 can be used to reduce the wafer bow. In some other embodiments, the wafer bow can be estimated using available data and previous records without directly measuring the wafer bow. The data that can be used for the bow estimation can include the materials used, the processes performed, and the measurement data other than the measurement data of the wafer bow detection. The previous records can include previously obtained measurement data and bow reduction solutions.

[0059] The gate line gap 160 may be filled with a dielectric material 164, including, for example, silicon oxide, silicon nitride, another dielectric material, or a combination of two or more of these materials. During the filling process, an air gap may be formed in the dielectric material 164, such as FIG. 9A to FIG. 9C In various embodiments, the air gap may be surrounded by a dielectric material filled in the corresponding gate line gap, or by a dielectric material together with one or more sidewalls of the corresponding gate line gap.

[0060] The position, size, quantity and shape of the air gap can be designed and configured based on the measurement result or estimation result of the wafer bending to reduce the wafer bending. In some embodiments, the state of the wafer bending can be calculated using the measurement result or estimation result. Then, the width value can be calculated or obtained based on the wafer bending state. The maximum width of the air gap in the Y direction can be configured to be equal to or greater than the width value to reduce the wafer bending. For example, the maximum width of the air gap can be equal to or greater than half of the gate line gap width in the Y direction.

[0061] In various embodiments, the extent of the air gap in the Z direction may be adjusted to reduce wafer bow. Fig. 9A As shown, the air gap 161 may extend in a direction approximately perpendicular to the substrate 110 , wherein the bottom of the air gap 161 is close to the bottom of the gate line gap 160 , and the top of the air gap 161 is close to the top of the gate line gap 160 .

[0062] In another example, if Fig. 9B As shown, the air gap 162 may be formed and located at an upper portion of the gate line slit 160 , and extend in a direction approximately perpendicular to the substrate 110 .

[0063] In another example, Fig. 9CAs shown, the air gap 163 may be formed and located at a lower portion of the gate line slit 160 , and extend in a direction approximately perpendicular to the substrate 110 .

[0064] In yet another example, a plurality of air gaps (not shown) may be formed in the gate line slit 160. For example, two air gaps (not shown) may be formed in upper and lower portions of the gate line slit 160, respectively, and extend in a direction approximately perpendicular to the substrate 110.

[0065] Therefore, air gaps can be formed at locations around the middle, upper (top) and / or lower (bottom) portions of the same gate line gap or different gate line gaps, and can be formed with the same or different shapes and / or sizes within the same or different gate line gaps for reducing wafer bending.

[0066] In some embodiments, when the gate line gap 160 is filled with the dielectric material 164, the air gap (e.g., air gap 161, 162, or 163) can be formed in the same or similar manner to have the same or similar position, shape, and size. In some embodiments, when the gate line gap 160 is filled with the dielectric material 164, the air gap can be formed in different manners to have different positions, shapes, and / or sizes.

[0067] For example, the 3D array device 100 may have a structure similar to Fig. 9A Some air gaps of 161 and similar to Fig. 9B Air gap 162 or Fig. 9C In some embodiments, after the gate line slits 160 are filled with the dielectric material 164, some of the gate line slits may have air gaps (e.g., air gaps 161, 162, and / or 163), while some of the gate line slits may not have air gaps or have air gaps that are much smaller than or otherwise different from the air gaps 161-163. For example, in some embodiments, one gate line slit 160 may have an air gap 161, while another gate line slit 160 may not have an air gap or have only a tiny air gap, for example, the width of the air gap is less than one tenth of the width of the air gap 161 in the Y direction.

[0068] When the gate line gap 160 is filled with dielectric material 164 (e.g., silicon oxide or silicon nitride), an air gap can be formed by controlling the deposition process. An exemplary method for forming an air gap is pinch-off deposition. A combination of two or more of CVD, PVD, ALD or these processes can be used in the filling process. For example, an oxide material can be grown on the sidewall and bottom of the gate line gap 160 at a relatively slow deposition rate. After the thickness of the oxide material at the bottom of the gate line gap 160 reaches a certain value, the deposition rate can be increased. Since the deposition rate may be greater at the sidewall area near the gap opening than at the sidewall area away from the gap opening, the gate line gap 160 can be "closed" or completely filled with dielectric material at the gap opening before filling the large gap portion inside the gate line gap. In this way, an air gap similar to air gap 161 can be formed.

[0069] In order to form an air gap similar to air gap 162 in the upper portion of the gate line gap, an oxide material may be grown on the sidewalls and bottom of the gate line gap 160 at a relatively slow deposition rate. During deposition, if an air gap is formed in the lower portion, a dry etching process may be performed to remove some of the oxide material to allow continuous deposition of the oxide material until the lower portion of the gate line gap 160 is filled with the oxide material. Thereafter, the deposition rate may be increased to seal the gap and form an air gap similar to air gap 162.

[0070] In order to form an air gap similar to air gap 163 in the lower part of the gate line gap, the deposition rate can be relatively slow at first. After the thickness of the oxide material at the bottom of the gate line gap 160 reaches a certain value, the deposition rate can be increased. If the top of the air gap is too high after the air gap is formed, a dry etching process can be performed to remove some oxide materials deposited above the air gap. The deposition process can then continue at a relatively high rate until the air gap is formed again. If the top of the air gap is still too high in the Z direction, the etching deposition process can be repeated until an air gap similar to air gap 163 is formed. In the following description, air gap 161 will be used as an example of a manufacturing process for 3D array device 100.

[0071] After filling the gate line gap 160, openings for the peripheral contact 171 and the word line contact 172 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes. The openings for the peripheral contact 171 and the word line contact 172 are then filled with a conductive material by CVD, PVD, ALD, electroplating, chemical plating, or any combination thereof. The conductive material forming the peripheral contact 171 and the word line contact 172 may include W, Co, Cu, Al, or a combination of two or more of these materials. In some embodiments, when manufacturing the peripheral contact 171 and the word line contact 172, a conductive material (e.g., titanium nitride) layer may be deposited as a contact layer before depositing another conductive material.

[0072] Next, a CVD or PVD process may be performed to deposit a dielectric material (e.g., silicon oxide or silicon nitride) on the 3D array device 100. The dielectric layer 121 becomes thicker. Then, openings for vias may be formed by a dry etching process or a combination of dry and wet etching processes. Some vias are configured for peripheral contacts 171 and word line contacts 172. Some other vias are configured for each bit line contact, which electrically contacts the upper end of the corresponding NAND string and individually addresses the corresponding NAND string. The openings are then filled with a conductive material such as W, Co, Cu, Al, or a combination of two or more of these materials to form vias 173, 174, and 175. CVD, PVD, ALD, electroplating, chemical plating, or a combination thereof may be performed. Vias 173, 174, and 175 are electrically connected to peripheral contacts 171, word line contacts 172, and bit line contacts, respectively. In some embodiments, a layer of conductive material (eg, titanium nitride) may first be deposited before filling the openings to form vias 173 - 175 .

[0073] Then, a dielectric material (eg, silicon oxide or silicon nitride) may be deposited to bury the vias 173-175 and further thicken the dielectric layer 121, such as Fig.10 Similar to the formation of vias 173-175, openings are made and then filled to form contacts 176, 177 and 178 for interconnection with peripheral devices. Fig.11 As shown, contacts 176-178 are electrically connected to vias 173-175, respectively. Contacts 176-178 may include W, Co, Cu, Al, or a combination of two or more of these materials. In some embodiments, before filling the openings to form contacts 176-178, a contact layer 179 of a conductive material (e.g., titanium nitride) may be first deposited.

[0074] Figure 12-17 The manufacturing process of an exemplary 3D memory device 190 in a cross-sectional view according to an embodiment of the present disclosure is schematically shown. The 3D memory device 190 may include Fig.113D array device 100 and a peripheral device 180 configured to control array device 100 are shown in FIG. 1 . Peripheral device 180 may include substrate 181, which may include single crystal silicon, Ge, SiGe, SiC, SOI, GOI, polycrystalline silicon, or a III-V compound (e.g., GaAs or InP). Peripheral circuits (e.g., control circuits) (not shown) may be fabricated on substrate 181 and used to facilitate the operation of 3D memory device 190. For example, the peripheral circuits may include metal oxide semiconductor field effect transistors (MOSFETs) and provide functional devices such as page buffers, sense amplifiers, column decoders, and row decoders. Dielectric layer 182, contacts 183 and 184, and vias may be formed on substrate 181. Dielectric layer 182 may include one or more dielectric materials, such as silicon oxide and silicon nitride. Contacts 183 and 184 are configured as interconnects with 3D array device 100 and may include conductive materials such as W, Co, Cu, Al, or combinations thereof.

[0075] The 3D array device 100 and the peripheral device 180 can be bonded by a flip chip bonding method. In some embodiments, the 3D array device 100 can be flipped and turned upside down, wherein the top surfaces of the contacts 176-178 face downward in the Z direction. Then, the peripheral device 180 can be placed under the 3D array device 100. After performing an alignment step (for example, the contacts 176 and 178 can be aligned with the contacts 183 and 184, respectively), the 3D array device 100 and the peripheral device 180 can be joined and bonded together, as shown in FIG. Fig.12 As shown. Then, the layer stack 140 and the peripheral circuit (or MOSFET) are sandwiched between the substrates 110 and 181. In some embodiments, solder or a conductive adhesive may be used to bond the contact 176 to the contact 183, and to bond the contact 178 to the contact 184. In this way, the contact 176 is electrically connected to the contact 183, and the contact 178 is electrically connected to the contact 184, respectively. After completing the flip chip bonding process, the 3D array device 100 and the peripheral device 180 are electrically connected.

[0076] Thereafter, the substrate 110 of the 3D array device 100 may be thinned by a thinning process such as wafer grinding, dry etching, wet etching, CMP, or a combination thereof. Then, a dielectric layer 112 may be grown on the doped region 111 by a deposition process (e.g., a CVD or PVD process). The opening 113 may be formed by a dry etching process or a combination of dry etching and wet etching processes. The opening 113 penetrates the dielectric layer 112 and the doped region 111 and exposes the peripheral contact 171, such as Fig.13Then, a dielectric material (e.g., silicon dioxide or silicon nitride) may be deposited to form a dielectric layer 114 over the dielectric layer 112 and on the sidewalls and bottom of the opening 113. A deposition process such as CVD or PVD may be performed to grow the dielectric layer 114, followed by a dry etching process or a dry etching process and a wet etching process to form an opening 115 extending through the dielectric layers 114 and 112 and partially through the doped region 111.

[0077] Afterwards, an etching process (eg, a dry etching process) may be performed to remove a portion of the dielectric layer 114 located on the top surface of the dielectric layer 112 and the bottom surface of the opening 113, such as Fig.15 As shown. Openings 113 and 115 may be filled with a conductive material (e.g., W, Co, Cu, Al, or a combination thereof) to form vias 191 and 192. Vias 191 and 192 may be used as contact structures, and via 191 may also be referred to as a through-silicon contact (TSC). CVD, PVD, ALD, electroplating, chemical plating, or a combination thereof may be performed to form vias 191 and 192. Fig.16 The vias 191 and 192 are electrically connected to the peripheral contact 171 and the doped region 111, respectively. In some embodiments, before filling the openings to form the vias 191 and 192, a contact layer 193 of a conductive material (eg, titanium nitride) may be first deposited.

[0078] like Fig.17 As shown, metal layers 193 and 194 can be formed in a deposition process (e.g., CVD, PVD, ALD, electroplating, chemical plating, or a combination thereof). Metal layer 193 can be used as a pad layer that covers and electrically contacts one of vias 191. Metal layer 194 electrically connects via 192 to another via 191. Then, a dielectric layer 116 can be deposited to cover metal layers 193 and 194 and the exposed portion of dielectric layer 112 by a process such as CVD, PVD, ALD, or a combination thereof. Dielectric layer 116 can be used as a passivation layer, which can include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, TEOS, or a combination thereof. Thereafter, an etching process (e.g., a dry or wet etching process) can be performed to remove a portion of dielectric layer 116, thereby exposing metal layer 193.

[0079] In some embodiments, the 3D memory device 190 may include the 3D array device 100 and a plurality of peripheral devices (not shown) that are the same as or similar to the peripheral device 180. In some embodiments, the 3D memory device 190 may include the peripheral device 180 and a plurality of 3D array devices (not shown) that are the same as or similar to the 3D array device 100. In some embodiments, when there are a plurality of peripheral devices (or a plurality of 3D array devices), the plurality of peripheral devices (or 3D array devices) may be sequentially bonded to the corresponding 3D array device (or the corresponding peripheral device) in a separate bonding process. In some other embodiments, the plurality of peripheral devices (or 3D array devices) may be bonded to the corresponding 3D array device (or the corresponding peripheral device) simultaneously in one bonding process.

[0080] In some embodiments, the 3D array device 100 and the peripheral device 180 may be integrated together. For example, after the peripheral device 180 is manufactured, the 3D array device 100 may be manufactured on the dielectric layer 182 of the peripheral device 180. During the manufacturing process, certain vias may be manufactured to interconnect the 3D array device 100 and the peripheral device 180.

[0081] Fig.18 A schematic flow chart 200 for manufacturing a 3D memory device according to an embodiment of the present disclosure is shown. At 211, a sacrificial layer of a 3D array device may be deposited over the top surface of a substrate. The substrate may include a semiconductor substrate, such as a single crystal silicon substrate. In some embodiments, a capping layer may be deposited on the substrate before depositing the sacrificial layer. The capping layer may include a single layer or multiple layers sequentially deposited over the substrate. In some embodiments, the capping layer may include silicon oxide, silicon nitride, and / or aluminum oxide. In some other embodiments, the sacrificial layer may be deposited without first depositing a capping layer over the substrate. The sacrificial layer may include single crystal silicon, polycrystalline silicon, silicon oxide, or silicon nitride.

[0082] On top of the sacrificial layer, a layer stack of the 3D array device may be deposited. The layer stack includes a first stack layer and a second stack layer that are alternately stacked. In some embodiments, the first stack layer may include a first dielectric layer, and the second stack layer may include a second dielectric layer that is different from the first dielectric layer. In some embodiments, one of the first dielectric layer and the second dielectric layer is used as a sacrificial stack layer.

[0083] At 212, a step formation process may be performed to trim the layer stack formed at 211. The step formation process may include multiple etchings for converting the layer stack into a step structure of a 3D array device. In some embodiments, the height of the step structure of the layer stack may decrease in a stepwise manner along one direction.

[0084] At 213, a channel hole may be formed, the channel hole extending through the layer stack and the sacrificial layer to expose a portion of the substrate. The functional layer and the channel layer may be deposited on the sidewalls and bottom surface of each channel hole. Forming the functional layer may include depositing a barrier layer on the sidewalls of the channel hole, depositing a charge trapping layer on the barrier layer, and depositing a tunnel insulating layer on the charge trapping layer. The channel layer deposited on the tunnel insulating layer serves as a semiconductor channel and may include a polysilicon layer.

[0085] At 214, a gate line gap of a 3D array device can be formed, which extends vertically through the layer stack and enters the sacrificial layer, and exposes a portion of the sacrificial layer. The gate line gap can also extend in the horizontal direction. Some gate line gaps can be arranged to divide the NAND memory cell into a plurality of storage block areas. The storage block area includes a channel hole area, and the channel hole area includes a channel hole. In some embodiments, the wafer bending can be directly measured at 214. In some embodiments, the wafer bending is estimated by calculating the data obtained by using previous records and measurements other than direct wafer bending detection. In some embodiments, the number, position, size and / or profile of the gate line gaps can be configured to reduce the wafer bending. For example, after the state of the wafer bending is obtained by direct measurement or estimation using previous records and other data, the number, position, size and / or profile of the gate line gaps can be determined or adjusted to minimize the wafer bending. For example, additional gate line gaps can be configured.

[0086] At 215, the sacrificial layer can be etched away and a cavity can be created above the substrate. The cavity exposes a bottom portion of the barrier layer of the functional layer in the cavity. If a capping layer is deposited on the substrate, it is also exposed in the cavity. Then, the layers of the functional layer that are sequentially exposed in the cavity, including the barrier layer, the charge trapping layer, and the tunnel insulating layer, are etched away, respectively, by, for example, one or more selective etching processes. As a result, the portion of the functional layer close to the substrate can be removed in the cavity. If a capping layer is deposited, the capping layer can also be etched away during the process of etching a portion of the functional layer or in another selective etching process. Therefore, a portion of the substrate and a portion of the channel layer are exposed in the cavity.

[0087] Afterwards, a deposition process may be performed to grow a polysilicon layer in the cavity. The polysilicon layer electrically contacts the channel layer and the substrate.

[0088] In some embodiments, the layer stack includes two dielectric stack layers, and one of the stack layers is sacrificial. At 216, the sacrificial stack layer can be etched away to leave a cavity, which can then be filled with a conductive material to form a conductor layer. The conductive material can include a metal such as W, Co, Cu, or Al.

[0089] At 217, the gate line gaps may be filled with a dielectric material such as silicon oxide or silicon nitride. In some embodiments, the wafer curvature may be measured directly before the filling process. In some embodiments, the wafer curvature may be estimated by calculation using previously recorded and measured data other than direct wafer curvature detection. In some embodiments, when the gate line gaps are filled with a filling material, an air gap may be formed to reduce the wafer curvature. The air gap may be surrounded or enclosed by the filling material, and a predetermined shape may be formed in the gap. In some embodiments, the number, position, size, and / or shape of the air gaps may be configured to reduce the wafer curvature. For example, after obtaining the state of the wafer curvature by direct measurement or estimation using previously recorded and other data, the number, position, size, and / or shape of the air gaps may be determined to minimize the wafer curvature.

[0090] At 218, an etching and filling process may be performed to form word line contacts, peripheral contacts, and vias electrically connected to the word line contacts and the peripheral contacts. Contacts for interconnection between the 3D array device and the peripheral device may also be formed.

[0091] At 219, a flip chip bonding process may be performed to bond the 3D array device and the peripheral device or to fasten the 3D array device and the peripheral device together. In some embodiments, the 3D array device may be flipped upside down and positioned above the peripheral device. The 3D array device and the peripheral device may be aligned. For example, the contacts for interconnection of the 3D array device and the contacts for interconnection of the peripheral device may be aligned and then bonded. After the bonding process, the 3D array device and the peripheral device are combined to form a 3D memory device.

[0092] Figure 19-24 The manufacturing process of an exemplary 3D array device 300 according to an embodiment of the present disclosure is schematically shown. Figure 19-24 In , the cross-section view is in the YZ plane, and the top view is in the XY plane. Fig.19 As shown, the 3D array device 300 includes a substrate 310. In some embodiments, the substrate 310 may include a single crystal silicon layer. In some other embodiments, the substrate 310 may include another semiconductor material, such as Ge, SiGe, SiC, SOI, GOI, polysilicon, GaAs or InP. In the following description, as an example, the substrate 310 includes an undoped or lightly doped single crystal silicon layer.

[0093] In some embodiments, the top portion of the substrate 310 may be doped with n-type dopants via ion implantation and / or diffusion to form a doped region 311. Fig.19As shown, the capping layer 320 may be deposited on the doped region 311. The capping layer 320 is a sacrificial layer and may include a single layer or multiple layers. For example, the capping layer 320 may include one or more of a silicon oxide layer and a silicon nitride layer. The capping layer 320 may be deposited by CVD, PVD, ALD, or a combination of two or more of these methods. In some other embodiments, the capping layer 320 may include another material such as aluminum oxide.

[0094] On the capping layer 320, a sacrificial layer 330 may be deposited. The sacrificial layer 330 may include a semiconductor material or a dielectric material. In the following description, as an example, the sacrificial layer 330 is a polysilicon layer. After forming the sacrificial layer 330, a layer stack 340 may be deposited. The layer stack 340 includes a plurality of pairs of stacked layers 341 and 342, that is, the stacked layers 341 and 342 are alternately stacked.

[0095] In some embodiments, stacked layers 341 and 342 may include a first dielectric material and a second dielectric material different from the first dielectric material, respectively. Alternating stacked layers 341 and 342 may be deposited via CVD, PVD, ALD, or a combination of two or more of these processes. In the following discussion, exemplary materials for stacked layers 341 and 342 are silicon oxide and silicon nitride, respectively. A silicon oxide layer may be used as an isolation stacked layer, and a silicon nitride layer may be used as a sacrificial stacked layer.

[0096] After depositing the layer stack 340, a step forming process may be performed to trim the layer stack 340 into a step structure, such as Fig. 20 Then, the stepped structure may be covered by a dielectric material (eg, silicon oxide) forming a dielectric layer 321 .

[0097] Fig.21 and Fig. 22 A top view and a cross-sectional view of a 3D array device 300 after some processes according to an embodiment of the present disclosure are schematically shown. A channel hole 350 may be formed in the layer stack 340 . Fig.21 and Fig. 22 The number, size, and arrangement of the channel holes 350 shown in FIG. 3 are exemplary and are used to describe the structure and manufacturing method of the 3D array device 300. The channel holes 350 are configured as an array extending in the Z direction and forming a predetermined pattern in the XY plane. Fig. 22 The cross-section shown is along Fig.21 Intercepted by line CC'.

[0098] The channel hole 350 may have a cylindrical shape or a column shape, which extends through the layer stack 340, the sacrificial layer 330, and the capping layer 320, and partially penetrates the doping region 311. After forming the channel hole 350, a functional layer 351 may be deposited on the sidewall and bottom of the channel hole. The functional layer 351 may include a blocking layer 352 on the sidewall and bottom of the channel hole to block the outflow of charges, a charge trapping layer 353 on the surface of the blocking layer 352 to store charges, and a tunnel insulating layer 354 on the surface of the charge trapping layer 353.

[0099] In some embodiments, the functional layer 351 may include an ONO structure, which is used in the following description. Fig. 22 As shown, a silicon oxide layer may be deposited on the sidewalls of the channel hole 350 as a barrier layer 352. A silicon nitride layer may be deposited on the barrier layer 352 as a charge trapping layer 353. Another silicon oxide layer may be deposited on the charge trapping layer 353 as a tunnel insulating layer 354. On the tunnel insulating layer 354, a polysilicon layer may be deposited as a channel layer 355. Like the channel hole, the channel layer 355 also extends through the layer stack 340 and into the doped region 311. After forming the channel layer 355, the channel hole 350 may be filled with an oxide material 356. The channel hole 350 may be sealed by a plug including a conductive material (e.g., metal W) and electrically contacting the channel layer 355.

[0100] After depositing the functional layer 351 and the channel layer 355, the wafer bow of the 3D device 300 can be measured directly or estimated using available data and previous records. Then, the number, location, size and / or profile of the gateline slits 360 can be determined to reduce the wafer bow.

[0101] In some embodiments, the size and shape of the grid line gaps can be the same. In some other embodiments, the size and shape of the grid line gaps can be arranged differently to reduce wafer bending. For example, the maximum gap width of one grid line gap can be different from the maximum gap width of another grid line gap in the Y direction.

[0102] The gate line gap 360 may be formed by, for example, a dry etching process or a combination of a dry etching process and a wet etching process. Fig. 22 As shown, the gate line gap 360 can extend through the layer stack 340 and reach or partially penetrate the sacrificial layer 330 in the Z direction. Therefore, at the bottom of the gate line gap 360, a portion of the sacrificial layer 330 is exposed. Then, a spacer layer (not shown) can be deposited on the sidewall and bottom of the gate line gap 360. The spacer layer is configured to protect the stacked layers 341 and 342, and can include, for example, silicon oxide and silicon nitride.

[0103] Portions of the spacer layer at the bottom of the gap 360 may be removed by etching to expose the sacrificial layer 330. The sacrificial layer 330 is then etched away. The removal of the sacrificial layer 330 creates a cavity and exposes the bottom portions of the capping layer 320 and the blocking layer 352 formed in the channel hole 350. Next, portions of the blocking layer 352, the charge trapping layer 353, and the tunnel insulating layer 354 are etched away to expose the bottom portion of the channel layer 355. When the bottom of the functional layer 351 is etched away or in an additional selective etching process, the capping layer 320 may be removed to expose the top surface of the doped region 311.

[0104] Then, the cavity may be filled with a semiconductor material (e.g., polysilicon) to form a semiconductor layer 331 by a deposition process (e.g., a CVD and / or PVD process). In some embodiments, the semiconductor layer 331 may be doped with an n-type dopant to form an n-well region and deposited on the surfaces of the exposed portions of the doped region 311 and the channel layer 355. The semiconductor layer 331 is electrically connected to the doped region 311 and the channel layer 355.

[0105] After the semiconductor layer 331 is formed, the stacked layer 342 may be removed by etching and replaced with a conductor layer 344 including a conductive material (eg, W).

[0106] Each conductor layer 344 is configured to electrically connect one or more rows of NAND memory cells along the Y direction or in the XY plane, and is configured as a word line of the 3D array device 300. The channel layer 355 formed in the channel hole 350 is configured to electrically connect the NAND strings along the Z direction, and is configured as a bit line of the 3D array device 300. The 3D array device 300 includes a 2D array of NAND strings. A portion of the conductor layer 344 surrounding a portion of the channel hole 350 may be used as a control gate or gate electrode of the NAND memory cell.

[0107] In some embodiments, after forming the conductor layer 344, the wafer bow of the device 300 can be measured, and the filling of the gate line gap 360 can be used to reduce the wafer bow. In some other embodiments, the wafer bow can be estimated using available data and previous records without directly measuring the wafer bow. The data that can be used for the bow estimation can include the materials used, the processes performed, and the measurement results in addition to the bow detection data. The previous records can include previously obtained measurement records and bow reduction solutions.

[0108] The gate line gap 360 may be filled with a dielectric material 364, such as silicon oxide, silicon nitride, another dielectric material, or a combination of two or more of these materials. During the filling process, an air gap 361 may be formed, such as Fig.23AAs shown in . The position, size, number and shape of the air gap 361 can be configured using the measurement results or estimation results to reduce wafer bending. For example, the maximum width of the air gap 361 in the Y direction can be equal to or greater than the width value that can be calculated using the measurement results or estimation results to reduce wafer bending. Similarly, the extension of the air gap 361 in the Z direction can also be used to reduce wafer bending. For example, the air gap 361 can extend vertically through the layer stack 340, wherein the bottom of the air gap 361 is close to the bottom of the gate line gap 360, and the top of the air gap 361 is close to the top of the gate line gap 360. In another example, the air gap can be formed to extend vertically through the upper portion of the layer stack 340, such as Fig. 23B Alternatively, the air gap may be formed to extend vertically through the lower portion of the layer stack 340, for example Fig.23C The air gap 363 shown in FIG. Therefore, the air gap can be configured to have different shapes and spans at different positions of the gate line gap 360 to minimize wafer bending. In some other embodiments, multiple air gaps can be formed in the gate line gap to minimize wafer bending.

[0109] In some embodiments, the air gaps of the 3D array device 300 may have the same or similar positions, shapes and sizes to reduce wafer bending. In some embodiments, the air gaps of the 3D array device 300 may have different positions, shapes and / or sizes to reduce wafer bending. In some embodiments, some gate line gaps may have one or more air gaps, and some gate line gaps may not have air gaps or only have tiny air gaps. The air gaps may be formed using CVD, PVD, ALD or a combination of two or more of these processes. For the following manufacturing process of the 3D array device 300, air gap 361 will be used as an example.

[0110] After filling the gate line gap 360, openings for the peripheral contact 371, the word line contact 372, and the source contact 3791 may be formed. The openings for the contacts 371, 372, and 3791 are then filled with a conductive material (e.g., W, Co, Cu, Al, or a combination thereof). In some embodiments, when making the contacts 371, 372, and 3791, a conductive material (e.g., titanium nitride) layer may be deposited as a contact layer before depositing another conductive material.

[0111] Next, a dielectric material (eg, silicon oxide or silicon nitride) may be deposited on the 3D array device 300. The dielectric layer 321 becomes thicker. Vias 373, 374, and 375 for contacts 371, 372 and bit line contacts may be formed, respectively. A via for source contact 3791 may also be made.

[0112] Then, a dielectric material (e.g., silicon oxide or silicon nitride) may be deposited to bury the vias (e.g., vias 373-375) and further thicken the dielectric layer 321. Contacts 376, 377, 378, and 3792 may be formed for interconnection with peripheral devices. Fig.24 As shown, contacts 376-378 are electrically connected to vias 373, 374, 375, respectively. Contact 3792 is electrically connected to the via of source contact 3791. Contacts 376-378 and 3792 and the via may include conductive materials such as W, Co, Cu, Al, or combinations thereof.

[0113] Fig.25 A peripheral device 380 in a cross-sectional view according to an embodiment of the present disclosure is schematically shown. The peripheral device 380 may include a semiconductor substrate 381 (e.g., a single crystal silicon substrate). Peripheral circuits (e.g., control circuits) (not shown) may be fabricated on the substrate 381 and used to facilitate the operation of the 3D array device 300. A dielectric layer 382, ​​contacts 383 and 384, and vias may be formed over the substrate 381. The contacts 383 and 384 are configured for interconnection with the 3D array device 300 and may include a conductive material (e.g., W, Co, Cu, Al, or a combination thereof).

[0114] Fig.26 An exemplary 3D memory device 390 is schematically shown in a cross-sectional view according to an embodiment of the present disclosure. The 3D memory device 390 may include Fig.24 The 3D array device 300 and Fig.25 The peripheral device 380 shown. The 3D array device 300 and the peripheral device 380 can be bonded by a flip chip bonding method. In some embodiments, the 3D array device 300 can be turned upside down and then placed above the peripheral device 380. After performing an alignment step (for example, contacts 376 and 378 are aligned with contacts 383 and 384, respectively), the 3D array device 300 and the peripheral device 380 can be joined and bonded. In some embodiments, solder or a conductive adhesive can be used to bond contact 376 to contact 383, and to bond contact 378 to contact 384. In this way, contacts 376 are electrically connected to contacts 383, respectively, and contacts 378 are electrically connected to contacts 384, respectively. After implementing the flip chip bonding process, the 3D array device 300 is electrically connected to the peripheral device 380.

[0115] Then, the substrate 310 of the 3D array device 300 may be thinned by a thinning process. A dielectric layer 312 may be deposited on the layer 311. A via 391 serving as a TSC may be formed, which penetrates the dielectric layer 312 and the doped region 311 and electrically contacts the peripheral contacts 371, respectively. Pad layers 392 and 393 may be formed on the via 391, respectively, and contact the via 391, respectively. The via 391 and the pad layers 392 and 393 may be deposited using a conductive material such as W, Co, Cu, Al, or a combination thereof. CVD, PVD, ALD, electroplating, chemical plating, or a combination thereof may be performed.

[0116] On top of dielectric layer 312 and pad layers 392, 393, dielectric layer 313 may be deposited by a process such as CVD, PVD, ALD, or a combination thereof. Dielectric layer 313 may be used as a passivation layer, which may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, TEOS, or a combination thereof. Subsequently, an etching process (e.g., a dry or wet etching process) may be performed to remove portions of dielectric layer 313, thereby exposing pad layers 392 and 393.

[0117] Figure 27-32 FIG. 4 schematically shows a manufacturing process of an exemplary 3D array device 400 according to an embodiment of the present disclosure. Fig. 27 As shown, the 3D array device 400 includes a substrate 410. The substrate 410 may include a single crystal silicon layer. In some other embodiments, the substrate 410 may include another semiconductor material, such as Ge, SiGe, SiC, SOI, GOI, polysilicon, GaAs or InP. In the following description, as an example, the substrate 410 includes an undoped or lightly doped single crystal silicon layer. In some embodiments, the top portion of the substrate 410 may be doped by a p-type dopant via ion implantation and / or diffusion to form a doped region 411.

[0118] On top of the doped region 411, a sacrificial layer 420 and a layer stack 440 may be deposited. The layer stack 440 includes a plurality of pairs of stacked layers 441 and 442, i.e., the stacked layers 441 and 442 are alternately stacked. In some embodiments, the stacked layers 441 and 442 may include a first dielectric material and a second dielectric material different from the first dielectric material, respectively. The sacrificial layer 420 and the stacked layers 442 may have the same material. The sacrificial layer 420 and the stacked layers 441 and 442 may be deposited via CVD, PVD, ALD, or a combination thereof. In the following discussion, exemplary materials for the stacked layers 441 and 442 are silicon oxide and silicon nitride, respectively. The stacked layer 441 may be used as an isolation stacked layer, and the stacked layer 442 may be used as a sacrificial stacked layer.

[0119] After depositing the layer stack 440, a step forming process may be performed to trim the layer stack 440 into a step structure, such as Fig.28 Thereafter, the stepped structure may be covered by a dielectric material (eg, silicon oxide) forming a dielectric layer 421 .

[0120] Fig.29 and Fig.30 Schematically illustrating a top view and a cross-sectional view of a 3D array device 400 after some processes according to an embodiment of the present disclosure. A channel hole 450 is formed in a layer stack 440 . Fig.29 and Fig.30 The number, size, and arrangement of the channel holes 450 shown in FIG. 4 are exemplary and are used to describe the structure and manufacturing method of the 3D array device 400. The channel holes 450 are configured to extend in the Z direction and form an array of a predetermined pattern in the XY plane. Fig.30 The cross-section shown is along Fig.29 The line DD' is intercepted.

[0121] The channel hole 450 may have a cylindrical shape or a column shape, which extends through the layer stack 440 and the sacrificial layer 420, and partially penetrates the doped region 411 in a direction approximately perpendicular to the substrate 410. After the channel hole 450 is formed, the doped region 411 is exposed at the bottom of the channel hole. In some embodiments, an epitaxial growth process may be performed to grow an epitaxial layer 457 from the doped region 411. The epitaxial layer 457 may extend from the doped region 411 to a region between the layer stack 440 and the sacrificial layer 420. In some embodiments, the epitaxial layer 457 may be a single crystal silicon layer electrically contacting the doped region 411.

[0122] Thereafter, a functional layer 451 may be deposited on the sidewalls of the channel hole 450 and the top surface of the epitaxial layer 457. The functional layer 451 may include a blocking layer 452 on the sidewalls of the channel layer 450 and the top surface of the epitaxial layer 457, a charge trapping layer 453 on the surface of the blocking layer 452, and a tunnel insulating layer 454 on the surface of the charge trapping layer 453.

[0123] In some embodiments, the functional layer 451 may include an ONO structure, which is used in the following description. Fig.30 As shown, a silicon oxide layer may be deposited as a blocking layer 452. A silicon nitride layer may be deposited on the blocking layer 452 as a charge trapping layer 453. Another silicon oxide layer may be deposited on the charge trapping layer 453 as a tunnel insulating layer 454.

[0124] Portions of the functional layer on top of the epitaxial layer 457 may be removed by etching (e.g., a selective dry etching process) to expose portions of the epitaxial layer 457. Then, a polysilicon layer may be deposited as a channel layer 455. The channel layer 455 may be deposited on the tunnel insulating layer 454 and the exposed portions of the epitaxial layer 457. In this way, the channel layer 455 electrically contacts the epitaxial layer 457 and extends through the layer stack 440. After forming the channel layer 455, the channel hole 450 may be filled with an oxide material 456.

[0125] Since the formation of the layer stack 440 and the channel hole 450 affects the wafer bow, the wafer bow of the 3D array device 400 can be directly measured or estimated using available data and previous records. In some embodiments, the number, location, size and / or profile of the gate line gaps 460 can be determined based on the measurement results or estimation results to reduce the wafer bow.

[0126] For example, the size and shape of the gate line gaps 460 can be the same. In another example, the size and shape of the gate line gaps 460 can be arranged to be different to reduce wafer bending. In yet another example, the maximum gap width of one gap can be different from the maximum gap width of another gap in the Y direction.

[0127] The gate line gap 460 may be formed by, for example, a dry etching process or a combination of a dry etching process and a wet etching process. Fig.30 As shown, the gate line gap 460 can extend through the layer stack 440 and the sacrificial layer 420, and reach or partially penetrate the doped region 411 in the Z direction or along a direction approximately perpendicular to the substrate 410. Therefore, at the bottom of the gate line gap 460, the doped region 411 is exposed. In some embodiments, the area around the bottom of the gate line gap 460 can be doped with an n-type dopant to form an n-well region (not shown).

[0128] Afterwards, selective etching (e.g., selective wet etching) may be performed to etch away the stacked layer 442 and replace the stacked layer 442 with a conductor layer 444 including a conductive material (e.g., W). When replacing the stacked layer 442, the sacrificial layer 420 is also etched away and replaced by the select gate 422. The conductor layer 444 and the select gate 422 may have the same material. In some embodiments, an oxidation process (e.g., a dry and / or wet oxidation process) may be performed after the selective etching process of removing the stacked layer 442 and the sacrificial layer 420. The removal of the sacrificial layer 420 exposes a side portion of the epitaxial layer 457, and the side portion of the epitaxial layer 457 may be oxidized to form an insulating region 458 in the oxidation process.

[0129] In some embodiments, the select gate 422 can be used as a source select gate. Each conductor layer 444 is configured to electrically connect one or more rows of NAND memory cells along the Y direction or in the XY plane, and is configured as a word line of the 3D array device 400. The channel layer 455 formed in the channel hole 450 is configured to electrically connect the NAND string along the Z direction and is configured as a bit line of the 3D array device 400. The 3D array device 400 includes a 2D array of NAND strings. A portion of the conductor layer 444 surrounding a portion of the channel hole 450 can be used as a control gate or gate electrode of the NAND memory cell.

[0130] In some embodiments, after forming the conductor layer 444, the wafer bow of the 3D array device 400 can be measured directly, and the filling of the gate line gap 460 can be used to reduce the wafer bow. In some other embodiments, the wafer bow can be estimated using available data and previous records without directly measuring the wafer bow. The data that can be used for the bow estimation can include the materials used, the processes implemented, and the measurement data in addition to the bow detection data. The previous records can include previously obtained measurement records and bow reduction solutions.

[0131] Then, a deposition process may be performed to deposit a dielectric material 466 (e.g., silicon oxide or silicon nitride) to form an isolation layer on the sidewalls and bottom of the gate line gap 460. The isolation layer on the bottom surface of the gate line gap 460 may be etched away by a selective dry etching process to expose the doped region 411. Then, the gate line gap 460 may be filled with a conductive material to form a source contact electrically contacting the doped region 411. In some embodiments, a conductive material (e.g., titanium nitride) may be deposited first. Next, another conductive material 461 (e.g., polysilicon) may be deposited for a filling process. Then, the gate line gap 460 may be sealed by a plug 462, which may include a conductive material such as tungsten, and the deposition may be performed by a combination of CVD, PVD, ALD, or two or more of these processes.

[0132] During the filling process, an air gap 463 may be formed, such as Fig.31AAs shown in . The air gap 463 is surrounded or enclosed by the conductive material 461. The position, size, number and shape of the air gap 463 can be determined based on the measurement results or estimation results to reduce the wafer bending. For example, the maximum width of the air gap 463 in the Y direction can be configured to be equal to or greater than a value that can be calculated using the measurement results or estimation results. Similarly, the extension range of the air gap 463 in the Z direction can also be obtained by calculation. For example, the air gap 463 can extend through the layer stack 440, wherein the bottom of the air gap 463 is close to the bottom of the gate line gap 460, and the top of the air gap 463 is close to the top of the gate line gap 460. In another example, the air gap can be formed to extend through the upper portion of the layer stack 440, such as Fig.31B Alternatively, the air gap may be formed to extend through a lower portion of the layer stack 440, such as the air gap 464 shown in FIG. Fig. 31C Thus, the air gaps may be configured to have different shapes at different locations of the gateline slits 460 to minimize wafer bowing.

[0133] In some embodiments, the air gaps of 3D array device 400 may have the same or similar positions, shapes and sizes to reduce wafer bending. In some embodiments, the air gaps of 3D array device 400 may have different positions, shapes and / or sizes to reduce wafer bending. In some embodiments, some gate line gaps may have one or more air gaps, and some gate line gaps may not have air gaps or only have tiny air gaps. The air gaps may be formed using CVD, PVD, ALD or a combination thereof. For the following manufacturing process of device 400, air gap 463 will be used as an example.

[0134] After filling the gate line gap 460 with the conductive material 461 and the plug 462, an opening for the contact 471 and the word line contacts 472 and 4791 may be formed. The openings for the contacts 471, 472 and 4791 are then filled with a conductive material such as W, Co, Cu, Al or a combination thereof. In some embodiments, when making the contacts 471, 472 and 4791, before depositing another conductive material, a conductive material (e.g., titanium nitride) layer may be deposited as a contact layer. The contact 471 is electrically connected to the doped region 411. The word line contacts 472 and 4791 are electrically connected to the conductor layer 444 and the select gate 422, respectively.

[0135] Next, a dielectric material (e.g., silicon oxide or silicon nitride) may be deposited on the 3D array device 400, which makes the dielectric layer 421 thicker. Vias 473, 474, and 475 for contacts 471, 472 and bit line contacts may be formed, respectively. Vias 4792 and 4793 for contact 4791 and source contacts may also be made.

[0136] Then, a dielectric material (e.g., silicon oxide or silicon nitride) may be deposited to bury the vias 473-475 and 4792-4793 and further make the dielectric layer 421 thicker. Contacts 476, 477, 478, 4794, and 4795 may be formed for interconnection with peripheral devices. Fig.32 As shown, contacts 476-478 are electrically connected to vias 473-475, respectively. Contacts 4794 and 4795 are electrically connected to vias 4792 and 4793, respectively. Contacts 476-478 and 4794-4795 and vias may include conductive materials such as W, Co, Cu, Al, or combinations thereof.

[0137] Fig.33 A peripheral device 480 in a cross-sectional view according to an embodiment of the present disclosure is schematically shown. The peripheral device 480 may include a semiconductor substrate 481 (e.g., a single crystal silicon substrate). Transistors (e.g., MOSFETs) and peripheral circuits (e.g., control circuits) (not shown) may be fabricated on the substrate 481 and used to facilitate the operation of the 3D array device 400. A dielectric layer 482, contacts 483, 484, and 485, and a plurality of vias may be formed over the substrate 481. The contacts 483-485 are configured for interconnection with the 3D array device 400 and may include a conductive material (e.g., W, Co, Cu, Al, or a combination thereof).

[0138] Fig.34 An exemplary 3D memory device 490 is schematically shown in a cross-sectional view according to an embodiment of the present disclosure. The 3D memory device 490 may include Fig.32 The 3D array device 400 and Fig.33 The peripheral device 480 shown. The 3D array device 400 and the peripheral device 480 can be bonded by a flip chip bonding method. In some embodiments, the 3D array device 400 can be turned upside down and placed above the peripheral device 480. After performing an alignment step (for example, contacts 476, 478, and 4795 can be aligned with contacts 483, 484, and 485, respectively), the 3D array device 400 and the peripheral device 480 can be joined and bonded. In some embodiments, solder or a conductive adhesive can be used to bond contact 476 to contact 483, contact 478 to contact 484, and contact 4795 to contact 485, respectively. In this way, the contacts from the two devices are electrically interconnected. After implementing the flip chip bonding process, the 3D array device 400 and the peripheral device 480 are electrically connected.

[0139] After bonding devices 400 and 480, substrate 410 of 3D array device 400 may be thinned by a thinning process (e.g., wafer grinding, dry etching, wet etching, CMP, or a combination thereof). Then, dielectric layers 412 and 413 may be deposited over doped regions 411. CVD, PVD, ALD, or a combination thereof may be performed. Dielectric layer 413 may be used as a passivation layer. Dielectric layers 412 and 413 may include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS, or a combination thereof, respectively.

[0140] By using the disclosed memory structure and method, wafer bow can be directly measured or estimated during the manufacturing process. The air gap can be configured based on the measurement results or the estimation results to reduce the wafer bow. Therefore, the wafer bow can be minimized during the manufacturing process. The 3D memory process can be optimized and the yield can be improved.

[0141] Although the principles and embodiments of the present disclosure are described by specific embodiments in the specification, the above description of the embodiments is only intended to help understand the present disclosure. In addition, the features of the above-mentioned different embodiments can be combined to form additional embodiments. Those of ordinary skill in the art can modify the specific embodiments and application scope according to the ideas of the present disclosure. Therefore, the contents of the specification should not be interpreted as limiting the present disclosure.

Claims

1. A semiconductor device, comprising: A stacked structure, comprising a first dielectric layer and a conductive layer alternately stacked along a first direction; A first semiconductor layer, located on a first side of the stacked structure along the first direction; A second semiconductor layer, located between the first semiconductor layer and the stacked structure; a channel layer and a functional layer, wherein the channel layer and the functional layer penetrate the stacked structure and the second semiconductor layer along the first direction and extend into the first semiconductor layer; The peripheral circuit is located at a second side of the stack structure opposite to the first side; A first contact structure, located at a side of the first semiconductor layer away from the stacking structure and in contact with the first semiconductor layer; as well as A gate line gap structure penetrates the stacked structure to the second semiconductor layer along the first direction, wherein the gate line gap structure includes an air gap.

2. The semiconductor device according to claim 1, wherein: The second semiconductor layer penetrates the functional layer and contacts the channel layer.

3. The semiconductor device according to claim 1, wherein: The first contact structure is connected to the peripheral circuit.

4. The semiconductor device according to claim 1, further comprising: A first insulating layer is located at a side of the first semiconductor layer away from the stacked structure, and the first contact structure penetrates the first insulating layer and contacts the first semiconductor layer.

5. The semiconductor device according to claim 4, further comprising: a stepped structure located at at least one side edge of the stacked structure; a second dielectric layer covering the stepped structure; as well as A second contact structure, at least a portion of which is located in the second dielectric layer and connected to the peripheral circuit.

6. The semiconductor device according to claim 5, wherein: The second contact structure is connected to the first contact structure.

7. The semiconductor device according to claim 5, further comprising: The metal layer is located on a side of the first insulating layer away from the first semiconductor layer and is connected to the first contact structure.

8. The semiconductor device according to claim 7, wherein: The metal layer is connected to the second contact structure.

9. The semiconductor device according to claim 7, further comprising: The second insulating layer is located on a side of the metal layer away from the first semiconductor layer.

10. The semiconductor device according to claim 5, wherein: The second contact structure penetrates the first semiconductor layer and the first insulating layer along the first direction.

11. The semiconductor device according to claim 10, wherein: The second contact structure includes a conductive structure and a third insulating layer. The third insulating layer is disposed around a portion of a sidewall of the conductive structure and is located between the conductive structure and the first semiconductor layer.

12. The semiconductor device according to claim 10, wherein: In a cross section parallel to the first direction, along a second direction, a size of a portion of the second contact structure located in the first semiconductor layer is larger than a size of a portion located in the second dielectric layer, and the second direction is perpendicular to the first direction.

13. The semiconductor device according to claim 1, wherein: The gate line gap structure includes a third dielectric layer and a conductive material layer, and the third dielectric layer is located between the conductive material layer and the stacked structure.

14. The semiconductor device according to claim 13, wherein: The air gap is located in the conductive material layer.

15. The semiconductor device according to claim 1, wherein: The gate line gap structure includes a first gate line gap structure and a second gate line gap structure, the first gate line gap structure includes a first air gap, and the second gate line gap structure includes a second air gap; The first air gap and the second air gap are different in shape, position and quantity in the corresponding gate line gap structure.

16. The semiconductor device according to claim 1, wherein: The first semiconductor layer and the second semiconductor layer include N-type doped portions.

17. A method for manufacturing a semiconductor device, comprising: forming a stacked structure, the stacked structure comprising a first dielectric layer and a conductive layer alternately stacked along a first direction; forming a first semiconductor layer, wherein the first semiconductor layer is located on a first side of the stacked structure along the first direction; forming a second semiconductor layer, wherein the second semiconductor layer is located between the first semiconductor layer and the stacked structure; forming a channel layer and a functional layer, wherein the channel layer and the functional layer penetrate the stacked structure and the second semiconductor layer along the first direction and extend into the first semiconductor layer; forming a first contact structure, wherein the first contact structure is located at a side of the first semiconductor layer away from the stacking structure and contacts the first semiconductor layer; as well as A gate line gap structure is formed, wherein the gate line gap structure penetrates the stacked structure to the second semiconductor layer along the first direction, wherein at least one of the gate line gap structures includes an air gap.

18. The method of claim 17, wherein: The forming of the stacked structure comprises: Forming first stacked layers and second stacked layers alternately stacked along the first direction on the first semiconductor layer; removing the first stacked layer; and A conductive layer is formed in the cavity left by etching the first stacked layer.

19. The method of claim 18, wherein: The forming of one or more gate line gap structures comprises: forming a slit extending along a second direction and penetrating through the first stacked layer and the second stacked layer along the first direction, wherein the second direction intersects the first direction; The slit is filled with a filler, wherein the filler includes an air gap.

20. The method of claim 18, wherein: The forming of the channel layer and the functional layer comprises: forming a channel hole penetrating the first stacked layer and the second stacked layer along the first direction; and A functional layer is formed on the sidewall of the channel hole, and a channel layer is formed on the sidewall of the functional layer.

21. The method of claim 18, wherein: Forming the second semiconductor layer includes: forming a sacrificial material layer on the first semiconductor layer; removing the sacrificial material layer through the slit, and removing a portion of the functional layer in contact with the sacrificial material layer; and A second conductive layer is formed in the cavity left by removing the sacrificial material layer and a portion of the functional layer in contact with the sacrificial material layer.

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