Capacitor structure and semiconductor structure

Abstract

The embodiments of the present application relate to the field of semiconductor technology, and provide a capacitor structure and a semiconductor structure, wherein the capacitor structure comprises: at least one first plate structure including a first main plate arranged in sequence along a first direction, at least two first extensions, and a plurality of first conductive through holes; the first conductive through hole connects the first main plate and the first extension closest to the first main plate, or connects two adjacent first extensions; at least one second plate structure including a second main plate arranged in sequence along a second direction, at least two second extensions, and a plurality of second conductive through holes; the second conductive through hole connects the second main plate and the second extension closest to the second main plate, or connects two adjacent second extensions; the second extension has at least four side walls extending in the first direction, and the first extension surrounds at least two side walls of the second extension. The embodiments of the present application are at least conducive to improving the quality factor of the capacitor structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a capacitor structure and a semiconductor structure. Background Art

[0002] With the continuous development of modern integrated circuits and communication technologies, in the field of chip design, chips are often required to work at frequencies of several GHz or even tens of GHz. In the LC structures of high-frequency oscillators, filters, resonators, etc., the Q value is a key design indicator. As the frequency increases, the quality factor of the capacitor decreases significantly, and the circuit performance is also affected. It is particularly important to improve the quality factor of the capacitor without increasing the layout area.

[0003] However, traditional interdigital MOM capacitors (i.e. Metal-Oxide-Metal capacitors) often have large parasitic resistance inside, which is insufficient to meet the requirements of high quality factor. Summary of the invention

[0004] The embodiments of the present application provide a capacitor structure and a semiconductor structure, which are at least beneficial to improving the quality factor of the capacitor structure.

[0005] On the one hand, an embodiment of the present application provides a capacitor structure, characterized in that it includes: at least one first electrode plate structure, the first electrode plate structure includes a first main electrode plate and at least two first extension portions arranged in sequence along a first direction, and a plurality of first conductive through holes; the first conductive through hole connects the first main electrode plate and the first extension portion closest to the first main electrode plate, or connects two adjacent first extension portions; at least one second electrode plate structure; the second electrode plate structure includes a second main electrode plate and at least two second extension portions arranged in sequence along a second direction, and a plurality of second conductive through holes; the second conductive through hole connects the second main electrode plate and the second extension portion closest to the second main electrode plate, or connects two adjacent second extension portions, and the first direction is opposite to the second direction; wherein the second extension portion has at least four side walls extending along the first direction, and the first extension portion at least surrounds two of the side walls of the second extension portion.

[0006] According to the capacitor structure provided in the present application, the first extension portion and the second extension portion correspond one to one, and the first extension portion and the second extension portion are arranged in the same layer.

[0007] According to the capacitor structure provided in the present application, at least a part of the first conductive vias located in the same layer are distributed at equal intervals, and / or at least a part of the first conductive vias located in different layers are opposite each other along the first direction; at least a part of the second conductive vias located in the same layer are distributed at equal intervals, and / or at least a part of the second conductive vias located in different layers are opposite each other along the first direction.

[0008] According to the capacitor structure provided by the present application, a first electrode plate structure and a second electrode plate structure facing each other along the first direction constitute a capacitor basic unit, and in the same capacitor basic unit, one of the first main electrode plate and the second main electrode plate is an upper electrode plate, and the other is a lower electrode plate, and the polarity of the upper electrode plate is different from the polarity of the lower electrode plate; a plurality of the capacitor basic units are arranged at intervals along the third direction and / or arranged at intervals along the fourth direction, and the first direction, the third direction and the fourth direction intersect each other; wherein, in two adjacent capacitor basic units along the third direction, one of the two adjacent first main electrode plates is the upper electrode plate, and the other is the lower electrode plate; and / or, in two adjacent capacitor basic units along the fourth direction, one of the two adjacent first main electrode plates is the upper electrode plate, and the other is the lower electrode plate.

[0009] On the other hand, the present application provides a semiconductor structure, comprising: a substrate, the substrate having a main inductance region and a capacitance region adjacent to each other along a fourth direction; a capacitance structure according to any one of the above items, the capacitance structure being located on the capacitance region; an inductance structure, the inductance structure comprising a main body and two legs respectively connected to two ends of the main body, the main body being located on the main inductance region, and the legs being located on the capacitance region; wherein the capacitance structure is located between the substrate and the legs, and the fourth direction is an extension direction of the legs; and a plurality of third conductive through holes, the third conductive through holes connecting the first main pole plate and at least one of the legs, and / or connecting the second main pole plate and at least one of the legs.

[0010] According to the semiconductor structure provided by the present application, a first electrode plate structure and a second electrode plate structure facing each other along the first direction constitute a basic capacitor unit, in the same basic capacitor unit, one of the first main electrode plate and the second main electrode plate is an upper electrode plate, and the other is a lower electrode plate, the upper electrode plate is electrically connected to one of the legs, and the first direction is the direction in which the substrate points to the inductor structure; at least two basic capacitor units arranged at intervals along the fourth direction are located on the capacitor region, and in two adjacent basic capacitor units along the fourth direction, one of the two adjacent first main electrodes is the upper electrode plate, and the other is the lower electrode plate; and / or, at least two basic capacitor units arranged at intervals along the third direction are located on the capacitor region, and in two adjacent basic capacitor units along the third direction, one of the two adjacent first main electrodes is the upper electrode plate, and the other is the lower electrode plate, and the third direction intersects with the fourth direction.

[0011] According to the semiconductor structure provided by the present application, the capacitor area includes a first sub-capacitor area, a switch area, and a second sub-capacitor area arranged in sequence along the fourth direction; a first plate structure and a second plate structure facing each other along the first direction constitute a capacitor basic unit, in the same capacitor basic unit, one of the first main plate and the second main plate is an upper plate, and the other is a lower plate, the upper plate is electrically connected to one of the legs, and the first direction is the direction in which the substrate points to the inductor structure; at least two of the capacitor basic units arranged at intervals along the fourth direction are located on the first sub-capacitor area, and / or, at least two of the capacitor basic units arranged at intervals along the fourth direction are located on the second sub-capacitor area, and two adjacent ones along the fourth direction are located on the second sub-capacitor area. In the capacitor basic units, one of the two adjacent first main plates is the upper plate, and the other is the lower plate; and / or, at least two of the capacitor basic units arranged at intervals along the third direction are located on the first sub-capacitor area, and / or, at least two of the capacitor basic units arranged at intervals along the third direction are located on the second sub-capacitor area, and in two adjacent capacitor basic units along the third direction, one of the two adjacent first main plates is the upper plate, and the other is the lower plate; the semiconductor structure also includes: a switching device, located on the switching area, and the switching device is used to selectively connect the capacitor basic unit located on the first sub-capacitor area and the capacitor basic unit located on the second sub-capacitor area.

[0012] According to the semiconductor structure provided by the present application, at least two of the capacitor basic units arranged at intervals along the fourth direction are located on the first sub-capacitor region, and at least two of the capacitor basic units arranged at intervals along the fourth direction are located on the second sub-capacitor region. Among the two adjacent capacitor basic units along the fourth direction, one of the two adjacent first main plates is the upper plate, and the other is the lower plate; the lower plates of at least two of the capacitor basic units located on the first sub-capacitor region and arranged along the fourth direction are electrically connected to form a first bus, and the lower plates of at least two of the capacitor basic units located on the second sub-capacitor region and arranged along the fourth direction are electrically connected to form a second bus, and the switching device is used to selectively connect the first bus and the second bus; one of the two legs of the inductor structure is electrically connected to the upper plates of at least two of the capacitor basic units located on the first sub-capacitor region and arranged along the fourth direction, and the other is electrically connected to the upper plates of at least two of the capacitor basic units located on the second sub-capacitor region and arranged along the fourth direction.

[0013] According to the semiconductor structure provided by the present application, a first electrode plate structure and a second electrode plate structure facing each other along a first direction constitute a basic capacitor unit, and the first direction is the direction in which the substrate points to the inductor structure; in the basic capacitor unit facing the leg along the first direction, the first extension portion is a ring structure with a break; in the basic capacitor unit not facing the leg along the first direction, the first extension portion is a closed ring structure or a ring structure with a break.

[0014] The technical solution provided by this application has at least the following advantages:

[0015] Different regions of the extension part in the capacitor structure can be electrically connected to the main pole plate by means of at least one conductive through hole closest to it. In other words, the length of the current transmission path between different regions in the same extension part and the main pole plate is basically the same, which is conducive to significantly reducing the difference in wiring resistance between different regions in the same extension part and the main pole plate, thereby improving the quality factor of the capacitor structure. Among them, the extension part includes a first extension part and a second extension part, and each region in the first extension part is mainly electrically connected to the first main pole plate by selecting the shortest current transmission path by means of at least one first conductive through hole, and each region in the second extension part is mainly electrically connected to the second main pole plate by means of at least one second conductive through hole.

[0016] In addition, designing the first extension portion to surround at least two side walls of the second extension portion is beneficial to increasing the facing area of ​​the first extension portion and the second extension portion, so that more sidewall capacitance is generated between the first extension portion and the second extension portion; further, designing the first electrode plate structure to include at least two first extension portions, and the second electrode plate structure to include at least two second extension portions is beneficial to further improving the capacitance value of the capacitor structure by increasing the number of first extension portions and the number of second extension portions when the layout area perpendicular to the second direction is constant. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present application or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A top view of an interdigital capacitor;

[0019] Figure 2 A schematic diagram of a three-dimensional structure of a first plate structure in a capacitor structure provided in an embodiment of the present application;

[0020] Figure 3 A schematic diagram of a three-dimensional structure of a second plate structure in a capacitor structure provided in an embodiment of the present application;

[0021] Figure 4 A schematic diagram of a partial top view of a capacitor structure provided in one embodiment of the present application;

[0022] Figure 5 A graph showing the quality factor of a conventional interdigital capacitor and a capacitor structure provided by an embodiment of the present application as a function of frequency;

[0023] Figure 6 A schematic diagram of a first partial cross-sectional structure of a capacitor structure provided in an embodiment of the present application;

[0024] Figure 7 A schematic diagram of a second partial cross-sectional structure of a capacitor structure provided in an embodiment of the present application;

[0025] Figure 8 A schematic diagram of a third partial cross-sectional structure of a capacitor structure provided in an embodiment of the present application;

[0026] Fig. 9 for Figure 4 A schematic diagram of a cross-sectional structure of the capacitor structure shown along a first cross-sectional direction AA1;

[0027] Fig.10 for Figure 4 A schematic diagram of a cross-sectional structure of the capacitor structure shown along a second cross-sectional direction BB1;

[0028] Fig.11 A schematic diagram of another cross-sectional structure of a capacitor structure provided by an embodiment of the present application along the first cross-sectional direction AA1;

[0029] Fig.12 A schematic diagram of another cross-sectional structure of a capacitor structure provided by an embodiment of the present application along a second cross-sectional direction BB1;

[0030] Fig.13 A schematic diagram of a fourth partial cross-sectional structure of a capacitor structure provided in an embodiment of the present application;

[0031] Fig.14 A schematic diagram of a first partial bottom-up structure of a semiconductor structure provided by another embodiment of the present application;

[0032] Fig.15 A schematic diagram of a second partial bottom-up structure of a semiconductor structure provided by another embodiment of the present application;

[0033] Fig.16 A third partial bottom-up structural schematic diagram of a semiconductor structure provided by another embodiment of the present application;

[0034] Fig.17 for Fig.16 The semiconductor structure shown is a schematic cross-sectional structure diagram along a third cross-sectional direction CC1.

[0035] Description of reference numerals:

[0036] 10. Upper electrode plate; 20. Upper electrode fork finger; 30. Lower electrode plate; 40. Lower electrode fork finger;

[0037] 100, capacitor structure; 110, capacitor basic unit; 101, first plate structure; 111, first main plate; 121, first extension; 121a, closed ring structure; 121b, ring structure with a break; 1211, first upper extension; 1212, first lower extension; 131, first conductive through hole; 102, second plate structure; 112, second main plate; 122, second extension; 122a, side wall; 122b, opening; 122c, inner side Wall; 1221, second upper extension; 1222, second lower extension; 132, second conductive through hole; 103, upper plate; 104, lower plate; 114, first bus; 124, second bus; 105, substrate; 115, main inductor region; 125, capacitor region; 135, first sub-capacitor region; 145, switch region; 155, second sub-capacitor region; 106, inductor structure; 116, main body; 126, leg; 107, third conductive through hole; 108, switch device. DETAILED DESCRIPTION

[0038] As known from the background technology, the quality factor of the capacitor structure needs to be improved.

[0039] The analysis found that the reference Figure 1 , Figure 1 It is a top view of a finger capacitor, which includes an upper pole and a lower pole arranged relatively, the upper pole includes an upper pole plate 10 and a plurality of upper pole fingers 20 connected to the upper pole plate 10, the lower pole includes a lower pole plate 30 and a plurality of lower pole fingers 40 connected to the lower pole plate 30, there is a lower pole finger 40 between adjacent upper pole fingers 20, and there is an upper pole finger 20 between adjacent lower pole fingers 40. Side wall capacitance will be parasitic between adjacent upper pole fingers 20 and lower pole fingers 40 in the same layer, and multiple layers of upper pole fingers 20 and lower pole fingers 40 are stacked to increase the capacitance value per unit area.

[0040] However, on the one hand, the sidewall capacitance generated on each upper pole fork finger 20 needs to be connected to the upper pole plate 10 after passing through a section of metal routing, and the sidewall capacitance generated on each lower pole fork finger 40 also needs to be connected to the lower pole plate 30 after passing through a section of metal routing, which will generate a certain routing resistance, resulting in a low quality factor of the fork finger capacitor; on the other hand, based on the layout design of the fork finger capacitor, the distances between different regions of the same upper pole fork finger 20 and the upper pole plate 10 are different, and the distances between different regions of the same lower pole fork finger 40 and the lower pole plate 30 are different, resulting in a large difference in the length of the current transmission path between different regions in the same fork finger and the pole plate, that is, a large difference in routing resistance, which is also likely to lead to a low quality factor of the fork finger capacitor.

[0041] In addition, in order to improve the quality factor of the interdigital capacitor, the traditional approach is to widen the width of each interdigital finger or strengthen the connection between the upper and lower plates to reduce the wiring resistance. However, this approach requires more wiring resources and a larger layout area, which easily leads to an increase in chip costs.

[0042] The embodiments of the present application provide a capacitor structure and a semiconductor structure, in which different regions of the extension portion of the capacitor structure can be electrically connected to the main pole plate by means of at least one conductive through hole closest to the extension portion. In other words, the length of the current transmission path between different regions in the same extension portion and the main pole plate is substantially the same, which is conducive to significantly reducing the difference in wiring resistance between different regions in the same extension portion and the main pole plate, thereby improving the quality factor of the capacitor structure. The extension portion includes a first extension portion and a second extension portion, and each region in the first extension portion is mainly electrically connected to the first main pole plate by selecting the shortest current transmission path by means of at least one first conductive through hole, and each region in the second extension portion is mainly electrically connected to the second main pole plate by selecting the shortest current transmission path by means of at least one second conductive through hole. In addition, designing the first extension portion to surround at least two side walls of the second extension portion is beneficial to increasing the facing area of ​​the first extension portion and the second extension portion, so that more sidewall capacitance is generated between the first extension portion and the second extension portion; further, designing the first electrode plate structure to include at least two first extension portions, and the second electrode plate structure to include at least two second extension portions is beneficial to further improving the capacitance value of the capacitor structure by increasing the number of first extension portions and the number of second extension portions when the layout area perpendicular to the second direction is constant.

[0043] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0044] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0045] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0046] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0047] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present application.

[0048] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0049] In the accompanying drawings corresponding to the embodiments of the present application, the thickness and area of ​​the layer are exaggerated for better understanding and ease of description. When describing a component (such as a layer, film, region or substrate) on another component or on the surface of another component, the component can be "directly" located on the surface of the other component, or a third component can exist between the two components. On the contrary, when describing a component on the surface of another component or when another component is formed or provided on the surface of a component, it means that there is no third component between the two components. In addition, when describing a component as "substantially" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a partial edge of the entire surface.

[0050] In the description of the embodiments of the present application, when a component "includes" another component, unless otherwise specified, other components are not excluded, and other components may be further included. In addition, when a component such as a layer, film, region, or plate is referred to as "on / located on" another component, it can be "directly on" the other component (i.e., located on the surface of the other component without other components between the two), or another component may exist in between. In addition, when a component such as a layer, film, region, or plate is "directly located on" another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it means that no other components are located in between.

[0051] The terms used in the description of the various embodiments described herein are only used to describe specific embodiments and are not intended to be limiting. As used in the description of the various embodiments described and in the appended claims, "the components" are also intended to include plural forms unless the context clearly indicates otherwise. Among them, components include components such as layers, films, regions, or plates.

[0052] The following will be described in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the embodiments of the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present application can be implemented.

[0053] An embodiment of the present application provides a capacitor structure, which will be described in detail below with reference to the accompanying drawings.

[0054] refer to Figures 2 to 4 The capacitor structure 100 includes: at least one first plate structure 101, the first plate structure 101 includes a first main plate 111 and at least two first extensions 121 arranged in sequence along a first direction X1, and a plurality of first conductive through holes 131; the first conductive through holes 131 connect the first main plate 111 and the first extension 121 closest to the first main plate 111, or connect two adjacent first extensions 121; at least one second plate structure 102; the second plate structure 102 includes a first main plate 111 and a first extension 121 arranged in sequence along a first direction X2. A second main pole plate 112 and at least two second extension portions 122 are arranged in a spaced relationship, and a plurality of second conductive through holes 132; the second conductive through holes 132 connect the second main pole plate 112 and the second extension portion 122 closest to the second main pole plate 112, or connect two adjacent second extension portions 122, and the first direction X1 and the second direction X2 are opposite; wherein the second extension portion 122 has at least four side walls extending along the first direction X1, and the first extension portion 121 at least surrounds two side walls 122a of the second extension portion 122.

[0055] in, Figure 2 A schematic diagram of a three-dimensional structure of a first plate structure in a capacitor structure provided in an embodiment of the present application; Figure 3 A schematic diagram of a three-dimensional structure of a second plate structure in a capacitor structure provided in an embodiment of the present application; Figure 4 This is a partial top view of a capacitor structure provided in an embodiment of the present application. It should be noted that, in order to clearly illustrate the first extension portion 121 and the first conductive through hole 131, Figure 2 In the figure, the first main pole plate 111 is drawn in perspective; in order to clearly illustrate the first extension portion 121, the first conductive through hole 131, the second main pole plate 112, the second extension portion 122 and the second conductive through hole 132, Figure 4 In the figure, the first main pole plate 111 and the second extension portion 122 are both drawn in perspective.

[0056] It is worth noting that the capacitor structure 100 provided in an embodiment of the present disclosure is different from the conventional interdigital capacitor. Compared with the conventional interdigital capacitor, the difference in wiring resistance from different areas of the interdigital to the plate is larger. Different areas of the extension portion in the capacitor structure 100 can be electrically connected to the main plate by means of the conductive through-holes closest to them. In other words, the length of the current transmission path between different areas in the same extension portion and the main plate is basically the same, which is conducive to greatly reducing the difference in wiring resistance between different areas in the same extension portion and the main plate, thereby improving the quality factor of the capacitor structure 100. Moreover, a first plate structure 101 and a second plate structure 102 facing each other along the first direction X1 constitute a capacitor basic unit 110, and the capacitor structure 100 may include at least one capacitor basic unit 110.

[0057] It is worth emphasizing that the capacitor structure provided in an embodiment of the present application is applied to the field of chip design. In other words, the capacitor structure provided in an embodiment of the present application can be used as a local electrical component in a chip, for example, an on-chip capacitor, to improve the quality factor of the on-chip capacitor.

[0058] In some embodiments, reference Figure 5 , Figure 5 The graph is a graph showing the quality factor of the conventional interdigital capacitor and the capacitor structure provided by an embodiment of the present application as a function of frequency. The red line represents Figure 1 The curve of the quality factor of the traditional interdigital capacitor as it varies with frequency is shown, and the green line represents the curve of the quality factor of the capacitor structure 100 provided in an embodiment of the present application as it varies with frequency. It can be seen that compared with the traditional interdigital capacitor, the quality factor of the capacitor structure 100 provided in an embodiment of the present application is significantly improved.

[0059] It should be noted that the extension portion mentioned in the above description includes a first extension portion 121 and a second extension portion 122, the main pole plate includes a first main pole plate 111 and a second main pole plate 112, and the conductive through hole includes a first conductive through hole 131 and a second conductive through hole 132. The following takes a single capacitor basic unit 110 as an example to describe the first extension portion 121 and the second extension portion 122 in detail.

[0060] refer to Figure 2 , it is designed that there are a plurality of first conductive through holes 131 between the first main pole plate 111 and the first extension part 121 closest to the first main pole plate 111, and there are a plurality of first conductive through holes 131 between adjacent first extension parts 121. In this way, the first conductive through holes 131 of different layers can realize current transmission through the local area of ​​the first extension part 121 located between the two, and no matter which first extension part 121, at least one first conductive through hole 131 closest to it can be preferentially selected to realize electrical connection with the first main pole plate 111. In other words, the length of the current transmission path between different areas in the same first extension part 121 and the first main pole plate 111 is basically the same, which is conducive to greatly reducing the difference in wiring resistance between different areas in the same first extension part 121 and the first main pole plate 111, thereby improving the quality factor of the capacitor structure 100.

[0061] refer to Figure 3 , it is designed that there are a plurality of second conductive through holes 132 between the second main pole plate 112 and the second extension part 122 closest to the second main pole plate 112, and there are a plurality of second conductive through holes 132 between adjacent second extension parts 122. In this way, the second conductive through holes 132 of different layers can realize current transmission through the local area of ​​the second extension part 122 located between the two, and no matter which second extension part 122, at least one second conductive through hole 132 closest to it can be preferentially selected to realize electrical connection with the second main pole plate 112. In other words, the length of the current transmission path between different areas in the same second extension part 122 and the second main pole plate 112 is basically the same, which is conducive to significantly reducing the difference in wiring resistance between different areas in the same second extension part 122 and the second main pole plate 112, thereby improving the quality factor of the capacitor structure 100.

[0062] In addition, combined with reference Figures 2 to 4On the basis of the above-mentioned concept of reducing the wiring resistance inside the capacitor basic unit 110, the first extension portion 121 is designed to at least surround the two side walls 122a of the second extension portion 122, which is beneficial to increase the facing area of ​​the first extension portion 121 and the second extension portion 122, so that more sidewall capacitance is generated between the first extension portion 121 and the second extension portion 122; further, the first electrode plate structure 101 includes at least two first extension portions 121 arranged at intervals along the first direction X1, and the second electrode plate structure 102 includes at least two second extension portions 122 arranged in sequence at intervals along the second direction X2, which is beneficial to further improve the capacitance value of the capacitor structure 100 by increasing the number of first extension portions 121 and the number of second extension portions 122 when the layout area perpendicular to the second direction X2 is constant.

[0063] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings.

[0064] It is worth noting that reference Figure 6 , Figure 7 or Figure 8 The second extension portion 122 has at least four sidewalls 122a extending along the first direction, and at least includes the following two situations: In some cases, referring to Figure 6 or Figure 7 , the second extension portion 122 is a long plate-like structure, and the second extension portion 122 has four side walls 122a extending along the first direction; in other cases, refer to Figure 8 The second extension part 122 is a long plate-like structure with an opening 122b in the middle. The second extension part 122 has four side walls 122a extending along the first direction as its outer side walls. The second extension part 122 also has four inner side walls 122c extending along the first direction. This is beneficial to increase the facing area of ​​the first extension part 121 and the second extension part 122 while reducing the local metal density. Figure 6 A schematic diagram of a first partial cross-sectional structure of a capacitor structure provided in an embodiment of the present application; Figure 7 A schematic diagram of a second partial cross-sectional structure of a capacitor structure provided in an embodiment of the present application; Figure 8 This is a schematic diagram of a third partial cross-sectional structure of a capacitor structure provided in an embodiment of the present application. It should be noted that the plane formed by the third direction Y and the fourth direction Z is used as a reference cross section. Figures 6 to 8 All of them are schematic diagrams of partial cross-sectional structures of the capacitor structure along the reference cross section. In some examples, the reference cross section formed by the third direction Y and the fourth direction Z is perpendicular to the first direction X1.

[0065] In both of the above situations, the first extension portion 121 can at least surround the two side walls 122a of the second extension portion 122. It should be noted that: Figures 6 to 8In the figure, the first extension portion 121 surrounding the four side walls 122a of the second extension portion 122 is taken as an example. In actual application, the first extension portion may also only surround two side walls or three side walls of the second extension portion.

[0066] In some embodiments, reference Figure 6 or Figure 8 , the first extension portion 121 is a closed annular structure 121a; in other embodiments, refer to Figure 7 , the first extension portion 121 is a ring structure 121b with a break. It is worth noting that, no matter whether the first extension portion 121 is a closed ring structure 121a or a ring structure 121b with a break, the first extension portion 121 can surround the four side walls 122a of the second extension portion 122 to enhance the side wall capacitance generated between the first extension portion 121 and the second extension portion 122; and, taking the plane perpendicular to the first direction X1 as the projection plane, the second extension portion 122 is located in the orthographic projection area enclosed by the first extension portion 121. In other words, the orthographic projection area of ​​the second extension portion 122 will not affect the layout area required to be occupied by the capacitor structure 100 in the direction perpendicular to the first direction X1.

[0067] In addition, designing the first extension portion 121 as a ring structure 121 b with a break is beneficial to reducing the magnetic field generated by the induced current of the ring structure on the surface of the first extension portion 121, thereby reducing the impact of the eddy current effect on other nearby electrical devices (such as: inductor structure).

[0068] It should be noted that the following detailed description will be mainly given in the form of the first extension portion 121 being a closed annular structure 121a. In practical applications, the first extension portion in the subsequent embodiments may also be applicable to an annular structure with a fracture.

[0069] In some embodiments, reference Figures 6 to 8 , taking the plane formed by the third direction Y and the fourth direction Z as the reference cross section, the cross-sectional shape of the first conductive via 131 can be a square or a rectangle, and the cross-sectional shape of the second conductive via 132 can also be a square or a rectangle. In some embodiments, in combination with reference Fig. 9 and Fig.10 , or in combination with reference Fig.11 and Fig.12, the first extension part 121 and the second extension part 122 can correspond to each other one by one, and the first extension part 121 and the second extension part 122 are arranged in the same layer, that is, the first extension part 121 and the second extension part 122 are located in the same layer. In this way, it is beneficial to make the number of metal layers occupied by the first plate structure 101 and the second plate structure 102 the same, and to ensure that each first extension part 121 has a second extension part 122 arranged in the same layer, so that the layout of the first extension part 121 and the second extension part 122 in the capacitor structure 100 is compact, which is beneficial to ensure that there is sufficient facing area between the first plate structure 101 and the second plate structure 102 in the capacitor structure 100, so as to improve the capacitance value of the capacitor structure 100 when the layout area occupied by the capacitor structure 100 in the direction perpendicular to the first direction X1 is limited.

[0070] in, Fig. 9 for Figure 4 A schematic diagram of a cross-sectional structure of the capacitor structure shown along a first cross-sectional direction AA1; Fig.10 for Figure 4 A schematic diagram of a cross-sectional structure of the capacitor structure shown along a second cross-sectional direction BB1; Fig.11 A schematic diagram of another cross-sectional structure of a capacitor structure provided by an embodiment of the present application along the first cross-sectional direction AA1; Fig.12 A schematic diagram of another cross-sectional structure of a capacitor structure provided in an embodiment of the present application along the second cross-sectional direction BB1.

[0071] It is worth noting that, based on the plurality of first conductive through holes 131, a plurality of current transmission paths are formed between the first extension portion 121 and the first main pole plate 111. Figure 4 , Figures 6 to 8 , at least part of the first conductive vias 131 located in the same layer may be distributed at equal intervals, and, with reference to Figure 2 , Figures 9 to 12, at least part of the number of first conductive through holes 131 located in different layers can be directly opposite along the first direction X1, so that it is beneficial to further reduce the length difference of multiple current transmission paths formed between the first extension portion 121 and the first main pole plate 111, so that the current transmission path between the first extension portion 121 and the first main pole plate 111 is more evenly distributed, thereby reducing the difference in wiring resistance between different regions in the first extension portion 121 and the first main pole plate 111, thereby improving the quality factor of the capacitor structure 100. Moreover, designing at least part of the number of first conductive through holes 131 located in the same layer to be distributed at equal intervals, and designing at least part of the number of first conductive through holes 131 located in different layers to be directly opposite along the first direction X1, both of which are beneficial to ensure the uniformity of the layout of the designed capacitor structure 100. At the same time, in accordance with the requirements of the process factory, making as many first conductive through holes 131 as possible and directly opposite along the first direction X1 are beneficial to reduce the wiring resistance between different regions in the first extension portion 121 and the first main pole plate 111, thereby improving the quality factor of the capacitor structure 100.

[0072] In other embodiments, according to actual needs, at least some of the first conductive vias in the same layer may be designed to be equally spaced, but at least some of the first conductive vias in different layers may not be directly opposite each other along the first direction; or, at least some of the first conductive vias in different layers may be designed to be directly opposite each other along the first direction, but at least some of the adjacent first conductive vias in the same layer may have different spacings.

[0073] It should be noted that Figure 4 , Figures 6 to 8 In the example, the multiple first conductive vias 131 located in the same layer and arranged along the fourth direction Z are distributed at equal intervals, but the interval between the first conductive via 131 located at the corner and the first conductive via 131 adjacent to it along the fourth direction Z is not equal to the interval between the first conductive via 131 located at the corner and the first conductive via 131 adjacent to it along the third direction Y. In practical applications, among the multiple first conductive vias electrically connected to the same first extension portion, there is no restriction on the number of first conductive vias arranged along the third direction and the number of second conductive vias arranged along the fourth direction, and the number of first conductive vias arranged at equal intervals and the positions of contact and connection with the first extension portion can be designed according to requirements. For example, the interval between any two adjacent first conductive vias can be designed to be a set fixed value.

[0074] In addition, at least part of the first conductive vias 131 located in different layers are facing each other along the first direction X1, which means that, with a plane perpendicular to the first direction X1 as the projection plane, the orthographic projections of two adjacent first conductive vias 131 along the first direction X1 can overlap. Figure 2In the example, any pair of two first conductive vias 131 adjacent to each other along the first direction X1 are directly opposite to each other. In practical applications, only a part of the first conductive vias located in different layers may be designed to be directly opposite to each other along the first direction.

[0075] It is worth noting that, based on the plurality of second conductive through holes 132, a plurality of current transmission paths are formed between the second extension portion 122 and the second main plate 112. Figure 4 , Figures 6 to 8 , at least a portion of the second conductive vias 132 located in the same layer may be distributed at equal intervals, and, with reference to Figure 3 , Figures 9 to 12 , at least part of the number of second conductive through holes 132 located in different layers can be directly opposite along the first direction X1. In this way, it is beneficial to further reduce the length difference of multiple current transmission paths formed between the second extension portion 122 and the second main pole plate 112, so that the current transmission path between the second extension portion 122 and the second main pole plate 112 is more evenly distributed, thereby reducing the difference in wiring resistance between different regions in the second extension portion 122 and the second main pole plate 112, thereby improving the quality factor of the capacitor structure 100. Moreover, designing at least part of the number of second conductive through holes 132 located in the same layer to be equally spaced, and designing at least part of the number of second conductive through holes 132 located in different layers to be directly opposite along the first direction X1, both of which are beneficial to ensure the uniformity of the layout of the designed capacitor structure 100. At the same time, in accordance with the requirements of the process factory, making as many second conductive through holes 132 as possible and directly opposite along the first direction X1 are beneficial to reduce the wiring resistance between different regions in the second extension portion 122 and the second main pole plate 112, thereby improving the quality factor of the capacitor structure 100.

[0076] In other embodiments, according to actual needs, at least a part of the second conductive vias in the same layer may be designed to be equally spaced, but at least a part of the second conductive vias in different layers may not be directly opposite along the first direction; or, at least a part of the second conductive vias in different layers may be designed to be directly opposite along the first direction, but the spacing between at least a part of the adjacent second conductive vias in the same layer is different.

[0077] It should be noted that Figure 4 , Figures 6 to 8 In the example, multiple second conductive vias 132 located in the same layer and arranged along the fourth direction Z are evenly spaced. In practical applications, among the multiple second conductive vias electrically connected to the same second extension portion, only a portion of the second conductive vias can be evenly spaced according to requirements. Figure 3 , Figure 6 and Figure 7In the example, the second extension portion 122 is a long plate-like structure, and the plurality of second conductive through holes 132 are arranged only along the fourth direction Z. In practical applications, the plurality of second conductive through holes connected to the second extension portion may also be arranged along the third direction, or, as Figure 8 As shown, the second extension portion 122 is a long plate-like structure with an opening 122b in the middle. A plurality of second conductive vias 132 connected to the second extension portion 122 are arranged in a manner surrounding the opening 122b, and the number of second conductive vias arranged at equal intervals and the position of contact and connection with the second extension portion can be designed according to requirements.

[0078] In addition, at least part of the second conductive vias 132 located in different layers are facing each other along the first direction X1, which means that, taking a plane perpendicular to the first direction X1 as a projection plane, the orthographic projections of two adjacent second conductive vias 132 along the first direction X1 can overlap. Figure 3 In the example, any pair of two second conductive vias 132 adjacent to each other along the first direction X1 are directly opposite to each other. In practical applications, only a part of the second conductive vias located in different layers may be designed to be directly opposite to each other along the first direction.

[0079] In some embodiments, in conjunction with reference Fig. 9 and Fig.10 , or in combination with reference Fig.11 and Fig.12 A first plate structure 101 and a second plate structure 102 facing each other along the first direction X1 constitute a capacitor basic unit 110. In the same capacitor basic unit 110, one of the first main plate 111 and the second main plate 112 is an upper plate 103, and the other is a lower plate 104. The polarity of the upper plate 103 is different from that of the lower plate 104.

[0080] It should be noted that Fig. 9 and Fig.10 In the example, the first main plate 111 in the same capacitor basic unit 110 is the upper plate 103, and the second main plate 112 is the lower plate 104; Fig.11 and Fig.12 In the example, the first main plate 111 in the same capacitor basic unit 110 is the lower plate 104, and the second main plate 112 is the upper plate 103; Fig. 9 and Fig.10 The capacitor basic unit 110 and Fig.11 and Fig.12 The capacitor basic units 110 shown may be different capacitor basic units 110 in the same capacitor structure.

[0081] refer to Fig.13 , Fig.13This is a schematic diagram of a second partial top view of a capacitor structure provided by an embodiment of the present application, wherein a plurality of capacitor basic units 110 are arranged at intervals along the third direction Y and arranged at intervals along the fourth direction Z, and the first direction X1, the third direction Y, and the fourth direction Z intersect each other. In other words, a plurality of capacitor basic units 110 are arranged at intervals along the third direction Y, and a plurality of capacitor basic units 110 are arranged at intervals along the fourth direction Z.

[0082] Among them, combined with reference Fig.10 , Fig.12 and Fig.13 In two capacitor basic units 110 adjacent to each other along the third direction Y, one of the two adjacent first main plates 111 is the upper plate 103, and the other is the lower plate 104; and in two capacitor basic units 110 adjacent to each other along the fourth direction Z, one of the two adjacent first main plates 111 is the upper plate 103, and the other is the lower plate 104.

[0083] It is worth noting that in order to reflect the difference between adjacent capacitor basic units 110, Fig.13 Only the first extension portion 121 and the second extension portion 122 in the capacitor basic unit 110 are shown, and the first extension portion 121 is electrically connected to the first main plate 111. In order to distinguish the first main plate 111 as the upper plate 103 and the lower plate 104, Fig.13 The first extension portion 121 is divided into: a first upper extension portion 1211 electrically connected to the first main pole plate 111 as the upper pole plate 103, and a first lower extension portion 1212 electrically connected to the first main pole plate 111 as the lower pole plate 104; the second extension portion 122 is electrically connected to the second main pole plate 112, in order to distinguish the second main pole plate 112 as the upper pole plate 103 and the lower pole plate 104, Fig.13 The second extension portion 122 is divided into: a second upper extension portion 1221 electrically connected to the second main pole plate 112 as the upper pole plate 103, and a second lower extension portion 1222 electrically connected to the second main pole plate 112 as the lower pole plate 104. In addition, Fig.13 Different filling methods are used to draw the first upper extension part 1211 and the first lower extension part 1212, and different filling methods are used to draw the second upper extension part 1221 and the second lower extension part 1222, and the second upper extension part 1221 is surrounded by the first lower extension part 1212, and the second lower extension part 1222 is surrounded by the first upper extension part 1211. It is worth emphasizing that Fig.13 In the figure, the first upper extension portion 1211 and the second upper extension portion 1221 are drawn with lighter filling to indicate that the first upper extension portion 1211 and the second upper extension portion 1221 are both electrically connected to the upper electrode plate 103; Fig.13The first lower extension portion 1212 and the second lower extension portion 1222 are both drawn with darker filling to indicate that the first lower extension portion 1212 and the second lower extension portion 1222 are both electrically connected to the lower electrode plate 104 .

[0084] In this way, it is beneficial to make the polarities of the two adjacent first main plates 111 in the two adjacent capacitor basic units 110 along the third direction Y or the fourth direction Z different, and the polarities of the two adjacent second main plates 112 are different, so that the polarities of the two adjacent first plate structures 101 are different, and the polarities of the two adjacent second plate structures 102 are also different, which is beneficial to generate side wall capacitance between the side walls of the two adjacent first plate structures 101, thereby helping to further improve the capacitance value of the capacitor structure 100.

[0085] It should be noted that Fig.13 In the example, only a plurality of capacitor basic units 110 are arranged at intervals along the third direction Y, and a plurality of capacitor basic units 110 are arranged at intervals along the fourth direction Z. In actual applications, a plurality of capacitor basic units may be arranged at intervals only along the third direction, or a plurality of capacitor basic units may be arranged at intervals only along the fourth direction. Regardless of the direction in which the capacitor basic units are arranged at intervals, one of the two first main plates in two adjacent capacitor basic units is an upper plate, and the other is a lower plate, to ensure that sidewall capacitance is generated between the side walls of the two first plate structures in the two adjacent capacitor basic units.

[0086] In summary, different regions of the extension portion in the capacitor structure 100 can be electrically connected to the main pole plate by means of at least one conductive through hole closest to it. In other words, the length of the current transmission path between different regions in the same extension portion and the main pole plate is basically the same, which is conducive to significantly reducing the difference in wiring resistance between different regions in the same extension portion and the main pole plate, thereby improving the quality factor of the capacitor structure. Among them, the extension portion includes a first extension portion 121 and a second extension portion 122, and each region in the first extension portion 121 mainly selects the shortest current transmission path to be electrically connected to the first main pole plate 111 by means of at least one first conductive through hole 131, and each region in the second extension portion 122 mainly selects the shortest current transmission path to be electrically connected to the second main pole plate 112 by means of at least one second conductive through hole 132. In addition, designing the first extension portion 121 to at least surround the two side walls 122a of the second extension portion 122 is beneficial to increasing the facing area of ​​the first extension portion 121 and the second extension portion 122, so that more sidewall capacitance is generated between the first extension portion 121 and the second extension portion 122; further, designing the first electrode structure 101 to include at least two first extension portions 121, and the second electrode structure 102 to include at least two second extension portions 122 is beneficial to further improve the capacitance value of the capacitor structure 100 by increasing the number of first extension portions 121 and the number of second extension portions 122 when the layout area perpendicular to the second direction X2 is constant.

[0087] Another embodiment of the present application further provides a semiconductor structure, including the capacitor structure provided in the above embodiment. The semiconductor structure provided in another embodiment of the present application will be described in detail below in conjunction with the accompanying drawings. It should be noted that the parts that are the same or corresponding to the above embodiment will not be repeated here.

[0088] refer to Figures 14 to 17 The semiconductor structure includes: a substrate 105, on which a main inductance region 115 and a capacitor region 125 adjacent to each other along a fourth direction Z are formed; the capacitor structure 100 provided in the above-mentioned embodiment, the capacitor structure 100 is located on the capacitor region 125; the inductance structure 106, the inductance structure 106 includes a main body 116 and two legs 126 respectively connected to two ends of the main body 116, the main body 116 is located on the main inductance region 115, and the legs 126 are located on the capacitor region 125; wherein the capacitor structure 100 is located between the substrate 105 and the legs 126, and the fourth direction Z is the extension direction of the legs 126; a plurality of third conductive through holes 107, the third conductive through holes 107 connecting the first main pole plate 111 and at least one leg 126, or connecting the second main pole plate 112 and at least one leg 126.

[0089] in, Fig.14 A schematic diagram of a first partial bottom-up structure of a semiconductor structure provided by another embodiment of the present application; Fig.15 A schematic diagram of a second partial bottom-up structure of a semiconductor structure provided by another embodiment of the present application; Fig.16 A third partial bottom-up structural schematic diagram of a semiconductor structure provided by another embodiment of the present application; Fig.17 for Fig.16 The semiconductor structure shown is a schematic cross-sectional structure diagram along a third cross-sectional direction CC1.

[0090] It should be noted that, in conjunction with the reference Fig.14 , Fig.16 and Fig.17 , the capacitor structure 100 includes a plurality of capacitor basic units 110 arranged along a fourth direction Z, and a single leg 126 can be electrically connected to the first main plates 111 in a portion of the capacitor basic units 110 through the third conductive via 107, and electrically connected to the second main plates 112 in another portion of the capacitor basic units 110 through the third conductive via 107. In addition, in order to reflect the difference between adjacent capacitor basic units 110, for the capacitor basic units 110, Fig.14 and Fig.16 Only the first extension portion 121 and the second extension portion 122 in the capacitor basic unit 110 are shown. Fig.14 and Fig.16 Zhongyu Fig.13 The same or corresponding parts will not be described in detail here.

[0091] It is worth noting that based on the first extension 121, the second extension 122, the first conductive through-hole 131 and the second conductive through-hole 132 in the capacitor structure 100, it is helpful to reduce the difference in wiring resistance between the various regions inside the capacitor structure 100, so as to improve the quality factor of the capacitor structure 100. On this basis, the first main pole plate 111 or the second main pole plate 112 is designed to be electrically connected to the leg 126 of the inductor structure 106 by means of multiple third conductive through-holes 107, so that the leg 126 and multiple regions of the first main pole plate 111 or the second main pole plate 112 have a conductive path based on different third conductive through-holes 107. In this way, no matter which region in the first main pole plate 111 or which region in the second main pole plate 112, at least one third conductive through-hole 107 closest to it can be preferentially selected to achieve electrical connection with the leg 126. In other words, it is beneficial It is useful for reducing the difference in the length of the current transmission path between different areas in the same first main pole plate 111 and the leg 126, and reducing the difference in the length of the current transmission path between different areas in the same second main pole plate 112 and the leg 126, thereby helping to reduce the difference in the wiring resistance between different areas in the same first main pole plate 111 and the leg 126, and reducing the difference in the wiring resistance between different areas in the same second main pole plate 112 and the leg 126, thereby improving the quality factor of the semiconductor structure, making the semiconductor structure more suitable for high-frequency working environments.

[0092] It is worth emphasizing that the semiconductor structure provided in another embodiment of the present application is applied to the field of chip design. In other words, the semiconductor structure provided in another embodiment of the present application can be used as a local electrical component in a chip, for example, the capacitor structure 100 is used as an on-chip capacitor and the inductor structure 106 is used as an on-chip inductor, so that the chip containing the semiconductor structure is more suitable for high-frequency working environments. In some cases, reference Figures 14 to 17 , one end of the capacitor basic unit 110, i.e., one of the first main plate 111 or the second main plate 112, is electrically connected to the leg 126, and the other end of the capacitor basic unit 110, i.e., the other of the first main plate 111 or the second main plate 112, can be connected to other devices, for example, the other of the first main plate 111 or the second main plate 112 can be grounded. In other cases, the two ends of the capacitor basic unit can be electrically connected to two legs in the same inductor structure, i.e., one of the first main plate or the second main plate is electrically connected to one leg, and the other of the first main plate or the second main plate is electrically connected to the other leg.

[0093] In some embodiments, in conjunction with reference Fig.14 , Fig.16 and Fig.17 A first plate structure 101 and a second plate structure 102 facing each other along the first direction X1 constitute a capacitor basic unit 110. In the same capacitor basic unit 110, one of the first main plate 111 and the second main plate 112 is an upper plate 103, and the other is a lower plate 104. The upper plate 103 is electrically connected to a leg 126. The first direction X1 is the direction from the substrate 105 to the inductor structure 106.

[0094] It is worth noting that the polarities of different first main plates 111 belonging to different capacitor basic units 110 can be different or the same. Similarly, the polarities of different second main plates 112 belonging to different capacitor basic units 110 can be different or the same. The design of different first main plates 111 and different second main plates 112 belonging to different capacitor basic units 110 is described in detail below.

[0095] In some cases, in conjunction with reference Fig.14 , Fig.16 and Fig.17, at least two capacitor basic units 110 arranged at intervals along the fourth direction Z are located on the capacitor area 125, and in two adjacent capacitor basic units 110 along the fourth direction Z, one of the two adjacent first main plates 111 is the upper plate 103, and the other is the lower plate 104. In other words, the two adjacent capacitor basic units 110 along the fourth direction Z are respectively used as the first capacitor basic unit and the second capacitor basic unit, the first main plate 111 electrically connected to the first extension portion 121 in the first capacitor basic unit is the upper plate 103, and the first main plate 111 electrically connected to the first extension portion 121 in the second capacitor basic unit is the lower plate 104, so that the polarities of the first extension portions 121 in the first capacitor basic unit and the second capacitor basic unit are different, so that sidewall capacitance can be generated between adjacent first extension portions 121 in adjacent capacitor basic units 110, so as to improve the capacitance value of the capacitor structure 100.

[0096] In other cases, continue to combine reference Fig.14 , Fig.16 and Fig.17 , at least two capacitor basic units 110 arranged at intervals along the third direction Y are located on the capacitor area 125, and in two adjacent capacitor basic units 110 along the third direction Y, one of the two adjacent first main plates 111 is an upper plate 103, and the other is a lower plate 104, and the third direction Y intersects with the fourth direction Z. In other words, the two adjacent capacitor basic units 110 along the third direction Y are respectively used as the third capacitor basic unit and the fourth capacitor basic unit, and the first main plate 111 electrically connected to the first extension portion 121 in the third capacitor basic unit is the upper plate 103, and the first main plate 111 electrically connected to the first extension portion 121 in the fourth capacitor basic unit is the lower plate 104, so that the polarities of the first extension portions 121 in the third capacitor basic unit and the fourth capacitor basic unit are different, so that sidewall capacitance can be generated between adjacent first extension portions 121 in adjacent capacitor basic units 110, so as to improve the capacitance value of the capacitor structure 100.

[0097] It should be noted that the same capacitor structure 100 can include both of the above situations. In other words, the same capacitor structure 100 not only has a plurality of capacitor basic units 110 arranged at intervals along the third direction Y, but also has a plurality of capacitor basic units 110 arranged at intervals along the fourth direction Z. In practical applications, according to requirements, it is also possible to design that the same capacitor structure has a plurality of capacitor basic units arranged at intervals only along the fourth direction, then one of the two adjacent first main plates of the two adjacent capacitor basic units along the fourth direction is the upper plate, and the other is the lower plate; or, it is also possible to design that the same capacitor structure has a plurality of capacitor basic units arranged at intervals only along the third direction, then one of the two adjacent first main plates of the two adjacent capacitor basic units along the third direction is the upper plate, and the other is the lower plate.

[0098] also, Fig.14 In the example, eight capacitor basic units 110 located on the capacitor region 125 are arranged at intervals along the third direction Y, and three capacitor basic units 110 located on the capacitor region 125 are arranged at intervals along the fourth direction Z. In practical applications, there is no limitation on the number of capacitor basic units located on the capacitor region and arranged at intervals along the third direction and the fourth direction, and for example, the number may be 4, 5, 6 or 7.

[0099] In some embodiments, in conjunction with reference Figures 15 to 17 , the capacitor area 125 may include a first sub-capacitor area 135, a switch area 145, and a second sub-capacitor area 155 arranged in sequence along the fourth direction Z; a first plate structure 101 and a second plate structure 102 facing each other along the first direction X1 constitute a capacitor basic unit 110, in the same capacitor basic unit 110, one of the first main plate 111 and the second main plate 112 is an upper plate 103, and the other is a lower plate 104, the upper plate 103 is electrically connected to a leg 126, and the first direction X1 is the direction from the substrate 105 to the inductor structure 106. It should be noted that, in order to clearly illustrate the first sub-capacitor area 135, the switch area 145 and the second sub-capacitor area 155, Fig.15 The capacitor structures in the first sub-capacitor region 135 and the second sub-capacitor region 155 are not drawn.

[0100] The layout relationship between the capacitor basic unit 110 and the first sub-capacitor region 135 and the second sub-capacitor region 155 is described in detail below.

[0101] In some cases, in conjunction with reference Fig.15 and Fig.16 , at least two capacitor basic units 110 arranged at intervals along the fourth direction Z are located on the first sub-capacitor area 135, and / or, at least two capacitor basic units 110 arranged at intervals along the fourth direction Z are located on the second sub-capacitor area 155, and in two adjacent capacitor basic units 110 along the fourth direction Z, one of the two adjacent first main plates 111 is the upper plate 103, and the other is the lower plate 104. In other words, at least two capacitor basic units 110 are arranged at intervals along the fourth direction Z in at least one of the first sub-capacitor area 135 and the second sub-capacitor area 155.

[0102] It should be noted that Fig.16In the example, two capacitor basic units 110 located on the first sub-capacitor region 135 are arranged at intervals along the fourth direction Z, and two capacitor basic units 110 located on the second sub-capacitor region 155 are arranged at intervals along the fourth direction Z. In practical applications, there is no limitation on the number of capacitor basic units located on the first sub-capacitor region or the second sub-capacitor region and arranged at intervals along the fourth direction, for example, both can be 3, 4, 5, 6 or 7, or only one capacitor basic unit is arranged along the fourth direction on one of the first sub-capacitor region and the second sub-capacitor region, and at least two capacitor basic units arranged at intervals on the other are arranged along the fourth direction.

[0103] In other cases, continue to refer to Fig.16 At least two capacitor basic units 110 arranged at intervals along the third direction Y are located on the first sub-capacitor area 135, and / or at least two capacitor basic units 110 arranged at intervals along the third direction Y are located on the second sub-capacitor area 155, and in two adjacent capacitor basic units 110 along the third direction Y, one of the two adjacent first main plates 111 is the upper plate 103, and the other is the lower plate 104.

[0104] It should be noted that Fig.16 In the example, six capacitor basic units 110 located on the first sub-capacitor region 135 are arranged at intervals along the third direction Y, and six capacitor basic units 110 located on the second sub-capacitor region 155 are arranged at intervals along the third direction Y. In practical applications, there is no limitation on the number of capacitor basic units located on the first sub-capacitor region or the second sub-capacitor region and arranged at intervals along the third direction, for example, both can be 3, 4, 5, 7 or 8, or only one capacitor basic unit is arranged along the third direction on one of the first sub-capacitor region and the second sub-capacitor region, and at least two capacitor basic units arranged at intervals on the other are arranged along the third direction.

[0105] In addition, the same capacitor structure 100 may include both of the above situations. In other words, whether it is the first sub-capacitor region 135 or the second sub-capacitor region 155, a plurality of capacitor basic units 110 spaced apart along the fourth direction Z and a plurality of capacitor basic units 110 spaced apart along the third direction Y may be provided. Moreover, whether it is located in the first sub-capacitor region 135 or the second sub-capacitor region 155, and whether it is two adjacent capacitor basic units 110 along the fourth direction Z or the third direction Y, one of the two adjacent first main plates 111 is the upper plate 103, and the other is the lower plate 104.

[0106] In each of the above cases, refer to Fig.16 and Fig.17The semiconductor structure may further include: a switch device 108, located on the switch area 145, and the switch device 108 is used to selectively connect the capacitor basic unit 110 located on the first sub-capacitor area 135 and the capacitor basic unit 110 located on the second sub-capacitor area 155. In this way, it is beneficial to adjust the number of capacitor basic units 110 in the capacitor structure 100 that actually work with the inductor structure 106 by means of the on or off function of the switch device 108, thereby adjusting the capacitance value of the capacitor structure 100, so that the semiconductor structure including the capacitor structure 100 can adapt to more application scenarios.

[0107] In some examples, in conjunction with reference Fig.15 and Fig.17 , at least two capacitor basic units 110 arranged at intervals along the fourth direction Z are located on the first sub-capacitor area 135, and at least two capacitor basic units 110 arranged at intervals along the fourth direction Z are located on the second sub-capacitor area 155, in two adjacent capacitor basic units 110 along the fourth direction Z, one of the two adjacent first main plates 111 is an upper plate 103, and the other is a lower plate 104; the lower plates 104 of at least two capacitor basic units 110 located on the first sub-capacitor area 135 and arranged along the fourth direction Z are electrically connected to form a first bus 114, and, located at the second sub-capacitor area 155 The lower plates 104 of at least two capacitor basic units 110 on the second sub-capacitor region 155 and arranged along the fourth direction Z are electrically connected to form a second bus 124, and the switching device 108 is used to optionally connect the first bus 114 and the second bus 124. One of the two legs 126 of the inductor structure 106 is electrically connected to the upper plates 103 of at least two capacitor basic units 110 located on the first sub-capacitor region 135 and arranged along the fourth direction Z, and the other is electrically connected to the upper plates 103 of at least two capacitor basic units 110 located on the second sub-capacitor region 155 and arranged along the fourth direction Z.

[0108] In other words, the upper plates 103 of at least two capacitor basic units 110 located on the first sub-capacitor area 135 and arranged along the fourth direction Z, and the upper plates 103 of at least two capacitor basic units 110 located on the second sub-capacitor area 155 and arranged along the fourth direction Z are respectively electrically connected to the two legs 126 of the inductor structure 106.

[0109] It is worth emphasizing that Fig.16 Only four capacitor basic units 110 (see FIG. 1 ) that are directly opposite to one leg 126 of the inductor structure 106 along the first direction X1 are shown. Fig.15 ). Moreover, combined with reference Fig.15 and Fig.16Among the four capacitor basic units 110 directly facing a leg 126 of the inductor structure 106 along the first direction X1, the upper plates 103 of two capacitor basic units 110 located on one of the first sub-capacitor area 135 and the second sub-capacitor area 155 are electrically connected to the leg 126, for example, the electrical connection between the upper plates 103 of the above two capacitor basic units 110 and the leg 126 is achieved by means of the third conductive through-hole 107. Different from this, the upper plates 103 of the two capacitor basic units 110 located on the other of the first sub-capacitor area 135 and the second sub-capacitor area 155 are electrically insulated from the leg 126 and are electrically connected to the other leg 126 of the inductor structure 106.

[0110] It is worth noting that the lower plates 104 of at least two capacitor basic units 110 arranged along the fourth direction Z on the first sub-capacitor region 135 are electrically connected to form a first bus 114, and the lower plates 104 of at least two capacitor basic units 110 arranged along the fourth direction Z on the second sub-capacitor region 155 can be integrally formed to form a second bus 124. In this way, it is not only beneficial to manage multiple capacitor basic units 110 by means of the first bus 114 or the second bus 124, but also beneficial to control the number of capacitor basic units 110 actually working with the inductor structure 106 by means of the switch device 108. For example, when the switch device 108 is turned on, the at least two capacitor basic units 110 arranged along the fourth direction Z on the first sub-capacitor region 135 and the at least two capacitor basic units 110 arranged along the fourth direction Z on the second sub-capacitor region 155, which are respectively connected between the two legs 126 of the inductor structure 106, are in a working state.

[0111] It should be noted that, in order to clearly illustrate the differences between adjacent capacitor basic units 110, Fig.16 In the figure, both the first bus 114 and the second bus 124 are drawn in perspective.

[0112] In one example, continue to refer to Fig.16 At least two basic capacitor units 110 are arranged along the third direction Y in the first sub-capacitor area 135 and the second sub-capacitor area 155. Based on this, the number of switch devices 108 can be multiple, and the switch devices 108 can correspond to the number of basic capacitor units 110 arranged along the third direction Y. In other words, multiple switch devices 108 are also arranged along the third direction Y, and one switch device 108 can be optionally connected to two lower plates 104 respectively located in the first sub-capacitor area 135 and the second sub-capacitor area 155 along the fourth direction Z.

[0113] It is worth noting that when at least one switch device 108 is turned off, the overall capacitance of the capacitor structure 100 between the two legs 126 electrically connected to the inductor structure 106 can be reduced, and when at least one switch device 108 is turned on, the overall capacitance of the capacitor structure 100 between the two legs 126 electrically connected to the inductor structure 106 can be increased. In addition, the switch device 108 can be implemented by one or more transistors known in the art.

[0114] In addition, based on Figures 1 to 13 The design of the capacitor basic unit 110 is to improve the capacitance value of the capacitor structure 100, so that a plurality of capacitor basic units 110 can be arranged at intervals on the first sub-capacitor area 135, or a plurality of capacitor basic units 110 can be arranged at intervals on the second sub-capacitor area 155, so as to increase the length of the capacitor structure 100 in the third direction Y without increasing the width of the capacitor structure 100 in the fourth direction Z, so that the length of the capacitor structure 100 in the third direction Y is more matched with the length of the main body 116 in the inductor structure 106 in the third direction Y, so as to achieve the effect of fully utilizing the layout space of the area where the leg 126 of the inductor structure 106 is located, so as to make full use of the routing resources in the semiconductor structure and improve the integration of the semiconductor structure.

[0115] In some embodiments, in conjunction with reference Figure 6 , Figure 7 , Fig.12 , Fig.14 and Fig.15 A first plate structure 101 and a second plate structure 102 facing each other along a first direction X1 constitute a capacitor basic unit 110, and the first direction X1 is the direction from the substrate 105 to the inductor structure 106; in the capacitor basic unit 110 facing the leg 126 along the first direction X1, the first extension portion 121 is a ring structure 121b with a break; in the capacitor basic unit 110 not facing the leg 126 along the first direction X1, the first extension portion 121 is a closed ring structure 121a or a ring structure 121b with a break.

[0116] It is worth noting that the first extension 121 is a ring-shaped structure 121b with a break, which is conducive to reducing the magnetic field generated by the induced current of the ring structure on the surface of the first extension 121, thereby reducing the impact of the eddy current effect on other adjacent electrical devices (for example: inductor structure). Moreover, the part of the capacitor structure 100 that is closest to the inductor structure 106 is the capacitor basic unit 110 that is directly opposite to the leg 126. Based on this, the first extension 121 in the capacitor basic unit 110 that is directly opposite to the leg 126 is designed to be a ring-shaped structure 121b with a break, which is conducive to specifically avoiding the first extension 121 from forming a closed ring structure, thereby reducing the magnetic field generated by the induced current on the surface of the capacitor structure 100, and reducing the impact of the eddy current effect on the adjacent inductor structure 106. In addition, at least a portion of the first extension portions 121 in the capacitor basic unit 110 that are not directly opposite to the leg portion 126 are designed to be a ring structure 121b with a break, which is beneficial to further reduce the magnetic field generated by the induced current on the surface of the capacitor structure 100, and further reduce the impact of the eddy current effect on the adjacent inductor structure 106, and the remaining portion of the first extension portions 121 can also be a closed ring structure 121a.

[0117] It can be understood by those skilled in the art that the above-mentioned embodiments are specific embodiments of the present application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present application. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application, so the protection scope of the embodiments of the present application shall be based on the scope defined in the claims.

Claims

1. A capacitor structure, characterized in that: include: At least one first electrode plate structure, the first electrode plate structure comprising a first main electrode plate and at least two first extensions arranged in sequence along a first direction, and a plurality of first conductive through holes; the first conductive through holes connect the first main electrode plate and the first extension closest to the first main electrode plate, or connect two adjacent first extensions; At least one second electrode plate structure; the second electrode plate structure comprises a second main electrode plate and at least two second extensions arranged in sequence along a second direction, and a plurality of second conductive through holes; the second conductive through hole connects the second main electrode plate and the second extension closest to the second main electrode plate, or connects two adjacent second extensions, and the first direction is opposite to the second direction; Wherein, the second extension portion has at least four side walls extending along the first direction, and the first extension portion at least surrounds two side walls of the second extension portion; A first electrode plate structure and a second electrode plate structure facing each other along the first direction constitute a basic capacitor unit, in which one of the first main electrode plate and the second main electrode plate is an upper electrode plate and the other is a lower electrode plate, and the polarity of the upper electrode plate is different from the polarity of the lower electrode plate; The plurality of capacitor basic units are arranged at intervals along the third direction and / or arranged at intervals along the fourth direction, and the first direction, the third direction and the fourth direction intersect each other; Among them, in two adjacent capacitor basic units along the third direction, one of the two adjacent first main pole plates is the upper pole plate, and the other is the lower pole plate; and / or, in two adjacent capacitor basic units along the fourth direction, one of the two adjacent first main pole plates is the upper pole plate, and the other is the lower pole plate.

2. The capacitor structure according to claim 1, characterized in that: The first extension portion and the second extension portion correspond to each other one by one, and a first extension portion and a second extension portion are arranged in the same layer.

3. The capacitor structure according to claim 1, characterized in that: At least part of the first conductive vias located in the same layer are distributed at equal intervals, and / or at least part of the first conductive vias located in different layers are directly opposite to each other along the first direction; At least part of the second conductive vias in the same layer are distributed at equal intervals, and / or at least part of the second conductive vias in different layers are directly opposite to each other along the first direction.

4. The capacitor structure according to claim 1, characterized in that: The first extension portion is a closed annular structure or an annular structure with a break.

5. A semiconductor structure, characterized in that: include: A substrate having a main inductance region and a capacitance region adjacent to each other along a fourth direction; The capacitor structure according to any one of claims 1 to 4, wherein the capacitor structure is located on the capacitor region; An inductor structure, the inductor structure comprising a main body and two legs respectively connected to two ends of the main body, the main body is located on the main inductor region, and the legs are located on the capacitor region; Wherein, the capacitor structure is located between the substrate and the leg portion, and the fourth direction is the extension direction of the leg portion; A plurality of third conductive through holes are provided, wherein the third conductive through holes connect the first main pole plate and at least one of the legs, or connect the second main pole plate and at least one of the legs.

6. The semiconductor structure according to claim 5, characterized in that: A first electrode plate structure and a second electrode plate structure facing each other along a first direction constitute a basic capacitor unit, in the same basic capacitor unit, one of the first main electrode plate and the second main electrode plate is an upper electrode plate, and the other is a lower electrode plate, the upper electrode plate is electrically connected to one of the legs, and the first direction is the direction in which the substrate points to the inductor structure; At least two of the capacitor basic units arranged at intervals along the fourth direction are located on the capacitor area, and in two adjacent capacitor basic units along the fourth direction, one of the two adjacent first main plates is the upper plate, and the other is the lower plate; and / or, At least two of the capacitor basic units arranged at intervals along the third direction are located on the capacitor area, and in two adjacent capacitor basic units along the third direction, one of the two adjacent first main pole plates is the upper pole plate, and the other is the lower pole plate, and the third direction intersects with the fourth direction.

7. The semiconductor structure according to claim 5, characterized in that: The capacitor region includes a first sub-capacitor region, a switch region, and a second sub-capacitor region sequentially arranged along the fourth direction; a first plate structure and a second plate structure facing each other along the first direction constitute a capacitor basic unit, in the same capacitor basic unit, one of the first main plate and the second main plate is an upper plate, and the other is a lower plate, the upper plate is electrically connected to one of the legs, and the first direction is the direction in which the substrate points to the inductor structure; At least two of the capacitor basic units arranged at intervals along the fourth direction are located on the first sub-capacitor region, and / or, at least two of the capacitor basic units arranged at intervals along the fourth direction are located on the second sub-capacitor region, and in two adjacent capacitor basic units along the fourth direction, one of the two adjacent first main plates is the upper plate, and the other is the lower plate; and / or, At least two of the capacitor basic units arranged at intervals along the third direction are located on the first sub-capacitor region, and / or at least two of the capacitor basic units arranged at intervals along the third direction are located on the second sub-capacitor region, and in two adjacent capacitor basic units along the third direction, one of the two adjacent first main plates is the upper plate, and the other is the lower plate; The semiconductor structure further includes: a switch device located on the switch region, wherein the switch device is used to connect the capacitor basic unit located on the first sub-capacitor region and the capacitor basic unit located on the second sub-capacitor region.

8. The semiconductor structure according to claim 7, characterized in that: At least two of the capacitor basic units arranged at intervals along the fourth direction are located on the first sub-capacitor region, and at least two of the capacitor basic units arranged at intervals along the fourth direction are located on the second sub-capacitor region, and in two adjacent capacitor basic units along the fourth direction, one of the two adjacent first main plates is the upper plate, and the other is the lower plate; The lower plates of at least two of the capacitor basic units located on the first sub-capacitor region and arranged along the fourth direction are electrically connected to form a first bus, and the lower plates of at least two of the capacitor basic units located on the second sub-capacitor region and arranged along the fourth direction are electrically connected to form a second bus, and the switch device is used to connect the first bus and the second bus; One of the two legs of the inductor structure is electrically connected to the upper plates of at least two of the capacitor basic units located on the first sub-capacitor area and arranged along the fourth direction, and the other is electrically connected to the upper plates of at least two of the capacitor basic units located on the second sub-capacitor area and arranged along the fourth direction.

9. The semiconductor structure according to claim 5, characterized in that: A first plate structure and a second plate structure facing each other along a first direction form a basic capacitor unit, and the first direction is the direction from the substrate to the inductor structure; In the capacitor basic unit that is directly opposite to the leg along the first direction, the first extension portion is a ring structure with a break; in the capacitor basic unit that is not directly opposite to the leg along the first direction, the first extension portion is a closed ring structure or a ring structure with a break.

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