Semiconductor device

Abstract

The purpose of the present disclosure is to improve conduction loss in a semiconductor device provided with a first gate electrode and a second gate electrode. A semiconductor device (101) is provided with a gate electrode embedded in each of a plurality of first trenches via an insulating film. The gate electrode includes: a first gate electrode (12) electrically connected to the first gate pad (30); and a second gate electrode (15) electrically connected to the second gate pad (31). The charging period and the discharging period of the gate capacitance parasitic on the second gate electrode (15) are shorter than the charging period and the discharging period of the gate capacitance parasitic on the first gate electrode (12), respectively.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Patent document 1 discloses a semiconductor device having a first gate electrode and a second gate electrode disposed on a semiconductor substrate. In the semiconductor device described in Patent document 1, the second gate electrode is turned off earlier than the first gate electrode when turned off, and the second gate electrode is turned on later than the first gate electrode when turned on. Thus, switching loss is reduced.

[0003] Patent Document 1: Japanese Patent No. 5742672

[0004] In the semiconductor device described in Patent Document 1, it is not considered to charge and discharge the gate capacitance parasitic on the second gate electrode at a high speed. Therefore, there is a problem that the period of low on-voltage is short and the conduction loss is large. Specifically, since the second gate electrode becomes on, an n-type accumulation layer is formed around the second gate electrode. Since the accumulation layer becomes a hole barrier, the hole density in the drift layer can be increased, thereby reducing the on-voltage. When the charge and discharge time of the second gate electrode is long, there is a problem that the period of the second gate electrode becoming on becomes shorter, and the conduction loss worsens. Summary of the invention

[0005] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to improve conduction loss in a semiconductor device including a first gate electrode and a second gate electrode.

[0006] The semiconductor device disclosed in the present invention comprises: a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; an upper surface electrode formed on the first main surface of the semiconductor substrate; a lower surface electrode formed on the second main surface of the semiconductor substrate; a first gate pad; and a second gate pad controlled independently of the first gate pad. The semiconductor substrate comprises: a drift layer of the first conductivity type; a base layer of the second conductivity type formed on the first main surface side of the drift layer; a source layer of the first conductivity type formed on the first main surface side of the base layer; and a plurality of first trenches penetrating from the source layer through the base layer and reaching the drift layer. The semiconductor device comprises a gate electrode buried in each of the plurality of first trenches via an insulating film. The gate electrode comprises: a first gate electrode electrically connected to the first gate pad; and a second gate electrode electrically connected to the second gate pad. The charging period and the discharging period of the gate capacitance parasitic on the second gate electrode are respectively shorter than the charging period and the discharging period of the gate capacitance parasitic on the first gate electrode.

[0007] According to the semiconductor device disclosed in the present invention, the charge and discharge period of the gate capacitance parasitic on the second gate electrode is shorter than the charge and discharge period of the gate capacitance parasitic on the first gate electrode. Therefore, the conduction period of the second gate electrode can be extended. As a result, the period of low conduction voltage becomes longer, and the conduction loss is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a top view of the semiconductor device according to the first embodiment.

[0009] Figure 2 It is along Figure 1 A cross-sectional view of the semiconductor device according to the first embodiment taken along line AA.

[0010] Figure 3 This is a diagram showing the driving timing of the semiconductor device.

[0011] Figure 4 This is a cross-sectional view of a semiconductor device according to a first variation of the first embodiment.

[0012] Figure 5 This is a cross-sectional view of a semiconductor device according to a second variation of the first embodiment.

[0013] Figure 6 This is a cross-sectional view of a semiconductor device according to a third variation of the first embodiment.

[0014] Figure 7 This is a cross-sectional view of a semiconductor device according to the second embodiment.

[0015] Figure 8 This is a cross-sectional view of a semiconductor device according to a third embodiment.

[0016] Fig. 9 This is a cross-sectional view of a semiconductor device according to a first variation of the third embodiment.

[0017] Fig.10 It is a cross-sectional view of a semiconductor device according to a second variation of the third embodiment.

[0018] Fig.11 This is a cross-sectional view of a semiconductor device according to a third variation of the third embodiment.

[0019] Fig.12 This is a cross-sectional view of a semiconductor device according to a fourth variation of the third embodiment.

[0020] Fig.13 This is a cross-sectional view of a semiconductor device according to a fifth variation of the third embodiment.

[0021] Fig.14This is a cross-sectional view of a semiconductor device according to a sixth variation of the third embodiment.

[0022] Fig.15 This is a cross-sectional view of a semiconductor device according to a fourth embodiment.

[0023] Fig.16 This is a cross-sectional view of a semiconductor device according to a first variation of the fourth embodiment.

[0024] Fig.17 It is a top view of the semiconductor device involved in Embodiment 5.

[0025] Fig.18 It is a top view of a semiconductor device according to a first variation of the fifth embodiment.

[0026] Fig.19 It is a top view of the semiconductor device involved in Embodiment 6.

[0027] Fig. 20 It is along Fig.16 A cross-sectional view of the semiconductor device according to Embodiment 6 taken along line BB.

[0028] Fig.21 This is a diagram showing the driving timing of the semiconductor device according to the sixth embodiment.

[0029] Fig. 22 This is a cross-sectional view of a semiconductor device according to a first variation of the sixth embodiment.

[0030] Fig.23 This is a cross-sectional view of a semiconductor device according to a seventh embodiment.

[0031] Fig.24 This is a diagram showing the driving timing of the semiconductor device according to the seventh embodiment.

[0032] Fig.25 This is a cross-sectional view of a semiconductor device according to a first variation of the seventh embodiment.

[0033] Description of Reference Numerals

[0034] 1...emitter electrode; 2...interlayer insulating film; 3...n+ type source layer; 4...p type base layer; 5...n type carrier storage layer; 6...n- type drift layer; 7...n type buffer layer; 8...p type collector layer; 9...collector electrode; 10, 40...trench; 11...first gate insulating film; 12...first gate electrode; 13...boundary insulating film; 14...second gate insulating film; 15...second gate electrode; 16...insulating film; 17...trench emitter electrode; 18...insulating material; 19...third gate insulating film; 20...third gate electrode; 21... .n-type cathode layer; 30...the first gate pad; 31...the second gate pad; 32...the third gate pad; 50...the first gate wiring; 51...the second gate wiring; 52...the third gate wiring; 60...the semiconductor substrate; 101, 101A, 101B, 101C, 102, 103, 103A, 103B, 103C, 104, 104A, 105, 106, 106A, 107, 107A...the semiconductor device; Cgc...the collector capacitance; Cge...the emitter capacitance; IGBT...reverse conduction; S1...the first main surface; S2...the second main surface. DETAILED DESCRIPTION

[0035] In the following description, n and p represent the conductivity type of the semiconductor. Although the first conductivity type is set as n-type and the second conductivity type is set as p-type in the present disclosure, the first conductivity type may be set as p-type and the second conductivity type may be set as n-type. In addition, n- indicates that the impurity concentration is lower than n, and n+ indicates that the impurity concentration is higher than n. Similarly, p- indicates that the impurity concentration is lower than p, and p+ indicates that the impurity concentration is higher than p.

[0036] <A. Implementation method 1>

[0037] <A-1. Structure>

[0038] Figure 1 is a top view of the semiconductor device 101 according to the first embodiment. Figure 1 In FIG. 1 , the interlayer insulating film 2 and the emitter electrode 1 are omitted from illustration. Figure 2 It is along Figure 1 1 is a cross-sectional view of the semiconductor device 101 taken along line AA of FIG. The semiconductor device 101 configures an insulated gate bipolar transistor (IGBT).

[0039] like Figure 2As shown, the semiconductor device 101 includes a semiconductor substrate 60. The semiconductor substrate 60 includes a first main surface S1 and a second main surface S2 which is a main surface opposite to the first main surface S1. The semiconductor substrate 60 is configured to include an n+ type source layer 3, a p-type base layer 4, an n-type carrier storage layer 5, an n-type drift layer 6, an n-type buffer layer 7, and a p-type collector layer 8. The n-type carrier storage layer 5 is provided on the first main surface S1 side of the n-type drift layer 6. The p-type base layer 4 is provided on the first main surface S1 side of the n-type carrier storage layer 5. The n+ type source layer 3 is provided on the first main surface S1 side of the p-type base layer 4. The n-type buffer layer 7 is provided on the second main surface S2 side of the n-type drift layer 6. The p-type collector layer 8 is provided on the second main surface S2 side of the n-type buffer layer 7.

[0040] A plurality of trenches 10 are formed from the upper surface of the n+ type source layer 3 through the n+ type source layer 3, the p type base layer 4 and the n type carrier storage layer 5 and reaching the n- type drift layer 6. Figure 1 As shown, these multiple grooves 10 extend in the same direction. Figure 1 Four grooves 10 are shown in FIG. 1 , but the number of the grooves 10 is not limited thereto.

[0041] Although in Figure 2 Although not shown in the figure, a p+ type contact layer is also provided on the p-type base layer 4. The n+ type source layer 3 and the p+ type contact layer are alternately provided along the extension direction of each trench 10. The n+ type source layer 3 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity. The concentration of the n-type impurity in the n+ type source layer 3 is 1.0×10 17 / cm 3 Above and 1.0×10 20 / cm 3 The p+ type contact layer is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity in the p+ type contact layer is 1.0×10 15 / cm 3 Above and 1.0×10 20 / cm 3 the following.

[0042] The n-type drift layer 6 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity. The concentration of the n-type impurity in the n-type drift layer 6 is 1.0×10 12 / cm 3 Above and 1.0×10 15 / cm 3 the following.

[0043] The n-type carrier storage layer 5 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity. The concentration of the n-type impurity in the n-type carrier storage layer 5 is 1.0×10 13 / cm3 Above and 1.0×10 17 / cm 3 However, in the semiconductor device 101, the n-type carrier accumulation layer 5 is not an essential structure, and the p-type base layer 4 may be directly provided on the n-type drift layer 6. The conduction loss when the current flows through the n-type carrier accumulation layer 5 is reduced. In this specification, the n-type carrier accumulation layer 5 and the n-type drift layer 6 are sometimes collectively referred to as a drift layer.

[0044] The p-type base layer 4 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity in the p-type base layer 4 is 1.0×10 12 / cm 3 Above and 1.0×10 19 / cm 3 Below. The p-type base layer 4 is in contact with the first gate insulating film 11 of the trench 10. An n+ type source layer 3 is provided on the first main surface S1 side of the p-type base layer 4 in contact with the first gate insulating film 11, and a p+ type contact layer is provided in the remaining area. The n+ type source layer 3 and the p+ type contact layer constitute the first main surface of the semiconductor substrate. The p+ type contact layer is a region where the concentration of p-type impurities is higher than that of the p-type base layer 4. In this specification, the p+ type contact layer and the p-type base layer 4 are sometimes collectively referred to as the p-type base layer.

[0045] The n-type buffer layer 7 is a semiconductor layer having a higher concentration of n-type impurities than the n-type drift layer 6. The n-type buffer layer 7 is provided to suppress punch-through caused by the depletion layer extending from the p-type base layer 4 to the second main surface S2 when the semiconductor device 101 is in the off state. The n-type impurities in the n-type buffer layer 7 are, for example, at least one of phosphorus (P) and protons (H+). The concentration of the n-type impurities in the n-type buffer layer 7 is 1.0×10 12 / cm 3 Above and 1.0×10 18 / cm 3 In addition, the n-type buffer layer 7 is not an essential structure in the semiconductor device 101, and the p-type collector layer 8 may be directly provided on the second main surface S2 side of the n-type drift layer 6. In this specification, the n-type buffer layer 7 and the n-type drift layer 6 are sometimes collectively referred to as a drift layer.

[0046] A p-type collector layer 8 is provided on the second main surface S2 side of the n-type buffer layer 7. That is, the p-type collector layer 8 is provided between the n-type drift layer 6 and the second main surface S2. The p-type collector layer 8 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity in the p-type collector layer 8 is 1.0×10 16 / cm 3 Above and 1.0×1020 / cm 3 Next, the p-type collector layer 8 constitutes the second main surface of the semiconductor substrate.

[0047] The first gate electrode 12 is embedded in a portion of the plurality of trenches 10 via the first gate insulating film 11. The first gate insulating film 11 is disposed on the inner wall of the trenches 10. The second gate electrode 15 is embedded in the remaining trenches 10 via the second gate insulating film 14. The second gate insulating film 14 is disposed on the inner wall of the trenches 10. Figure 1 As shown, the first gate electrode 12 is electrically connected to the first gate pad 30 via the first gate wiring 50. The second gate electrode 15 is electrically connected to the second gate pad 31 via the second gate wiring 51. The turning on and off timings of the first gate pad 30 and the second gate pad 31 are independently controlled by a control unit (not shown).

[0048] When a gate driving voltage is applied to the first gate electrode 12 through the first gate pad 30, a channel is formed in the p-type base layer 4 in contact with the first gate insulating film 11, and an n-type accumulation layer is formed in the n-type carrier accumulation layer 5 and the n-type drift layer 6 in contact with the first gate insulating film 11. Similarly, when a gate driving voltage is applied to the second gate electrode 15 through the second gate pad 31, a channel is formed in the p-type base layer 4 in contact with the second gate insulating film 14, and an n-type accumulation layer is formed in the n-type carrier accumulation layer 5 and the n-type drift layer 6 in contact with the second gate insulating film 14.

[0049] The first gate electrode 12 and the second gate electrode 15 are formed by depositing polysilicon doped with n-type or p-type impurities. The impurity concentration of the polysilicon in the first gate electrode 12 is 1.0×10 17 / cm 3 Above and 1.0×10 22 / cm 3 The impurity concentration of the polysilicon in the second gate electrode 15 is higher than the impurity concentration of the polysilicon in the first gate electrode 12. As a result, the semiconductor device 101 has a characteristic that the resistivity of the second gate electrode 15 is lower than the resistivity of the first gate electrode 12. The impurity concentration of the polysilicon in the second gate electrode 15 is, for example, 1.0×10 19 / cm 3 Above and 1.0×10 22 / cm 3 Below, preferably 1.0×10 20 / cm 3 Above and 1.0×10 22 / cm 3 the following.

[0050] Although in Figure 1, two first gate electrodes 12 and two second gate electrodes 15 are shown, but the ratio of the first gate electrode 12 to the second gate electrode 15 is not limited to Figure 1 In addition, the first gate electrodes 12 and the second gate electrodes 15 may not be arranged alternately.

[0051] like Figure 2 As shown in FIG. 1 , an interlayer insulating film 2 is provided on the first gate electrode 12 and the second gate electrode 15. Figure 2 Although not shown in the figure, a barrier metal is formed on the area of ​​the first main surface S1 where the interlayer insulating film 2 is not provided, and on the interlayer insulating film 2. The barrier metal is, for example, a conductor containing titanium (Ti). The barrier metal is, for example, titanium nitride, or TiSi formed by alloying titanium or silicon (Si). The barrier metal is in ohmic contact with the n+ type source layer 3 and the p+ type contact layer, and is electrically connected to the n+ type source layer 3 and the p+ type contact layer.

[0052] An emitter electrode 1 as an upper surface electrode is provided on the barrier metal. The emitter electrode 1 is formed of, for example, an aluminum alloy such as an aluminum silicon alloy (Al-Si alloy). The emitter electrode 1 may also be an electrode composed of a multilayer metal film formed by forming a coating based on chemical plating or electrolytic plating on an aluminum alloy film. Here, the coating may be, for example, a nickel (Ni) coating. In the case where the emitter electrode 1 cannot be well embedded in a fine area such as between adjacent interlayer insulating films 2, tungsten having better embedding properties than the emitter electrode 1 may be arranged in the area, and the emitter electrode 1 may be provided on the tungsten.

[0053] In addition, the emitter electrode 1 may be directly provided on the n+ type source layer 3 and the p+ type contact layer without providing a barrier metal. In addition, the barrier metal may be provided only on the n-type semiconductor layer such as the n+ type source layer 3. In this specification, the barrier metal and the emitter electrode 1 are sometimes collectively referred to as the emitter electrode.

[0054] A collector electrode 9 as a lower surface electrode is provided on the second main surface S2 side of the p-type collector layer 8. The collector electrode 9 may also be composed of an aluminum alloy, or an aluminum alloy and a plated film, similarly to the emitter electrode 1. In addition, the collector electrode 9 may also have a structure different from that of the emitter electrode 1. The collector electrode 9 is in ohmic contact with the p-type collector layer 8 and is electrically connected to the p-type collector layer 8.

[0055] <A-2. Manufacturing process>

[0056] The manufacturing method of the semiconductor device 101 involved in the first embodiment is described. First, a semiconductor substrate 60 constituting the n-type drift layer 6 is prepared. The semiconductor substrate 60 is, for example, an FZ wafer produced by the FZ (Floating Zone) method or an MCZ wafer produced by the MCZ (Magnetic applied CZochralski) method, and may be an n-type wafer containing n-type impurities. The semiconductor substrate 60 is, for example, a Si substrate. The concentration of the n-type impurities contained in the semiconductor substrate 60 is appropriately selected according to the withstand voltage of the semiconductor device 101 to be manufactured. For example, in the case of manufacturing a semiconductor device 101 with a withstand voltage of 1200V, the concentration of the n-type impurities is adjusted in such a way that the resistivity of the n-type drift layer 6 constituting the semiconductor substrate 60 becomes 40Ω·cm or more and 120Ω·cm or less. In the process of preparing the semiconductor substrate 60, the semiconductor substrate 60 as a whole becomes the n-type drift layer 6. P-type or n-type impurity ions are injected from the first main surface S1 side or the second main surface S2 side of such a semiconductor substrate 60, and the impurity ions are diffused into the semiconductor substrate 60 by subsequent heat treatment, thereby forming a p-type or n-type semiconductor layer and manufacturing the semiconductor device 101.

[0057] Next, n-type impurities such as phosphorus (P) are implanted from the first main surface S1 side of the semiconductor substrate 60 to form an n-type carrier accumulation layer 5 on the first main surface S1 side of the n-type drift layer 6. In addition, p-type impurities such as boron (B) are implanted from the first main surface S1 side of the semiconductor substrate 60 to form a p-type base layer 4 on the first main surface S1 side of the n-type carrier accumulation layer 5. The n-type carrier accumulation layer 5 and the p-type base layer 4 are formed by implanting impurity ions into the semiconductor substrate and then diffusing the impurity ions by heat treatment. The n-type impurities and the p-type impurities are selectively formed on the first main surface S1 side of the semiconductor substrate 60 because they are ion implanted after performing masking on the first main surface S1 of the semiconductor substrate 60. The so-called masking is a process of forming a mask on the semiconductor substrate 60 by applying a resist on the semiconductor substrate 60 and forming an opening in a predetermined area of ​​the resist using a photolithography technique. Ion implantation or etching is performed on a predetermined region of the semiconductor substrate 60 through the opening of the mask.

[0058] Next, after masking is performed on the first main surface S1 of the semiconductor substrate 60, n-type impurities are selectively injected into the first main surface side of the p-type base layer 4 to form an n+ type source layer 3. The injected n-type impurities are, for example, arsenic (As) or phosphorus (P). In addition, after masking is performed on the first main surface S1 of the semiconductor substrate 60, p-type impurities are selectively injected into the first main surface S1 side of the p-type base layer 4 to form a p+ type contact layer. The injected p-type impurities are, for example, boron (B) or aluminum (Al).

[0059] Next, a plurality of trenches 10 are formed from the first main surface S1 side of the semiconductor substrate 60 through the p-type base layer 4 and reaching the n-type drift layer 6. The sidewalls of the plurality of trenches 10 penetrating the n+ type source layer 3 constitute a part of the n+ type source layer 3. Each trench 10 can be formed by depositing SiO on the semiconductor substrate 60. 2 After the oxide film is formed, masking is performed, and then etching is performed to form an opening in the portion of the oxide film where the trench 10 is to be formed, and the semiconductor substrate 60 is etched using the oxide film with the opening as a mask.

[0060] Next, by heating the semiconductor substrate 60 in an atmosphere containing oxygen, a first gate insulating film 11 is formed on the inner wall of the trench 10 and the first main surface S1 of the semiconductor substrate 60. The first gate insulating film 11 formed on the first main surface S1 of the semiconductor substrate 60 is removed in a later step.

[0061] Next, polysilicon doped with n-type or p-type impurities is deposited in the plurality of trenches 10 by using a method such as CVD (chemical vapor deposition) to form the first gate electrode 12 .

[0062] Next, a mask is formed by masking to open the trenches 10 to be filled with the second gate electrode 15, and the first gate electrode 12 in the trenches to be filled with the second gate electrode 15 is etched. Thereafter, the first gate insulating film 11 in the trenches to be filled with the second gate electrode 15 is removed.

[0063] Next, the semiconductor substrate 60 is heated in an atmosphere containing oxygen to form a second gate insulating film 14 on the inner wall of the trench to be filled with the second gate electrode 15 and on the first main surface S1 of the semiconductor substrate 60. The second gate insulating film 14 formed on the first main surface S1 of the semiconductor substrate is removed in a later step.

[0064] Next, polysilicon doped with n-type or p-type impurities is deposited in the trench to be filled with the second gate electrode 15 by using a method such as CVD (chemical vapor deposition), thereby forming the second gate electrode 15 .

[0065] Next, the interlayer insulating film 2 is formed on the trench 10. Thereafter, the first gate insulating film 11 and the second gate insulating film 14 formed on the first main surface S1 of the semiconductor substrate 60 are removed. The interlayer insulating film 2 is, for example, SiO 2 Then, contact holes are formed in the deposited interlayer insulating film 2 by masking. The contact holes are formed on the n+ type source layer 3 and the p+ type contact layer.

[0066] Next, a barrier metal is formed on the first main surface S1 of the semiconductor substrate 60 and the interlayer insulating film 2, and the emitter electrode 1 is further formed on the barrier metal. The barrier metal is formed by forming a film of titanium nitride by PVD (physical vapor deposition) or CVD.

[0067] The emitter electrode 1 is formed, for example, by depositing an aluminum silicon alloy (Al-Si alloy) on a barrier metal by PVD such as sputtering or evaporation. In addition, a nickel alloy (Ni alloy) may be further formed on the aluminum silicon alloy by chemical plating or electrolytic plating, and these two alloy layers may be used as the emitter electrode 1. In this way, since a thick metal film can be easily formed by plating as the emitter electrode 1, the thermal capacitance of the emitter electrode 1 can be increased, thereby improving the heat resistance. In addition, the electroplating process for forming the above-mentioned nickel alloy may also be implemented after the processing of the second main surface S2 side of the semiconductor substrate 60.

[0068] Next, the second main surface S2 side of the semiconductor substrate 60 is ground to thin the semiconductor substrate 60 to a desired thickness. The thickness of the ground semiconductor substrate 60 is, for example, 80 μm or more and 200 μm or less.

[0069] Next, n-type impurities are implanted from the second main surface S2 side of the semiconductor substrate 60 to form an n-type buffer layer 7 . Also, p-type impurities are implanted from the second main surface S2 side of the semiconductor substrate 60 to form a p-type collector layer 8 .

[0070] The n-type buffer layer 7 is formed by, for example, injecting one or both of phosphorus (P) ions and protons (H+). Protons can be injected into a deep position from the second main surface S2 of the semiconductor substrate 60 using relatively low acceleration energy. In addition, the injection depth of protons can be relatively easily changed by changing the acceleration energy. Therefore, when protons are injected multiple times while changing the acceleration energy, an n-type buffer layer 7 having a wider width in the thickness direction of the semiconductor substrate 60 can be formed compared to the case where it is formed by phosphorus.

[0071] In addition, compared with protons, phosphorus can increase the activation rate as an n-type impurity. Therefore, by forming the n-type buffer layer 7 with phosphorus, even if the semiconductor substrate 60 is thinned, it is possible to more reliably suppress the situation of depletion layer punch-through. In order to further thin the semiconductor substrate 60, it is preferred to form the n-type buffer layer 7 by injecting both protons and phosphorus. In this case, protons are injected into a deeper position from the second main surface S2 than phosphorus.

[0072] The p-type collector layer 8 is formed by, for example, implanting boron (B). After ion implantation from the second main surface S2 side of the semiconductor substrate 60, the second main surface S2 is irradiated with laser for laser annealing, thereby activating the implanted boron to form the p-type collector layer 8. At this time, phosphorus for the n-type buffer layer 7, which is implanted from the second main surface S2 of the semiconductor substrate 60 to a relatively shallow position, is also activated at the same time. On the other hand, since protons are activated at a relatively low annealing temperature of 350°C or more and 500°C or less, after the protons are implanted, in addition to the process for activating the protons, it is necessary to avoid the semiconductor substrate 60 as a whole becoming above 350°C. Through laser annealing, since only the vicinity of the second main surface S2 of the semiconductor substrate 60 can be made high temperature, it can be used to activate n-type impurities or p-type impurities other than protons after the protons are implanted.

[0073] Next, the collector electrode 9 is formed on the second main surface S2 of the semiconductor substrate 60. The collector electrode 9 may also be formed over the entire second main surface S2 of the semiconductor substrate 60. The collector electrode 9 is formed, for example, by depositing aluminum silicon alloy (Ai-Si alloy) or titanium (Ti) on the second main surface S2 of the semiconductor substrate 60 using PVD such as sputtering or evaporation. Alternatively, the collector electrode 9 may also be formed by stacking a plurality of metals such as aluminum silicon alloy, titanium, nickel or gold. In addition, on the metal film formed by PVD, a metal film may be further formed by chemical plating or electrolytic plating, and these two metal layers may become the collector electrode 9.

[0074] The semiconductor device 101 is manufactured through the above-described steps. A plurality of semiconductor devices 101 are manufactured in a matrix on one n-type wafer. Thereafter, the wafer is divided by laser dicing or blade dicing to obtain one semiconductor device 101 .

[0075] <A-3. Action>

[0076] Figure 3 1 is a diagram showing the driving timing of the semiconductor device 101. Figure 3 In FIG. 1 , Vg1 represents the applied voltage of the first gate pad 30 and the first gate electrode 12, and Vg2 represents the applied voltage of the second gate pad 31 and the second gate electrode 15. The second gate pad 31 is controlled by a control unit (not shown) to be turned on at a later time than the first gate pad 30 and turned off at a earlier time than the first gate pad 30. That is, after the first gate pad 30 is turned on, the second gate pad 31 is turned on, and after the second gate pad 31 is turned off, the first gate pad 30 is turned off. The period during which the turning off of the second gate pad 31 is delayed compared with the turning off of the first gate pad 30 is called a delay period. In addition, the period during which the turning on of the second gate pad 31 is earlier than the turning on of the first gate pad 30 is called an advance period.

[0077] In the semiconductor device 101, since the resistivity of the second gate electrode 15 is lower than that of the first gate electrode 12, the gate current drop in the second gate electrode 15 can be reduced. As a result, the charging and discharging of the gate capacitance parasitic on the second gate electrode 15 can be accelerated. Figure 3 As shown, the charging period and the discharging period of the gate capacitance parasitic on the second gate electrode 15 can be made shorter than the charging period and the discharging period of the gate capacitance parasitic on the first gate electrode 12, respectively. Accordingly, the on-period of the second gate electrode 15 becomes longer. Since the second gate electrode 15 becomes in the on-state, an n-type accumulation layer is formed around the second gate electrode 15. Since the accumulation layer becomes a hole barrier, the holes injected from the p-type collector layer 8 are not easily discharged from the emitter electrode 1, but are accumulated in the n-type drift layer 6. As a result, the conductivity modulation is promoted and the on-voltage is reduced.

[0078] <A-4. Modification>

[0079] Figure 4 is a cross-sectional view of a semiconductor device 101A according to a first variation of the first embodiment. Figure 1 The top view of the semiconductor device 101 is also shown. Figure 4 The cross-sectional view is along Figure 1 1. A cross-sectional view of the semiconductor device 101A cut along line AA of FIG. 1. In the semiconductor device 101A, although the n+ type source layer 3 is in contact with the first gate insulating film 11, it is not in contact with the second gate insulating film 14. The structure of the semiconductor device 101A other than the n+ type source layer 3 is the same as that of the semiconductor device 101.

[0080] Figure 5 is a cross-sectional view of a semiconductor device 101B according to a second variation of the first embodiment. Figure 1 The top view of the semiconductor device 101 is also shown. Figure 5 The cross-sectional view is along Figure 1 1 is a cross-sectional view of the semiconductor device 101B cut along the line AA of FIG. In the semiconductor device 101B, the trench emitter electrode 17 is buried in a portion of the trench 10 via the insulating film 16. That is, in the semiconductor device 101B, there are the trench 10 in which the first gate electrode 12 is buried, the trench 10 in which the second gate electrode 15 is buried, and the trench 10 in which the trench emitter electrode 17 is buried. The trench emitter electrode 17 is electrically connected to the emitter electrode 1.

[0081] In addition, if Figure 5As shown, in the semiconductor device 101B, the semiconductor region adjacent to the second gate insulating film 14 is insulated from the emitter electrode 1 by the interlayer insulating film 2 and is not electrically connected to the emitter electrode 1. The structure of the semiconductor device 101B is the same as that of the semiconductor device 101 except for these points.

[0082] Figure 6 is a cross-sectional view of a semiconductor device 101C according to a third variation of the first embodiment. Figure 1 The top view of the semiconductor device 101 is also shown. Figure 6 The cross-sectional view is along Figure 1 AA line is a cross-sectional view of the semiconductor device 101C.

[0083] The semiconductor device 101C forms a RC-IGBT (Reverse Conducting IGBT). In the semiconductor device 101C, an n-type cathode layer 21 is provided on the second main surface S2 side of the n-type buffer layer 7 in addition to the p-type collector layer 8. The structure of the semiconductor device 101C other than the n-type cathode layer 21 is the same as that of the semiconductor device 101.

[0084] According to the semiconductor device 101C, since electrons are injected by turning on the second gate electrode 15 for a short time before the recovery action of the diode, the holes in the n-type drift layer 6 can be reduced by recoupling, so the recovery loss can be reduced. In the case where the charge and discharge of the second gate electrode 15 are slow, the electron injection becomes excessive, and a snapback phenomenon occurs in which the current does not flow at a specified voltage. However, in this structure, the charge and discharge can be accelerated, so the electron injection amount when the second gate electrode 15 is turned on can be reduced, and the snapback phenomenon can be suppressed.

[0085] The semiconductor device 101 according to the first embodiment constitutes an IGBT. However, the semiconductor device 101 may also constitute a MOSFET (metal-oxide-semiconductor field-effect transistor) without the p-type collector layer 8. As an effect that contributes to the unipolar MOSFET, the second gate electrode 15 shares the gate capacitance parasitic on the first gate electrode 12, and the effective gate capacitance at the time of turning on can be reduced, thereby reducing the switching loss. In addition, since the charging and discharging of the second gate electrode 15 can be accelerated, the period during which the on-resistance is short can be extended, and the conduction loss can be reduced.

[0086] As the material of the second gate electrode 15, amorphous silicon may be used instead of polysilicon. Amorphous silicon can reduce surface unevenness compared to polysilicon. Therefore, by forming the second gate electrode 15 from amorphous silicon, the surface area of ​​the second gate electrode 15 in contact with the second gate insulating film 14 becomes smaller. As a result, the gate capacitance parasitic on the second gate electrode 15 becomes smaller, and the charging and discharging of the gate capacitance is accelerated, so that the period of low on-voltage becomes longer, and the conduction loss is improved.

[0087] In addition, as a material of the first gate electrode 12 , amorphous silicon may be used instead of polycrystalline silicon.

[0088] Metal may be used instead of polysilicon as the material of the second gate electrode 15. By forming the second gate electrode 15 from metal, the resistivity of the second gate electrode 15 becomes smaller. Therefore, the charging and discharging of the gate capacitance parasitic on the second gate electrode 15 is accelerated, the period of low on-voltage becomes longer, and the conduction loss is improved.

[0089] For the semiconductor substrate 60, SiC, GaN, Ga 2 O 3 The substrate made of wide bandgap semiconductors such as Si can be used instead of Si substrate. In this case, due to the difference in physical properties, the thickness of the gate oxide film can be made about half of that of Si, so the gate capacitance, which is inversely proportional to the thickness of the gate oxide film, is easier to be larger than that of Si. Therefore, the structure based on the present disclosure has a large effect of effectively reducing the gate capacitance, and the switching loss is reduced. In addition, due to the high speed of charging and discharging of the gate capacitance, the period of short on-resistance becomes longer, which can reduce the conduction loss.

[0090] <B. Implementation method 2>

[0091] Figure 7 is a cross-sectional view of a semiconductor device 102 according to Embodiment 2. Figure 1 The top view of the semiconductor device 101 is also shown. Figure 7 The cross-sectional view is along Figure 1 FIG. 1 is a cross-sectional view of the semiconductor device 102 taken along line AA.

[0092] In the semiconductor device 102, the second gate insulating film 14 is thicker than the first gate insulating film 11. The structure of the semiconductor device 102 except for the thickness of the second gate insulating film 14 is the same as that of the semiconductor device 101. In addition, in the semiconductor device 102, similarly to the semiconductor device 101, the resistivity of the second gate electrode 15 can be made lower than the resistivity of the first gate electrode 12 by making the impurity concentration of the polysilicon of the second gate electrode 15 higher than the impurity concentration of the polysilicon of the first gate electrode 12.

[0093] In the semiconductor device 102 , since the second gate insulating film 14 is thicker than the first gate insulating film 11 , the gate capacitance parasitic on the second gate electrode 15 is smaller than the gate capacitance parasitic on the first gate electrode 12 .

[0094] The thickness of the first gate insulating film 11 is, for example, not less than 50 nm and not more than 150 nm. The thickness of the second gate insulating film 14 is, for example, not less than 150 nm and not more than 500 nm, preferably not less than 300 nm and not more than 500 nm. Since the thickness of the second gate insulating film 14 is at least twice, preferably at least three times, the thickness of the first gate insulating film 11, the gate capacitance parasitic on the second gate electrode 15 can be sufficiently reduced. As a result, since the charging and discharging of the gate capacitance parasitic on the second gate electrode 15 is accelerated, the period of low on-voltage becomes longer, and the conduction loss is improved.

[0095] Here, "gate capacitance parasitic on the second gate electrode 15" or "gate capacitance parasitic on the first gate electrode 12" refers to the sum of the gate-emitter capacitance Cge and the gate-collector capacitance Cgc. However, in the semiconductor device 102, the gate-emitter capacitance Cge parasitic on the second gate electrode 15 may be smaller than the gate-emitter capacitance Cge parasitic on the first gate electrode 12. In addition, the gate-collector capacitance Cgc parasitic on the second gate electrode 15 may be smaller than the gate-collector capacitance Cgc parasitic on the first gate electrode 12.

[0096] exist Figure 7 In the embodiment, the number of trenches 10 including the first gate electrode 12 is the same as the number of trenches 10 including the second gate electrode 15. However, the number of trenches 10 is not limited to the same. For example, in order to reduce the gate capacitance parasitic on the second gate electrode 15, the number of trenches 10 including the second gate electrode 15 may be smaller than the number of trenches 10 including the first gate electrode 12.

[0097] <C. Implementation method 3>

[0098] <C-1. Structure>

[0099] Figure 8 is a cross-sectional view of a semiconductor device 103 according to Embodiment 3. Figure 1 The top view of the semiconductor device 101 is also shown. Figure 8 The cross-sectional view is along Figure 1 FIG. 1 is a cross-sectional view of the semiconductor device 103 taken along line AA.

[0100] In the semiconductor device 103, the electrodes inside each trench 10 are formed into a two-stage structure of a first gate electrode 12 at the top and a second gate electrode 15 at the bottom. Such a structure of the trench 10 is called a split gate. The first gate electrode 12 and the second gate electrode 15 are insulated by a boundary insulating film 13. The structure of the semiconductor device 103 except the split gate is the same as that of the semiconductor device 101.

[0101] Generally, the electrode on the lower side of the split gate becomes the emitter potential, so no accumulation layer is formed around the lower electrode, and the on-voltage is high. On the other hand, in the semiconductor device 103 of the present embodiment, the second gate electrode 15 is arranged on the lower side of the split gate, and the accumulation layer is formed around the second gate electrode 15. Therefore, the electrons injected through the channel formed by the first gate insulating film 11 on the upper side and the p-type base layer 4 are conducted with low resistance due to the accumulation layer formed around the second gate electrode 15, so the on-voltage is reduced.

[0102] In the above description, the semiconductor device 103 is described as a structure in which the split gate is applied to the semiconductor device 101 according to the first embodiment. However, the semiconductor device 103 may be a structure in which the split gate is applied to the semiconductor device 102 according to the second embodiment. Figure 8 In the embodiment, the second gate insulating film 14 is formed thicker than the first gate insulating film 11. In any structure, the charging and discharging of the gate capacitance parasitic on the second gate electrode 15 can be accelerated, the period of low on-voltage can be extended, and the conduction loss can be improved.

[0103] <C-2. Modification>

[0104] Fig. 9 is a cross-sectional view of a semiconductor device 103A according to a first variation of the third embodiment. Figure 1 The top view of the semiconductor device 101 is also shown. Fig. 9 The cross-sectional view is along Figure 1 FIG. 1 is a cross-sectional view of the semiconductor device 103A cut along the line AA of FIG. In the semiconductor device 103A, in a portion of the trench 10, both the upper side and the lower side of the split gate are the second gate electrode 15. The structure of the semiconductor device 103A is otherwise the same as that of the semiconductor device 103. According to such a structure, the gate-emitter capacitance Cge parasitic on the first gate electrode 12 is reduced, thereby reducing the turn-on loss.

[0105] Fig.10 is a cross-sectional view of a semiconductor device 103B according to a second variation of the third embodiment. Figure 1The top view of the semiconductor device 101 is also shown. Fig.10 The cross-sectional view is along Figure 1 AA line is a cross-sectional view of the semiconductor device 103B.

[0106] In the semiconductor device 103B, in a part of the trench 10, the upper side of the split gate is a trench emitter electrode 17. The trench emitter electrode 17 is electrically connected to the emitter electrode. An insulating film 16 is formed between the trench emitter electrode 17 and the inner wall of the trench 10. The structure of the semiconductor device 103B is the same as that of the semiconductor device 103. According to such a structure, the gate-emitter capacitance Cge parasitic on the first gate electrode 12 becomes smaller, so the turn-on loss is reduced. In addition, compared with the semiconductor device 103A, the gate-emitter capacitance Cge parasitic on the second gate electrode 15 becomes smaller, so the charging and discharging of the gate-emitter capacitance Cge parasitic on the second gate electrode 15 can be accelerated. As a result, the period of low on-voltage becomes longer, and the conduction loss is improved.

[0107] Fig.11 1 is a cross-sectional view of a semiconductor device 103C according to a third variation of the third embodiment. Figure 1 The top view of the semiconductor device 101 is also shown. Fig.11 The cross-sectional view is along Figure 1 AA line is a cross-sectional view of the semiconductor device 103C.

[0108] In a portion of the trench 10 of the semiconductor device 103C, an insulator 18 is filled on the upper side of the split gate. According to the structure of the semiconductor device 103B, a gate-emitter capacitance Cge is generated between the trench emitter electrode 17 and the second gate electrode 15. According to the structure of the semiconductor device 103C, a gate-emitter capacitance Cge is generated between the second gate electrode 15 and the p-type base layer 4, but it can be reduced compared to the gate-emitter capacitance Cge generated between the trench emitter electrode 17 and the second gate electrode 15 in the above-mentioned semiconductor device 103B. Therefore, the charging and discharging of the gate-emitter capacitance Cge parasitic on the second gate electrode 15 can be accelerated, and the period of low on-voltage can be extended.

[0109] In the above description, a structure in which split gates are formed in all trenches 10 is described. However, as shown in the following modified example, a structure in which a split gate and a normal gate (hereinafter also referred to as a "primary gate") which is a combination of a split gate and a non-split gate may be used. Fig.12 is a cross-sectional view of a semiconductor device 103D according to a fourth variation of the third embodiment. Figure 1 The top view of the semiconductor device 101 is also shown. Fig.12 The cross-sectional view is along Figure 1 AA line is a cross-sectional view of the semiconductor device 103D.

[0110] In the semiconductor device 103D, a split gate including a first gate electrode 12 at the top and a second gate electrode 15 at the bottom is formed in a portion of the trench 10. In the split gate, a first gate insulating film 11 is provided between the first gate electrode 12 and the inner wall of the trench 10, and a second gate insulating film 14 is provided between the second gate electrode 15 and the inner wall of the trench 10. A boundary insulating film 13 is provided between the first gate electrode 12 and the second gate electrode 15 to insulate the two. On the other hand, the first gate electrode 12 is formed in the remaining trench 10 via the first gate insulating film 11.

[0111] In the case where the second gate electrode 15 is provided on the lower side of the split gate, when the second gate pad 31 is turned off, no accumulation layer is formed around the second gate electrode 15, and the electron injection efficiency is reduced. Therefore, the on-voltage during the period until the first gate pad 30 is turned off becomes high. In particular, when the off-voltage of the second gate pad 31 is large on the negative side, a p-type inversion layer is formed around the second gate electrode 15 on the lower side, so there is a unique problem that even if the first gate electrode 12 on the upper side is turned on, electron injection is greatly suppressed, and the on-voltage increases. In contrast, in the semiconductor device 103D, by combining the split gate and the primary gate, the on-voltage during the period until the first gate pad 30 is turned off can be reduced.

[0112] Fig.13 is a cross-sectional view of a semiconductor device 103E according to a fifth variation of the third embodiment. Figure 1 The top view of the semiconductor device 101 is also shown. Fig.13 The cross-sectional view is along Figure 1 AA line is a cross-sectional view of the semiconductor device 103E.

[0113] In the semiconductor device 103E, the lower side of the split gate is set as the trench emitter electrode 17, and the electrode of the primary gate is set as the second gate electrode 15. An insulating film 16 is formed between the trench emitter electrode 17 and the inner wall of the trench 10. A second gate insulating film 14 is formed between the second gate electrode 15 and the inner wall of the trench 10. The structure of the semiconductor device 103E is the same as that of the semiconductor device 103D. In the semiconductor device 103E, by setting the electrode of the primary gate as the second gate electrode 15, electrons are efficiently injected from the first gate electrode 12 on the upper side of the split gate even after the second gate pad 31 is turned off. In addition, the increase in the on-voltage after the second gate pad 31 is turned off is suppressed.

[0114] Fig.14 1 is a cross-sectional view of a semiconductor device 103F according to a sixth variation of the third embodiment. Figure 1 The top view of the semiconductor device 101 is also shown. Fig.14 The cross-sectional view is along Figure 1 AA line is a cross-sectional view of the semiconductor device 103F.

[0115] In the semiconductor device 103F, the upper side of the split gate is set as the second gate electrode 15, and the electrode of the primary gate is set as the first gate electrode 12. A second gate insulating film 14 is formed between the second gate electrode 15 and the inner wall of the trench 10, and a first gate insulating film 11 is formed between the first gate electrode 12 and the inner wall of the trench 10. The structure of the semiconductor device 103F is the same as that of the semiconductor device 103E. In the semiconductor device 103F, even after the second gate pad 31 is turned off, more electrons are injected from the primary gate forming the accumulation layer. Therefore, the increase in the on-voltage after the second gate pad 31 is turned off is suppressed.

[0116] <D. Implementation method 4>

[0117] <D-1. Structure>

[0118] Fig.15 is a cross-sectional view of a semiconductor device 104 according to Embodiment 4. Figure 1 The top view of the semiconductor device 101 is also shown. Fig.15 The cross-sectional view is along Figure 1 FIG. 1 is a cross-sectional view of the semiconductor device 104 taken along line AA.

[0119] In the semiconductor device 104, the cross-sectional area of ​​the second gate electrode 15 is larger than the cross-sectional area of ​​the first gate electrode 12. Specifically, at least one of the depth d and the width w of the second gate electrode 15 is larger than the depth or the width of the first gate electrode 12. By increasing the cross-sectional area of ​​the second gate electrode 15, the resistivity of the second gate electrode 15 is reduced, and the charging and discharging of the gate capacitance parasitic on the second gate electrode 15 is accelerated. As a result, the period of low on-voltage is prolonged, and the conduction loss is improved.

[0120] <D-2. Modification>

[0121] Fig.16 is a cross-sectional view of a semiconductor device 104A according to a first variation of the fourth embodiment. Figure 1 The top view of the semiconductor device 101 is also shown. Fig.13 The cross-sectional view is along Figure 1 1 is a cross-sectional view of the semiconductor device 104A taken along line AA.

[0122] In the semiconductor device 104A, the surface area of ​​the second gate electrode 15 is smaller than the surface area of ​​the first gate electrode 12. Specifically, at least one of the depth d and the width w of the second gate electrode 15 is smaller than the depth or the width of the first gate electrode 12. By reducing the surface area of ​​the second gate electrode 15, it is possible to reduce the gate capacitance parasitic on the second gate electrode 15. As a result, the charging and discharging of the gate capacitance parasitic on the second gate electrode 15 is accelerated, the period of low on-voltage is prolonged, and the conduction loss is improved.

[0123] <E. Implementation method 5>

[0124] <E-1.Structure>

[0125] Fig.17 1 is a top view of a semiconductor device 105 according to Embodiment 5. The first gate electrode 12 is electrically connected to the first gate pad 30 via the first gate wiring 50 and the first built-in gate resistor 60. The second gate electrode 15 is electrically connected to the second gate pad 31 via the second gate wiring 51 and the second built-in gate resistor 61. The second built-in gate resistor 61 is smaller than the first built-in gate resistor 60. Therefore, the gate capacitance parasitic on the second gate electrode 15 can be charged and discharged at a high speed, the period of low on-voltage becomes longer, and the conduction loss is improved.

[0126] <E-2. Modification>

[0127] Fig.181 is a top view of a semiconductor device 105A according to a first variant of the fifth embodiment. The semiconductor device 105A is different from the semiconductor device 105 and does not include the first built-in gate resistor 60 and the second built-in gate resistor 61. In the semiconductor device 105A, the cross-sectional area of ​​the second gate wiring 51 is larger than the cross-sectional area of ​​the first gate wiring 50. Specifically, the width of the second gate wiring 51 is larger than the width of the first gate wiring. Thus, the resistivity of the second gate wiring 51 is smaller than the resistivity of the first gate wiring 50. As a result, the resistance formed by the second gate wiring 51 is smaller than the resistance formed by the first gate wiring 50. Therefore, the charging and discharging of the gate capacitance parasitic on the second gate electrode 15 can be accelerated, the period of low on-voltage is prolonged, and the conduction loss is improved.

[0128] <F. Implementation method 6>

[0129] <F-1. Structure>

[0130] Fig.19 It is a top view of the semiconductor device 106 involved in Embodiment 6. Fig. 20 It is along Fig.19 FIG. 1 is a cross-sectional view of the semiconductor device 106 taken along line BB.

[0131] The semiconductor device 106 includes a third gate pad 32 , a third gate insulating film 19 , and a third gate electrode 20 in addition to the structure of the semiconductor device 101 according to the first embodiment.

[0132] In the plurality of trenches 10 , the first gate electrode 12 is buried in a portion of the trenches 10 via the first gate insulating film 11 , the second gate electrode 15 is buried in another portion of the trenches 10 via the second gate insulating film 14 , and the third gate electrode 20 is buried in yet another portion of the trenches 10 via the third gate insulating film 19 .

[0133] The resistivity of the third gate electrode 20 is lower than the resistivity of the second gate electrode 15. Alternatively, the gate capacitance parasitic on the third gate electrode 20 is smaller than the gate capacitance parasitic on the second gate electrode 15. Therefore, the charging period and the discharging period of the gate capacitance parasitic on the third gate electrode 20 are shorter than the charging period and the discharging period of the gate capacitance parasitic on the second gate electrode 15, respectively.

[0134] The third gate electrode 20 is electrically connected to the third gate pad 32 via the third gate wiring 52. The timing of turning on and off the first gate pad 30, the second gate pad 31, and the third gate pad 32 is independently controlled by a control unit (not shown). That is, the semiconductor device 106 has a triple-gate structure.

[0135] Fig.21 1 is a diagram showing the driving timing of the semiconductor device 106. Fig.21 In FIG. 1 , Vg3 represents the applied voltage of the third gate pad 32 and the third gate electrode 20. The third gate pad 32 is controlled by a control unit (not shown) to be turned off earlier than the first gate pad 30 and turned on earlier than the second gate pad 31. That is, after the third gate pad 32 is turned on, the second gate pad 31 is turned on, and after the third gate pad 32 is turned off, the first gate pad 30 is turned off. The timing of turning on and off the first gate pad 30 and the second gate pad 31 is the same as that of the first embodiment.

[0136] Since the third gate pad 32 is turned off earlier than the first gate pad 30, the gate capacitance at the time of cutoff is only the gate capacitance parasitic on the first gate electrode 12, so the gate capacitance becomes smaller and the turn-off loss is reduced. In addition, since the third gate pad 32 is turned on earlier than the second gate pad 31, the channel density increases by an amount equivalent to the channel formed by the third gate electrode 20, the electron injection amount increases, and the current time change becomes faster, and the turn-on loss is reduced.

[0137] <F-2. Modification example>

[0138] Fig. 22 1 is a cross-sectional view of a semiconductor device 106A according to a first variation of Embodiment 6. The semiconductor device 106A adopts a split gate structure in the triple-gate semiconductor device 106. In the trench 10, the second gate electrode 15 is buried in the lower portion via the second gate insulating film 14, the first gate electrode 12 is buried in the upper portion via the first gate insulating film 11, or the third gate electrode 20 is buried in the upper portion via the third gate insulating film 19.

[0139] In the semiconductor device 106A, since the second gate insulating film 14 is not in contact with the p-type base layer 4, the second gate electrode 15 does not contribute to the high channel density. Therefore, by making the second gate electrode 15 conduct the operation later than the first gate electrode 12 and the third gate electrode 20 when turned on, the turn-on speed can be increased by an amount equivalent to the gate capacitance parasitic on the second gate electrode 15, and the turn-on loss can be reduced.

[0140] <G. Implementation method 7>

[0141] <G-1. Structure>

[0142] Fig.231 is a cross-sectional view of a semiconductor device 107 according to Embodiment 7. The semiconductor device 107 is obtained by adopting a double-sided gate structure for the semiconductor device 101 according to Embodiment 1. In the semiconductor device 107, in addition to the trench 10 formed from the first main surface S1 to the n-type drift layer 6, a trench 40 is formed from the second main surface S2 of the semiconductor substrate 60 to penetrate the p-type collector layer 8 and the n-type buffer layer 7 and reach the n-type drift layer 6. In order to distinguish between the two, the trench 10 is sometimes referred to as the first trench, and the trench 40 is sometimes referred to as the second trench.

[0143] A first gate insulating film 11 is formed on the inner wall of the trench 10, and a first gate electrode 12 is embedded in the trench 10 via the first gate insulating film 11. A second gate insulating film 14 is formed on the inner wall of the trench 40, and a second gate electrode 15 is embedded in the trench 10 via the second gate insulating film 14. In this way, the semiconductor device 107 also has a gate structure on the second main surface S2 side (back side) of the semiconductor substrate 60.

[0144] Fig.24 1 is a diagram showing the driving timing of the semiconductor device 107. Fig.24 In FIG. 1 , Vg1 represents the applied voltage of the first gate pad 30 and the first gate electrode 12, and Vg2 represents the applied voltage of the second gate pad 31 and the second gate electrode 15. The control unit (not shown) controls so that, when turned off, the second gate pad 31 is turned on earlier than the first gate pad 30 is turned off. That is, after the second gate pad 31 is turned on, the first gate pad 30 is turned off.

[0145] In the double-sided gate structure, by turning on the second gate pad 31 when turning off, electrons are discharged through the channel formed on the back side, so that the electron density on the back side is reduced. Along with this, the hole density is reduced in a manner to keep the charge neutral, so the turn-off loss is reduced. On the other hand, since the hole density is reduced and the on-voltage is increased, it is preferred that the charging period of the gate capacitance parasitic on the second gate pad 31 is short, that is, the timing of turning on the second gate pad 31 is late.

[0146] In the semiconductor device 107, similarly to the semiconductor device 101 according to the first embodiment, the resistivity of the second gate electrode 15 is made lower than the resistivity of the first gate electrode 12. Alternatively, in the semiconductor device 107, similarly to the semiconductor device 102 according to the second embodiment, the gate capacitance parasitic on the second gate electrode 15 is made smaller than the gate capacitance parasitic on the first gate electrode 12. Therefore, in the semiconductor device 107, the gate capacitance parasitic on the second gate electrode 15 can be charged at a higher speed, so that the timing of turning on the second gate pad 31 can be delayed. In this way, according to the semiconductor device 107, the period during which the hole density is high, that is, the period during which the on-voltage is low can be extended, and the conduction loss can be improved.

[0147] <G-2. Modification example>

[0148] Fig.25 1 is a cross-sectional view of a semiconductor device 107A according to a first variant of Embodiment 7. The semiconductor device 107A is configured such that the gate structure on the back side of the semiconductor device 107 is made planar rather than trench-shaped. By making the gate structure on the back side planar, the manufacturing process of the trench 40 on the back side, which is difficult to manufacture, can be reduced, and the manufacturing cost can be reduced.

[0149] Although preferred embodiments are described in detail above, they are not limited to the above embodiments, but can be variously modified and replaced without departing from the scope of the claims. In addition, the features of the semiconductor device involved in each embodiment can also be appropriately combined.

[0150] Hereinafter, various aspects of the present disclosure are collectively described as supplementary notes.

[0151] (Supplementary Note 1) A semiconductor device, wherein:

[0152] The semiconductor device comprises:

[0153] A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;

[0154] An upper surface electrode formed on the first main surface of the semiconductor substrate;

[0155] A lower surface electrode formed on the second main surface of the semiconductor substrate;

[0156] a first gate pad; and

[0157] The second gate pad is controlled independently of the first gate pad.

[0158] The semiconductor substrate comprises:

[0159] A drift layer of a first conductivity type;

[0160] a second conductive type base layer formed on the first main surface side of the drift layer;

[0161] a first conductivity type source layer formed on the first main surface side of the base layer; and

[0162] A plurality of first trenches penetrate the base layer from the source layer and reach the drift layer.

[0163] A gate electrode embedded in each of the plurality of first trenches via an insulating film is provided,

[0164] The gate electrode comprises:

[0165] a first gate electrode electrically connected to the first gate pad; and

[0166] a second gate electrode electrically connected to the second gate pad;

[0167] A charging period and a discharging period of the gate capacitance parasitic on the second gate electrode are respectively shorter than a charging period and a discharging period of the gate capacitance parasitic on the first gate electrode.

[0168] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein:

[0169] The resistivity of the second gate electrode is lower than the resistivity of the first gate electrode.

[0170] (Supplementary Note 3) The semiconductor device according to Supplementary Note 2, wherein:

[0171] The impurity concentration of the semiconductor material constituting the second gate electrode is higher than the impurity concentration of the semiconductor material constituting the first gate electrode.

[0172] (Supplementary Note 4) The semiconductor device according to Supplementary Note 2, wherein:

[0173] A cross-sectional area of ​​the second gate electrode is larger than a cross-sectional area of ​​the first gate electrode.

[0174] (Supplementary Note 5) The semiconductor device according to Supplementary Note 2, wherein:

[0175] The second gate electrode is made of metal.

[0176] (Supplementary Note 6) The semiconductor device according to Supplementary Note 1, wherein:

[0177] The gate capacitance parasitic on the second gate electrode is smaller than the gate capacitance parasitic on the first gate electrode.

[0178] (Supplementary Note 7) The semiconductor device according to Supplementary Note 6, wherein:

[0179] The second gate insulating film formed between the second gate electrode and the inner wall of the first trench is thicker than the first gate insulating film formed between the first gate electrode and the inner wall of the first trench.

[0180] (Supplementary Note 8) The semiconductor device according to Supplementary Note 6, wherein:

[0181] The surface area of ​​the second gate electrode is smaller than the surface area of ​​the first gate electrode.

[0182] (Supplementary Note 9) The semiconductor device according to Supplementary Note 6, wherein:

[0183] The second gate electrode is made of amorphous silicon.

[0184] (Supplementary Note 10) The semiconductor device according to Supplementary Note 1, wherein:

[0185] The semiconductor device further comprises:

[0186] a first built-in gate resistor disposed between the first gate electrode and the first gate pad; and

[0187] The second built-in gate resistor is provided between the second gate electrode and the second gate pad.

[0188] The second built-in gate resistor is smaller than the first built-in gate resistor.

[0189] (Supplementary Note 11) The semiconductor device according to Supplementary Note 10, wherein:

[0190] The first built-in gate resistor is formed by a first gate wiring connecting the first gate electrode and the first gate pad.

[0191] The second built-in gate resistor is formed by a second gate wiring connecting the second gate electrode and the second gate pad.

[0192] The resistivity of the second gate wiring is lower than the resistivity of the first gate wiring.

[0193] (Supplement 12) The semiconductor device according to any one of Supplements 1 to 11, wherein

[0194] In at least one first trench among the plurality of first trenches, the second gate electrode is buried at a lower portion, the first gate electrode is buried at an upper portion, and a boundary insulating film is provided between the first gate electrode and the second gate electrode to insulate the two.

[0195] (Supplement 13) The semiconductor device according to any one of Supplements 1 to 12, wherein

[0196] After the first gate pad is turned on, the second gate pad is turned on.

[0197] After the second gate pad is turned off, the first gate pad is turned off.

[0198] (Supplement 14) The semiconductor device according to any one of Supplements 1 to 13, wherein

[0199] The semiconductor device further includes a third gate pad, the third gate pad being controlled independently of the first gate pad and the second gate pad.

[0200] The gate electrode includes a third gate electrode, and the third gate electrode is electrically connected to the third gate pad.

[0201] A charging period and a discharging period of the gate capacitance parasitic on the third gate electrode are respectively shorter than a charging period and a discharging period of the gate capacitance parasitic on the second gate electrode.

[0202] (Supplementary Note 15) The semiconductor device according to Supplementary Note 14, wherein:

[0203] After the third gate pad is turned on, the second gate pad is turned on.

[0204] After the third gate pad is turned off, the first gate pad is turned off.

[0205] (Supplement 16) The semiconductor device according to any one of Supplements 1 to 11, wherein

[0206] The semiconductor substrate includes at least one second trench extending from the second main surface to the drift layer.

[0207] The second gate electrode is buried in the second trench instead of in the first trench.

[0208] (Supplementary Note 17) The semiconductor device according to Supplementary Note 16, wherein

[0209] After the second gate pad is turned on, the first gate pad is turned off.

[0210] (Supplementary Note 18) The semiconductor device according to any one of Supplementary Notes 1 to 17, wherein

[0211] The semiconductor device is an RC-IGBT.

[0212] (Supplement 19) The semiconductor device according to any one of Supplements 1 to 17, wherein

[0213] The semiconductor device is a MOSFET.

[0214] (Supplementary Note 20) The semiconductor device according to any one of Supplementary Notes 1 to 19, wherein the semiconductor substrate is made of a wide bandgap semiconductor.

Claims

1. A semiconductor device, wherein: The semiconductor device comprises: A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; An upper surface electrode formed on the first main surface of the semiconductor substrate; A lower surface electrode formed on the second main surface of the semiconductor substrate; a first gate pad; and a second gate pad, which is controlled independently of the first gate pad; The semiconductor substrate comprises: A drift layer of a first conductivity type; a second conductive type base layer formed on the first main surface side of the drift layer; a first conductive type source layer formed on the first main surface side of the base layer; as well as a plurality of first trenches extending from the source layer through the base layer and reaching the drift layer; A gate electrode embedded in each of the plurality of first trenches via an insulating film is provided, The gate electrode comprises: a first gate electrode electrically connected to the first gate pad; and a second gate electrode electrically connected to the second gate pad, A charging period and a discharging period of the gate capacitance parasitic on the second gate electrode are respectively shorter than a charging period and a discharging period of the gate capacitance parasitic on the first gate electrode.

2. The semiconductor device according to claim 1, wherein The resistivity of the second gate electrode is lower than the resistivity of the first gate electrode.

3. The semiconductor device according to claim 2, wherein: The impurity concentration of the semiconductor material constituting the second gate electrode is higher than the impurity concentration of the semiconductor material constituting the first gate electrode.

4. The semiconductor device according to claim 2, wherein: A cross-sectional area of ​​the second gate electrode is larger than a cross-sectional area of ​​the first gate electrode.

5. The semiconductor device according to claim 2, wherein: The second gate electrode is made of metal.

6. The semiconductor device according to claim 1, wherein A gate capacitance parasitic on the second gate electrode is smaller than a gate capacitance parasitic on the first gate electrode.

7. The semiconductor device according to claim 6, wherein: The second gate insulating film formed between the second gate electrode and the inner wall of the first trench is thicker than the first gate insulating film formed between the first gate electrode and the inner wall of the first trench.

8. The semiconductor device according to claim 6, wherein: The surface area of ​​the second gate electrode is smaller than the surface area of ​​the first gate electrode.

9. The semiconductor device according to claim 6, wherein: The second gate electrode is made of amorphous silicon.

10. The semiconductor device according to claim 1, wherein The semiconductor device further comprises: a first built-in gate resistor disposed between the first gate electrode and the first gate pad; and a second built-in gate resistor, disposed between the second gate electrode and the second gate pad, The second built-in gate resistor is smaller than the first built-in gate resistor.

11. The semiconductor device according to claim 10, wherein The first built-in gate resistor is formed by a first gate wiring connecting the first gate electrode and the first gate pad. The second built-in gate resistor is formed by a second gate wiring connecting the second gate electrode and the second gate pad. The resistivity of the second gate wiring is lower than the resistivity of the first gate wiring.

12. The semiconductor device according to any one of claims 1 to 11, wherein: In at least one first trench among the plurality of first trenches, the second gate electrode is buried at a lower portion, the first gate electrode is buried at an upper portion, and a boundary insulating film is provided between the first gate electrode and the second gate electrode to insulate the two.

13. The semiconductor device according to any one of claims 1 to 12, wherein: After the first gate pad is turned on, the second gate pad is turned on, After the second gate pad is turned off, the first gate pad is turned off.

14. The semiconductor device according to any one of claims 1 to 13, wherein: The semiconductor device further includes a third gate pad that is controlled independently of the first gate pad and the second gate pad. The gate electrode includes a third gate electrode, and the third gate electrode is electrically connected to the third gate pad. A charging period and a discharging period of the gate capacitance parasitic on the third gate electrode are respectively shorter than a charging period and a discharging period of the gate capacitance parasitic on the second gate electrode.

15. The semiconductor device according to claim 14, wherein: After the third gate pad is turned on, the second gate pad is turned on, After the third gate pad is turned off, the first gate pad is turned off.

16. The semiconductor device according to any one of claims 1 to 11, wherein The semiconductor substrate includes at least one second trench extending from the second main surface to the drift layer. The second gate electrode is buried in the second trench instead of being buried in the first trench.

17. The semiconductor device according to claim 16, wherein: After the second gate pad is turned on, the first gate pad is turned off.

18. The semiconductor device according to any one of claims 1 to 17, wherein: The semiconductor device is an RC-IGBT.

19. The semiconductor device according to any one of claims 1 to 17, wherein: The semiconductor device is a MOSFET.

20. The semiconductor device according to any one of claims 1 to 19, wherein The semiconductor substrate is composed of a wide bandgap semiconductor.

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