Preparation method of radio frequency triode and radio frequency triode

Abstract

The invention provides a preparation method of a radio frequency triode and the radio frequency triode, and relates to the technical field of semiconductors, a P-type base region is formed above a substrate, and then an oxide layer is deposited; etching on the oxide layer to form a groove extending to the P-type base region, and then depositing a heavily doped N-type polycrystalline silicon layer on the upper surface of the groove; and forming an electrode metal layer on the substrate on which the heavily doped N-type polycrystalline silicon layer is formed so as to prepare the radio frequency triode. Wherein the electrode metal layer at least comprises an emitter metal layer, and the emitter metal layer extends to the heavily doped N-type polycrystalline silicon layer. The invention has the beneficial effects that the width of the base region is further obviously reduced from the bottom of the heavily doped N-type polycrystalline silicon layer to the bottom of the P-type base region, namely, the base region is thinner, so that the requirement of high-frequency application is better met; the contact area of the emitter metal layer and the base region is obviously increased, the resistance of the emitter metal layer is reduced, and the current density is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a radio frequency triode and the radio frequency triode. Background Art

[0002] RF triode is an indispensable component in modern electronic technology, especially in high-frequency applications. Compared with ordinary triodes, its main features are small size, low breakdown voltage, extremely high characteristic frequency, and difficult manufacturing process. It is generally used in high-frequency broadband low-noise amplifiers such as VHF (ultra-high frequency), UHF (ultra-high frequency), CATV (cable TV), wireless remote control, RF modules, etc. These applications are mostly used under low voltage, small signal, small current, and low noise conditions.

[0003] In order to achieve high-frequency characteristics, RF transistors usually use shallow junction technology to reduce the base width, thereby shortening the carrier transit time in the base to increase the characteristic frequency. The faster the carrier migration speed, the stronger the signal amplification ability, thereby adapting to higher frequency application requirements. Therefore, it is necessary to design and manufacture RF transistors with thinner bases.

[0004] In addition, RF transistors need to reduce the resistance of the emitter and collector while achieving high-frequency characteristics. This is because excessive resistance will cause signal attenuation, thus affecting the amplification effect. In high-frequency applications, the current changes very quickly, and any unnecessary resistance will cause energy loss. Therefore, reducing the emitter and collector resistance as much as possible is another key factor in improving the performance of RF transistors. Summary of the invention

[0005] In view of the problems existing in the prior art, the present invention provides a method for preparing a radio frequency triode, comprising:

[0006] Step S1, forming a P-type base region on the substrate, and then depositing an oxide layer;

[0007] Step S2, etching the oxide layer to form a groove extending to the P-type base region, and then depositing a heavily doped N-type polysilicon layer on the upper surface of the groove;

[0008] Step S3, forming an electrode metal layer on the substrate on which the heavily doped N-type polysilicon layer is formed, so as to prepare a radio frequency triode;

[0009] Wherein, the electrode metal layer at least includes an emitter metal layer, and the emitter metal layer extends to the heavily doped N-type polysilicon layer.

[0010] Preferably, in the step S1, before depositing the oxide layer, the step further includes etching at both side edges of the substrate to form isolation grooves extending to the substrate.

[0011] Preferably, in step S1, the substrate is an N-type substrate, an N-type epitaxial layer is grown on the N-type substrate, and then ion implantation is performed on the N-type epitaxial layer to form the P-type base region;

[0012] The isolation trench sequentially passes through the P-type base region and the N-type epitaxial layer and extends into the N-type substrate.

[0013] Preferably, the N-type substrate is a heavily doped N-type substrate, and the resistivity of the N-type substrate is less than 0.01Ω·cm; the thickness of the N-type epitaxial layer is 2-8μm, and the resistivity is greater than 0.1Ω·cm.

[0014] Preferably, step S3 comprises:

[0015] Step S311, performing ion implantation on the P-type base region on both sides of the heavily doped N-type polysilicon layer to form a heavily doped P region extending into the N-type epitaxial layer;

[0016] Step S312, depositing a dielectric layer on the oxide layer, and then forming a front metal layer on the dielectric layer, the front metal layer extending to the heavily doped P region and the front metal layer extending to the N-type polysilicon layer respectively;

[0017] Step S313, depositing a passivation layer on the dielectric layer, and then etching to expose the upper surface of the front metal to form a base metal layer extending to the heavily doped P region and the emitter metal layer extending to the N-type polysilicon layer;

[0018] Step S314, thinning the side of the N-type substrate away from the N-type epitaxial layer and then depositing metal to form a collector metal layer to prepare the radio frequency triode.

[0019] Preferably, the substrate is an SOI substrate, comprising a silicon layer, a buried oxide layer and an N-type silicon layer stacked from bottom to top, and the P-type base region is formed by ion implantation in the N-type silicon layer;

[0020] The isolation trench is located at both sides of the P-type base region and penetrates the N-type silicon layer to the upper surface of the buried oxide layer.

[0021] Preferably, the step S1 further comprises performing ion implantation on the N-type silicon layer on both sides of the P-type base region to form a heavily doped N region; then the step S3 comprises:

[0022] Step S321, performing ion implantation on the P-type base region on both sides of the heavily doped N-type polysilicon layer to form a heavily doped P region extending into the N-type epitaxial layer;

[0023] Step S322, depositing a dielectric layer on the oxide layer, and then forming a front metal layer on the dielectric layer, which extends to the heavily doped P region, the N-type polysilicon layer and the heavily doped N region respectively;

[0024] Step S323, depositing a passivation layer on the dielectric layer, and then etching to expose the upper surface of the front metal, forming a base metal layer extending to the heavily doped P region, the emitter metal layer extending to the N-type polysilicon layer, and a collector metal layer extending to the heavily doped N region, so as to prepare the RF triode.

[0025] Preferably, etching to form the isolation groove comprises:

[0026] A deep trench is first formed by dry etching, and then a dielectric is filled into the deep trench by a low-temperature deposition process to form the isolation trench.

[0027] Preferably, in the step S1, before depositing the oxide layer, a field oxide layer is further formed at the interface between the two sides of the P-type base region and the substrate.

[0028] The present invention also provides a radio frequency triode, which is prepared by the above-mentioned preparation method, and the radio frequency triode comprises:

[0029] A substrate, a P-type base region is formed on the substrate, and an oxide layer is deposited on the P-type base region;

[0030] A groove, penetrating the oxide layer and extending into the P-type base region, a heavily doped N-type polysilicon layer being deposited on an upper surface of the groove;

[0031] An electrode metal layer is formed on the substrate having the heavily doped N-type polysilicon layer, and the electrode metal layer at least includes an emitter metal layer, the bottom of which contacts the upper surface of the heavily doped N-type polysilicon layer.

[0032] The above technical solution has the following advantages or beneficial effects:

[0033] 1) The formation of the P-type base region does not require a high-temperature furnace heating process, so that the formed P-type base region itself has a shallow junction depth. Then, by etching a shallow groove and depositing a heavily doped N-type polysilicon layer, the base region width is from the bottom of the heavily doped N-type polysilicon layer to the bottom of the P-type base region. Obviously, its thickness is further reduced, that is, it has a thinner base region width, thereby better meeting the needs of high-frequency applications;

[0034] 2) The bottom and side of the heavily doped N-type polysilicon layer are in contact with the P-type base region, which significantly increases the contact area between the emitter metal layer and the base region, which is beneficial to reducing the resistance of the emitter metal layer and increasing the current density;

[0035] 3) Add isolation grooves on the outside of the chip to effectively improve the stability of electrical parameters and durability reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 The figure is a flow chart of a method for preparing a radio frequency triode in a preferred embodiment of the present invention;

[0037] Figures 2 to 9 This is a schematic diagram of a process for preparing a radio frequency triode in Example 1 of the present invention;

[0038] Fig.10 This is a schematic diagram of a sub-process of step S3 in Embodiment 1 of the present invention;

[0039] Fig.11 This is a schematic structural diagram of a radio frequency triode prepared in Example 2 of the present invention;

[0040] Fig.12 This is a schematic diagram of a sub-process of step S3 in Embodiment 2 of the present invention;

[0041] Fig.13 This is a schematic diagram of the structure of the radio frequency triode prepared in Example 3 of the present invention. DETAILED DESCRIPTION

[0042] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment, and other embodiments may also fall within the scope of the present invention as long as they conform to the gist of the present invention.

[0043] In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a method for preparing a radio frequency triode is provided, such as Figure 1 As shown, including:

[0044] Step S1, forming a P-type base region on the substrate, and then depositing an oxide layer;

[0045] Step S2, etching the oxide layer to form a groove extending to the P-type base region, and then depositing a heavily doped N-type polysilicon layer on the upper surface of the groove;

[0046] Step S3, forming an electrode metal layer on the substrate on which the heavily doped N-type polysilicon layer is formed, so as to prepare a radio frequency triode;

[0047] The electrode metal layer at least includes an emitter metal layer, and the emitter metal layer extends to the heavily doped N-type polysilicon layer.

[0048] In a preferred embodiment of the present invention, in step S1, before depositing the oxide layer, the step further includes etching at both side edges of the substrate to form isolation grooves extending to the substrate.

[0049] Embodiment 1:

[0050] In this embodiment, Figures 2 to 4 As shown, in step S1, the substrate is an N-type substrate N+Sub, an N-type epitaxial layer N-epi is grown on the N-type substrate N+Sub, and then ion implantation is performed on the N-type epitaxial layer N-epi to form a P-type base region P-base; then, the two side edges of the substrate are respectively etched to form an isolation groove 1 extending to the substrate. Among them, the isolation groove 1 sequentially passes through the P-type base region P-base and the N-type epitaxial layer N-epi and extends into the N-type substrate N+Sub.

[0051] Preferably, the N-type substrate N+Sub is a heavily doped N-type substrate, and the resistivity of the N-type substrate N+Sub is less than 0.01Ω·cm; the use of low-resistivity materials as the N-type substrate N+Sub is beneficial to reducing the collector resistance. The thickness of the N-type epitaxial layer N-epi is 2 to 8μm, and the resistivity is greater than 0.1Ω·cm. More preferably, the thickness of the N-type epitaxial layer N-epi is 2 to 4μm, and the resistivity is 0.5 to 1.5Ω·cm. The use of a higher resistivity N-epi can ensure that the collector-base and collector-emitter have a higher breakdown voltage, usually greater than 12V.

[0052] Preferably, the implantation element for ion implantation on the N-epi layer to form the P-base region is boron or boron difluoride, and the implantation dose is 1E12-1E14 / cm 2 , injection energy 20~200KeV.

[0053] After ion implantation to form the P-type base region P-base, the above surface is coated with glue, exposed, and developed to define the deep groove etching area window, and then deep grooves are etched by dry etching, and the medium is filled in the deep grooves. The medium can be silicon dioxide or undoped polysilicon to form an isolation groove, and then the excess medium on the front is removed, leaving only the medium in the groove. Among them, the depth of the isolation groove 1 is greater than the thickness of the N-type epitaxial layer N-epi. The width of the isolation groove 1 is 0.8 to 1.6μm. Low-temperature deposition technology is used in the process of filling the isolation groove 1, which will not cause the P-type base region P-base to diffuse due to heat.

[0054] After forming the isolation trench 1, as Figure 5 As shown, a thin oxide layer 2 is deposited on the surface, and then a shallow groove area window is defined by photolithography, and then a shallow groove, that is, the groove 3, is etched by dry etching, and then a heavily doped N-type polysilicon layer 4 is deposited on the entire surface, and then the excess polysilicon is removed by photolithography and etching. The retained polysilicon is the polysilicon emitter.

[0055] Preferably, the etching depth of the groove 3 is 0.5-2um, and the polysilicon can be made low-resistance by doping while depositing, or by first depositing and then ion implanting (implanting phosphorus or arsenic elements). The polysilicon is in direct contact with the P-type base region P-base in the groove 3 and in contact with the oxide layer 2 on the surface.

[0056] In this embodiment, Fig.10 As shown, step S3 includes:

[0057] Step S311, performing ion implantation on the P-type base regions on both sides of the heavily doped N-type polysilicon layer to form heavily doped P regions extending into the N-type epitaxial layer;

[0058] Step S312, depositing a dielectric layer on the oxide layer, and then forming a front metal layer on the dielectric layer, which extends to the heavily doped P region and to the N-type polysilicon layer respectively;

[0059] Step S313, depositing a passivation layer on the dielectric layer, and then etching to expose the upper surface of the front metal to form a base metal layer extending to the heavily doped P region and an emitter metal layer extending to the N-type polysilicon layer;

[0060] Step S314, thinning the side of the N-type substrate away from the N-type epitaxial layer and then depositing metal to form a collector metal layer to prepare a radio frequency triode.

[0061] Specifically, Figure 6 As shown, after the oxide layer 2 is formed, a P+ implantation window is defined by photolithography, and then P+ ion implantation is performed to form a heavily doped P region P+. A rapid thermal annealing process is then performed to repair implantation damage and activate impurity ions.

[0062] Preferably, P+ is implanted with boron or boron difluoride, with an implantation dose of 1E15-1E16 / cm 2 , the injection energy is 30-100 KeV. The rapid thermal annealing process temperature is above 1000°C and the time is 20-40 seconds. Rapid thermal annealing can effectively inhibit the diffusion of impurities in all directions while activating impurities, ensuring that the junction depth is still relatively shallow.

[0063] like Figure 7 As shown, a dielectric layer 5 is then deposited on the surface, and then photolithography and etching are performed to form contact holes. The dielectric layer 5 can be an oxide layer, borophosphorus glass, or a combination of multiple insulating layers. Metal deposition is then performed, and photolithography and metal etching are performed to form a front metal layer 6.

[0064] Furthermore, Figure 8As shown, a passivation layer 7 is deposited on the surface, and then metal windows are opened by photolithography and etching to form an emitter metal layer 8 and a base metal layer 9. The passivation layer 7 can be an oxide layer, or silicon nitride, or a combination of multiple insulating layers.

[0065] When thinning the back side, the front side of the chip can be protected by a film, and then the back side can be thinned, that is, the thickness of the N-type substrate N+Sub can be reduced by chemical mechanical polishing. Then the front side protective film is removed and metal deposition is performed on the back side, such as Fig. 9 As shown, a back collector metal layer 10 is formed.

[0066] Preferably, thinning the back surface can effectively reduce the collector resistance. In this embodiment, the thickness is thinned to 80-100 um.

[0067] Embodiment 2:

[0068] In this embodiment, the substrate is an SOI substrate, such as Fig.11 As shown, it includes a silicon layer Si, a buried oxide layer BOX and an N-type silicon layer N-type Si stacked from bottom to top, and a P-type base region P-base is formed by ion implantation in the N-type silicon layer N-type Si;

[0069] The isolation trench 1 is located on both sides of the P-type base region P-base and penetrates the N-type silicon layer N-type Si to the upper surface of the buried oxide layer BOX. Among them, the thin silicon layer on the upper part of the SOI substrate is the N-type silicon layer N-type Si, with a thickness of 2 to 8 um.

[0070] In this embodiment, step S1 also includes performing ion implantation on the N-type silicon layer N-type Si on both sides of the P-type base region P-base to form a heavily doped N region N+; adding heavily doped N regions N+ at the same distance on both sides of the P-type base region P-base, and adjusting the distance between the heavily doped N region N+ and the P-type base region P-base to control the collector-base breakdown voltage. The heavily doped N region N+ has metal drawn out from the surface, which is the collector metal layer 10. An isolation groove 1 is provided outside the heavily doped N region N+, and the depth of the isolation groove 1 is the same as the thickness of the N-type silicon layer N-type Si.

[0071] If Fig.12 As shown, step S3 includes:

[0072] Step S321, performing ion implantation on the P-type base regions on both sides of the heavily doped N-type polysilicon layer to form heavily doped P regions extending into the N-type epitaxial layer;

[0073] Step S322, depositing a dielectric layer on the oxide layer, and then forming a front metal layer on the dielectric layer that extends to the heavily doped P region, the N-type polysilicon layer, and the heavily doped N region respectively;

[0074] In step S323, a passivation layer is deposited on the dielectric layer, and then etched to expose the upper surface of the front metal to form a base metal layer extending to the heavily doped P region, an emitter metal layer extending to the N-type polysilicon layer, and a collector metal layer extending to the heavily doped N region to prepare a radio frequency triode.

[0075] Embodiment 3:

[0076] In this embodiment, the same substrate structure as in Embodiment 1 is used, except that the field oxide layer 11 is used in this embodiment to replace the isolation trench 1, and has the same function. Fig.12 As shown, in step S1, before depositing the oxide layer 2, a field oxide layer 11 is formed at the interface between the two sides of the P-type base region P-base and the substrate.

[0077] The present invention also provides a radio frequency triode, which is prepared by the above-mentioned preparation method. Fig. 9 , Fig.11 and Fig.13 As shown, the radio frequency triode includes:

[0078] A substrate, a P-type base region P-base is formed on the substrate, and an oxide layer 2 is deposited on the P-type base region P-base;

[0079] A groove is formed through the oxide layer 2 and extends into the P-type base region P-base, and a heavily doped N-type polysilicon layer 4 is deposited on the upper surface of the groove;

[0080] The electrode metal layer is formed on a substrate having a heavily doped N-type polysilicon layer. The electrode metal layer at least includes an emitter metal layer 6 , and the bottom of the emitter metal layer 6 is in contact with the upper surface of the heavily doped N-type polysilicon layer 4 .

[0081] The above description is only a preferred embodiment of the present invention, and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the contents of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. A method for preparing a radio frequency triode, characterized in that: include: Step S1, forming a P-type base region on the substrate, and then depositing an oxide layer; Step S2, etching the oxide layer to form a groove extending to the P-type base region, and then depositing a heavily doped N-type polysilicon layer on the upper surface of the groove; Step S3, forming an electrode metal layer on the substrate on which the heavily doped N-type polysilicon layer is formed, so as to prepare a radio frequency triode; Wherein, the electrode metal layer at least includes an emitter metal layer, and the emitter metal layer extends to the heavily doped N-type polysilicon layer.

2. The preparation method according to claim 1, characterized in that: In the step S1, before depositing the oxide layer, the step further includes etching at both side edges of the substrate to form isolation grooves extending to the substrate.

3. The preparation method according to claim 2, characterized in that: In the step S1, the substrate is an N-type substrate, an N-type epitaxial layer is grown on the N-type substrate, and then ion implantation is performed on the N-type epitaxial layer to form the P-type base region; The isolation trench sequentially passes through the P-type base region and the N-type epitaxial layer and extends into the N-type substrate.

4. The preparation method according to claim 3, characterized in that: The N-type substrate is a heavily doped N-type substrate, and the resistivity of the N-type substrate is less than 0.01Ω·cm; the thickness of the N-type epitaxial layer is 2-8μm, and the resistivity is greater than 0.1Ω·cm.

5. The preparation method according to claim 3, characterized in that: The step S3 comprises: Step S311, performing ion implantation on the P-type base region on both sides of the heavily doped N-type polysilicon layer to form a heavily doped P region extending into the N-type epitaxial layer; Step S312, depositing a dielectric layer on the oxide layer, and then forming a front metal layer on the dielectric layer, the front metal layer extending to the heavily doped P region and the front metal layer extending to the N-type polysilicon layer respectively; Step S313, depositing a passivation layer on the dielectric layer, and then etching to expose the upper surface of the front metal to form a base metal layer extending to the heavily doped P region and the emitter metal layer extending to the N-type polysilicon layer; Step S314, thinning the side of the N-type substrate away from the N-type epitaxial layer and then depositing metal to form a collector metal layer to prepare the radio frequency triode.

6. The preparation method according to claim 2, characterized in that: The substrate is an SOI substrate, comprising a silicon layer, a buried oxide layer and an N-type silicon layer stacked from bottom to top, and the P-type base region is formed by ion implantation in the N-type silicon layer; The isolation trench is located at both sides of the P-type base region and penetrates the N-type silicon layer to the upper surface of the buried oxide layer.

7. The preparation method according to claim 6, characterized in that: In the step S1, ion implantation is also performed on the N-type silicon layer on both sides of the P-type base region to form a heavily doped N region; then the step S3 includes: Step S321, performing ion implantation on the P-type base region on both sides of the heavily doped N-type polysilicon layer to form a heavily doped P region extending into the N-type epitaxial layer; Step S322, depositing a dielectric layer on the oxide layer, and then forming a front metal layer on the dielectric layer, which extends to the heavily doped P region, the N-type polysilicon layer and the heavily doped N region respectively; Step S323, depositing a passivation layer on the dielectric layer, and then etching to expose the upper surface of the front metal, forming a base metal layer extending to the heavily doped P region, the emitter metal layer extending to the N-type polysilicon layer, and a collector metal layer extending to the heavily doped N region, so as to prepare the RF triode.

8. The preparation method according to claim 2, characterized in that: Etching to form the isolation groove comprises: A deep trench is first formed by dry etching, and then a dielectric is filled into the deep trench by a low-temperature deposition process to form the isolation trench.

9. The preparation method according to claim 1, characterized in that: In the step S1, before depositing the oxide layer, a field oxide layer is formed at the interface between the two sides of the P-type base region and the substrate.

10. A radio frequency triode, characterized in that: The radio frequency triode is prepared by the preparation method according to any one of claims 1 to 9, and comprises: A substrate, a P-type base region is formed on the substrate, and an oxide layer is deposited on the P-type base region; A groove, penetrating the oxide layer and extending into the P-type base region, a heavily doped N-type polysilicon layer being deposited on an upper surface of the groove; An electrode metal layer is formed on the substrate having the heavily doped N-type polysilicon layer, and the electrode metal layer at least includes an emitter metal layer, the bottom of which contacts the upper surface of the heavily doped N-type polysilicon layer.

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