Partially depleted silicon-on-insulator semiconductor device and method of manufacturing same

Abstract

The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a partially depleted silicon-on-insulator semiconductor device and a manufacturing method thereof. The partially depleted silicon-on-insulator semiconductor device comprises a bottom silicon layer, an insulating layer and a top silicon layer which are stacked, the top layer silicon comprises a first side surface and a second side surface which are opposite to each other; the top silicon comprises a body region, the upper part of the body region close to the first side surface is doped to form a source region, the source region is doped to form a source heavily doped region, the upper part of the body region close to the second side surface is doped to form a drain region, and the drain region is doped to form a drain heavily doped region; a gate structure is bridged on the top layer silicon between the source heavily doped region and the drain heavily doped region; a charge recombination center doped band is formed at the junction of the source region and the body region, and the charge recombination center doped band extends into the body region.

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