Extended drain metal oxide semiconductor device with dual thickness gate dielectric layer

Abstract

The invention relates to an extended drain metal oxide semiconductor device with a dual thickness gate dielectric layer. A structure for expanding a drain metal oxide semiconductor device and a method of forming a structure for expanding a drain metal oxide semiconductor device. The structure includes a semiconductor layer, a source region, a drain region, and a gate between the source region and the drain region. The gate includes a gate conductor layer, a first gate dielectric layer having a first thickness, and a second gate dielectric layer having a second thickness greater than the first thickness. A first gate dielectric layer is disposed on a top surface of the semiconductor layer, and a second gate dielectric layer includes a first portion on the top surface of the semiconductor layer and a second portion adjacent a sidewall of the semiconductor layer. The gate conductor layer has an overlapping relationship with the first gate dielectric layer, the first portion of the second gate dielectric layer, and the second portion of the second gate dielectric layer.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices and integrated circuit fabrication, and more particularly to structures for extended drain metal oxide semiconductor devices and methods of forming structures for extended drain metal oxide semiconductor devices. Background Art

[0002] For example, high voltage integrated circuits used in microwave / RF power amplifiers often require specialized device structures that can withstand higher voltages. Extended drain metal oxide semiconductor (EDMOS) devices, also known as laterally diffused metal oxide semiconductor (LDMOS) devices, are designed to handle this higher voltage by incorporating additional features such as an extended drain that facilitate the higher voltage handling capability. The breakdown voltage and prompt shift of extended drain metal oxide semiconductor devices may be limited by charge trapping centers at the drift region or under the gate.

[0003] Improved structures for extended drain metal oxide semiconductor devices and methods of forming extended drain metal oxide semiconductor devices are needed. Summary of the invention

[0004] In an embodiment, a structure for an extended drain metal oxide semiconductor device is provided. The structure includes: a semiconductor layer including sidewalls and a top surface; a source region located in the semiconductor layer; a drain region located in the semiconductor layer; and a gate positioned between the source region and the drain region. The gate includes a gate conductor layer, a first gate dielectric layer having a first thickness, and a second gate dielectric layer having a second thickness greater than the first thickness. The first gate dielectric layer is disposed on the top surface of the semiconductor layer. The second gate dielectric layer includes a first portion located on the top surface of the semiconductor layer and a second portion adjacent to the sidewall of the semiconductor layer. The gate conductor layer has an overlapping relationship with the first gate dielectric layer, the first portion of the second gate dielectric layer, and the second portion of the second gate dielectric layer.

[0005] In an embodiment, a method for forming a structure for an extended drain metal oxide semiconductor device is provided. The method includes: forming a source region in a semiconductor layer; forming a drain region in the semiconductor layer; and forming a gate positioned between the source region and the drain region. The gate includes a gate conductor layer, a first gate dielectric layer having a first thickness, and a second gate dielectric layer having a second thickness greater than the first thickness. The first gate dielectric layer is disposed on a top surface of the semiconductor layer. The second gate dielectric layer includes a first portion located on the top surface of the semiconductor layer and a second portion adjacent to a sidewall of the semiconductor layer. The gate conductor layer has an overlapping relationship with the first gate dielectric layer, the first portion of the second gate dielectric layer, and the second portion of the second gate dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the present invention and, together with the general description of the present invention given above and the detailed description of the embodiments given below, are used to explain embodiments of the present invention. In the accompanying drawings, the same reference numerals represent the same features in each view.

[0007] Figure 1 is a top view of a structure at an initial manufacturing stage according to an embodiment of the present invention.

[0008] Figure 2 It is roughly along Figure 1 A cross-sectional view taken along line 2-2 in FIG.

[0009] Figure 2A It is roughly along Figure 1 A cross-sectional view taken along line 2A-2A in FIG.

[0010] Figure 3 is Figure 1 , 2 , a top view of the structure at the manufacturing stage after 2A.

[0011] Figure 4 It is roughly along Figure 3 A cross-sectional view taken along line 4-4 in FIG.

[0012] Figure 4A It is roughly along Figure 3 A cross-sectional view taken along line 4A-4A in FIG.

[0013] Figure 5 is Figure 3 , 4 , a top view of the structure at the manufacturing stage after 4A.

[0014] Figure 6 It is roughly along Figure 5 A cross-sectional view taken along line 6-6 in FIG.

[0015] Fig. 6A It is roughly along Figure 5 A cross-sectional view taken along line 6A-6A in FIG.

[0016] Figure 6B It is roughly along Figure 5 A cross-sectional view taken along line 6B-6B in FIG.

[0017] Figure 7 , 7A 7B is in Figure 5 , 6 , 6A, and 6B are cross-sectional views of the structure at the manufacturing stage after. DETAILED DESCRIPTION

[0018] refer to Figure 1 , 2 , 2A, and according to an embodiment of the present invention, a semiconductor-on-insulator substrate including a semiconductor layer 12, a buried insulator layer 14, and a semiconductor substrate 16 can be used to form a structure 10 for an extended drain metal oxide semiconductor device. The semiconductor layer 12 and the semiconductor substrate 16 can be composed of a semiconductor material such as single crystal silicon. The buried insulator layer 14 can be composed of a dielectric material such as silicon dioxide. The semiconductor layer 12 is separated from the semiconductor substrate 16 by the dielectric material of the buried insulator layer 14 in between. The buried insulator layer 14 has a lower interface with the semiconductor substrate 16 and an upper interface with the semiconductor layer 12. The semiconductor layer 12 is electrically isolated from the semiconductor substrate 16 by the buried insulator layer 14.

[0019] A shallow trench isolation region 18 may be formed in the semiconductor layer 12. In an embodiment, the shallow trench isolation region 18 may be formed by applying and patterning a hard mask, etching a trench using the patterned hard mask, depositing a dielectric material (e.g., silicon dioxide) in the trench, and planarizing using chemical mechanical polishing. The shallow trench isolation region 18 may surround a device region of the semiconductor layer 12. In an embodiment, the shallow trench isolation region 18 may completely penetrate the semiconductor layer 12 to the buried insulator layer 14.

[0020] The semiconductor layer 12 may include an upper portion composed of an epitaxial semiconductor material added to thicken the semiconductor layer 12 in the device region. In an embodiment, the epitaxial semiconductor material may be added to the semiconductor layer 12 after forming the shallow trench isolation region 18. The epitaxial semiconductor material added to the semiconductor layer 12 may be composed of a semiconductor material (e.g., single crystal silicon) formed by a selective epitaxial growth process.

[0021] The upper portion of the thickened semiconductor layer 12 protrudes at an altitude above the level of the shallow trench isolation region 18. The upper portion of the semiconductor layer 12 is raised relative to the shallow trench isolation region 18. The upper portion of the semiconductor layer 12 may have a sidewall 20, a sidewall 22 opposite to the sidewall 20, a sidewall 24, a sidewall 26 opposite to the sidewall 24, and a top surface 25. The sidewalls 20, 22, 24, 26 arranged around the periphery of the upper portion of the semiconductor layer 12 may be shared with the lower portion of the semiconductor layer 12. In an embodiment, the sidewall 24 of the semiconductor layer 12 may be aligned parallel to or substantially parallel to the sidewall 26 of the semiconductor layer 12. The sidewalls 20, 22, 24, 26 of the upper portion of the semiconductor layer 12 may extend from the shallow trench isolation region 18 to the top surface 25 of the semiconductor layer 12 in a vertical direction. The sidewalls 24, 26 of the upper portion of the semiconductor layer 12 may extend from the sidewall 20 to the sidewall 22 in a lateral direction.

[0022] Structure 10 may include doped regions 28, 30, 32 formed in respective portions of semiconductor layer 12. Doped regions 28 and 30 may extend in a vertical direction over the entire thickness of semiconductor layer 12 to buried insulator layer 14. Doped region 32 may extend over a portion of the thickness of semiconductor layer 12. Doped regions 28, 30, 32 may extend in a lateral direction from sidewall 24 to sidewall 26, and doped regions 28, 30, 32 may abut top surface 25.

[0023] In an embodiment, the doped regions 28, 30, 32 may include a concentration of n-type dopants (e.g., arsenic or phosphorus) to provide n-type conductivity. The doped region 28 may be formed by selectively implanting ions (e.g., ions including n-type dopants) with an implantation mask having an opening that defines the intended location of the doped region 28 in the semiconductor layer 12. The doped region 30 may be formed by selectively implanting ions (e.g., ions including n-type dopants) with an implantation mask having an opening that defines the intended location of the doped region 30 in the semiconductor layer 12. The doped region 32 may be formed by selectively implanting ions (e.g., ions including n-type dopants) with an implantation mask having an opening that defines the intended location of the doped region 32 in the semiconductor layer 12. The implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to adjust the electrical and physical properties of the doped regions 28, 30, 32. Doped regions 28 , 32 may be heavily doped with an n-type dopant, and doped region 30 may be lightly doped with a lower concentration of n-type dopant than doped regions 28 , 32 .

[0024] The structure 10 may include doped regions 34, 36 formed in respective portions of the semiconductor layer 12. The doped regions 34, 36 may each extend in a vertical direction over the entire thickness of the semiconductor layer 12 to the buried insulator layer 14. The doped region 32 may be disposed in a portion of the doped region 36 adjacent to the doped region 34. The doped regions 34, 36 may extend in a lateral direction from the sidewall 24 to the sidewall 26, and the doped regions 34, 36 may abut the top surface 25.

[0025] In an embodiment, the doped regions 34, 36 may contain a concentration of p-type dopants (e.g., boron) to provide p-type conductivity. The doped regions 34 may be formed by selectively implanting ions (e.g., ions including p-type dopants) with an implantation mask having an opening that defines the intended location of the doped regions 34 in the semiconductor layer 12. The doped regions 36 may be formed by selectively implanting ions (e.g., ions including p-type dopants) with an implantation mask having an opening that defines the intended location of the doped regions 36 in the semiconductor layer 12. The implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to adjust the electrical and physical properties of the doped regions 34, 36. The doped regions 34 may be heavily doped with p-type dopants, and the doped regions 36 may be more lightly doped with p-type dopants at a lower concentration than the doped regions 34.

[0026] Doped region 28 may define a drain region of the extended drain metal oxide semiconductor device, doped region 30 may define a drift region of the extended drain metal oxide semiconductor device, and doped region 32 may define a source region of the extended drain metal oxide semiconductor device. Doped region 36 may define a body of the extended drain metal oxide semiconductor device, and doped region 34 may define a body contact. Sidewalls 24, 26 that overlap the drain region, source region, drift region, body, and body contact extend in a lateral direction from the source region to the drain region.

[0027] refer to Figure 3 , 4 , 4A, wherein the same reference numerals refer to Figure 1 , 2 , 2A, and at a subsequent manufacturing stage, structure 10 may include a gate dielectric layer 38 formed on an upper portion of semiconductor layer 12. In an embodiment, gate dielectric layer 38 may be composed of silicon dioxide. In an embodiment, gate dielectric layer 38 may be composed of silicon dioxide formed by thermal oxidation of the semiconductor material of semiconductor layer 12. Although not shown, the formation of gate dielectric layer 38 may consume a thin surface layer of semiconductor layer 12. In an embodiment, gate dielectric layer 38 may have a thickness in a range of about 100 nanometers (nm) to about 300 nm.

[0028] The gate dielectric layer 38 covers all surfaces of the upper portion of the semiconductor layer 12. In this regard, the gate dielectric layer 38 overlaps all sidewalls 20, 22, 24, 26 and the top surface 25 of the upper portion of the semiconductor layer 12. The gate dielectric layer 38 wraps around the edges and corners of the upper portion of the semiconductor layer 12 defined by the respective intersections of the sidewalls 20, 22, 24, 26 and the top surface 25. In an embodiment, the gate dielectric layer 38 on the sidewalls 20, 22, 24, 26 and the top surface 25 may have a uniform thickness T. In an alternative embodiment, the gate dielectric layer 38 on the sidewalls 20, 22, 24, 26 and the top surface 25 may have a substantially uniform thickness T1. In an embodiment, the gate dielectric layer 38 may directly contact the sidewalls 20, 22, 24, 26 and the top surface 25.

[0029] refer to Figure 5 , 6 , 6A, 6B, wherein the same reference numerals refer to Figure 3 , 4 , 4A, and in a subsequent manufacturing stage, the gate dielectric layer 38 can be patterned by photolithography and etching processes to define portions 42, 44, 46. Portion 42 of the gate dielectric layer 38 is disposed on the top surface 25 of the semiconductor layer 12. In an embodiment, after the gate dielectric layer 38 is patterned, the top surface 25 between the portion 42 and each sidewall 20, 22 can be exposed. Portion 42 of the gate dielectric layer 38 overlaps the drift region defined by the doped region 30. Portion 44 of the gate dielectric layer 38 is disposed adjacent to the sidewall 24 of the upper portion of the semiconductor layer 12. Portion 46 of the gate dielectric layer 38 is disposed adjacent to the sidewall 26 of the upper portion of the semiconductor layer 12. In an embodiment, portions 44, 46 of the gate dielectric layer 38 can be disposed on the respective sidewalls 24, 26. Portion 44 of gate dielectric layer 38 overlaps a portion of the adjacent sidewall 24 of shallow trench isolation region 18, and portion 46 of gate dielectric layer 38 overlaps a portion of the adjacent sidewall 26 of shallow trench isolation region 18. Portion 42 of gate dielectric layer 38 may extend across top surface 25 of semiconductor layer 12 from portion 44 of gate dielectric layer 38 to portion 46 of gate dielectric layer 38 such that portion 44 is connected to portion 46 by a strip of dielectric material.

[0030] refer to Figure 7 , 7A , 7B, wherein the same reference numerals refer to Figure 5 , 6A, 6B, and in a subsequent manufacturing stage, a gate 50 is formed, the gate 50 including a gate conductor layer 52 and a gate dielectric layer 54 overlapped and covered by the gate conductor layer 52. The gate dielectric layer 54 is composed of a dielectric material such as silicon dioxide. In an embodiment, the gate dielectric layer 54 can be formed by thermal oxidation of the semiconductor layer 12 not covered by the portions 42, 44, 46 of the gate dielectric layer 38. The gate dielectric layer 54 overlaps a portion of the drift region defined by the doped region 30 and a portion of the body defined by the doped region 36. The gate dielectric layer 54 has a thickness T2, and the thickness T1 of the portions 42, 44, 46 of the gate dielectric layer 38 is greater than the thickness T2. In an embodiment, the thickness T1 can be at least twice the thickness T2. The gate conductor layer 52 can be composed of a conductor such as doped polysilicon. The gate 50 is defined by patterning the gate conductor layer 52 and the gate dielectric layer 54 using photolithography and etching processes.

[0031] Gate conductor layer 52 overlaps a portion of portion 42 of gate dielectric layer 38 on top surface 25. Gate conductor layer 52 overlaps a portion of portion 44 of gate dielectric layer 38 at sidewall 24. The overlapping portion of portion 44 is disposed between respective non-overlapping portions of portion 44 along sidewall 22. Gate conductor layer 52 overlaps a portion of portion 46 of gate dielectric layer 38 at sidewall 26. The overlapping portion of portion 46 is disposed between respective non-overlapping portions of portion 46 along sidewall 26. Portion 42 of gate dielectric layer 38 is vertically disposed between a portion of gate conductor layer 52 and semiconductor layer 12, portion 44 of gate dielectric layer 38 is laterally disposed between a portion of gate conductor layer 52 and semiconductor layer 12 at sidewall 24, and portion 46 of gate dielectric layer 38 is laterally disposed between a portion of gate conductor layer 52 and semiconductor layer 12 at sidewall 26.

[0032] The double thickness of dielectric material provided by portions 42, 44, 46 of thick gate dielectric layer 38 and thin gate dielectric layer 54 can function to improve performance metrics of the extended drain metal oxide semiconductor device during device operation. The double thickness of dielectric material provided by portions 42, 44, 46 of thick gate dielectric layer 38 and thin gate dielectric layer 54 can reduce or eliminate the presence of charge trapping centers at the drift region defined by doped region 30 or under gate 50, which can reduce limitations on breakdown voltage and transients of the extended drain metal oxide semiconductor device. The double thickness of dielectric material provided by portions 42, 44, 46 of thick gate dielectric layer 38 and thin gate dielectric layer 54 can function to increase breakdown voltage. The double thickness of dielectric material provided by portions 42, 44, 46 of thick gate dielectric layer 38 and thin gate dielectric layer 54 can also function to reduce transients.

[0033] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. The chips can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate product or a final product. The final product can be any product that includes an integrated circuit chip, such as a computer product or a smartphone with a central processing unit.

[0034] References herein to terms modified by approximate language such as "approximately," "about," "substantially" are not limited to the exact value specified. Approximate language may correspond to the precision of the instrument used to measure the value, and, unless instrument precision is relied upon, + / - 10% of the stated value(s) may be indicated.

[0035] References to terms such as "vertical", "horizontal", etc. herein are by way of example and not limitation to establish a frame of reference. As used herein, the term "horizontal" is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to directions perpendicular to the horizontal direction just defined. The term "lateral" refers to a direction within a horizontal plane.

[0036] A feature that is "connected" or "coupled" to or "connected to" or "coupled to" another feature may be directly connected or coupled to or to the other features, or one or more intermediate features may be present. A feature may be "directly connected" or "directly coupled" to or "directly connected to" or "directly coupled to" another feature if there are no intermediate features. A feature may be "indirectly connected" or "indirectly coupled" to or "indirectly connected to" or "indirectly coupled to" another feature if there is at least one intermediate feature. A feature that is "on" or "contacting" another feature may be directly on or in direct contact with the other features, or one or more intermediate features may be present. A feature may be "directly on" or "directly in contact with" another feature if there are no intermediate features. A feature may be "indirectly on" or "indirectly in contact with" another feature if there is at least one intermediate feature. Different features may "overlap" if one feature extends over another feature and covers a portion of another feature.

[0037] The description of various embodiments of the present invention is given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are intended to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found on the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure for an extended drain metal oxide semiconductor device, the structure comprising: a semiconductor layer comprising a first sidewall and a top surface; a source region located in the semiconductor layer; a drain region located in the semiconductor layer; as well as A gate is positioned between the source region and the drain region, the gate comprising a gate conductor layer, a first gate dielectric layer having a first thickness, and a second gate dielectric layer having a second thickness greater than the first thickness, the first gate dielectric layer is located on the top surface of the semiconductor layer, the second gate dielectric layer comprises a first portion located on the top surface of the semiconductor layer and a second portion adjacent to the first sidewall of the semiconductor layer, and the gate conductor layer has an overlapping relationship with the first gate dielectric layer, the first portion of the second gate dielectric layer, and the second portion of the second gate dielectric layer.

2. The structure according to claim 1, further comprising: A shallow trench isolation region is located in the semiconductor layer, The second portion of the second dielectric layer overlaps the shallow trench isolation region.

3. The structure according to claim 2, further comprising: substrate; as well as a dielectric layer located on the substrate, The semiconductor layer is disposed on the dielectric layer, and the shallow trench isolation region passes through the semiconductor layer to reach the dielectric layer.

4. The structure according to claim 2, wherein: The semiconductor layer includes a device region surrounded by the shallow trench isolation region, and the device region includes a portion protruding above the shallow trench isolation region.

5. The structure according to claim 2, wherein: The first sidewall of the semiconductor layer extends from the shallow trench isolation region to the top surface of the semiconductor layer.

6. The structure according to claim 1, wherein: The first sidewall extends from the source region to the drain region.

7. The structure according to claim 1, wherein: The semiconductor layer includes a second sidewall, and the second gate dielectric layer includes a third portion adjacent to the second sidewall of the semiconductor layer.

8. The structure according to claim 7, wherein: The first portion of the second gate dielectric layer extends across the top surface of the semiconductor layer from the second portion of the second gate dielectric layer to the third portion of the second gate dielectric layer.

9. The structure according to claim 8, wherein: The first sidewall of the semiconductor layer is aligned parallel to the second sidewall of the semiconductor layer.

10. The structure according to claim 8, wherein: The first gate dielectric layer extends across the top surface of the semiconductor layer from the second portion of the second gate dielectric layer to the third portion of the second gate dielectric layer.

11. The structure according to claim 7, wherein: The second portion of the second gate dielectric layer is disposed on the first sidewall of the semiconductor layer, and the third portion of the second gate dielectric layer is disposed on the second sidewall of the semiconductor layer.

12. The structure according to claim 7, wherein: The second portion of the second gate dielectric layer is laterally located between the gate conductor layer and the semiconductor layer at the first sidewall, and the third portion of the second gate dielectric layer is laterally located between the gate conductor layer and the semiconductor layer at the second sidewall.

13. The structure according to claim 7, wherein: The gate conductor layer overlaps a portion of the second portion of the second gate dielectric layer, and the gate conductor layer overlaps a portion of the third portion of the second gate dielectric layer.

14. The structure according to claim 1, wherein: The second portion of the second gate dielectric layer is disposed on the first sidewall of the semiconductor layer.

15. The structure according to claim 14, wherein: The second portion of the second gate dielectric layer directly contacts the first sidewall of the semiconductor layer.

16. The structure of claim 1, wherein: The gate conductor layer overlaps a first portion of the second portion of the second gate dielectric layer.

17. The structure according to claim 16, wherein: The drain region includes a first doped region located in the semiconductor layer, the source region includes a second doped region located in the semiconductor layer, the second portion of the second gate dielectric layer includes a second portion adjacent to the first doped region, and the second portion of the second gate dielectric layer includes a third portion adjacent to the second doped region.

18. The structure of claim 1, wherein: The second thickness of the second gate dielectric layer is in a range from about 100 nanometers to about 300 nanometers.

19. The structure of claim 1, wherein: The first portion of the second gate dielectric layer is vertically located between the gate conductor layer and the semiconductor layer, and the second portion of the second gate dielectric layer is laterally located between the gate conductor layer and the semiconductor layer at the first sidewall.

20. A method of forming a structure for an extended drain metal oxide semiconductor device, the method comprising: forming a source region in the semiconductor layer; forming a drain region in the semiconductor layer; as well as forming a gate positioned between the source region and the drain region, Wherein, the gate includes a gate conductor layer, a first gate dielectric layer having a first thickness, and a second gate dielectric layer having a second thickness greater than the first thickness, the first gate dielectric layer is arranged on the top surface of the semiconductor layer, the second gate dielectric layer includes a first portion located on the top surface of the semiconductor layer and a second portion adjacent to the side wall of the semiconductor layer, and the gate conductor layer has an overlapping relationship with the first gate dielectric layer, the first portion of the second gate dielectric layer, and the second portion of the second gate dielectric layer.

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