Shield gate trench field-effect transistor integrated with buffer and preparation method of shield gate trench field-effect transistor

Abstract

The invention provides a shield gate trench field effect transistor integrated with a buffer and a preparation method thereof, and belongs to the technical field of power semiconductors, and the preparation method comprises the steps: arranging an RC buffer between a source electrode and a drain electrode of the shield gate trench field effect transistor; the RC buffer comprises a floating island region and a body region, the floating island region is a high-resistance floating island region, and junction capacitance is formed between the body region and the epitaxial layer of the carrier. The beneficial effects are that when LC oscillation occurs, bypass is carried out through the RC buffer, voltage spike and high-frequency oscillation are effectively suppressed, and robustness and EMI characteristics of a device are improved; meanwhile, a resistor in the RC buffer is formed by the high-resistance-state floating island region, a capacitor is formed by a junction capacitor formed between the body region and the epitaxial layer, and the variable capacitance is realized due to the fact that the junction capacitor changes along with the change of withstand voltage; in addition, the method is compatible with a preparation process of a traditional SGT device, is convenient to implement and low in operation cost, and has good industrial value.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductors, and in particular to a shielded gate trench field effect transistor with an integrated buffer and a preparation method thereof. Background Art

[0002] Shielded Gate Trench Metal-Oxide-Semiconductor Field-Effect Transistor (SGT MOSFET) devices have the advantages of low characteristic on-resistance and small Miller capacitance (Cgd), which greatly reduces the conduction loss (mainly caused by on-resistance) and switching loss (mainly caused by Miller capacitance) generated by the device during operation. Therefore, SGT MOSFET devices are widely used in various application fields such as load switching, short-circuit protection, bridge drive, etc.

[0003] However, while pursuing low power consumption and high efficiency, SGT MOSFET devices have a Miller capacitance of only 10% of that of traditional trench MOSFETs, which greatly shortens the Miller platform time during the switching process and dramatically increases the switching speed. The above oscillations introduced in the same application environment will be more severe, and the device will face the problem of large voltage change rate (dv / dt) and current change rate (di / dt) shocks. Especially in specific high-current application scenarios, the impact resistance and robustness of SGT devices are relatively weak. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides a shielded gate trench field effect transistor with integrated buffer and a preparation method thereof.

[0005] The technical problem solved by the present invention can be achieved by adopting the following technical solutions:

[0006] A shielded gate trench field effect transistor with integrated buffer, wherein an RC buffer is arranged between a source and a drain of the shielded gate trench field effect transistor;

[0007] The RC buffer includes a floating island region and a body region, wherein the floating island region is a high-resistance floating island region, and a junction capacitor is formed between the body region and an epitaxial layer of a carrier.

[0008] Preferably, the carrier comprises a substrate and an epitaxial layer formed on the upper surface of the substrate; the substrate and the epitaxial layer both have a first conductivity type; and the substrate is formed by a heavy doping process, and the epitaxial layer is formed by a light doping process;

[0009] The shielded gate trench field effect transistor is formed in the active region of the epitaxial layer;

[0010] The RC snubber is formed in a protection area of ​​the epitaxial layer.

[0011] Preferably, the shielded gate trench field effect transistor comprises:

[0012] A plurality of first trenches are formed in the active region of the epitaxial layer, and a gate polysilicon electrode is disposed on the top of the first trench;

[0013] A plurality of second trenches are formed in the protection area of ​​the epitaxial layer, and source polysilicon electrodes are provided at the bottom and top of the second trenches and the bottom of the first trench;

[0014] A body region of a second conductivity type is formed in a region of the epitaxial layer excluding the first trench and the second trench, and a junction capacitor is formed between the body region located in the protection region and the epitaxial layer;

[0015] A source region having a first conductivity type is formed in the body region of the active region.

[0016] Preferably, it also includes:

[0017] a dielectric layer formed on the upper surface of the epitaxial layer;

[0018] A plurality of contact holes, penetrating the dielectric layer into the body region;

[0019] A source metal layer is formed on the upper surface of the dielectric layer and filled in the contact hole.

[0020] Preferably, the high-resistance floating island region is located between two adjacent second trenches.

[0021] Preferably, the bottom of the high-resistance floating island region is at least higher than the bottom of the second groove by a first preset value;

[0022] The top of the high-resistance floating island region is at least a second preset value lower than the bottom of the body region.

[0023] Preferably, the first preset value is 0.3 μm;

[0024] The second preset value is 0.3 μm.

[0025] Preferably, the high-resistance floating island region is formed by a light doping process.

[0026] Preferably, the high-resistance floating island region and the epitaxial layer have the same conductivity type.

[0027] The present invention also provides a method for preparing a shielded gate trench field effect transistor with an integrated buffer, which is used to prepare the shielded gate trench field effect transistor with an integrated buffer as described above, comprising:

[0028] An RC buffer is formed between the source and drain of the shielded gate trench field effect transistor; the RC buffer includes a floating island region and a body region, the floating island region is a high-resistance floating island region, and a junction capacitor is formed between the body region and the epitaxial layer of the carrier.

[0029] The advantages or beneficial effects of the technical solution of the present invention are:

[0030] The present invention integrates an RC buffer in a shielded gate trench field effect transistor. When LC oscillation occurs, the RC buffer is used for bypassing, thereby effectively suppressing voltage spikes and high-frequency oscillations, and improving the robustness and electromagnetic interference (EMI) characteristics of the device. At the same time, a high-resistance floating island area is used to form a resistor in the RC buffer, and a junction capacitor formed between a body area and an epitaxial layer forms a capacitor. Since the junction capacitance changes with the withstand voltage, a variable capacitance is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is an equivalent circuit diagram of a power MOSFET device in the prior art;

[0032] Figure 2 It is a structural schematic diagram of a traditional SGT MOSFET device in the prior art;

[0033] Figure 3 The equivalent circuit diagram of the shielded gate trench field effect transistor with integrated buffer in the preferred embodiment of the present invention;

[0034] Figure 4 An equivalent circuit diagram of an RC snubber in a preferred embodiment of the present invention;

[0035] Figure 5 It is a structural schematic diagram of a shielded gate trench field effect transistor with integrated buffer in a preferred embodiment of the present invention;

[0036] Figure 6 An equivalent diagram of a shielded gate trench field effect transistor with integrated buffer in a preferred embodiment of the present invention;

[0037] Figure 7 A schematic diagram of the distribution of active areas and protection areas in a preferred embodiment of the present invention;

[0038] Figure 8 A schematic diagram of a preparation method in a preferred embodiment of the present invention;

[0039] Figure 9-15 It is a structural schematic diagram of each step in the preparation method in a preferred embodiment of the present invention.

[0040] Description of reference numerals:

[0041] 100, active area; 200, protection area; 1, carrier; 11, substrate; 12, epitaxial layer; 20, first trench; 21, second trench; 201, first oxide layer; 202, first source polysilicon electrode; 203, second oxide layer; 204, gate polysilicon electrode; 211, second source polysilicon electrode; 3, body region; 4, source region; 5, dielectric layer; 6, contact hole; 7, source metal layer; 8, high-resistance floating island region; 120, first photoresist blocking layer; 121, photoresist shielding region; 122, photoresist window region; 123, second photoresist blocking layer. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0044] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0045] In practical applications of power MOSFET devices, the parasitic inductance in the printed circuit board (PCB) wiring and the leakage inductance of discrete devices (such as resistors and capacitors) form an equivalent inductance Lpa in series with the MOSFET device. The equivalent inductance Lpa and the drain-source parasitic capacitance Coss of the MOSFET device together form an LC oscillation loop, such as Figure 1 shown.

[0046] During the switching process of MOSFET, especially during the shutdown process, the energy accumulated in the parasitic equivalent inductance Lpa needs to be released through the loop, interacting with the drain-source parasitic capacitance Coss, resulting in voltage spikes and high-frequency oscillations in the drain-source voltage Vds. The larger the loop current during conduction, the larger the voltage spike and the more violent the oscillation.

[0047] SGT MOSFET devices have a small Miller capacitance Cgd and fast switching time. Therefore, under the same application environment, the above oscillations introduced by SGT MOSFET devices will be more intense than those of ordinary MOSFET devices. SGT MOSFET devices have the advantages of small characteristic on-resistance and small Miller capacitance Cgd, which result in smaller conduction and switching losses during operation. They are increasingly used in various short-circuit protection and half-bridge drive scenarios. In actual circuit waveforms, especially in fast drive environments, the above Vds oscillations are easily stimulated, which further causes the MOSFET tube to burn out as the short circuit and load current increase. This is also an important reason why many MOSFET tubes have insufficient short-circuit tolerance and insufficient device robustness in actual applications.

[0048] like Figure 2 The schematic diagram of the structure of a conventional SGT MOSFET device is shown. The device includes a carrier 1, a first trench 20, a P-type body region 3, an N+-type source region 4, a dielectric layer 5, a contact hole 6, and a source metal layer 7; wherein the carrier 1 includes an N+-type substrate 11 and an N--type epitaxial layer 12 formed on the substrate 11.

[0049] The first trench 20 is a shielding gate trench, including a first oxide layer 201, a first source polysilicon electrode 202, a second oxide layer 203 and a gate polysilicon electrode 204; wherein, the first oxide layer 201 is located at the bottom and side walls of the trench, and the first source polysilicon electrode 202 is filled in the first oxide layer 201; the second oxide layer 203 is located above the first oxide layer 201 and the first source polysilicon electrode 202 and on the side walls of the trench, and the gate polysilicon electrode 204 is filled in the second oxide layer 203.

[0050] Furthermore, an interlayer isolation layer (not shown in the figure) is further included between the first source polysilicon electrode 202 and the gate polysilicon electrode 204 .

[0051] The embodiment of the present invention proposes a novel SGT MSOFET device with an integrated RC snubber structure between the drain and source. The circuit schematic diagram is shown in FIG. Figure 3 The Snubber buffer structure can bypass the voltage spike and oscillation on the drain-source voltage Vds through the RC loop when the system LC oscillates, effectively suppressing the voltage spike and oscillation, greatly improving the impact resistance of the device in various extreme situations, and enhancing the device robustness and EMI characteristics.

[0052] The RC snubber circuit, also known as the absorption circuit, is an important protection circuit for power electronic devices.

[0053] RC snubber circuit as Figure 4 As shown, the mechanism of suppressing voltage spikes and absorbing oscillations is:

[0054] The capacitive reactance formula of the parallel capacitor Cs is:

[0055] Xc=1 / 2πfC;

[0056] Where, f is the signal frequency; C is the capacitance value; Xc is the capacitive reactance value.

[0057] It can be seen that as the signal frequency f increases, the capacitive reactance value Xc decreases.

[0058] When voltage spikes and oscillations occur outside the protected unit due to various reasons, such as LC oscillation, the frequency of the voltage spikes and oscillations is very high, nearly 100 megahertz.

[0059] The capacitance C is set to a value between tens and hundreds of pf; at this level, the capacitive reactance Xc is approximately in the order of tens of milliohms; such a small capacitive reactance is equivalent to a short-circuit state relative to the high-frequency signal, and the high-frequency signal will be directly discharged through the capacitor Cs of the RC buffer, thereby protecting the protected unit in parallel.

[0060] The resistor Rs of the RC snubber acts as an oscillation damper and is a damping unit that absorbs and suppresses ringing.

[0061] Based on the existing process and design of SGT MOSFET, the present invention skillfully integrates the RC snubber protection circuit inside the device, which advantageously improves the shortcoming of SGT MOSFET, that is, poor impact resistance in certain specific harsh working environments due to its fast switching speed, suppresses the voltage spike and ringing of the SGT MOSFET device, and effectively improves the robustness and EMI characteristics of the device; and the method has good compatibility with the original SGT MOSFET design and process, low economic cost, significant effect, and has very important application expansion significance and industrial value.

[0062] See also Figure 5 and Figure 6 In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a shielded gate trench field effect transistor with integrated buffer is provided, comprising:

[0063] An RC snubber is provided between the source and drain of a shielded gate trench field effect transistor (SGT MOSFET);

[0064] The RC buffer includes a floating island region and a body region. The floating island region is a high-resistance floating island region 8 . A junction capacitor is formed between the body region 3 and the epitaxial layer 12 of the carrier 1 , which is denoted as Cs.

[0065] In this embodiment, the RC buffer includes a resistor Rs and a capacitor Cs, which are connected in series between the drain and the source of the SGTMOSFET device.

[0066] In this embodiment, the high-resistance floating island region serves as the resistor Rs of the RC buffer; the PN junction capacitor formed between the body region 3 located in the protection area and the epitaxial layer 12 serves as the capacitor Cs of the RC buffer.

[0067] Furthermore, the PN junction capacitor is a variable capacitor. When the withstand voltages at both ends of the PN junction are different, the thickness of the PN junction depletion layer will be different, and the capacitance of the PN junction capacitor will change accordingly.

[0068] Compared with the fixed capacitor structure, the PN junction capacitor of the present invention has a variable capacitance, a relatively large capacitance, and can achieve a good buffering effect; moreover, when buffering the external peak current Iincrush signal, the variable capacitor can bear more current sharing. If a fixed capacitor structure is used, this current sharing effect cannot be achieved.

[0069] As a preferred embodiment, the carrier 1 includes a substrate 11 and an epitaxial layer 12 formed on the upper surface of the substrate 11; the substrate 11 and the epitaxial layer 12 both have a first conductivity type; and the substrate 11 is formed by a heavy doping process, and the epitaxial layer 12 is formed by a light doping process;

[0070] The shielded gate trench field effect transistor is formed in the active region of the epitaxial layer 12;

[0071] The RC snubber is formed in the protection area of ​​the epitaxial layer 12 .

[0072] Specifically, in this embodiment, the device carrier is single crystal silicon, including a substrate 11 and an epitaxial layer 12 .

[0073] The device structure is mainly in the epitaxial layer 12 region.

[0074] In this embodiment, the substrate 11 and the epitaxial layer 12 have the same conductivity type but different doping concentrations.

[0075] In this embodiment, the substrate 11 is an N+ type substrate; and the epitaxial layer 12 is an N- type substrate.

[0076] It should be noted that N+ type, N type, N- type, P+ type, P type and P- type all refer to different doping concentrations. Specifically, the doping concentration of N- type is less than that of N type, the doping concentration of N type is less than that of N+ type, the doping concentration of P- type is less than that of P type, and the doping concentration of P type is less than that of P+ type.

[0077] As a preferred embodiment, the shielded gate trench field effect transistor includes:

[0078] A plurality of first trenches 20 are formed in the active region of the epitaxial layer 12, and a gate polysilicon electrode is disposed on the top of the first trenches 20;

[0079] A plurality of second trenches 21 are formed in the protection area of ​​the epitaxial layer 12, and source polysilicon electrodes are provided at the bottom and top of the second trenches 21 and the bottom of the first trench 20;

[0080] A body region 3 of the second conductivity type is formed in the epitaxial layer 12 in a region other than the first trench 20 and the second trench 21, and a junction capacitor is formed between the body region 3 in the protection region and the epitaxial layer 12;

[0081] A source region 4 having a first conductivity type is formed in the body region 3 of the active region.

[0082] Specifically, the first conductivity type is opposite to the second conductivity type. In this embodiment, the first conductivity type is N type and the second conductivity type is P type as an example.

[0083] That is, the conductivity type of the body region 3 is opposite to the conductivity type of the epitaxial layer 12 to form a PN junction capacitor, which serves as the capacitor Cs of the RC buffer.

[0084] Further, a gate polysilicon electrode 202 is formed on the top of the first trench 20;

[0085] The source polysilicon electrode is formed at the bottom of the first trench 20 and the bottom and top of the second trench 21 .

[0086] Specifically, the source polysilicon electrode includes a first source polysilicon electrode 201 and a second source polysilicon electrode 202 ; wherein the first source polysilicon electrode 201 is formed at the bottom of the first trench 20 and the bottom of the second trench 21 ; and the second source polysilicon electrode 202 is formed at the top of the second trench 21 .

[0087] The first trench 20 in the active region has the same structure as that of the existing SGT MOSFET device.

[0088] The second trench 21 in the protection area has a similar internal structure to the first trench 20 in the active area, except that the gate polysilicon electrode at the top of the trench is replaced by a source polysilicon electrode. That is, there is no gate polysilicon electrode 202 in the second trench 21, and the bottom and top polysilicon electrodes are both source polysilicon electrodes.

[0089] In this embodiment, since the second trench 21 and the first trench 20 use different top polysilicon, the protection zone will not involve the SGT MOSFET when forming resistance or adjusting, which simplifies the control process, reduces process costs, and increases device economic benefits.

[0090] As a preferred embodiment, the invention further comprises:

[0091] A dielectric layer 5 formed on the upper surface of the epitaxial layer 12;

[0092] A plurality of contact holes 6, penetrating the dielectric layer 5 to the body region 3;

[0093] The source metal layer 7 is formed on the upper surface of the dielectric layer 5 and fills the contact hole 6 .

[0094] As a preferred embodiment, the high-resistance floating island region 8 is located between two adjacent second trenches 21 .

[0095] Specifically, the high-resistance floating island region 8 is located in the protection area and between two adjacent second trenches and between the second trench and the edge of the device.

[0096] As a preferred embodiment, the bottom of the high-resistance floating island region 8 is at least higher than the bottom of the second trench 21 by a first preset value;

[0097] The top of the high-resistance floating island region 8 is lower than the bottom of the body region 3 by at least a second preset value.

[0098] Specifically, in the present embodiment, the junction depth range of the high-resistance floating island region 8 is set above a first preset value calculated from the bottom of the trench, and at the same time is maintained below a second preset value calculated from the junction depth of the P-type body region 3, to ensure that after the subsequent heat treatment diffusion process, the high-resistance floating island region 8 can remain within the depth range of the trench, while being closely combined with the PN junction capacitor at its top to improve protection efficiency; at the same time, its resistance value is easier to control, thereby achieving more optimized performance.

[0099] As a preferred embodiment, the first preset value is 0.3 μm;

[0100] The second preset value is 0.3 μm.

[0101] Specifically, in the present embodiment, the junction depth of the high-resistance floating island region 8 is set to be greater than 0.3 μm from the bottom of the trench and less than 0.3 μm from the junction depth of the P-type body region 3 .

[0102] As a preferred embodiment, the high-resistance floating island region 8 is formed by a light doping process.

[0103] As a preferred embodiment, the high-resistance floating island region 8 and the epitaxial layer 12 have the same conductivity type.

[0104] Specifically, the doping element type of the high-resistance floating island region 8 is opposite to the doping element type of the epitaxial layer 12. For example, the epitaxial layer 12 uses a first doping element type, such as phosphorus; the high-resistance floating island region 8 uses a second doping element type, such as boron. By using doping with elements of opposite doping types, the element concentration of the original epitaxial layer 12 is neutralized, and at the same time, it is necessary to ensure that the doping concentration is reduced without changing the original doping conductivity type, so as to improve the resistivity.

[0105] In this embodiment, the high-resistance floating island region 8 has a first conductivity type.

[0106] Specifically, in this embodiment, the high-resistance floating island region 8 includes an N-type high-resistance floating island.

[0107] The present invention provides an SGT MOSFET device structure with an internally integrated RC snubber, such as Figure 7 As shown, the overall structure consists of the SGT MOSFET region (active region) and the Snubber region (buffer protection region).

[0108] The SGT MOSFET region is the active region of the structure and includes a shielded gate trench field effect transistor, which is the same as a conventional SGT MOSFET device and is responsible for the functional work of the MOS device.

[0109] The shielded gate trench field effect transistor comprises a first trench 20, a P-type body region 3, an N+ type source region 4 and a source metal layer 7. The first trench 20 has a first oxide layer 201, a second oxide layer 203 and a polysilicon electrode; wherein the first oxide layer 201 is thick oxide, the second oxide layer 203 is thin gate oxide, and the polysilicon electrode is divided into bottom polysilicon and top polysilicon, the bottom polysilicon is the first source polysilicon electrode 201, and the top polysilicon is the gate polysilicon electrode 202. The first source polysilicon electrode 201 is used to assist in the establishment of a blocking electric field, and the gate polysilicon electrode 202 is used to control the establishment and closing of the device channel.

[0110] The RC snubber area is the RC protection circuit area, which includes the second trench 21, the N-type high-resistance floating island area 8, the P-type body area 3 and the source metal layer 7. The second trench 21 has a similar internal structure to the first trench 20, except that there is no gate polysilicon electrode 202, and the bottom and top polysilicon are both source polysilicon electrodes. It does not play any role when the device is in normal operation, but works when the device drain-source voltage Vds is disturbed and oscillated by the spike voltage, protects the device, absorbs and releases the spike signal, and smoothes the Vds output waveform.

[0111] Furthermore, the RC snubber region and the SGT MOSFET region are process compatible, and the structural differences and implementation methods are:

[0112] Compared with the SGT MOSFET region, an N-type high-resistance floating island region 8 is added between the trenches of the RC snubber region. This is achieved by performing high-energy implantation of boron elements in the RC snubber region before trench etching. Boron is a P-type impurity element that can neutralize and reduce the phosphorus doping concentration of the original N-epitaxial layer, thereby forming a high-resistance floating island. This high-resistance floating island region is the resistor Rs in the RC buffer.

[0113] Compared with the SGT MOSFET region, the RC snubber region has no heavily doped N+ type source region, and in the RC snubber region, the P-type body region 3 and the N-type epitaxial layer 12 form a PN junction capacitor Cs. The N+ type source region shielding is achieved by adjusting the N+ type source region layout drawing. The P-type body region 3 injection is compatible with the original MOSFET process and is an overall carpet injection.

[0114] The internal physical structure of the second trench 21 in the RC snubber area is exactly the same as the first trench 20 in the SGT MOSFET area, except that: since it has no MOS function, no gate control electrode is required, and the bottom polysilicon and top polysilicon of the trench in this area are both set as source polysilicon electrodes; this point is realized in the layout drawing of the contact hole layout, and the process is fully compatible with the SGTMOSFET area.

[0115] The present invention also provides a method for preparing a shielded gate trench field effect transistor with an integrated buffer, which is used to prepare the shielded gate trench field effect transistor with an integrated buffer as described above. Figure 8 As shown, including:

[0116] Step S1, providing a carrier 1, the carrier 1 comprising a substrate 11 and an epitaxial layer 12 formed on an upper surface of the substrate 11;

[0117] The substrate 11 is an N+ type substrate heavily doped with N type, and an N− type epitaxial layer 12 is formed on the substrate 11 .

[0118] Step S2, forming a high-resistance floating island region 8 in the protection area of ​​the epitaxial layer 12;

[0119] like Fig. 9 and Fig.10 As shown, with the first photoresist blocking layer 120 as a mask, the device carrier is divided into a photoresist shielding area 121 and a photoresist window area 122; selective high-energy implantation of high-resistance floating islands in the RC Snubber area is performed on the epitaxial layer 12, wherein only the window implantation is performed in the RC snubber area, and the SGT MOSFET area is shielded by the photoresist.

[0120] Regarding the selection of injection conditions, take 100V SGT as an example:

[0121] The resistivity specification of the N-type epitaxial layer 12 used in the current 100V SGT MOSFET is about 0.3Ω*cm, and the thickness is in the range of 9μm. The resistivity of the N-type epitaxial layer 12 is 0.3Ω*cm, which is converted into a phosphorus doping concentration of 1.87E16 / cm 3 At this time, in order to obtain a floating island with a certain range of high resistance in the epitaxial layer 12, the method adopted is: using P-type boron element doping of the opposite doping type to neutralize the phosphorus concentration in the original N-type epitaxial layer 12.

[0122] For 1.87E16 / cm 3 The phosphorus doping concentration can be 0~1.4E16 / cm 3 The boron implantation concentration is reduced to achieve the purpose of not changing the original doping conductivity type but reducing the doping concentration and increasing the resistivity.

[0123] As a preferred embodiment, the present invention can use 1E16 / cm 3 The doping concentration is injected into the body, and the concentration fed back to the injection surface is the injected impurity is boron, and the injection dose is about 1E12 / cm 2 .

[0124] Regarding the selection of the implantation energy of the high-resistance floating island region 8, the implantation energy is determined by inverse deduction based on the required junction depth.

[0125] In the embodiment of the present invention, the junction depth of the high-resistance floating island region 8 needs to be defined as more than 0.3 μm from the bottom of the trench and less than 0.3 μm from the junction depth of the P-type body region 3. The purpose is to ensure that after subsequent thermal diffusion, the high-resistance floating island can be clamped within the trench depth, closely combined with the PN junction capacitor on its top, improve protection efficiency, and make the resistance value more controllable.

[0126] Taking a 100V SGT MOSFET as an example, the junction depth of the second trench 21 is about 5.8μm, and the junction depth of the P-type body region 3 is 0.8μm. Therefore, the floating island injection range needs to be controlled outside 1.1μm and within 5.5μm. In view of the energy limitation of the implanter, the embodiment of the present invention can select an injection range of 1.1 to 1.8um. ​​By looking up the injection range table, the corresponding injection energy is in the energy range of 500KEV to 1.4Mev.

[0127] Based on the above analysis, for 100V SGT MOSFET, the implantation conditions of the N-type high-resistance floating island region 8 are: the implantation element is boron, the implantation energy is 1Mev, and the implantation dose is 1E12, so as to form the following: Fig.10 The high-resistance floating island region 8 is shown.

[0128] It should be noted that the above-mentioned injection condition selection of the high-resistance floating island region 8 is only a rough method guide, and specific simulation adjustment can be carried out using simulation software.

[0129] For device types with other voltages, suitable injection conditions can be obtained by referring to the above general method, which will not be repeated here.

[0130] The embodiment of the present invention forms the floating island resistor by ion implantation. The resistance value of the resistor can be adjusted by adjusting the implantation dosage. The resistor is compatible with the conventional SGT MOSFET process and does not require any additional process.

[0131] Step S3, forming a plurality of first trenches 20 in the active area, forming a plurality of second trenches 21 in the protection area, and forming a body region 3 in the epitaxial layer 12 except the first trenches 20 and the second trenches 21; wherein a junction capacitor is formed between the body region 3 in the protection area and the epitaxial layer 12;

[0132] like Fig.11 As shown, the trench and the oxide layer in the trench, the polysilicon electrode are formed, and the P-type body region 3 is implanted and annealed. This process is completely consistent with the conventional SGT MOSFET process and will not be repeated here;

[0133] Step S4, forming a source region 4 in the body region 3 of the active region;

[0134] like Fig.12 and Fig.13 As shown, the second photoresist shielding layer 123 is used as an N+ type source region photomask, and selective implantation of N+ type source region doping is performed in the photoresist window area 122 .

[0135] Preferably, the implantation conditions are conventional conditions of SGT MOSFET, the implantation element is arsenic, the implantation energy is 50 KeV, and the implantation dose is 6E15.

[0136] Step S5, forming a dielectric layer 5 on the upper surface of the epitaxial layer 12, wherein the dielectric layer 5 includes a plurality of contact holes 6 penetrating the dielectric layer 5 to the body region 2;

[0137] like Fig.14 and 15 As shown, silicon dioxide is deposited to form a dielectric layer 5; then, contact holes 6 are photolithographically and etched on the dielectric layer 5; the layout diagram is shown in FIG. Fig.14 As shown, the device process structure is shown in Fig.15 shown.

[0138] As a preferred embodiment, the dielectric layer 5 is deposited to a thickness of

[0139] Preferably, the lithography and etching steps of the contact hole 6 are the determining steps for defining the polycrystalline electrodes in the grooves. In the first trench 20 of the SGTMOSFET region, the bottom polycrystalline silicon is defined as the source polycrystalline silicon electrode, and the top polycrystalline silicon is defined as the gate polycrystalline silicon electrode 202; and in the second trench 21 of the RC Snubber region, the bottom polycrystalline silicon and the top polycrystalline silicon are both in contact and defined as the source polycrystalline silicon electrode.

[0140] Step S6 , forming a source metal layer 7 on the upper surface of the dielectric layer 5 , and filling the contact hole 6 with the source metal layer 7 .

[0141] Specifically, metal is sputtered and etched on the surface of the device prepared in step S5, and finally a Figure 5 The device structure shown.

[0142] Furthermore, the deposition and etching of the passivation layer and the formation of the back surface process may be performed, which is consistent with the conventional SGTMOSFET and will not be described in detail here.

[0143] The advantages or beneficial effects of adopting the above technical solution are: the present invention integrates an RC buffer in the shielded gate trench field effect transistor, and when LC oscillation occurs, the RC buffer is used for bypass, thereby effectively suppressing voltage spikes and high-frequency oscillations, and improving the robustness and electromagnetic interference (EMI) characteristics of the device; at the same time, the high-resistance floating island area is used to form the resistor in the RC buffer, and the junction capacitance formed between the body area and the epitaxial layer constitutes the capacitance. Since the junction capacitance changes with the withstand voltage, variable capacitance is achieved; in addition, the device of the present invention is compatible with the traditional SGT manufacturing process platform, the process implementation cost is low, and the practicability is strong.

[0144] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the contents of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. A shielded gate trench field effect transistor with integrated buffer, characterized in that: An RC buffer is provided between the source and the drain of the shielded gate trench field effect transistor; The RC buffer includes a floating island region and a body region, wherein the floating island region is a high-resistance floating island region, and a junction capacitor is formed between the body region and an epitaxial layer of a carrier.

2. The shielded gate trench field effect transistor with integrated buffer according to claim 1, characterized in that: The carrier includes a substrate and an epitaxial layer formed on the upper surface of the substrate; the substrate and the epitaxial layer both have a first conductivity type; and the substrate is formed by a heavy doping process, and the epitaxial layer is formed by a light doping process; The shielded gate trench field effect transistor is formed in the active region of the epitaxial layer; The RC snubber is formed in a protection area of ​​the epitaxial layer.

3. The shielded gate trench field effect transistor with integrated buffer according to claim 1, characterized in that: The shielded gate trench field effect transistor comprises: A plurality of first trenches are formed in the active region of the epitaxial layer, and a gate polysilicon electrode is disposed on the top of the first trench; A plurality of second trenches are formed in the protection area of ​​the epitaxial layer, and source polysilicon electrodes are provided at the bottom and top of the second trenches and the bottom of the first trench; A body region of a second conductivity type is formed in a region of the epitaxial layer excluding the first trench and the second trench, and a junction capacitor is formed between the body region located in the protection region and the epitaxial layer; A source region having a first conductivity type is formed in the body region of the active region.

4. The shielded gate trench field effect transistor with integrated buffer according to claim 3, characterized in that: Also includes: a dielectric layer formed on the upper surface of the epitaxial layer; A plurality of contact holes, penetrating the dielectric layer into the body region; A source metal layer is formed on the upper surface of the dielectric layer and filled in the contact hole.

5. The shielded gate trench field effect transistor with integrated buffer according to claim 3, characterized in that: The high-resistance floating island region is located between two adjacent second trenches.

6. The shielded gate trench field effect transistor with integrated buffer according to claim 3, characterized in that: The bottom of the high-resistance floating island region is at least a first preset value higher than the bottom of the second groove; The top of the high-resistance floating island region is at least a second preset value lower than the bottom of the body region.

7. The shielded gate trench field effect transistor with integrated buffer according to claim 6, characterized in that: The first preset value is 0.3 μm; The second preset value is 0.3 μm.

8. The shielded gate trench field effect transistor with integrated buffer according to claim 1, characterized in that: The high-resistance floating island region is formed by a light doping process.

9. The shielded gate trench field effect transistor with integrated buffer according to claim 1, characterized in that: The high-resistance floating island region and the epitaxial layer have the same conductivity type.

10. A method for preparing a shielded gate trench field effect transistor with an integrated buffer, characterized in that: A shielded gate trench field effect transistor for preparing an integrated buffer as claimed in any one of claims 1 to 9, comprising: An RC buffer is formed between the source and drain of the shielded gate trench field effect transistor; the RC buffer includes a floating island region and a body region, the floating island region is a high-resistance floating island region, and a junction capacitor is formed between the body region and the epitaxial layer of the carrier.

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