Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and electronic equipment, and relates to but not limited to a semiconductor technology. The semiconductor device comprises a channel arranged on one side of a substrate, an interface layer arranged on the side, away from the substrate, of the channel and a first gate dielectric layer arranged on the side, away from the substrate, of the interface layer, the material of the channel comprises a silicon-germanium compound, the material of the interface layer at least comprises silicon oxide, and the material of the first gate dielectric layer at least comprises silicon oxide. The interface layer is formed by oxidizing and growing the surface of the channel and is connected with the channel into a whole; therefore, the interface layer quality is ensured and the interface state density is reduced.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to but are not limited to semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the rapid development of integrated circuit technology, planar bulk silicon MOS devices face severe challenges. In order to improve device performance, 3D structure devices (such as FINFET, nanowires) have replaced traditional planar devices. In order to further improve device performance, high mobility materials such as silicon germanium, germanium, III-V compounds, etc., have replaced silicon materials as channel materials for devices.

[0003] For silicon germanium-based transistors, the difficulty lies in how to obtain a high-quality stacked structure of gate dielectric layer / interface layer / silicon germanium channel. The interface layer obtained by traditional oxidation methods has a high proportion of germanium oxide, which is unstable and easily causes the interface layer quality to deteriorate and the interface state density to increase. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] An embodiment of the present disclosure provides a semiconductor device, comprising: a channel arranged on one side of a substrate, an interface layer arranged on a side of the channel away from the substrate, and a first gate dielectric layer arranged on a side of the interface layer away from the substrate, wherein the material of the channel comprises a silicon-germanium compound, the material of the interface layer comprises at least silicon oxide, and the interface layer is grown by oxidation of the surface of the channel and is connected to the channel as a whole.

[0006] In an exemplary embodiment, the content of the silicon oxide in the interface layer is 95%-100%.

[0007] In an exemplary embodiment, the chemical formula of the silicon germanium compound is Si1-xGex, where x is greater than 0 and less than 1.

[0008] In an exemplary embodiment, the material of the interface layer further comprises germanium oxide, and the content of the germanium oxide in the interface layer is less than or equal to 5%.

[0009] In an exemplary embodiment, the thickness of the interface layer is less than or equal to 2 nanometers.

[0010] In an exemplary embodiment, the interface layer and the first gate dielectric layer are connected as one body.

[0011] In an exemplary embodiment, the thickness of the first gate dielectric layer is less than or equal to 2 nanometers.

[0012] In an exemplary embodiment, the first gate dielectric layer is a high dielectric constant material.

[0013] In an exemplary embodiment, a second gate dielectric layer is further included, and the second gate dielectric layer is disposed on a side of the first gate dielectric layer away from the substrate.

[0014] In an exemplary embodiment, the second gate dielectric layer is connected to the first gate dielectric layer as a whole.

[0015] In an exemplary embodiment, the second gate dielectric layer is a high dielectric constant material.

[0016] In an exemplary embodiment, the second gate dielectric layer is made of the same material as or different from the first gate dielectric layer.

[0017] The present disclosure also provides a method for manufacturing a semiconductor device, including:

[0018] forming a channel on a substrate, wherein the material of the channel comprises a silicon germanium compound;

[0019] Under vacuum conditions, using a weak oxidant and an atomic layer deposition process, a first gate dielectric layer is formed on a side of the channel away from the substrate;

[0020] Under vacuum conditions, a strong oxidant is used to perform strong oxidation treatment on the first gate dielectric layer, and a surface at the junction of the channel and the first gate dielectric layer is oxidized to form an interface layer, wherein the material of the interface layer at least includes silicon oxide.

[0021] In an exemplary embodiment, the material of the first gate dielectric layer is metal.

[0022] In an exemplary embodiment, the weak oxidizing agent is isopropyl ketone.

[0023] In an exemplary embodiment, the strong oxidant includes at least one of ozone, hydrogen peroxide, and active oxygen plasma.

[0024] In an exemplary embodiment, after the first gate dielectric layer is subjected to strong oxidation treatment and the surface of the junction between the channel and the first gate dielectric layer is oxidized to form an interface layer, the method further includes:

[0025] A second gate dielectric layer is formed on a side of the first gate dielectric layer away from the substrate by using a strong oxidant and an atomic layer deposition process.

[0026] An embodiment of the present disclosure also provides an electronic device, comprising the aforementioned semiconductor device.

[0027] The semiconductor device of the disclosed embodiment can stabilize the interface layer by oxidizing the grown interface layer on the surface of the channel, thereby ensuring the quality of the interface layer and reducing the interface state density.

[0028] The semiconductor device of the disclosed embodiment uses a weak oxidant to form a first gate dielectric layer through an atomic layer deposition process, thereby preventing the channel surface from being oxidized during the formation of the first gate dielectric layer, and preventing the channel surface from being oxidized to form an interface layer during the formation of the first gate dielectric layer.

[0029] The semiconductor device of the disclosed embodiment uses a strong oxidant to oxidize the first gate dielectric layer to improve the quality of the first gate dielectric layer, and oxidizes the surface at the junction of the channel and the first gate dielectric layer to form an interface layer. During this oxidation process, the first gate dielectric layer has a blocking effect on oxygen atoms, so that a small amount of oxygen atoms diffuse to the surface at the junction of the channel and the first gate dielectric layer. Since the silicon element in the channel is more easily combined with oxygen atoms, the oxygen atoms are combined with the silicon element in the channel to form an interface layer, which increases the formation of silicon oxide in the interface layer and effectively reduces the formation of germanium oxide in the interface layer, thereby ensuring the quality of the interface layer and reducing the interface state density.

[0030] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The objects and advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description and the drawings.

[0031] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution.

[0033] Figure 1 A schematic cross-sectional view of a semiconductor device provided as an exemplary embodiment;

[0034] Figure 2 A schematic diagram of a semiconductor device after forming a channel according to an exemplary embodiment;

[0035] Figure 3 It is a schematic diagram of a semiconductor device after forming a first gate dielectric layer according to an exemplary embodiment;

[0036] Figure 4 FIG. 1 is a schematic diagram of a semiconductor device after forming an interface layer according to an exemplary embodiment. DETAILED DESCRIPTION

[0037] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0038] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by one of ordinary skill in the art to which the present invention belongs.

[0039] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0040] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0041] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0042] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0043] In the present disclosure, a transistor refers to an element including at least three terminals: a gate, a drain electrode, and a source electrode. The transistor has a first channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the first channel region, and the source electrode. In the present disclosure, the first channel region refers to a region where current mainly flows.

[0044] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0045] In the present disclosure, "electrical connection" includes the situation where components are connected together through an element having some kind of electrical function. There is no particular limitation on the "element having some kind of electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some kind of electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0046] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0047] In the present disclosure, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film" in some cases. Similarly, "insulating film" may be replaced with "insulating layer" in some cases.

[0048] The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0049] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.

[0050] An embodiment of the present disclosure provides a semiconductor device, comprising: a channel arranged on one side of a substrate, an interface layer arranged on a side of the channel away from the substrate, and a first gate dielectric layer arranged on a side of the interface layer away from the substrate, wherein the material of the channel comprises a silicon-germanium compound, the material of the interface layer comprises at least silicon oxide, and the interface layer is grown by oxidation of the surface of the channel and is connected to the channel as a whole.

[0051] In some embodiments, the content of the silicon oxide in the interface layer is 95%-100%.

[0052] In some embodiments, the chemical formula of the silicon germanium compound is Si1-xGex, where x is greater than 0 and less than 1.

[0053] In some embodiments, the material of the interface layer further includes germanium oxide, and the content of the germanium oxide in the interface layer is less than or equal to 5%.

[0054] The semiconductor device disclosed in the present invention is described below by way of some exemplary embodiments.

[0055] Figure 1 FIG. 1 is a cross-sectional schematic diagram of a semiconductor device provided by an exemplary embodiment. In an exemplary embodiment, as Figure 1 As shown, the semiconductor device includes: a channel 101 arranged on one side of a substrate, an interface layer 11 arranged on the side of the channel 101 away from the substrate, a first gate dielectric layer 12 arranged on the side of the interface layer 11 away from the substrate, and a second gate dielectric layer 13 arranged on the side of the first gate dielectric layer 12 away from the substrate.

[0056] In an exemplary embodiment, the material of the channel 101 includes a silicon germanium compound, and the chemical formula of the silicon germanium compound is Si 1-x Ge x , and x is greater than 0 and less than 1.

[0057] In an exemplary embodiment, the interface layer 11 is formed by oxidation growth of the surface of the channel 101 and is connected to the channel 101 as a whole. The material of the interface layer 11 includes at least silicon oxide, and the silicon oxide in the interface layer 11 is formed by oxidation of silicon elements in the channel 101. The content of silicon oxide in the interface layer 11 is 95%-100%. The surface of the channel 101 is the surface close to the interface layer 11.

[0058] In an exemplary embodiment, the material of the interface layer 11 further includes germanium oxide, and the germanium oxide in the interface layer 11 is formed by oxidizing the germanium element in the channel 101. The content of the germanium oxide in the interface layer 11 is less than or equal to 5%.

[0059] In an exemplary embodiment, the material of the interface layer 11 can be composed only of silicon oxide, and the germanium element in the channel 101 is not oxidized to form the interface layer 11, that is, the content of silicon oxide in the interface layer is 100%, and the content of germanium in the interface layer 11 is 0, thereby ensuring the quality of the interface layer 11 and reducing the interface state density.

[0060] In an exemplary embodiment, the material of the interface layer 11 can be composed only of silicon oxide and germanium oxide. In the process of forming the interface layer 11, the content of silicon element oxidized in the channel 101 is much greater than the content of germanium element oxidized, thereby ensuring the quality of the interface layer 11 and reducing the interface state density. For example, the content of silicon oxide in the interface layer 11 is 95%, and the content of germanium oxide in the interface layer 11 is 5%.

[0061] In the process of forming the interface layer 11 by oxidizing the surface of the channel 101 of the semiconductor device of the embodiment of the present disclosure, the first gate dielectric layer 12 has a blocking effect on oxygen atoms, so that a small amount of oxygen atoms diffuse to the surface at the junction of the channel 101 and the first gate dielectric layer 12. Since the silicon elements in the channel 101 are more easily combined with oxygen atoms, the oxygen atoms are combined with the silicon elements in the channel 101 to form the interface layer 11, thereby increasing the formation of silicon oxide in the interface layer 11 and effectively reducing the formation of germanium oxide in the interface layer 11, thereby ensuring the quality of the interface layer 11 and reducing the interface state density.

[0062] In an exemplary embodiment, the interface layer 11 is connected as a whole with the first gate dielectric layer 12. The interface layer 11 is connected as a whole with the first gate dielectric layer 12 means that the interface layer 11 and the first gate dielectric layer 12 can be connected as a whole using different materials; or the interface layer 11 and the first gate dielectric layer 12 can be connected as a whole using the same material.

[0063] In an exemplary embodiment, the thickness of the interface layer 11 is less than or equal to 2 nanometers. For example, the thickness of the interface layer 11 is greater than or equal to 0.5 nanometers and less than or equal to 1.5 nanometers. The thickness of the interface layer 11 is determined by the type and thickness of the first gate dielectric layer material and the process parameters of the subsequent strong oxidation treatment.

[0064] In an exemplary embodiment, the first gate dielectric layer 12 is disposed on a surface of the interface layer 11 away from the channel 101, and the first gate dielectric layer 12 can be connected to the interface layer 11 as a whole. The first gate dielectric layer 12 can be a high dielectric constant material. Among them, the high dielectric constant material refers to a dielectric material with a dielectric constant K ≥ 3.9. For example, the high dielectric constant material can be a metal oxide, for example, aluminum oxide, hafnium oxide, hafnium aluminum oxide, and hafnium lanthanum oxide.

[0065] In an exemplary embodiment, the thickness of the first gate dielectric layer 12 is less than or equal to 2 nanometers. For example, the thickness of the first gate dielectric layer 12 is greater than or equal to 0.5 nanometers and less than or equal to 1.5 nanometers.

[0066] In an exemplary embodiment, the second gate dielectric layer 13 is disposed on a surface of the first gate dielectric layer 12 away from the channel 101, and the second gate dielectric layer 13 can be connected to the first gate dielectric layer 12 as a whole. The second gate dielectric layer 13 can be a high dielectric constant material. For example, the second gate dielectric layer 13 can be a metal oxide, for example, aluminum oxide, hafnium oxide, hafnium aluminum oxide, or hafnium lanthanum oxide.

[0067] In an exemplary embodiment, the second gate dielectric layer 13 may be made of the same material as or different from the first gate dielectric layer 12 .

[0068] In an exemplary embodiment, the semiconductor device of the present disclosure may be used in a planar device or a 3D device. For example, the semiconductor device of the present disclosure may be used in a fin field effect (FinFET) transistor, a nanowire transistor, and the like.

[0069] The present disclosure provides a method for manufacturing a semiconductor device, comprising:

[0070] forming a channel on a substrate, wherein the material of the channel comprises a silicon germanium compound;

[0071] Under vacuum conditions, using a weak oxidant and an atomic layer deposition process, a first gate dielectric layer is formed on a side of the channel away from the substrate;

[0072] Under vacuum conditions, a strong oxidant is used to perform strong oxidation treatment on the first gate dielectric layer, and a surface at the junction of the channel and the first gate dielectric layer is oxidized to form an interface layer, wherein the material of the interface layer at least includes silicon oxide.

[0073] In an exemplary embodiment, the weak oxidizing agent is isopropyl ketone.

[0074] In an exemplary embodiment, the strong oxidant includes at least one of ozone, hydrogen peroxide, and active oxygen plasma.

[0075] In an exemplary embodiment, forming a first gate dielectric layer includes: under vacuum conditions, first introducing a first precursor for growing the first gate dielectric layer to form a first precursor film on the channel, then purging the remaining first precursor, then using a weak oxidant to weakly oxidize the first precursor film to form a first gate dielectric film, and finally purging the remaining weak oxidant to complete a cycle; repeating the above cycles multiple times to form the first gate dielectric layer.

[0076] In an exemplary embodiment, after the first gate dielectric layer is subjected to strong oxidation treatment and the surface of the junction between the channel and the first gate dielectric layer is oxidized to form an interface layer, the method further includes:

[0077] A second gate dielectric layer is formed on a side of the first gate dielectric layer away from the substrate by using a strong oxidant and an atomic layer deposition process.

[0078] In an exemplary embodiment, forming the second gate dielectric layer includes: under vacuum conditions, first introducing a second precursor for growing the second gate dielectric layer to form a second precursor film on the channel, then purging the remaining second precursor film, then using a strong oxidant to strongly oxidize the second precursor film to form a second gate dielectric film, and finally purging the remaining strong oxidant to complete a cycle; repeating the above cycles multiple times to form the second gate dielectric layer.

[0079] The technical solution of this embodiment is further explained below through the manufacturing process of the semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of film layer, mask exposure and development, which are mature manufacturing processes in related technologies. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" still requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0080] In an exemplary embodiment, a process for manufacturing a semiconductor device may include:

[0081] Step 101: forming a channel.

[0082] Forming a channel includes: forming a channel 101 on a semiconductor substrate, such as Figure 2 The material of the channel 101 includes a silicon germanium compound, and the chemical formula of the silicon germanium compound is Si 1-x Ge x , and x is greater than 0 and less than 1.

[0083] Step 102: forming a first gate dielectric layer.

[0084] The first gate dielectric layer is formed by: forming a first gate dielectric layer 12 on the surface of the channel 101 by an atomic layer deposition process using a weak oxidant under vacuum conditions on the basis of the substrate having the aforementioned pattern, wherein the first gate dielectric layer 12 is connected to the channel 101 as a whole; in the process of forming the first gate dielectric layer 12, due to the use of a weak oxidant for oxidation treatment, the surface at the junction of the channel 101 and the first gate dielectric layer 12 is not oxidized, so that no interface layer is formed on the surface at the junction of the channel 101 and the first gate dielectric layer 12, such as Figure 3 Wherein, the weak oxidant is isopropyl ketone.

[0085] Step 103: forming an interface layer.

[0086] The formation of the interface layer comprises: on the basis of the substrate having the aforementioned pattern, under vacuum conditions, using a strong oxidant to perform a strong oxidation treatment on the first gate dielectric layer 13 to improve the film quality of the first gate dielectric layer, and oxidizing the surface at the junction of the channel 101 and the first gate dielectric layer 13 to form an interface layer 11, wherein the material of the interface layer 11 at least comprises silicon oxide, and the content of the silicon oxide in the interface layer 11 is 95%-100%, such as Figure 4 shown.

[0087] Wherein, the strong oxidant includes at least one of ozone, hydrogen peroxide and active oxygen plasma. The process conditions for strong oxidation treatment of the first gate dielectric layer 12 using a strong oxidant may be the same as or different from the process conditions for forming the first gate dielectric layer using a weak oxidant. For example, the temperature, oxidation time and pressure for strong oxidation treatment of the first gate dielectric layer 12 using a strong oxidant are the same as or different from the temperature, oxidation time and pressure for forming the first gate dielectric layer using a weak oxidant.

[0088] In the process of forming the interface layer 11 in the embodiment of the present disclosure, the first gate dielectric layer 12 has a blocking effect on oxygen atoms, so that a small amount of oxygen atoms diffuse to the surface at the junction of the channel 101 and the first gate dielectric layer 12. Since the silicon elements in the channel 101 are more easily combined with oxygen atoms, the oxygen atoms are combined with the silicon elements in the channel 101 to form the interface layer 11, thereby increasing the formation of silicon oxide in the interface layer 11 and effectively reducing the formation of germanium oxide in the interface layer 11, thereby ensuring the quality of the interface layer 11 and reducing the interface state density.

[0089] Step 104: forming a second gate dielectric layer.

[0090] The second gate dielectric layer is formed by: forming a second gate dielectric layer 13 on the surface of the first gate dielectric layer 12 by an atomic layer deposition process under vacuum conditions using a strong oxidant, and the second gate dielectric layer 13 is connected to the first gate dielectric layer 12 as a whole, such as Figure 1 The strong oxidant includes at least one of ozone, hydrogen peroxide and active oxygen plasma; the second gate dielectric layer 13 can be made of the same material as or different from the first gate dielectric layer 12 .

[0091] The present disclosure also provides an electronic device, including the semiconductor device described in any of the above embodiments. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include a memory in a computer, etc., which is not limited here.

[0092] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A semiconductor device, characterized in that: include: A channel is arranged on one side of the substrate, an interface layer is arranged on the side of the channel away from the substrate, and a first gate dielectric layer is arranged on the side of the interface layer away from the substrate. The material of the channel includes a silicon-germanium compound, the material of the interface layer includes at least silicon oxide, and the interface layer is grown by oxidation of the surface of the channel and is connected to the channel as a whole.

2. The semiconductor device according to claim 1, wherein: The content of the silicon oxide in the interface layer is 95%-100%.

3. The semiconductor device according to claim 1, wherein: The chemical formula of the silicon germanium compound is Si 1- x Ge x , x is greater than 0 and less than 1.

4. The semiconductor device according to claim 1, wherein: The material of the interface layer further includes germanium oxide, and the content of the germanium oxide in the interface layer is less than or equal to 5%.

5. The semiconductor device according to claim 1, wherein: The thickness of the interface layer is less than or equal to 2 nanometers.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that: The interface layer is connected to the first gate dielectric layer as a whole.

7. The semiconductor device according to any one of claims 1 to 5, characterized in that: The thickness of the first gate dielectric layer is less than or equal to 2 nanometers.

8. The semiconductor device according to any one of claims 1 to 5, characterized in that: The first gate dielectric layer is a high dielectric constant material.

9. The semiconductor device according to any one of claims 1 to 5, characterized in that: The invention also includes a second gate dielectric layer, wherein the second gate dielectric layer is arranged on a side of the first gate dielectric layer away from the substrate.

10. The semiconductor device according to claim 9, characterized in that The second gate dielectric layer is connected to the first gate dielectric layer as a whole.

11. The semiconductor device according to claim 9, characterized in that The second gate dielectric layer is made of a high dielectric constant material.

12. The semiconductor device according to claim 9, characterized in that The second gate dielectric layer and the first gate dielectric layer may be made of the same or different material.

13. A method for manufacturing a semiconductor device, characterized in that: include: forming a channel on a substrate, wherein the material of the channel comprises a silicon germanium compound; Under vacuum conditions, using a weak oxidant and an atomic layer deposition process, a first gate dielectric layer is formed on a side of the channel away from the substrate; Under vacuum conditions, a strong oxidant is used to perform strong oxidation treatment on the first gate dielectric layer, and a surface at the junction of the channel and the first gate dielectric layer is oxidized to form an interface layer, wherein the material of the interface layer at least includes silicon oxide.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The weak oxidant is isopropyl ketone.

15. The method for manufacturing a semiconductor device according to claim 13, wherein: The strong oxidant includes at least one of ozone, hydrogen peroxide and active oxygen plasma.

16. The method for manufacturing a semiconductor device according to claim 13, wherein: After the first gate dielectric layer is subjected to strong oxidation treatment and the surface of the junction between the channel and the first gate dielectric layer is oxidized to form an interface layer, the method further includes: A second gate dielectric layer is formed on a side of the first gate dielectric layer away from the substrate by using a strong oxidant and an atomic layer deposition process.

17. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 12.

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