Preparation method of stacked transistor, stacked transistor and semiconductor device

Abstract

The invention provides a preparation method of a stacked transistor, the stacked transistor and a semiconductor device. The method comprises the steps of performing primary etching on a semiconductor substrate to form a stack structure, wherein the stack structure comprises an active structure and a first sacrificial layer; forming a pseudo gate structure covering the stacked structure in the gate region; etching the stack structure which is not covered by the pseudo gate structure to form a first deep groove; epitaxially growing a first source drain structure in the first deep groove based on the first active structure in the gate region; removing the pseudo gate structure and the first sacrificial layer to expose the active structure in the gate region; depositing a gate dielectric material on the exposed active structure to form a gate dielectric layer; depositing a metal material on the first gate dielectric layer to form a first gate electrode layer; reversing and removing the semiconductor substrate; epitaxially growing a second source drain structure in the first deep groove based on a second active structure in the gate region; and depositing a metal material on the second gate dielectric layer to form a second gate electrode layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chip manufacturing, and in particular to a method for preparing a stacked transistor, a stacked transistor and a semiconductor device. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] In some schemes for preparing stacked transistors, active areas of upper and lower layers of homologous transistors are formed by etching, and stacked transistors are made on the front and back sides of the wafer by flipping the wafer. This can also be called a "self-aligned flip transistor" scheme. However, in the "self-aligned flip transistor" scheme, high aspect ratio processes need to be used multiple times, which will lead to problems such as high processing difficulty, easy occurrence of gaps, uneven etching rate, and insufficient bottom etching. Therefore, there is a certain room for optimization in the "self-aligned flip transistor" scheme. Summary of the invention

[0004] The present application provides a method for preparing a stacked transistor, a stacked transistor and a semiconductor device to optimize a "self-aligned flip-chip transistor" solution.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a stacked transistor, comprising: etching a stacked structure on a semiconductor substrate once, wherein the stacked structure comprises an active structure and a first sacrificial layer, and the active structure comprises a first active structure and a second active structure; the first active structure, the second active structure and the first sacrificial layer are stacked in sequence in a first direction, the first active structure is farther away from the semiconductor substrate than the first sacrificial layer, and the first direction is a direction perpendicular to the semiconductor substrate; in a gate region of the stacked transistor, a pseudo gate structure covering the stacked structure is formed; etching the stacked structure not covered by the pseudo gate structure to form a first deep trench; based on the first active structure in the gate region, epitaxially growing a first source-drain structure in the first deep trench; removing the pseudo gate structure; and The invention relates to a method for producing a semiconductor device for producing a semiconductor device and a semiconductor substrate, wherein the semiconductor device comprises a semiconductor layer and a first sacrificial layer to expose the active structure in the gate region; depositing a gate dielectric material on the exposed active structure to form a gate dielectric layer, wherein the gate dielectric layer comprises a first gate dielectric layer and a second gate dielectric layer, wherein the first gate dielectric layer wraps the first active structure, and the second gate dielectric layer wraps the second active structure; depositing a metal material on the first gate dielectric layer to form a first gate electrode layer, wherein the first gate dielectric layer and the first gate electrode layer together constitute a first gate structure; inverting the semiconductor substrate and removing the semiconductor substrate; epitaxially growing a second source-drain structure in the first deep trench based on the second active structure in the gate region; depositing a metal material on the second gate dielectric layer to form a second gate electrode layer, wherein the second gate dielectric layer and the second gate electrode layer together constitute a second gate structure.

[0006] In some possible embodiments, before epitaxially growing a first source-drain structure in a first deep trench based on a first active structure in the gate region, the method further includes: depositing an oxide material in the first deep trench to form a first filling structure, wherein a height of the first filling structure is less than a height of the first active structure and greater than a height of the second active structure; depositing an insulating material on the first filling structure to form an isolation layer, wherein the isolation layer is used to isolate the first source-drain structure from the second source-drain structure; before epitaxially growing a second source-drain structure in the first deep trench based on the second active structure in the gate region, the method further includes: removing the first filling structure in the first deep trench to expose the second active structure in the gate region.

[0007] In some possible embodiments, the active structure also includes: a second sacrificial layer, the second sacrificial layer is located between the first active structure and the second active structure; etching the stacked structure not covered by the dummy gate structure to form a first deep trench, including: etching the first active structure not covered by the dummy gate structure, the second sacrificial layer, the second active structure and the first sacrificial layer to form a first deep trench; in the gate area, depositing an insulating material at the position where the second sacrificial layer is removed to form an isolation structure.

[0008] In some possible embodiments, etching a stacked structure on a semiconductor substrate once includes: forming an initial stacked structure and an initial barrier layer on the semiconductor substrate, wherein the initial barrier layer is located between the initial stacked structure and the semiconductor substrate; etching the initial stacked structure and the initial barrier layer once to form a stacked structure and a barrier layer; depositing an oxide material on the semiconductor substrate to form a shallow trench isolation structure, wherein the shallow trench isolation structure wraps the barrier layer; after etching the stacked structure not covered by the dummy gate structure to form a first deep trench, the method further includes: etching the barrier layer at the bottom of the first deep trench to form a The method further comprises: forming an etched barrier layer, wherein the etched barrier layer is located in the gate region; depositing an oxide material at the position where the barrier layer is etched to form a second filling structure; inverting the wafer and removing the semiconductor substrate, including: inverting the wafer and removing the semiconductor substrate to expose the etched barrier layer and the shallow trench isolation structure; removing the shallow trench isolation structure and retaining the etched barrier layer; before epitaxially growing a second source-drain structure in the first deep trench based on a second active structure in the gate region, the method further comprises: sequentially etching the second filling structure and the first filling structure not covered by the etched barrier layer until the isolation layer is exposed.

[0009] In some possible embodiments, when the stacked transistor is a full-surround gate field effect transistor, the first active structure and the second active structure are both formed by alternatingly stacking channel layers and sacrificial layers; after etching the stacked structure not covered by the dummy gate structure to form a first deep trench, the method further includes: laterally etching the sacrificial layer in the active structure in the gate region to a preset depth; depositing insulating material at the position where the sacrificial layer is etched to form an internal sidewall, the internal sidewall including a first internal sidewall and a second internal sidewall, the first internal sidewall being opposite to the first active structure, and the second internal sidewall being opposite to the second active structure; after removing the dummy gate structure and the first sacrificial layer to expose the active structure in the gate region, the method further includes: removing the sacrificial layer in the gate region.

[0010] In some possible embodiments, the method also includes: after the first gate structure is formed, using a gate cutting process to remove the third gate structure in the first gate structure, and depositing an insulating material at the position where the third gate structure is removed to form a first gate isolation structure; wherein, in the second direction, the third gate structure is located at both ends of the first gate structure; the second direction is perpendicular to the first direction; and / or, after the second gate structure is formed, using a gate cutting process to remove the fourth gate structure in the second gate structure, and depositing an insulating material at the position where the fourth gate structure is removed to form a second gate isolation structure; wherein, in the second direction, the fourth gate structure is located at both ends of the second gate structure.

[0011] In some possible embodiments, after the first source-drain structure is epitaxially grown in the first deep trench based on the first active structure in the gate region, the method further includes: depositing a dielectric material on the first source-drain structure to form a first interlayer dielectric layer; depositing a metal material on the first gate dielectric layer to form a first gate electrode layer, the method further includes: depositing a dielectric material on the first gate electrode layer and the first interlayer dielectric layer to form a first dielectric layer; etching the first dielectric layer and the first interlayer dielectric until the first source-drain structure is exposed to form a first through hole; and depositing a metal material in the first through hole to form a first source-drain metal.

[0012] In some possible embodiments, the first source-drain structure and the first gate structure together constitute a first transistor, and the second source-drain structure and the second gate structure together constitute a second transistor; the first transistor or the second transistor is any one of the following: a fin field effect transistor, a full-surround gate field effect transistor, a vertical field effect transistor, a complementary field effect transistor, a fork-plate crystal transistor, and a planar field effect transistor.

[0013] In a second aspect, an embodiment of the present application provides a stacked transistor, which includes: a first transistor; a second transistor, the first transistor and the second transistor are arranged back to back, and the first active structure of the first transistor and the second active structure of the second transistor form an active structure; the first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned.

[0014] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a stacked transistor as described in the above embodiment.

[0015] In the embodiment of the present disclosure, a stacked structure is formed by etching a semiconductor substrate once, and the stacked structure includes an active structure, so that the active areas of the positive and negative layers of the stacked transistors are self-aligned. Subsequently, a pseudo-gate structure shared by the positive and negative layers of the transistors is formed, and after the first source-drain structure in the source-drain region is formed, the pseudo-gate structure and the first sacrificial layer are removed to expose the self-aligned active structure in the gate region. Subsequently, a self-aligned gate dielectric layer can be formed based on the self-aligned active structure in the exposed gate region, and finally the positive and negative transistors are completely self-aligned.

[0016] In this way, on the one hand, fewer high aspect ratio processes can be used, which is more compatible with fully self-aligned flip-chip stacking of various types of transistors, thereby further optimizing the "self-aligned flip-chip transistor" solution; on the other hand, by preferentially preparing the gate dielectric layer, it can be ensured that subsequent structures no longer bear a higher thermal budget, thereby effectively improving structural performance.

[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] Figure 1 A schematic diagram of an implementation process of a method for preparing a stacked transistor according to an embodiment of the present application;

[0020] Figure 2 is a top view of a stacked transistor according to an embodiment of the present application;

[0021] Figures 3 to 38 It is a schematic diagram of a preparation process of a stacked transistor according to an embodiment of the present application.

[0022] The above figures: 10, stacked transistor; 11, first transistor; 12, second transistor; 112, first source-drain structure; 113, first interlayer dielectric layer; 114, first gate structure; 115, first source-drain metal; 116, first metal interconnect layer; 122, second source-drain structure; 123, second interlayer dielectric layer; 124, second gate structure; 125, second source-drain metal; 126, second metal interconnect layer; 20, semiconductor substrate; 21, initial stacking structure; 22, initial barrier layer; 23, stacking structure; 24, barrier layer; 25, shallow trench isolation structure; 26, dummy gate structure; 27, dummy gate sidewall; 28, first gate isolation layer Isolation structure; 29, first active structure; 30, second sacrificial layer; 31, second active structure; 32, first sacrificial layer; 33, isolation structure; 34, sacrificial layer; 35, channel layer; 36, internal sidewall; 37, filling structure; 37a, first filling structure; 37b, second filling structure; 38, isolation layer; 39, gate dielectric layer; 39a, first gate dielectric layer; 39b, second gate dielectric layer; 40, third filling structure; 41, first gate isolation structure; 42, first dielectric layer; 43, insulating layer; 44, carrier wafer; 45, fourth filling structure; 46, second dielectric layer; 47, second gate isolation structure; 48, first deep trench. DETAILED DESCRIPTION

[0023] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0024] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot topic in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0025] In one embodiment, there are two schemes for manufacturing a stacked transistor, the first is a monolithic scheme, and the second is a sequential scheme.

[0026] The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate without using wafer bonding technology. This determines that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied on to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.

[0027] The second solution is based on wafer bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by bonding the wafer on top of the already manufactured lower transistor, and the two transistors are stacked vertically. However, the temperature needs to be strictly controlled during the thermal process of processing the upper transistor to avoid affecting the lower transistor and the interconnection lines. The advantage of this solution is that thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used in the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance.

[0028] In order to solve the technical problems of the above two solutions, a flip-chip solution for realizing self-aligned stacked transistors is proposed. The flip-chip solution forms the active areas of the upper and lower layers of the same source transistors by etching, and realizes the manufacture of stacked transistors on the front and back sides of the wafer by flipping the wafer to overcome the shortcomings of the above two solutions. This can also be called the "self-aligned flip-chip transistor" solution.

[0029] However, in the "self-aligned flip-chip transistor" solution, high aspect ratio processes need to be used multiple times, which will lead to high processing difficulty, easy occurrence of gaps, uneven etching rate, insufficient bottom etching, etc. Therefore, there is room for optimization in the "self-aligned flip-chip transistor" solution.

[0030] In order to solve the above technical problems, an embodiment of the present application provides a method for preparing a stacked transistor to optimize the "self-aligned flip-chip transistor" solution.

[0031] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a stacked transistor according to an embodiment of the present application, see Figure 1 As shown, the method for preparing a stacked transistor may include:

[0032] Step S101: etching once on a semiconductor substrate to form a stacked structure, wherein the stacked structure includes an active structure and a first sacrificial layer, and the active structure includes a first active structure and a second active structure; the first active structure, the second active structure and the first sacrificial layer are stacked in sequence in a first direction, the first active structure is farther away from the semiconductor substrate than the first sacrificial layer, and the first direction is a direction perpendicular to the semiconductor substrate;

[0033] Step S102: forming a dummy gate structure covering the stacked structure in the gate region of the stacked transistor;

[0034] Step S103: etching the stacked structure not covered by the dummy gate structure to form a first deep trench;

[0035] Step S104: epitaxially growing a first source-drain structure in the first deep trench based on the first active structure in the gate region;

[0036] Step S105: removing the dummy gate structure and the first sacrificial layer to expose the active structure in the gate region;

[0037] Step S106: depositing a gate dielectric material on the exposed active structure to form a gate dielectric layer, wherein the gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer, wherein the first gate dielectric layer wraps the first active structure, and the second gate dielectric layer wraps the second active structure;

[0038] Step S107: depositing a metal material on the first gate dielectric layer to form a first gate electrode layer, wherein the first gate dielectric layer and the first gate electrode layer together constitute a first gate structure;

[0039] Step S108: flipping the wafer and removing the semiconductor substrate;

[0040] Step S109: epitaxially growing a second source-drain structure in the first deep trench based on the second active structure in the gate region;

[0041] Step S110: depositing a metal material on the second gate dielectric layer to form a second gate electrode layer. The second gate dielectric layer and the second gate electrode layer together constitute a second gate structure.

[0042] It can be understood that the first direction may be the height direction of the active structure, and the third direction may be the extension direction of the active structure, such as the width direction of the gate structure. The second direction may be a direction perpendicular to the extension direction of the active structure, such as the length direction of the gate structure. In the third direction, the gate regions and the source-drain regions of the stacked transistors are arranged alternately in sequence, and the gate structures and the source-drain structures of the stacked transistors are arranged alternately in sequence.

[0043] It should be noted that Figure 1 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 1 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0044] It can be understood that by etching a stacked structure on a semiconductor substrate once, and the stacked structure includes an active structure, the active areas of the positive and negative layers of the stacked transistor can be self-aligned. Subsequently, a pseudo-gate structure shared by the positive and negative layers of the transistors is formed, and after the first source and drain structure in the source and drain region is formed, the pseudo-gate structure is removed to expose the self-aligned active structure in the gate region. Subsequently, a self-aligned gate dielectric layer can be formed based on the self-aligned active structure in the exposed gate region, and finally the positive and negative transistors are completely self-aligned.

[0045] In this way, on the one hand, fewer high aspect ratio processes can be used, which is more compatible with fully self-aligned flip-chip stacking of various types of transistors, thereby further optimizing the "self-aligned flip-chip transistor" solution; on the other hand, by preferentially preparing the gate dielectric layer, it can be ensured that subsequent structures no longer bear a higher thermal budget, thereby effectively improving structural performance.

[0046] Figure 2 FIG. 1 is a top view of a stacked transistor according to an embodiment of the present application, see Figure 2 As shown, only the nanosheet structure, the gate structure, and the source-drain structure of the stacked transistor 10 are shown in the top view.

[0047] In one embodiment, the stacked transistor 10 includes a first transistor and a second transistor, and the first transistor and the second transistor are self-aligned, that is, the first source-drain structure of the first transistor and the second source-drain structure of the second transistor are self-aligned, and the first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned.

[0048] In one embodiment, the first transistor and the second transistor may be transistors of the same type. For example, the first transistor and the second transistor may both be fin field effect transistors.

[0049] In one embodiment, the active structure in the stacked transistor 10 may be different depending on the type of the stacked transistor. In one example, when the stacked transistor 10 is a fin field effect transistor, the active structure may be a fin structure. When the stacked transistor 10 is a gate-all-around nanosheet (GAA Nanosheet), the active structure may be a nanosheet structure; wherein the nanosheet structure may be formed by alternately deposited silicon layers and silicon germanium layers. When the stacked transistor 10 is a planar transistor, the active structure may be a block structure.

[0050] In one embodiment, Figure 2 The stacked transistor 10 shown is a gate-all-around field effect transistor, and its active structure is a nanosheet structure.

[0051] Figures 3 to 38 FIG. 1 is a schematic diagram of a manufacturing process of a stacked transistor according to an embodiment of the present application. For ease of understanding, Figures 3 to 38 (a) shows the Figure 2 The cross-sectional view along the dashed line AA'. Figures 3 to 38 (b) shows the Figure 2 The cross-sectional view along the dotted line BB', Figures 3 to 38 (c) shows the Figure 2 The cross-sectional view along the dotted line CC'. Figures 1 to 38 The method for preparing a stacked transistor provided in an embodiment of the present application and the prepared stacked transistor 10 are exemplarily described.

[0052] In step S101, a stacked structure 23 is formed by etching the semiconductor substrate 20. Figure 5 shown.

[0053] It is understood that material layer deposition, epitaxial growth, photolithography and other processes may be performed on the semiconductor substrate 20 to form multiple material layers. Subsequently, the multiple material layers may be etched using a photolithography process to form a stacked structure 23 at one time.

[0054] In one embodiment, the steps of the photolithography process in the embodiment of the present application may include: depositing photoresist material, exposing and developing the photoresist material, removing a portion of the photoresist material, etching to remove the material layer corresponding to the portion of the photoresist material, etc.

[0055] In one embodiment, the stacked structure 23 includes an active structure and a first sacrificial layer 32, and the active structure includes a first active structure 29 and a second active structure 31. The first active structure 29, the second active structure 31 and the first sacrificial layer 32 are stacked in sequence in a first direction. The first active structure 29 is farther away from the semiconductor substrate 20 than the first sacrificial layer 32. The first direction is a direction perpendicular to the semiconductor substrate 20.

[0056] It can be understood that the stacked structure 23 includes an active structure and a first sacrificial layer 32, and the first sacrificial layer 32 is arranged between the active structure and the semiconductor substrate 20. The active structure includes a first active structure 29 and a second active structure 31, the first active structure 29 is used to form the active area of ​​the first transistor 11 (front transistor) of the stacked transistor 10; the second active structure 31 stacked along the first direction with the first active structure 29 is used to form the active area of ​​the second transistor 12 (reverse transistor) of the stacked transistor 10. The first sacrificial layer 32 can be removed in a subsequent step, and after removal, the space originally occupied by the first sacrificial layer 32 is used to fill the metal material to form the second gate structure 124 of the second transistor 12.

[0057] In one embodiment, the first sacrificial layer 32 may be formed of a material different from that of the active structure; or, the first sacrificial layer 32 may be formed of a material the same as that of the active structure; this embodiment of the present application does not specifically limit this.

[0058] In one example, the active structure is a nanosheet structure, the nanosheet structure may be formed of alternately deposited silicon layers and silicon germanium layers, and the first sacrificial layer 32 may be formed of silicon germanium.

[0059] In some embodiments, when the first active structure 29 and the second active structure 31 are formed by photolithography, a larger etching depth may be used. For example, the height of the nanosheet structure (which may also be a fin-shaped structure or a block-shaped structure) obtained by etching may be greater than 100 nm. It should be noted that the height of the nanosheet structure may be set according to actual conditions, and the embodiments of the present application do not specifically limit this.

[0060] In some embodiments, after the first active structure 29 and the second active structure 31 are formed by photolithography, ion implantation may be performed in the middle of the first active structure 29 and the second active structure 31 to electrically isolate the first active structure 29 and the second active structure 31 .

[0061] In one embodiment, the ions implanted in the middle of the first active structure 29 and the second active structure 31 include P-type ions, N-type ions or oxygen ions. The P-type ions include one or more of boron ions, gallium ions and indium ions; the N-type ions include one or more of phosphorus ions, arsenic ions and antimony ions.

[0062] In some embodiments, the stacked structure 23 located in the two side regions of the stacked transistor 10 may be removed by a fin cutting process, so that the active structures of a plurality of standard transistor units are disconnected from each other, thereby completing the isolation between adjacent transistor units.

[0063] In some embodiments, step S101 includes: forming an initial stacking structure 21 and an initial barrier layer 22 on a semiconductor substrate 20, wherein the initial barrier layer 22 is located between the initial stacking structure 21 and the semiconductor substrate 20; etching the initial stacking structure 21 and the initial barrier layer 22 at one time to form a stacking structure 23 and a barrier layer 24; depositing an oxide material on the semiconductor substrate 20 to form a shallow trench isolation structure 25, wherein the shallow trench isolation structure 25 wraps the barrier layer 24, see Figures 3 to 5 shown.

[0064] It can be understood that an initial barrier layer 22 can be formed on the semiconductor substrate 20, and an initial stacking structure 21 can be formed on the initial barrier layer 22. After the initial barrier layer 22 and the initial stacking structure 21 are formed, the initial stacking structure 21 and the initial barrier layer 22 can be photolithographically processed from top to bottom to form a stacking structure 23 and a barrier layer 24 at one time. At this time, the barrier layer 24 is located between the stacking structure 23 and the semiconductor substrate 20. An oxide material is deposited on the semiconductor substrate 20, and a shallow trench isolation structure 25 formed by the oxide material can wrap the barrier layer 24, while the stacking structure 23 is exposed outside the shallow trench isolation structure 25.

[0065] It is understood that the barrier layer 24 and the stacked structure 23 are formed by one etching process, and the barrier layer 24 is located opposite to the stacked structure 23. After flipping, the position of the active structure can be obtained according to the position of the barrier layer 24, which is conducive to the alignment of the front and back sides of the stacked transistor 10.

[0066] In one embodiment, the material of the barrier layer 24 may have a certain hardness. In one example, the material of the barrier layer 24 may be silicon germanium. In one example, the silicon germanium forming the barrier layer 24 is different from the silicon germanium forming the nanosheet structure. For example, the atomic percentage of germanium in the silicon germanium may be different.

[0067] In one embodiment, the oxide used to form the shallow trench isolation structure 25 may be a silicon-based oxide (SiOx, where x is the number of oxygen atoms), such as silicon dioxide (SiO 2 )wait.

[0068] In step S102, a dummy gate structure 26 covering the stacked structure 23 is formed in the gate region of the stacked transistor 10. Figure 6 shown.

[0069] It is understandable that based on the stacked structure 23 formed in step S101 , a semiconductor manufacturing process may be used to form a dummy gate structure 26 in the gate region of the stacked transistor 10 , and the dummy gate structure 26 may cover the stacked structure 23 .

[0070] In one embodiment, the dummy gate structure 26 is a dummy gate structure 26 shared by the first active structure 29 and the second active structure 31 .

[0071] In some embodiments, after the dummy gate structure 26 is formed, a dummy gate spacer 27 may be deposited on the semiconductor substrate 20. In one embodiment, the dummy gate spacer 27 covers the sidewalls of the dummy gate structure 26. In one embodiment, the dummy gate spacer 27 covers the structure in the source and drain regions of the stacked transistor 10, for example, the dummy gate spacer 27 may cover the stacked structure 23 in the source and drain regions.

[0072] In some embodiments, the material forming the dummy gate structure 26 may be polysilicon, amorphous silicon, or the like.

[0073] In step S103, the stacked structure 23 not covered by the dummy gate structure 26 is etched to form a first deep trench 48, see Fig.13 shown.

[0074] It is understood that the dummy gate structure 26 covers the stacked structure 23 in the gate region, but does not cover the stacked structure 23 in the source and drain region. By etching the stacked structure 23 not covered by the dummy gate structure 26, a first deep trench 48 can be formed in the source and drain region between two adjacent gate regions.

[0075] In some embodiments, the trench wall of the first deep trench 48 is formed by the stacked structure 23 in the gate region, and the trench bottom of the first deep trench 48 is formed by the bottom structure of the stacked structure 23 in the source / drain region.

[0076] In some embodiments, the active structure further includes: a second sacrificial layer 30 , and the second sacrificial layer 30 is located between the first active structure 29 and the second active structure 31 .

[0077] It is understandable that the second sacrificial layer 30 and the first active structure 29 and the second active structure 31 can be formed by the same etching process.

[0078] In some embodiments, the material forming the second sacrificial layer 30 can be set according to actual needs, and the embodiments of the present application do not specifically limit this. In one embodiment, the material forming the second sacrificial layer 30 can be silicon germanium. In one embodiment, the silicon germanium forming the second sacrificial layer 30 is different from the silicon germanium forming the nanosheet structure, for example, the atomic percentage of germanium in the silicon germanium is different.

[0079] In some embodiments, step S103 includes: etching the first active structure 29, the second sacrificial layer 30, the second active structure 31 and the first sacrificial layer 32 not covered by the dummy gate structure 26 to form a first deep trench 48; in the gate region, depositing an insulating material at a position where the second sacrificial layer 30 is removed to form an isolation structure 33, see Figures 6 to 13 shown.

[0080] It can be understood that the stacked structure 23 in the source and drain region is not covered by the dummy gate structure 26, and the first deep groove 48 can be formed by sequentially etching the first active structure 29, the second sacrificial layer 30, the second active structure 31 and the first sacrificial layer 32 in the source and drain region. Here, after etching the first active structure 29 in the source and drain region, the second sacrificial layer 30 can be exposed; then, the second sacrificial layer 30 in the source and drain region and the gate region is selectively removed, and the second active structure 31 in the source and drain region can be exposed. Then, the second active structure 31 in the source and drain region is etched to expose the first sacrificial layer 32. Then, the first sacrificial layer 32 in the source and drain region is etched to form the first deep groove 48.

[0081] It is understood that selectively removing the second sacrificial layer 30 between the first active structure 29 and the second active structure 31 in the gate region can form an unfilled space between the first active structure 29 and the second active structure 31 in the gate region. Subsequently, the unfilled space is filled with an insulating material to form an isolation structure 33.

[0082] In some embodiments, the isolation structure 33 is used to electrically isolate the first active structure 29 and the second active structure 31 within the gate region.

[0083] In some embodiments, before step S104 and after step S103, the process includes: depositing an oxide material in the first deep trench 48 to form a first filling structure 37a. Depositing an insulating material on the first filling structure 37a to form an isolation layer 38, see Figures 14 to 16 shown.

[0084] It can be understood that the first active structure 29 and the second active structure 31 can be formed before and after the flipping, respectively. Then, before forming the first active structure 29, an oxide material can be deposited in the first deep groove 48 to form a first filling structure 37a. The height of the first filling structure 37a is less than the height of the first active structure 29 and greater than the height of the second active structure 31. The first filling structure 37a completes the shielding of the second active structure 31 in the gate region, thereby ensuring that the first active structure 29 is formed only in the source and drain region before flipping. Subsequently, an insulating material is deposited on the first filling structure 37a to form an isolation layer 38. The isolation layer 38 is used to isolate the first source and drain structure 112 and the second source and drain structure 122 generated subsequently.

[0085] In some embodiments, when a barrier layer 24 is formed between the stacked structure 23 and the semiconductor substrate 20, after step S103, the following steps include: etching the barrier layer 24 at the bottom of the first deep trench 48 to form an etched barrier layer 24. Depositing an oxide material at the position where the barrier layer 24 is etched to form a second filling structure 37b.

[0086] It is understood that when a barrier layer 24 is formed on the semiconductor substrate 20, the barrier layer 24 at the bottom of the first deep trench 48 (the barrier layer 24 in the source and drain regions) can be etched after forming the first deep trench 48 to form an etched barrier layer 24. The etched barrier layer 24 is located in the gate region. Subsequently, an oxide material is deposited at the position where the barrier layer 24 is etched to form a second filling structure 37b.

[0087] In one embodiment, after flipping the wafer, the position of the gate region can be located according to the position of the barrier layer 24 after etching, so as to facilitate self-alignment of the stacked transistor 10 .

[0088] In some embodiments, an oxide material is deposited in the first deep trench 48 to simultaneously form a first filling structure 37a and a second filling structure 37b. Fig.15 shown.

[0089] In some embodiments, when the stacked transistor 10 is a full-surround gate field effect transistor, the first active structure 29 and the second active structure 31 are both formed by alternately stacking a channel layer 35 and a sacrificial layer 34. Step S103 includes: laterally etching the sacrificial layer 34 in the active structure in the gate region to a preset depth. Depositing an insulating material at the position where the sacrificial layer 34 is etched to form an internal spacer 36.

[0090] It is understood that when the stacked transistor 10 is a full-surround gate field effect transistor, the first deep groove 48 is formed to expose the active structure in the gate region. Subsequently, the sacrificial layer 34 in the exposed active structure can be etched to a preset depth. An insulating material can be deposited at the location where the sacrificial layer 34 is etched to form an internal sidewall 36 of the full-surround gate transistor.

[0091] In some embodiments, the internal sidewall spacer 36 of the full-ring gate transistor is used to electrically isolate the source-drain structure from the gate structure to ensure the stability of the transistor structure.

[0092] In some embodiments, the inner spacer 36 includes a first inner spacer and a second inner spacer. The first inner spacer is opposite to the first active structure 29 , and the second inner spacer is opposite to the second active structure 31 .

[0093] It can be understood that after forming the first deep trench 48, the internal spacers 36 in the first transistor 11 and the second transistor 12 can be formed simultaneously. The first internal spacer of the first transistor 11 is used to isolate the first source-drain structure 112 and the first gate structure 114. The second internal spacer of the second transistor 12 is used to isolate the second source-drain structure 122 and the second gate structure 124.

[0094] In one embodiment, the material forming the inner spacer 36 is the same as the material forming the dummy gate spacer 27 .

[0095] Step S104: Based on the first active structure 29 in the gate region, a first source-drain structure 112 is epitaxially grown in the first deep trench 48, see Fig.17 shown.

[0096] It is understood that after forming the first deep trench 48, the first source-drain structure 112 can be epitaxially grown based on the first active structure 29 in the gate region. Here, the direction of epitaxial growth is perpendicular to the first direction, and the direction of epitaxial growth is from the gate region to the source-drain region. After the epitaxial growth is completed, the first source-drain structure 112 can be formed in the first deep trench 48.

[0097] In one embodiment, after forming the first source-drain structure 112, a dielectric material may be deposited on the first source-drain structure 112 to form a first interlayer dielectric layer 113, see Fig.18 shown.

[0098] It can be understood that the first interlayer dielectric layer 113 wraps the first source-drain structure 112 and can electrically isolate the first source-drain structure 112 from other structures.

[0099] Step S105, removing the dummy gate structure 26 and the first sacrificial layer 32 to expose the active structure in the gate region, see Fig.19 shown.

[0100] It is understood that after the first source-drain structure 112 is formed, the dummy gate structure 26 may be removed to expose the stacked structure 23 covered by the dummy gate structure 26. Subsequently, the first sacrificial layer 32 in the exposed stacked structure 23 is removed to completely expose the active structure, see Fig. 20 shown.

[0101] In some embodiments, when the stacked transistor 10 is a full-surround gate field effect transistor, after step S105, the method further includes: removing the sacrificial layer 34 in the active structure in the gate region, retaining the channel layer 35 in the active structure, thereby completely exposing the channel layer 35 in the gate region.

[0102] Step S106, depositing a gate dielectric material on the exposed active structure to form a gate dielectric layer 39, see Fig.21 shown.

[0103] It can be understood that after the active structure in the gate region is exposed in step S105 , a gate dielectric material may be deposited on the exposed active structure to form a gate dielectric layer 39 .

[0104] In one embodiment, the gate dielectric layer 39 is located between the gate electrode layer and the active structure (channel). The gate dielectric layer 39 is used to prevent the gate current from directly flowing into the channel.

[0105] In one embodiment, the gate dielectric material forming the gate dielectric layer 39 can be set according to actual needs, and the embodiment of the present application does not limit this. In one example, the gate dielectric layer 39 can be composed of a silicon oxide layer plus a high-k hafnium oxide layer, and the thickness of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the first transistor 11. In one example, the gate dielectric layer 39 may include: a 0.6nm silicon oxide layer and a 1.7nm hafnium oxide layer.

[0106] In some embodiments, the gate dielectric layer 39 includes a first gate dielectric layer 39 a and a second gate dielectric layer 39 b , the first gate dielectric layer 39 a wraps around the first active structure 29 , and the second gate dielectric layer 39 b wraps around the second active structure 31 .

[0107] Step S107, depositing a metal material on the first gate dielectric layer 39a to form a first gate electrode layer, see Fig.23 shown.

[0108] It can be understood that after the gate dielectric layer 39 is formed, a metal material may be deposited on the first gate dielectric layer 39 a to form a first gate electrode layer.

[0109] In one embodiment, the first gate dielectric layer 39 a and the first gate electrode layer are used together to form a first gate structure 114 . The first gate structure 114 is a gate structure in the first transistor 11 .

[0110] In one embodiment, the metal material forming the gate electrode layer can be set according to actual needs, and the embodiment of the present application does not limit this. In one embodiment, the gate electrode layer can be composed of multiple layers of electrode materials, and the electrode material of each layer includes but is not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide and aluminum carbide).

[0111] In some embodiments, before step S107, the process includes: depositing an oxide material in the gate region to form a third filling structure 40, wherein the third filling structure 40 wraps the second active structure 31 and the gate dielectric layer 39, and exposes the first active structure 29 and the first gate dielectric layer 39a. A first gate structure 114 may be formed on the exposed first gate dielectric layer 39a, see Fig. 22 shown.

[0112] In some embodiments, after step S107, the process includes: depositing a dielectric material on the first gate electrode layer and the first interlayer dielectric layer 113 to form a first dielectric layer 42; etching the first dielectric layer 42 and the first interlayer dielectric layer 113 until the first source-drain structure 112 is exposed to form a first through hole; and depositing a metal material in the first through hole to form a first source-drain metal 115.

[0113] It is understood that after forming the first gate structure 114, a first dielectric layer 42 may be formed on the first gate structure 114 and the first interlayer dielectric layer 113. The first dielectric layer 42 is used to electrically isolate the source-drain metal and the gate oxide (e.g., the gate dielectric layer 39), thereby eliminating the adverse electrical effects caused by direct contact between the source-drain metal and the gate oxide layer. After the first dielectric layer 42 is formed, the first dielectric layer 42 and the first interlayer dielectric layer 113 in the source-drain region may be etched to form source-drain metal vias. Subsequently, a metal material may be deposited in the source-drain metal vias to form the first source-drain metal 115, see Fig.25 shown.

[0114] In some embodiments, after step S107, the method further includes: after the first gate structure 114 is formed, removing the third gate structure in the first gate structure 114 by a gate cutting process, and depositing an insulating material at the position where the third gate structure is removed to form a first gate isolation structure 41, see Fig.24 shown.

[0115] In one embodiment, in the second direction, the third gate structure is located at two ends of the first gate structure 114 .

[0116] It can be understood that after the first gate structure 114 is formed, the third gate structure in the first gate structure 114 can be removed, and the third gate structure is a structure located at both ends of the first gate structure 114 in the second direction, and can also be understood as a structure located at both ends of the stacked transistor 10 in the second direction. After the third gate structure is removed, an insulating material can be deposited at the position where the third gate structure is removed to form a first gate isolation structure 41.

[0117] In some embodiments, the insulating material forming the first gate isolation structure 41 can be selected according to actual needs, and the embodiments of the present application are not limited to this.

[0118] In some embodiments, while the third gate structure in the first gate structure 114 is removed by the gate cutting process, the third interlayer dielectric layer in the first interlayer dielectric layer 113 may be removed simultaneously, and the projection of the third interlayer dielectric layer toward the third direction coincides with the projection of the third gate structure toward the third direction. After the third interlayer dielectric layer is removed, an insulating material may also be deposited at the position where the third interlayer dielectric layer is removed to form a first gate isolation structure 41 that is continuous in the third direction.

[0119] In one embodiment, after forming the first gate structure 114 and the first source-drain metal 115, a first metal interconnect layer 116 may be formed on the first gate structure 114 and the first source-drain metal 115 by using a standard semiconductor manufacturing back-end process (such as interconnect line dielectric deposition, metal line formation, lead pad formation, etc.), see Fig.26 shown.

[0120] In some embodiments, after the first metal interconnection layer 116 is formed, the first transistor 11 may be formed.

[0121] It should be noted that, for ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source electrode structure and / or the first drain electrode structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, etc. are similar to the first source-drain groove, where "source-drain" is an abbreviation for "source electrode and / or drain electrode".

[0122] Step S108, flipping and removing the semiconductor substrate 20, see Fig.28 shown.

[0123] It can be understood that after obtaining the first transistor 11, the first transistor 11 can be flipped so that the completed first transistor 11 is located at the bottom, and the second active structure 31 of the unfinished second transistor 12 can be located at the top, which is convenient for the subsequent preparation of the second transistor 12.

[0124] In one embodiment, after the back-end process of the first transistor 11 is completed, the first transistor 11 may be bonded to the carrier wafer 44. For example, an insulating material (such as silicon oxide) may be deposited on the first transistor 11 to form an insulating layer 43, and the insulating layer 43 may be bonded to the carrier wafer 44. Then, the wafer is flipped. After the flip, the first transistor 11 is located at the bottom. Fig. 27 shown.

[0125] In the embodiment of the present application, the bonded carrier wafer 44 can provide physical support for the flipped first transistor 11 after flipping, thereby effectively preventing the first transistor 11 from being broken by external force during the preparation of the second transistor 12 .

[0126] In some embodiments, when a barrier layer 24 is disposed between the stacked structure 23 and the semiconductor substrate 20, step S108 includes: flipping the wafer and removing the semiconductor substrate 20 to expose the barrier layer 24 and the shallow trench isolation structure 25 after etching. The shallow trench isolation structure 25 is removed, and the barrier layer 24 after etching is retained. Fig.29 shown.

[0127] It is understandable that after flipping, the semiconductor substrate 20 can be removed by polishing or chemical mechanical planarization to expose the etched barrier layer 24 and the shallow trench isolation structure 25. Subsequently, the shallow trench isolation structure 25 can be selectively etched to expose the etched barrier layer 24 and the structure protected by the etched barrier layer 24.

[0128] It can be understood that the barrier layer 24 after etching is located in the gate region, so that the barrier layer 24 after etching can protect the structure in the gate region from being affected by etching.

[0129] It is understandable that the gate region of the stacked transistor 10 can be positioned by the etched barrier layer 24, thereby achieving self-alignment of the gate region and the source and drain regions of the front and back layers of the transistor.

[0130] Step S109: Based on the second active structure 31 in the gate region, a second source-drain structure 122 is epitaxially grown in the first deep trench 48, see Fig.32 shown.

[0131] It can be understood that after the second active structure 31 is exposed, the second source-drain structure 122 may be epitaxially grown in the first deep trench 48 based on the second active structure 31 in the gate region.

[0132] Here, the step of epitaxially growing the second source-drain structure 122 is the same as the step of epitaxially growing the first source-drain structure 112 , and for the sake of brevity of the specification, it will not be repeated here.

[0133] In some embodiments, during the process of preparing the first transistor 11, if the first filling structure 37a is filled into the first deep trench 48, then before step S109, the method further includes: removing the first filling structure 37a in the first deep trench 48 to expose the second active structure 31 in the gate region, see Fig.31 shown.

[0134] It can be understood that by removing the first filling structure 37 a in the first deep trench 48 , the second active structure 31 in the gate region can be exposed, so that the second source-drain structure 122 can be formed based on the exposed active structure.

[0135] In some embodiments, before step S109 , the process includes: sequentially etching the second filling structure 37 b and the first filling structure 37 a that are not covered by the etched barrier layer 24 until the isolation layer 38 is exposed.

[0136] It is understood that the second filling structure 37b and the first filling structure 37a not covered by the etched barrier layer 24 can be etched during the etching process. In this process, the etched barrier layer 24 is used as a hard mask to protect the structure covered by the etched barrier layer 24.

[0137] Step S110, depositing a metal material on the second gate dielectric layer 39b to form a second gate electrode layer, see Fig.35 shown.

[0138] It is understandable that the second gate dielectric layer 39 b can be formed simultaneously with the first gate dielectric layer 39 a . After flipping, it is only necessary to deposit metal material on the second gate dielectric layer 39 b to form a second gate electrode layer, and then form the second gate structure 124 .

[0139] In one embodiment, the second gate dielectric layer 39 b and the second gate electrode layer are used together to form a second gate structure 124 . The second gate structure 124 is a gate structure in the second transistor 12 .

[0140] In some embodiments, before step S110, the filling structure 37 formed in the gate region is removed to expose the second active structure 31 and the second gate dielectric layer 39b. A second gate structure 124 may be formed on the exposed second gate dielectric layer 39b.

[0141] In some embodiments, after step S107, the process includes: depositing a dielectric material on the second gate electrode layer and the second interlayer dielectric layer 123 to form a second dielectric layer 46; etching the second dielectric layer 46 and the second interlayer dielectric until the second source-drain structure 122 is exposed to form a second through hole; depositing a metal material in the second through hole to form a second source-drain metal 125, see Fig.37 shown.

[0142] It is understood that after forming the second gate structure 124, a second dielectric layer 46 may be formed on the second gate structure 124 and the second interlayer dielectric layer 123, and the function of the second dielectric layer 46 is the same as that of the first dielectric layer 42. After the second dielectric layer 46 is formed, the second dielectric layer 46 and the second interlayer dielectric layer 123 in the source-drain region may be etched to form a source-drain metal through hole. Subsequently, a metal material may be deposited in the source-drain metal through hole to form a second source-drain metal 125.

[0143] In some embodiments, after step S107, the method further includes: after the second gate structure 124 is formed, removing the fourth gate structure in the second gate structure 124 by a gate cutting process, and depositing an insulating material at the position where the fourth gate structure is removed to form a second gate isolation structure 47, see Fig.36 shown.

[0144] In one embodiment, in the second direction, the fourth gate structure is located at two ends of the second gate structure 124 .

[0145] It can be understood that after the second gate structure 124 is formed, the fourth gate structure in the second gate structure 124 can be removed, and the fourth gate structure is a structure located at both ends of the second gate structure 124 in the second direction, and can also be understood as a structure located at both ends of the stacked transistor 10 in the second direction. After the fourth gate structure is removed, an insulating material can be deposited at the position where the fourth gate structure is removed to form a second gate isolation structure 47.

[0146] In some embodiments, the insulating material forming the second gate isolation structure 47 can be selected according to actual needs, and the embodiments of the present application are not limited to this.

[0147] In some embodiments, while the fourth gate structure in the second gate structure 124 is removed by the gate cutting process, the fourth interlayer dielectric layer in the second interlayer dielectric layer 123 can be removed at the same time, and the projection of the fourth interlayer dielectric layer toward the third direction coincides with the projection of the fourth gate structure toward the third direction. After the fourth interlayer dielectric layer is removed, an insulating material can also be deposited at the position where the fourth interlayer dielectric layer is removed to form a second gate isolation structure 47 that is continuous in the third direction.

[0148] In some embodiments, the first gate isolation structure 41 and the second gate isolation structure 47 are disposed opposite to each other.

[0149] In one embodiment, after forming the second gate structure 124 and the second source-drain metal 125, a second metal interconnect layer 126 may be formed on the second gate structure 124 and the second source-drain metal 125 by using a standard semiconductor manufacturing back-end process (such as interconnect line dielectric deposition, metal line formation, lead pad formation, etc.), see Fig.38 shown.

[0150] In some embodiments, after the second metal interconnection layer 126 is formed, the second transistor 12 may be formed.

[0151] At this point, the preparation of the stacked transistor is completed. It should be noted that the first source-drain structure and the first gate structure together constitute a first transistor, and the second source-drain structure and the second gate structure together constitute a second transistor; the first transistor or the second transistor is any of the following: a fin field effect transistor, a full-surround gate field effect transistor, a vertical field effect transistor, a complementary field effect transistor, a fork-plate crystal transistor, and a planar field effect transistor, which is not limited in the present embodiment of the application.

[0152] In the embodiment of the present disclosure, by etching a stacked structure on a semiconductor substrate once, and the stacked structure includes an active structure, the active regions of the positive and negative layers of the stacked transistor can be self-aligned. Subsequently, a pseudo-gate structure shared by the positive and negative layers of the transistors is formed, and after the first source-drain structure in the source-drain region is formed, the pseudo-gate structure is removed to expose the self-aligned active structure in the gate region. Subsequently, a self-aligned gate dielectric layer can be formed based on the self-aligned active structure in the exposed gate region, and finally the positive and negative transistors are completely self-aligned.

[0153] In this way, on the one hand, fewer high aspect ratio processes can be used, which is more compatible with fully self-aligned flip-chip stacking of various types of transistors, thereby further optimizing the "self-aligned flip-chip transistor" solution; on the other hand, by preferentially preparing the gate dielectric layer, it can be ensured that subsequent structures no longer bear a higher thermal budget, thereby effectively improving structural performance.

[0154] Combine the following Figures 2 to 31 The manufacturing process of the stacked transistor shown is used as a specific example to illustrate the manufacturing method of the stacked transistor in the present application.

[0155] In one example, a process for preparing a stacked transistor may include the following steps:

[0156] Step 1: epitaxially grow silicon germanium and silicon on a semiconductor substrate 20 (formed from silicon) to form an initial stacking structure 21 and an initial barrier layer 22, and obtain Figure 3 The structure shown.

[0157] It can be understood that the initial barrier layer 22 is located between the semiconductor substrate 20 and the initial stacking structure 21 .

[0158] Here, the initial stacked structure 21 is formed by alternatingly arranging silicon germanium layers and silicon layers.

[0159] Step 2: Through photolithography, a stacked structure 23 and a barrier layer 24 are formed by etching at one time, and the obtained structure is as follows: Figure 4 The structure shown.

[0160] It can be understood that in the cross-sectional view along the AA′ direction and the cross-sectional view along the BB′ direction, portions on both sides of the initial stacked structure 21 are etched, thereby forming a stacked structure 23 for preparing a full-surround gate field effect transistor.

[0161] In some embodiments, the material forming the barrier layer 24 may have a certain hardness, so that the barrier layer 24 can be used as an etching barrier layer after flipping.

[0162] In the third step, an oxide material is deposited on the semiconductor substrate 20 to form a shallow trench isolation structure 25, and a Figure 5 The structure shown.

[0163] Here, the shallow trench isolation structure 25 wraps the barrier layer 24 , and the stacked structure 23 is exposed outside the shallow trench isolation structure 25 .

[0164] In the fourth step, a dummy gate structure 26 is formed to wrap the stacked structure 23. After the dummy gate structure 26 is formed, a dummy gate sidewall 27 is formed by deposition to obtain Figure 6 The structure shown.

[0165] It is understandable that the dummy gate structure 26 is a dummy gate structure shared by the front and back layers of crystals. When the dummy gate spacer 27 is formed by an isotropic deposition process, the dummy gate spacer 27 can cover the sidewalls of the dummy gate structure 26 in the gate region and the stacked structure 23 in the source and drain region.

[0166] In the fifth step, the pseudo gate spacer 27 is etched until the first active structure 29 and the second sacrificial layer 30 in the stacked structure 23 in the source and drain region are exposed, and the following is obtained: Figure 7 The structure shown.

[0167] It is understandable that an anisotropic etching process may be used to expose the first active structure 29 and the second sacrificial layer 30 .

[0168] It should be noted that if Figure 7 As shown, after the first active structure 29 and the second sacrificial layer 30 are exposed, in the cross-sectional view along the CC' direction, a portion of the dummy gate spacer 27 is still retained on the sidewall of the dummy gate structure 26. The dummy gate spacer 27 can be used as a hard mask in subsequent fabrication processes.

[0169] Step 6: etching the first active structure 29 in the source / drain region to obtain Figure 8 The structure shown.

[0170] It can be understood that by using the dummy gate structure 26 and the dummy gate spacer 27 as a hard mask, the first active structure 29 located in the source and drain regions can be selectively etched.

[0171] Step 7: selectively remove the second sacrificial layer 30 to isolate the first active structure 29 and the second active structure 31, and obtain Fig. 9 The structure shown.

[0172] It can be understood that by removing the second sacrificial layer 30 formed of silicon germanium, the first active structure 29 and the second active structure 31 can be electrically isolated.

[0173] In the eighth step, insulating materials such as silicon nitride are deposited, and the isolation structure 33 formed by the silicon nitride material is planarized by a mechanical planarization process to obtain Fig.10 The structure shown.

[0174] In the ninth step, an anisotropic etching process is used to remove the redundant isolation structure 33, and the isolation structure 33 between the first active structure 29 and the second active structure 31 in the gate region is retained to obtain Fig.11 The structure shown.

[0175] It can be understood that after removing the redundant isolation structure 33 , the isolation structure 33 may be formed at the position where the second sacrificial layer 30 is removed.

[0176] Step 10: Laterally etch the sacrificial layer 34 in the first active structure 29 to a certain depth. Deposit silicon nitride insulating material at the position where the sacrificial layer 34 is removed to form the inner sidewall 36 of the first transistor 11, and obtain Fig.12 The structure shown.

[0177] It is understood that in this embodiment, the stacked transistor 10 is a full-surround gate field effect transistor, and therefore, it is necessary to form an internal spacer 36. When the stacked transistor 10 is a fin field effect transistor, a planar field effect transistor, etc., it is not necessary to form the internal spacer 36.

[0178] In the eleventh step, the second active structure 31 in the source and drain region is etched by an anisotropic etching process. Subsequently, the sacrificial layer 34 in the second active structure 31 is laterally etched to a certain depth. A silicon nitride insulating material is deposited at the position where the sacrificial layer 34 is removed to form an inner sidewall 36 of the second transistor 12. Subsequently, the first sacrificial layer 32 at the bottom of the second active structure 31 is etched by an anisotropic etching process to obtain the following: Fig.13 The structure shown.

[0179] In some embodiments, the inner sidewall 36 of the second transistor 12 can be prepared after flipping. For example, after removing the filling structure 37 in the first deep trench, the sacrificial layer 34 in the second active structure 31 is laterally etched to a certain depth, and a silicon nitride insulating material is deposited at the position where the sacrificial layer 34 is removed to form the inner sidewall 36 of the second transistor 12.

[0180] In the twelfth step, the barrier layer 24 and the shallow trench isolation structure 25 in the source and drain regions are anisotropically etched to obtain Fig.14 The structure shown.

[0181] It is understood that after anisotropic etching of the barrier layer 24 in the source and drain regions, an etched barrier layer 24 is formed. The etched barrier layer 24 is located in the gate region, and after flipping, the position of the gate region can be obtained based on the etched barrier layer 24.

[0182] In the thirteenth step, a filling material is deposited in the source / drain region to form a filling structure 37, and a filling structure 37 is obtained. Fig.15 The structure shown.

[0183] In one embodiment, the filling structure 37 includes a first filling structure 37 a and a second filling structure 37 b . The first filling structure 37 a is opposite to the second active structure 31 , and the second filling structure 37 b is opposite to the etched barrier layer 24 .

[0184] In one embodiment, if Fig.15 As shown, the height of the top surface of the filling structure 37 is lower than the height of the top surface of the isolation structure 33 and higher than the height of the bottom surface of the isolation structure 33 .

[0185] In the fourteenth step, an insulating material is deposited in the source and drain regions to form an isolation layer 38, and the Fig.16 The structure shown.

[0186] It can be understood that the isolation layer 38 is used to electrically isolate the first source-drain structure 112 from the second source-drain structure 122 .

[0187] In step 15, based on the first active structure 29 in the gate region, a first source-drain structure 112 is formed in the source-drain region by epitaxy, so as to obtain Fig.17 The structure shown.

[0188] In the sixteenth step, an interlayer dielectric material is deposited in the source / drain region to form a first interlayer dielectric layer 113, and the Fig.18 The structure shown.

[0189] Step 17: remove the dummy gate structure 26 to obtain Fig.19 The structure shown.

[0190] It can be understood that after removing the dummy gate structure 26 , the active structure in the gate region can be exposed.

[0191] In step 18, the sacrificial layer 34 and the first sacrificial layer 32 in the active structure in the gate region are removed to obtain Fig. 20 The structure shown.

[0192] In the nineteenth step, a gate dielectric material is deposited on the retained channel layer 35 to form a gate dielectric layer 39, and the gate dielectric layer 39 is obtained as shown in FIG. Fig.21 The structure shown.

[0193] It can be understood that in this step, the gate dielectric layers 39 of the front and back transistors can be formed simultaneously, thereby improving the thermal budget for preparing subsequent structures.

[0194] It should be noted that the isolation structure 33 between the first gate structure 114 and the second gate structure 124 will also be wrapped by the gate dielectric layer 39 .

[0195] Step 20: deposit oxide material to form an initial filling structure. Then, the initial filling structure is flattened by a mechanical flattening process and etched to a preset height to form a third filling structure 40 that wraps the second active structure 31. Fig. 22 The structure shown.

[0196] In the twenty-first step, a metal material is deposited to form a first gate electrode layer of the first transistor 11. The first gate electrode layer and the first gate dielectric layer 39a together form a first gate structure 114, and the first gate electrode layer 114 is formed. Fig.23 The structure shown.

[0197] Step 22: forming a first gate isolation structure 41 to obtain Fig.24 The structure shown.

[0198] It can be understood that in the cross-sectional view along the AA′ direction and the cross-sectional view along the BB′ direction, the first gate isolation structure 41 is located on both sides.

[0199] In step 23, a dielectric material is deposited on the first interlayer dielectric layer 113 and the first gate structure 114 to form a first dielectric layer 42. Subsequently, the first dielectric layer 42 and the first interlayer dielectric layer 113 are etched until the first source-drain structure 112 is exposed, and then a first source-drain metal 115 is deposited to obtain the following. Fig.25 The structure shown.

[0200] Step 24: forming a first metal interconnection layer 116 to obtain Fig.26 The structure shown.

[0201] In step 25, an insulating material (such as silicon oxide) is deposited on the first metal interconnect layer 116 to form an insulating layer 43, and the insulating layer 43 is bonded to the carrier wafer 44. Then, the wafer is flipped. After flipping, the following is obtained: Fig. 27 The structure shown.

[0202] Step 26: remove the semiconductor substrate 20 to obtain Fig.28 The structure shown.

[0203] It can be understood that after the semiconductor substrate 20 is removed, the etched barrier layer 24 and the filling structure 37 in the source and drain regions can be exposed.

[0204] In step 27, the shallow trench isolation structure 25 wrapping the etched barrier layer is selectively etched to obtain Fig.29 The structure shown.

[0205] In step 28, polysilicon is deposited at the position where the shallow trench isolation structure 25 is removed to form a fourth filling structure 45, so as to obtain Fig.30 The structure shown.

[0206] Here, the fourth filling structure 45 is located to wrap the barrier layer after etching.

[0207] In some embodiments, the material forming the fourth filling structure 45 may be the same as the material forming the third filling structure 40. The material forming the third filling structure 40 is different from the material forming the barrier layer 24.

[0208] In step 29, the filling structure 37 in the source / drain region is removed until the isolation layer 38 is exposed, and the Fig.31 The structure shown.

[0209] It can be understood that the barrier layer 24 after etching is located in the gate region, and the position of the source and drain regions can be determined according to the position of the barrier layer 24 after etching.

[0210] In the 30th step, based on the second active structure 31 in the gate region, a second source-drain structure 122 is epitaxially grown in the source-drain region, and a dielectric material is deposited on the second source-drain structure 122 to form a second interlayer dielectric layer 123, so as to obtain Fig.32 The structure shown.

[0211] In some embodiments, before forming the second source-drain structure 122 , the sacrificial layer 34 in the second active structure 31 may be laterally etched to a certain depth, and silicon nitride insulating material may be deposited at the position where the sacrificial layer 34 is removed to form an internal sidewall 36 of the second transistor 12 .

[0212] In the 31st step, the semiconductor structure is thinned until the etched barrier layer 24 is removed to obtain Fig.33 The structure shown.

[0213] Step 32: Thin the third filling structure 40 to below the bottom of the second active structure 31 to expose the second active structure 31 in the gate region. After thinning, the third filling structure 40 can be used as an isolation structure for the first gate structure 114 and the second gate structure 124. Fig.34 The structure shown.

[0214] It can be understood that the second gate dielectric layer 39 b wraps the second active structure 31 .

[0215] In the thirty-third step, a metal material is deposited on the second gate dielectric layer 39b to form a second gate electrode layer. Fig.35 The structure shown.

[0216] It can be understood that the second gate dielectric layer 39 b and the second gate electrode layer together form the second gate structure 124 .

[0217] Step 34: forming a second gate isolation structure 47 to obtain Fig.36 The structure shown.

[0218] It can be understood that in the cross-sectional view along the AA′ direction and the cross-sectional view along the BB′ direction, the second gate isolation structure 47 is located on both sides.

[0219] In step 35, a dielectric material is deposited on the second interlayer dielectric layer 123 and the second gate structure 124 to form a second dielectric layer 46. Subsequently, the second dielectric layer 46 and the second interlayer dielectric layer 123 are etched until the second source-drain structure 122 is exposed, and then a second source-drain metal 125 is deposited to obtain the following. Fig.37 The structure shown.

[0220] Step 36: forming a second metal interconnection layer 126 to obtain Fig.38 The structure shown.

[0221] It can be understood that after forming the second metal interconnection layer, the stacked transistor in the embodiment of the present application is completed.

[0222] In the disclosed embodiment, by preparing the first transistor before flipping the chip and preparing the second transistor after flipping the chip, a complementary flip-chip stacked transistor can be formed. The pseudo-gate structures of the first transistor and the second transistor are integrally formed, so that fewer high aspect ratio processes are used, and fully self-aligned flip-chip stacking of transistors of various forms can be more compatible. Furthermore, the gate dielectric layer of the first transistor and the second transistor can be integrally formed before flipping the chip, so that the gate dielectric layer is generated before most of the transistor structure is formed, which can reduce the damage to the transistor caused by high temperature.

[0223] In an embodiment of the present disclosure, a stacked transistor is provided. The stacked transistor can be used Figure 1 The method of one or more corresponding embodiments is prepared. Fig.38 As shown, the stacked transistor 10 includes:

[0224] The first transistor 11 and the second transistor 12 are arranged opposite to each other, and the first active structure 29 of the first transistor 11 and the second active structure 31 of the second transistor 12 form an active structure; the first transistor 11 includes a first gate structure 114, and the second transistor 12 includes a second gate structure 124. The first gate structure 114 of the first transistor 11 and the second gate structure 124 of the second transistor 12 are self-aligned.

[0225] In some embodiments, the first transistor 11 or the second transistor 12 is any one of the following: a fin field effect transistor, a full-surround gate field effect transistor, a vertical field effect transistor, a complementary field effect transistor, a fork-plate crystal transistor, and a planar field effect transistor, which is not limited in the embodiments of the present application.

[0226] It is understandable that the flip-chip stacked transistor solution in the embodiment of the present application is self-aligned, which solves the long-standing problems of complex processes and alignment difficulties in the existing mainstream technical solutions for stacked transistors, and promotes the industrialization of transistor stacking technology. On the other hand, through the self-aligned "back-to-back" active structure and gate structure, the upper and lower transistors can have independent signal and power supply networks, and are interconnected through stacked transistors, which greatly releases metal wiring resources.

[0227] Finally, the solution of realizing upper and lower transistors by flipping the wafer is compatible with the existing mainstream device architecture, and can realize the front and back stacking of planar transistors, FinFET, GAA Nanosheet, Forksheet (fork sheet transistor) and even vertical transistors (VTFET), without the need for special process development for specific device architectures. It is highly flexible and has strong extensibility from the perspective of semiconductor process node iteration. The flip-chip transistor is very advanced in concept, has important industrial value, is highly practical, and has broad prospects for development.

[0228] The present application embodiment provides a semiconductor device, including: a stacked transistor as described in the above embodiment. The specific definition of the stacked transistor can be found in the above Fig.38 The stacked transistors shown are not described in detail here.

[0229] The present application embodiment provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the above stacked transistor. The specific definition of the stacked transistor can be found in the above Fig.38 The structure shown will not be described in detail here.

[0230] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0231] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a stacked transistor, characterized in that: The method comprises: Etching once on a semiconductor substrate to form a stacked structure, wherein the stacked structure includes an active structure and a first sacrificial layer, and the active structure includes a first active structure and a second active structure; the first active structure, the second active structure and the first sacrificial layer are stacked in sequence in a first direction, the first active structure is farther away from the semiconductor substrate than the first sacrificial layer, and the first direction is a direction perpendicular to the semiconductor substrate; In the gate region of the stacked transistor, forming a dummy gate structure covering the stacked structure; Etching the stacked structure not covered by the dummy gate structure to form a first deep trench; Based on the first active structure in the gate region, epitaxially growing a first source-drain structure in the first deep trench; removing the dummy gate structure and the first sacrificial layer to expose the active structure in the gate region; Depositing a gate dielectric material on the exposed active structure to form a gate dielectric layer, wherein the gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer, wherein the first gate dielectric layer wraps the first active structure, and the second gate dielectric layer wraps the second active structure; Depositing a metal material on the first gate dielectric layer to form a first gate electrode layer, wherein the first gate dielectric layer and the first gate electrode layer together constitute a first gate structure; Flipping and removing the semiconductor substrate; Based on the second active structure in the gate region, epitaxially growing a second source-drain structure in the first deep trench; A metal material is deposited on the second gate dielectric layer to form a second gate electrode layer. The second gate dielectric layer and the second gate electrode layer together constitute a second gate structure.

2. The preparation method according to claim 1, characterized in that: Before epitaxially growing a first source-drain structure in the first deep trench based on the first active structure in the gate region, the method further includes: Depositing an oxide material in the first deep trench to form a first filling structure, wherein a height of the first filling structure is less than a height of the first active structure and greater than a height of the second active structure; Depositing an insulating material on the first filling structure to form an isolation layer, wherein the isolation layer is used to isolate the first source-drain structure from the second source-drain structure; Before epitaxially growing a second source-drain structure in the first deep trench based on the second active structure in the gate region, the method further includes: The first filling structure in the first deep trench is removed to expose the second active structure in the gate region.

3. The preparation method according to claim 2, characterized in that: The active structure further includes: a second sacrificial layer, the second sacrificial layer being located between the first active structure and the second active structure; The etching of the stacked structure not covered by the dummy gate structure to form a first deep trench comprises: Etching the first active structure, the second sacrificial layer, the second active structure, and the first sacrificial layer that are not covered by the dummy gate structure to form the first deep trench; In the gate region, an insulating material is deposited at a position where the second sacrificial layer is removed to form an isolation structure.

4. The preparation method according to claim 2, characterized in that: The method of etching a semiconductor substrate once to form a stacked structure comprises: forming an initial stacking structure and an initial barrier layer on a semiconductor substrate, wherein the initial barrier layer is located between the initial stacking structure and the semiconductor substrate; Etching the initial stacking structure and the initial barrier layer at one time to form the stacking structure and the barrier layer; Depositing an oxide material on the semiconductor substrate to form a shallow trench isolation structure, wherein the shallow trench isolation structure wraps the barrier layer; After etching the stacked structure not covered by the dummy gate structure to form a first deep trench, the method further includes: Etching the barrier layer at the bottom of the first deep trench to form an etched barrier layer, wherein the etched barrier layer is located in the gate region; depositing an oxide material at the location where the barrier layer is etched to form a second filling structure; The flipping and removing of the semiconductor substrate comprises: Flipping and removing the semiconductor substrate to expose the etched barrier layer and the shallow trench isolation structure; Removing the shallow trench isolation structure and retaining the etched barrier layer; Before epitaxially growing a second source-drain structure in the first deep trench based on the second active structure in the gate region, the method further includes: The second filling structure and the first filling structure not covered by the etched barrier layer are sequentially etched until the isolation layer is exposed.

5. The preparation method according to claim 1, characterized in that: When the stacked transistor is a full-surround gate field effect transistor, the first active structure and the second active structure are both formed by alternately stacking channel layers and sacrificial layers; After etching the stacked structure not covered by the dummy gate structure to form a first deep trench, the method further includes: Laterally etching the sacrificial layer in the active structure in the gate region to a preset depth; Depositing an insulating material at a position where the sacrificial layer is etched to form an inner spacer, wherein the inner spacer includes a first inner spacer and a second inner spacer, wherein the first inner spacer is opposite to the first active structure, and the second inner spacer is opposite to the second active structure; After removing the dummy gate structure and the first sacrificial layer to expose the active structure in the gate region, the method further includes: The sacrificial layer in the gate region is removed.

6. The preparation method according to claim 1, characterized in that: The method further comprises: After the first gate structure is formed, a third gate structure in the first gate structure is removed by a gate cutting process, and an insulating material is deposited at a position where the third gate structure is removed to form a first gate isolation structure; wherein, in a second direction, the third gate structure is located at two ends of the first gate structure; and the second direction is perpendicular to the first direction; and / or, After the second gate structure is formed, a gate cutting process is used to remove the fourth gate structure in the second gate structure, and an insulating material is deposited at the position where the fourth gate structure is removed to form a second gate isolation structure; wherein, in the second direction, the fourth gate structure is located at both ends of the second gate structure.

7. The preparation method according to claim 1, characterized in that: After epitaxially growing a first source-drain structure in the first deep trench based on the first active structure in the gate region, the method further includes: Depositing a dielectric material on the first source-drain structure to form a first interlayer dielectric layer; After depositing a metal material on the first gate dielectric layer to form a first gate electrode layer, the method further includes: Depositing a dielectric material on the first gate electrode layer and the first interlayer dielectric layer to form a first dielectric layer; Etching the first dielectric layer and the first interlayer dielectric until the first source-drain structure is exposed to form a first through hole; A metal material is deposited in the first through hole to form a first source-drain metal.

8. The preparation method according to claim 1, characterized in that: The first source-drain structure and the first gate structure together constitute a first transistor, and the second source-drain structure and the second gate structure together constitute a second transistor; The first transistor or the second transistor is any one of the following: FinFET, gate-all-around FET, vertical FET, complementary FET, forkplate FET, and planar FET.

9. A stacked transistor, prepared using the preparation method according to any one of claims 1 to 8, characterized in that: include: a first transistor; a second transistor, wherein the first transistor and the second transistor are arranged opposite to each other, and a first active structure of the first transistor and a second active structure of the second transistor form an active structure; The first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned.

10. A semiconductor device, characterized in that: include: The stacked transistor as claimed in claim 9.

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