Enhanced GaN longitudinal field effect transistor with reverse follow current capability

Abstract

The invention belongs to the technical field of power semiconductors, and relates to an enhanced GaN longitudinal field effect transistor with reverse follow current capability. The fly-wheel diode is mainly characterized in that when the P-GaN layer is etched, the P-GaN layer below the grid electrode is reserved, the enhancement mode is achieved, meanwhile, part of the non-etched P-GaN layer is reserved at the other end of the device and makes contact with source electrode metal, and therefore the fly-wheel diode with the anode and the source electrode being in short circuit and the cathode and the drain electrode being in short circuit is integrated. The transistor is only turned on during reverse conduction and is in a turned-off state in forward conduction and blocking modes, so that the forward characteristic of the device is not influenced. And compared with a fly-wheel diode which is reversely connected in parallel outside the device, parasitic parameters are reduced, the power density is improved, and the process is simple and easy to implement.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductors and relates to an enhanced GaN longitudinal field effect transistor with reverse freewheeling capability. Background Art

[0002] Compared with GaN HEMT lateral devices at the same withstand voltage level, GaN vertical field effect transistors require a smaller chip area and can achieve higher power density. However, weak reverse freewheeling capability is also one of the main problems restricting its practical application. To solve this problem, a freewheeling diode is usually connected in reverse parallel to the outside of the device or a Schottky contact is formed between the source and the semiconductor. However, these methods will introduce additional parasitic parameters such as capacitance and inductance or increase the leakage current of the device in the off state, reducing the reliability of the device. Summary of the invention

[0003] Based on the application needs of GaN vertical field effect transistors, the present invention proposes an enhanced GaN vertical field effect transistor with reverse freewheeling capability. Its characteristics are that when etching the P-GaN layer, the P-GaN layer below the gate is retained, and while achieving the enhanced mode, a portion of the unetched P-GaN layer is retained at the other end of the device to form a contact with the source metal, thereby integrating a freewheeling diode with the anode short-circuited with the source and the cathode short-circuited with the drain.

[0004] To achieve the above-mentioned object of the invention, the technical solution of the present invention is as follows:

[0005] An enhanced GaN vertical field effect transistor with reverse freewheeling capability comprises a first conductive material 1, a substrate 2, a drift region 3, a barrier layer 5 and a dielectric passivation layer 6 which are sequentially stacked in a vertical direction of the device; a second conductive material 71 and a fourth conductive material 72 are respectively provided at two ends of the upper surface of the device, and the lower ends of the second conductive material 71 and the fourth conductive material 72 extend downward, sequentially penetrate the dielectric passivation layer 6 and the barrier layer 5, and then extend into the drift region 3; a first P-GaN layer 91 and a second P-GaN layer 92 are provided on the upper surface of the barrier layer 5 between the second conductive material 71 and the fourth conductive material 72, and the first P-GaN layer 91 and the second P-GaN layer 92 are wrapped by the dielectric passivation layer 6, wherein the first P-GaN layer 91 is located on a side close to the second conductive material 71, and there is a spacing between them; a first P-GaN buried layer 41 and a second P-GaN buried layer 42 are also provided in the drift region 3, and the first P-GaN layer 91 and the second P-GaN layer 92 are respectively provided in the drift region 3, There is a gap between the upper ends of the P-GaN buried layer 41 and the second P-GaN buried layer 42 and the upper end of the drift region 3, and one side of the upper end of the first P-GaN buried layer 41 contacts the lower end of the second conductive material 71, and the other side of the upper end of the first P-GaN buried layer 41 extends to be located directly below a portion of the first P-GaN layer 91, and one side of the upper end of the second P-GaN buried layer 42 contacts the lower end of the fourth conductive material 72, and the other side of the upper end of the second P-GaN buried layer 42 extends to be located directly below a portion of the second P-GaN layer 92; a third conductive material 8 is provided on the upper surface of the first P-GaN layer 91, and the third conductive material 8 extends to both sides of the portion that exceeds the upper surface of the dielectric passivation layer 6; a side of the fourth conductive material 72 close to the second P-GaN layer 92 extends toward the second P-GaN layer 92 to be directly above the second P-GaN layer 92, and the end extends downward to contact the upper surface of the second P-GaN layer 92;

[0006] The first conductive material 1 forms an ohmic contact with the GaN substrate 2 to lead out the drain; the second conductive material 71 forms an ohmic contact with the drift region 3 to lead out the source; the third conductive material 8 leads out the gate; the fourth conductive material 72 forms an ohmic contact with the drift region 3 to lead out the source.

[0007] Furthermore, the lower end of the second conductive material 71 is embedded in the upper end of the first P-GaN buried layer 41 ; and the lower end of the fourth conductive material 72 is embedded in the upper end of the second P-GaN buried layer 42 .

[0008] Furthermore, the lateral width of the third conductive material 8 located on the upper surface of the dielectric passivation layer 6 is smaller than the lateral width of the first P-GaN layer 91 .

[0009] Furthermore, the extended portion of the fourth conductive material 72 contacts the middle portion of the upper surface of the second P-GaN layer 92 .

[0010] Furthermore, the material used for the substrate 1 is one of sapphire, Si, SiC, AlN, GaN, AlGaN, ZnO, and GaAs.

[0011] Furthermore, the barrier layer 5 is made of one or a combination of AlN, AlGaN, InGaN and InAlN.

[0012] Furthermore, the material used for the dielectric passivation layer 6 is one of SiNx, SiO2, Al2O3, and AlN.

[0013] The beneficial effect of the present invention is that the integrated freewheeling diode overcomes the problems of large leakage current of the device in the off state and the introduction of additional parasitic capacitance and inductance. It is only turned on during reverse conduction and is in the off state during forward conduction and blocking mode, and will not affect the forward characteristics of the device. The freewheeling diode is integrated while realizing the enhanced type of the device, and the process difficulty is low and easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a structural schematic diagram of Example 1. DETAILED DESCRIPTION

[0015] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and embodiments:

[0016] Example 1

[0017] like Figure 1As shown, an enhanced GaN vertical field effect transistor with reverse freewheeling capability comprises a first conductive material 1, a substrate 2, a drift region 3, a barrier layer 5 and a dielectric passivation layer 6 which are sequentially stacked in the vertical direction of the device; a second conductive material 71 and a fourth conductive material 72 are respectively provided at two ends of the upper surface of the device, and the lower ends of the second conductive material 71 and the fourth conductive material 72 extend downward, sequentially penetrate the dielectric passivation layer 6 and the barrier layer 5, and then extend into the drift region 3; a first P-GaN layer 91 and a second P-GaN layer 92 are provided on the upper surface of the barrier layer 5 between the second conductive material 71 and the fourth conductive material 72, and the first P-GaN layer 91 and the second P-GaN layer 92 are wrapped by the dielectric passivation layer 6, wherein the first P-GaN layer 91 is located on a side close to the second conductive material 71, and there is a spacing between them; a first P-GaN buried layer 41 and a second P-GaN buried layer 42 are also provided in the drift region 3, There is a gap between the upper ends of the first P-GaN buried layer 41 and the second P-GaN buried layer 42 and the upper end of the drift region 3, and one side of the upper end of the first P-GaN buried layer 41 contacts the lower end of the second conductive material 71, and the other side of the upper end of the first P-GaN buried layer 41 extends to be located directly below a portion of the first P-GaN layer 91, and one side of the upper end of the second P-GaN buried layer 42 contacts the lower end of the fourth conductive material 72, and the other side of the upper end of the second P-GaN buried layer 42 extends to be located directly below a portion of the second P-GaN layer 92; a third conductive material 8 is provided on the upper surface of the first P-GaN layer 91, and the third conductive material 8 extends to both sides of the portion exceeding the upper surface of the dielectric passivation layer 6; a side of the fourth conductive material 72 close to the second P-GaN layer 92 extends toward the second P-GaN layer 92 to be directly above the second P-GaN layer 92, and the end extends downward to contact the upper surface of the second P-GaN layer 92;

[0018] The first conductive material 1 forms an ohmic contact with the GaN substrate 2 to lead out the drain; the second conductive material 71 forms an ohmic contact with the drift region 3 to lead out the source; the third conductive material 8 leads out the gate; the fourth conductive material 72 forms an ohmic contact with the drift region 3 to lead out the source.

[0019] The working principle of the present invention is as follows: during reverse freewheeling, the source is at a high potential relative to the drain, a 2DEG channel is formed under the second P-GaN layer, and the PN junction formed by the second P-GaN buried layer and the drift region is in a forward biased state, and the depletion region formed between the two shrinks, so that a conductive path is generated between the source and the drain, and the current flows from the source through the 2DEG channel and the drift region to the drain.

[0020] When forward conduction occurs, the 2DEG channel under the gate is opened, and the current flows from the drain through the drift region and then through the channel to the source. At this time, the 2DEG in the channel under the second P-GaN layer is depleted, and the PN junction formed by the second P-GaN buried layer and the drift region is in a reverse biased state. The depletion regions formed by the two overlap, blocking the conductive path and not affecting the forward characteristics of the device.

[0021] During forward blocking, the 2DEG in the channel below the first P-GaN layer is depleted, and the PN junction formed by the first P-GaN buried layer and the drift region is in a reverse biased state, and the depletion regions formed by the two overlap, blocking the conductive path; similarly, the 2DEG in the channel below the second P-GaN layer is depleted, and the PN junction formed by the second P-GaN buried layer and the drift region is in a reverse biased state, and the depletion regions formed by the two overlap, blocking the conductive path.

Claims

1. An enhanced GaN vertical field effect transistor with reverse freewheeling capability, characterized in that: The device comprises a first conductive material (1), a substrate (2), a drift region (3), a barrier layer (5) and a dielectric passivation layer (6) which are sequentially stacked in a vertical direction of the device; a second conductive material (71) and a fourth conductive material (72) are respectively provided at two ends of the upper surface of the device, and the lower ends of the second conductive material (71) and the fourth conductive material (72) extend downward, sequentially penetrate the dielectric passivation layer (6) and the barrier layer (5), and then extend into the drift region (3); between the second conductive material (71) and the fourth conductive material (72) ) have a first P-GaN layer (91) and a second P-GaN layer (92) on their upper surfaces, and the first P-GaN layer (91) and the second P-GaN layer (92) are wrapped by a dielectric passivation layer (6), wherein the first P-GaN layer (91) is located on a side close to the second conductive material (71) and there is a distance between them; and a first P-GaN buried layer (41) and a second P-GaN buried layer (42) are respectively provided in the drift region (3), and the first P-GaN buried layer ( The first P-GaN buried layer (41) and the second P-GaN buried layer (42) have a gap with the upper end of the drift region (3), and one side of the upper end of the first P-GaN buried layer (41) contacts the lower end of the second conductive material (71), and the other side of the upper end of the first P-GaN buried layer (41) extends to be located directly below a portion of the first P-GaN layer (91), and one side of the upper end of the second P-GaN buried layer (42) contacts the lower end of the fourth conductive material (72), and the other side of the upper end of the second P-GaN buried layer (42) extends to be located directly below a portion of the first P-GaN layer (91). The fourth conductive material (72) extends to be located directly below a portion of the second P-GaN layer (92); a third conductive material (8) is provided on the upper surface of the first P-GaN layer (91), and the portion of the third conductive material (8) that exceeds the upper surface of the dielectric passivation layer (6) extends to both sides; a side of the fourth conductive material (72) close to the second P-GaN layer (92) extends toward the second P-GaN layer (92) to be directly above the second P-GaN layer (92), and the end extends downward to contact the upper surface of the second P-GaN layer (92); The first conductive material (1) forms an ohmic contact with the GaN substrate (2) to lead out a drain electrode; the second conductive material (71) forms an ohmic contact with the drift region (3) to lead out a source electrode; the third conductive material (8) leads out a gate electrode; and the fourth conductive material (72) forms an ohmic contact with the drift region (3) to lead out a source electrode.

2. The enhanced GaN vertical field effect transistor with reverse freewheeling capability according to claim 1, characterized in that: The lower end of the second conductive material (71) is embedded in the upper end of the first P-GaN buried layer (41); and the lower end of the fourth conductive material (72) is embedded in the upper end of the second P-GaN buried layer (42).

3. The enhanced GaN vertical field effect transistor with reverse freewheeling capability according to claim 1, characterized in that: The lateral width of the third conductive material (8) located on the upper surface of the dielectric passivation layer (6) is smaller than the lateral width of the first P-GaN layer (91).

4. The enhanced GaN vertical field effect transistor with reverse freewheeling capability according to claim 1, characterized in that: The extended portion of the fourth conductive material (72) contacts the middle portion of the upper surface of the second P-GaN layer (92).

5. The enhanced GaN vertical field effect transistor with reverse freewheeling capability according to claim 1, characterized in that: The material used for the substrate (1) is one of sapphire, Si, SiC, AlN, GaN, AlGaN, ZnO, and GaAs.

6. The enhancement mode GaN vertical field effect transistor with reverse freewheeling capability according to claim 1, characterized in that: The material used for the barrier layer (5) is one or a combination of AlN, AlGaN, InGaN and InAlN.

7. The enhancement mode GaN vertical field effect transistor with reverse freewheeling capability according to claim 1, characterized in that: The material used for the dielectric passivation layer (6) is SiN x , one of SiO2, Al2O3, and AlN.

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