Chip, chip manufacturing method, computing device and signal transmission method

Abstract

The embodiment of the invention discloses a chip, a chip manufacturing method, computing equipment and a signal transmission method. A packaging substrate of the chip comprises a basic pattern unit with six signal pins, a first pin, a second pin, a third pin and a fourth pin of the basic pattern unit are sequentially arranged at intervals in a first direction, and a fifth pin and a sixth pin of the basic pattern unit are arranged at intervals in a second direction; the fifth pin and the sixth pin are located on the two sides of a connecting line of the second pin and the third pin respectively, the first pin, the fourth pin, the fifth pin and the sixth pin are data signal pins, and the second pin and the third pin are control signal pins. According to the scheme, the data signal pins are arranged at the four outwards-extending ends of the cross-shaped pattern unit respectively, the data signal pins are far away from one another, each data signal pin is not provided with an adjacent data signal pin capable of forming a crosstalk source, and electromagnetic crosstalk between the pins can be effectively reduced; meanwhile, the arrangement density of the pins can be improved, and the packaging area is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of electronic device packaging, and in particular, to a chip, a chip manufacturing method, a computing device, and a signal transmission method. Background Art

[0002] With the continuous development of storage technology, double data rate synchronous dynamic random access memory (DDR SDRAM) systems have been widely used in computing products, such as but not limited to server products. However, with the evolution of DDR generations, the performance improvement of DDR systems has put forward higher requirements for chip packaging technology.

[0003] In DDR systems, the number of channels increases, and the number of I / O (input / output) pins also increases, resulting in larger chip package sizes. Larger package sizes usually mean larger volumes and masses. The welding of chips to PCBs (Printed Circuit Boards) generates more heat. Chip packages and PCBs mostly have different material thermal expansion coefficients, which can lead to larger welding temperature gradients, causing thermal stress and thermal fatigue, and increasing the risk of solder joints. In addition, the deformation of large-size packages is more difficult to control, which can easily lead to the risk of welding defects and poor connections, directly affecting product costs and yields.

[0004] On the other hand, the DDR interface speed is getting faster and faster, which has a greater impact on the crosstalk between adjacent signals. In order to reduce the electromagnetic crosstalk between pins, a typical processing method is to set ground solder balls around the pins of the chip packaging substrate, which can reduce the impact of electromagnetic crosstalk, but the setting of ground solder balls will increase the chip size.

[0005] Therefore, the pin arrangement of the chip packaging substrate needs to take into account two trending design requirements: high-density arrangement and low crosstalk to meet the performance requirements of the product. Summary of the invention

[0006] The embodiments of the present application provide a chip, a chip manufacturing method, a computing device and a signal transmission method, which can improve the arrangement density and effectively reduce electromagnetic crosstalk.

[0007] The first aspect of the embodiment of the present application provides a chip, the core of the chip is arranged on its packaging substrate, and the packaging substrate is a carrier for the core packaging. A plurality of pin arrangement graphic units are arranged in the pin area of ​​the packaging substrate, and at least two of the plurality of pin arrangement graphic units are basic graphic units including six signal pins. Among them, the first pin, the second pin, the third pin and the fourth pin of the six signal pins of the basic graphic unit are arranged in sequence in a first direction, and the fifth pin and the sixth pin of the six signal pins are arranged in a second direction, the first direction is different from the second direction, and the fifth pin and the sixth pin are respectively located on both sides of the connection line between the second pin and the third pin. In addition, the first pin, the fourth pin, the fifth pin and the sixth pin are data signal pins, and the second pin and the third pin are control signal pins.

[0008] With this arrangement, the pins of the basic graphic unit are arranged in a cross-shaped pattern, the four data signal pins are arranged at the four protruding ends of the cross-shaped graphic unit, and the control signal pin is arranged in the middle of the cross-shaped graphic unit, so that the data signal pins are kept away from each other, and each data signal pin has no adjacent data signal pins that form a crosstalk source, which can effectively avoid the influence of electromagnetic crosstalk between adjacent data signal pins. Based on this Pinmap solution, on the one hand, the electromagnetic crosstalk between pins is effectively reduced, which can support a higher DDR operating rate; on the other hand, the density of the pin arrangement can be increased, saving packaging area, and providing technical support for further improving product yield and reducing processing costs.

[0009] Exemplarily, each pin in the pin area of ​​the package substrate may be a solder ball structure, which is electrically connected to a corresponding pad on the circuit board through welding. Each pin in the pin area of ​​the package substrate may also be a metal contact point structure, and a metal spring is correspondingly provided on the circuit board. The metal contact points and the metal springs may be provided in a one-to-one correspondence, and the assembled metal contact points press against the metal springs, and the deformed metal springs maintain a reliable electrical connection with the matching metal contact points.

[0010] In actual applications, the multiple pin arrangement graphic units in the pin area of ​​the package substrate can be configured into different pin arrangements according to actual functional requirements; for example, a part of the pin arrangement graphic units are configured as basic graphic units of the cross-shaped pattern to build channels of the DDR memory system; another part of the pin arrangement graphic units are configured as graphic units including other arrangements to achieve electrical connection with corresponding external circuits; that is, the pin arrangement of the pin area of ​​the package substrate can be obtained by combining and arranging several types of graphic units.

[0011] Based on the first aspect, the embodiment of the present application also provides a first implementation method of the first aspect: the fifth pin and the sixth pin are arranged on the perpendicular line of the line connecting the second pin and the third pin, where the first direction is perpendicular to the second direction. Further, the fifth pin and the sixth pin can be arranged on the perpendicular midline of the line connecting the second pin and the third pin, and have good structural symmetry as a whole, so as to obtain a more compact overall layout in the pin area.

[0012] In practical applications, the connection line between the fifth pin and the sixth pin may also intersect the connection line between the second pin and the third pin at other angles, which can also keep the data signal pins away from each other and reduce electromagnetic crosstalk.

[0013] Based on the first aspect, or the first implementation of the first aspect, the embodiment of the present application further provides a second implementation of the first aspect: the basic graphic unit adopts a central symmetric structure, or an axisymmetric structure. In this way, the pin area can be fully utilized to achieve high-density layout, and the package size can be more reasonably controlled on the basis of effectively reducing electromagnetic crosstalk between pins.

[0014] Based on the first aspect, or the first implementation manner of the first aspect, or the second implementation manner of the first aspect, the embodiment of the present application also provides a third implementation manner of the first aspect: the pins in the pin area of ​​the packaging substrate are arranged in an array, wherein the pins between rows and columns are staggered, that is, each row of pins and each column of pins are staggered with each other, and as many pins as possible can be arranged in a limited layout space, which can achieve a tight alternating arrangement of the cross-shaped graphic units and further improve the pin arrangement density.

[0015] Based on the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, the embodiment of the present application further provides a fourth implementation of the first aspect: the pins of the pin area of ​​the package substrate are arranged in a triangular grid, and the line connecting the pin and the two adjacent pins forms an equilateral triangle. In this way, the closely alternating arrangement of the cross-shaped arrangement graphic units can be further achieved, thereby improving the pin arrangement density.

[0016] Based on the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, or the fourth implementation of the first aspect, the embodiment of the present application further provides a fifth implementation of the first aspect: the basic graphic unit also includes a ground pin, where the ground pin is arranged around the six signal pins. In this way, based on the arrangement of the ground pins, a low-impedance ground path can be provided to form a uniform ground potential, thereby guiding the energy of the electromagnetic field to the ground plane, thereby reducing electromagnetic crosstalk between signal pins, helping to maintain signal integrity, and reducing noise.

[0017] Exemplarily, the ground pin may be a solder ball structure, or may be a metal contact point structure.

[0018] Based on the fifth implementation of the first aspect, the embodiment of the present application also provides a sixth implementation of the first aspect: the basic graphic unit has fourteen grounding pins, which are arranged on the periphery of the six signal pins, and the fourteen grounding pins are arranged in sequence; on the whole, the fourteen grounding pins are arranged in sequence to form a tetragon; the data signal pins adjacent to two adjacent grounding pins and the connection line between the two adjacent grounding pins form an equilateral triangle. This arrangement makes full use of the pin area space where the pin rows and columns are staggered, and constructs the Pinmap unit according to the rules of alternating arrangement, and the distance between any two adjacent pins is consistent. While providing the return ground function, it can increase the pin arrangement density and have a higher signal-to-ground ratio.

[0019] Based on the fifth implementation of the first aspect, or the sixth implementation of the first aspect, the embodiment of the present application further provides a seventh implementation of the first aspect: two basic graphic units are arranged adjacent to each other, one of which is a first basic graphic unit, and the other is a second basic graphic unit, and the adjacent sides of the first basic graphic unit and the second basic graphic unit share a ground pin, in other words, the ground pins on the adjacent sides of the two basic graphic units are common. In this way, in addition to effectively reducing electromagnetic crosstalk, the pin layout density is more compact and reasonable.

[0020] In practical applications, based on the staggered arrangement of the pin rows and columns in the pin area of ​​the package substrate, different forms of pin arrangement combination units can be formed by translation or rotation and translation and then splicing. For example, a cross-shaped pin arrangement graphic unit can correspond to the transmission of a half-byte unit of data, and a pin arrangement combination unit formed by splicing two pin arrangement graphic units can correspond to the transmission of a byte unit of data.

[0021] Exemplarily, one of the two pin arrangement graphic units of the pin arrangement combination unit may be a graphic unit formed by translation relative to the other; or one may be a graphic unit formed by rotation and translation relative to the other.

[0022] Based on the seventh implementation manner of the first aspect, the embodiment of the present application also provides an eighth implementation manner of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in a first direction, the first basic graphic unit and the second basic graphic have a common ground pin, and the first pin, the second pin, the third pin and the fourth pin of the first basic graphic unit are arranged in the same direction as the first pin, the second pin, the third pin and the fourth pin of the second basic graphic unit; the common ground pin is located between the fourth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0023] Based on the seventh implementation manner of the first aspect, the embodiment of the present application also provides a ninth implementation manner of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in the second direction, and the fifth pin and the sixth pin of the first basic graphic unit are arranged in the same direction as the fifth pin and the sixth pin of the second basic graphic unit; the first basic graphic unit and the second basic graphic have two spaced-apart common ground pins, and the two common ground pins are located between the sixth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit.

[0024] Based on the seventh implementation manner of the first aspect, the embodiment of the present application also provides a tenth implementation manner of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively, and the first pin, the second pin, the third pin and the fourth pin of the first basic graphic unit are arranged in the same direction as the sixth pin of the second basic graphic unit; the first basic graphic unit and the second basic graphic have two spaced-apart common ground pins, and the two common ground pins are located between the fourth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0025] Based on the seventh implementation manner of the first aspect, the embodiment of the present application also provides an eleventh implementation manner of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively, and the fifth pin and the sixth pin of the first basic graphic unit are arranged in the same direction as the first pin of the second basic graphic unit; the fourth pin of the first basic graphic unit is arranged in the same direction as the fifth pin and the sixth pin of the second basic graphic unit; the first basic graphic unit and the second basic graphic unit have four common grounding pins; the four common grounding pins are arranged in sequence, wherein two common grounding pins are located between the sixth pin of the first basic graphic unit and the first pin of the second basic graphic unit, and the other two common grounding pins are located between the fourth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit.

[0026] Based on the seventh implementation manner of the first aspect, the embodiment of the present application also provides a twelfth implementation manner of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively, and the fourth pin of the first basic graphic unit is arranged in the same direction as the first pin of the second basic graphic unit; the sixth pin of the first basic graphic unit is arranged in the same direction as the fifth pin of the second basic graphic unit; the first basic graphic unit and the second basic graphic unit have four common grounding pins; the four common grounding pins are arranged in sequence at intervals, wherein two common grounding pins are located between the fourth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit, and the other two common grounding pins are located between the sixth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0027] Based on the seventh implementation manner of the first aspect, the embodiment of the present application also provides a thirteenth implementation manner of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated and rotated graphics, the first pin and the fifth pin of the first basic graphic unit are arranged in the same direction as the fifth pin and the sixth pin of the second basic graphic unit; the sixth pin and the fourth pin of the first basic graphic unit are arranged in the same direction as the first pin of the second basic graphic unit; the first basic graphic unit and the second basic graphic have four common grounding pins; the four common grounding pins are arranged in sequence at intervals, two of which are adjacent to the fifth pin of the first basic graphic unit, and the other two common grounding pins are adjacent to the fourth pin of the first basic graphic unit.

[0028] Based on the fifth implementation of the first aspect, the embodiment of the present application further provides a fourteenth implementation of the first aspect: the basic graphic unit has fourteen grounding pins, and the fourteen grounding pins are sequentially arranged at intervals around the six signal pins; and in the first direction, the first grounding pin is located beside the first pin, and the eighth grounding pin is located beside the fourth pin, and at the same time, the second grounding pin, the third grounding pin, the fourth grounding pin, the fifth grounding pin, the sixth grounding pin and the seventh grounding pin are sequentially arranged between the first grounding pin and the eighth grounding pin; the ninth grounding pin, the tenth grounding pin, the eleventh grounding pin, the twelfth grounding pin, the thirteenth grounding pin and the fourteenth grounding pin are sequentially arranged between the eighth grounding pin and the first grounding pin. The overall layout is more compact and reasonable.

[0029] Based on the fourteenth implementation manner of the first aspect, the embodiment of the present application also provides the fifteenth implementation manner of the first aspect: two basic graphic units are arranged adjacent to each other, one of the two basic graphic units is a first basic graphic unit, and the other of the two basic graphic units is a second basic graphic unit, and adjacent sides of the first basic graphic unit and the second basic graphic unit share a ground pin.

[0030] Based on the fifteenth implementation of the first aspect, the embodiment of the present application also provides the sixteenth implementation of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, wherein the eighth ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are common ground pins.

[0031] Based on the fifteenth implementation manner of the first aspect, the embodiment of the present application also provides the sixteenth implementation manner of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, wherein the twelfth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are shared ground pins; wherein the eleventh ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are shared ground pins.

[0032] Based on the fifteenth implementation manner of the first aspect, the embodiment of the present application also provides the sixteenth implementation manner of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, wherein the seventh ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are a common ground pin; wherein the eighth ground pin of the first basic graphic unit and the fourteenth ground pin of the second basic graphic unit are a common ground pin.

[0033] Based on the fifteenth implementation manner of the first aspect, the embodiment of the present application also provides a sixteenth implementation manner of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, wherein the twelfth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are a common ground pin; wherein the eleventh ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are a common ground pin; wherein the tenth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are a common ground pin; wherein the ninth ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are a common ground pin.

[0034] Based on the fifteenth implementation manner of the first aspect, the embodiment of the present application also provides a sixteenth implementation manner of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, wherein the eleventh ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are a common ground pin; wherein the tenth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are a common ground pin; wherein the ninth ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are a common ground pin; wherein the eighth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are a common ground pin.

[0035] Based on the fifteenth implementation manner of the first aspect, the embodiment of the present application also provides the sixteenth implementation manner of the first aspect: the first basic graphic unit and the second basic graphic unit are mutually translated and rotated graphics; wherein, the fifth ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are shared ground pins; wherein, the sixth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are shared ground pins; wherein, the seventh ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are shared ground pins; wherein, the eighth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are shared ground pins.

[0036] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, or the third embodiment of the first aspect, or the fourth embodiment of the first aspect, or the fifth embodiment of the first aspect, or the sixth embodiment of the first aspect, or the seventh embodiment of the first aspect, or the eighth embodiment of the first aspect, or the ninth embodiment of the first aspect, or the tenth embodiment of the first aspect, or the eleventh embodiment of the first aspect, or the twelfth embodiment of the first aspect, or the thirteenth embodiment of the first aspect, or the fourteenth embodiment of the first aspect, or the fifteenth embodiment of the first aspect, or the sixteenth embodiment of the first aspect, this application The embodiment also provides a seventeenth implementation of the first aspect: for a basic graphic unit including six signal pins, its first pin, fourth pin, fifth pin and sixth pin are single-ended signal pins for transmitting DQ data signals; its second pin and third pin are differential signal pins for transmitting DQS signals, so that when the two control signal pins transmit the DQS differential clock signal, the polarity of the differential signal pair is opposite during transmission, that is, the amplitudes of the signals transmitted on the two pins of the differential signal pair are opposite, thereby, the interference to the two single-ended signal pins adjacent to it above and below in the second direction can be completely offset, and the crosstalk to the two single-ended signal pins on the left and right of the first direction can be partially offset, thereby reducing the total crosstalk amount received by the single-ended signal.

[0037] In practical applications, for example, in an X8 scenario, the differential signal pins can be configured as channels for multiplexing DM signals to transmit DM signals to provide shielding and selective writing of each data bit. When the control signal pins are used to transmit DM signals, the actual electromagnetic crosstalk generated is low and will not affect the data transmission of the data signal pins.

[0038] Based on the first aspect, the embodiment of the present application further provides an eighteenth implementation of the first aspect: the chip may be a central processing unit, wherein the central processing unit is configured with multiple memory channels, specifically, the memory channel includes multiple byte units, the byte units correspond to two of at least some of the basic graphic units, and the data signal pins in the basic graphic units are used to transmit the data signals of the corresponding byte units. Thus, based on the effective reduction of electromagnetic crosstalk between pins, a higher data transmission speed and higher access efficiency can be obtained.

[0039] A second aspect of an embodiment of the present application provides an electronic device, including a housing and a circuit board arranged in the housing, on which a chip is arranged; the chip adopts the chip described above, and the signal pins of the chip are electrically connected to the circuit board.

[0040] In practical applications, the electronic device may be a computing device such as a server, a supercomputer or an Ethernet switch, or a terminal device such as a mobile phone, a learning machine or a laptop computer.

[0041] The third aspect of the embodiment of the present application provides a chip manufacturing method, which sets a core particle on a packaging substrate, and assembles the core particle and the packaging substrate together to form the chip; specifically, a plurality of pin arrangement graphic units are set in the pin area of ​​the packaging substrate, and at least two of the plurality of pin arrangement graphic units are basic graphic units including six signal pins. Among them, the first pin, the second pin, the third pin and the fourth pin of the six signal pins of the basic graphic unit are arranged in sequence in a first direction, and the fifth pin and the sixth pin of the six signal pins are arranged in a second direction, the first direction is different from the second direction, and the fifth pin and the sixth pin are respectively located on both sides of the connection line between the second pin and the third pin; wherein the first pin, the fourth pin, the fifth pin and the sixth pin are data signal pins, and the second pin and the third pin are control signal pins; the method comprises the following steps: transmitting data signals through the first pin, the fourth pin, the fifth pin and the sixth pin, and transmitting control signals through the second pin and the third pin. Based on the cross-shaped basic graphic units, the chip ensures correct signal transmission through good anti-crosstalk performance, thus providing technical guarantee for high-performance and reliable system applications.

[0042] Based on the third aspect, the embodiment of the present application also provides a first implementation of the third aspect: the fifth pin and the sixth pin are arranged on a vertical line of the line connecting the second pin and the third pin, where the first direction is perpendicular to the second direction.

[0043] Based on the first implementation of the third aspect, the embodiment of the present application also provides a second implementation of the third aspect: the fifth pin and the sixth pin are arranged on the perpendicular bisector of the line connecting the second pin and the third pin, and the basic graphic unit adopts a centrally symmetrical structure and can also adopt an axially symmetrical structure.

[0044] Based on the third aspect, or the first implementation of the third aspect, or the second implementation of the third aspect, the embodiment of the present application further provides a third implementation of the third aspect: the pins in the pin area of ​​the package substrate are arranged in a triangular grid, and specifically, the pin and the connecting line of the two adjacent pins form an equilateral triangle. In this way, the closely alternating arrangement of the cross-shaped arrangement graphic units can be further realized, thereby improving the pin arrangement density.

[0045] Based on the third implementation of the third aspect, the embodiment of the present application further provides a fourth implementation of the third aspect: two basic graphic units are arranged adjacent to each other, one of the two basic graphic units is a first basic graphic unit, the other of the two basic graphic units is a second basic graphic unit, and the adjacent sides of the first basic graphic unit and the second basic graphic unit share a ground pin, in other words, the ground pins on the adjacent sides of the two basic graphic units are common. In this way, in addition to effectively reducing electromagnetic crosstalk, the pin layout density is more compact and reasonable.

[0046] Based on the fourth implementation of the third aspect, the embodiment of the present application also provides a fifth implementation of the third aspect: the first basic graphic unit and the second basic graphic unit are translated graphics of each other, and the translation can be a translation in a first direction. The first basic graphic unit and the second basic graphic have a common ground pin, and the common ground pin is located between the fourth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0047] Based on the fourth implementation of the third aspect, the embodiment of the present application also provides a sixth implementation of the third aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in the second direction. The first basic graphic unit and the second basic graphic have two spaced-apart common ground pins, and the two common ground pins are located between the sixth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit.

[0048] Based on the fourth implementation of the third aspect, the embodiment of the present application also provides a seventh implementation of the third aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively, and the first basic graphic unit and the second basic graphic have two spaced-apart common ground pins, and the two common ground pins are located between the fourth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0049] Based on the fourth implementation manner of the third aspect, the embodiment of the present application also provides an eighth implementation manner of the third aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively, and the first basic graphic unit and the second basic graphic have four common ground pins; the four common ground pins are arranged in sequence at intervals, wherein two common ground pins are located between the sixth pin of the first basic graphic unit and the first pin of the second basic graphic unit, and wherein the other two common ground pins are located between the fourth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit.

[0050] Based on the fourth implementation manner of the third aspect, the embodiment of the present application also provides a ninth implementation manner of the third aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively, and the first basic graphic unit and the second basic graphic have four common ground pins; the four common ground pins are arranged in sequence at intervals, wherein two common ground pins are located between the fourth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit, and wherein the other two common ground pins are located between the sixth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0051] Based on the fourth implementation manner of the third aspect, the embodiment of the present application also provides a tenth implementation manner of the third aspect: the first basic graphic unit and the second basic graphic unit are mutually translated and rotated graphics, and the first basic graphic unit and the second basic graphic have four common ground pins; the four common ground pins are arranged in sequence at intervals, two of which are adjacent to the fifth pin of the first basic graphic unit, and the other two are adjacent to the fourth pin of the first basic graphic unit.

[0052] The fourth aspect of the embodiment of the present application provides a signal transmission method, which is applied to a chip. Specifically, the chip includes a packaging substrate, and a plurality of pin arrangement graphic units are arranged in the pin area of ​​the packaging substrate. At least two of the plurality of pin arrangement graphic units are basic graphic units including six signal pins. Among them, the first pin, the second pin, the third pin and the fourth pin of the six signal pins of the basic graphic unit are arranged in sequence in a first direction, and the fifth pin and the sixth pin of the six signal pins are arranged in a second direction, the first direction is different from the second direction, and the fifth pin and the sixth pin are respectively located on both sides of the connection line between the second pin and the third pin; wherein the first pin, the fourth pin, the fifth pin and the sixth pin are data signal pins, and the second pin and the third pin are control signal pins; the method includes the following steps: transmitting data signals through the first pin, the fourth pin, the fifth pin and the sixth pin, and transmitting control signals through the second pin and the third pin. Based on the cross-shaped basic graphic units, the chip ensures correct signal transmission through good anti-crosstalk performance, thus providing technical guarantee for high-performance and reliable system applications.

[0053] Based on the fourth aspect, the embodiment of the present application also provides a first implementation of the fourth aspect: the fifth pin and the sixth pin are arranged on a vertical line of the line connecting the second pin and the third pin, where the first direction is perpendicular to the second direction.

[0054] Based on the first implementation of the fourth aspect, the embodiment of the present application also provides a second implementation of the fourth aspect: the fifth pin and the sixth pin are arranged on the perpendicular bisector of the line connecting the second pin and the third pin, and the basic graphic unit adopts a centrally symmetrical structure and can also adopt an axially symmetrical structure.

[0055] Based on the fourth aspect, or the first implementation of the fourth aspect, or the second implementation of the fourth aspect, the embodiment of the present application further provides a third implementation of the fourth aspect: the pins in the pin area of ​​the package substrate are arranged in a triangular grid, and specifically, the pin and the connecting line of the two adjacent pins form an equilateral triangle. In this way, the closely alternating arrangement of the cross-shaped arrangement graphic units can be further realized, thereby improving the pin arrangement density.

[0056] Based on the third implementation of the fourth aspect, the embodiment of the present application further provides a fourth implementation of the fourth aspect: two basic graphic units are arranged adjacent to each other, one of the two basic graphic units is a first basic graphic unit, the other of the two basic graphic units is a second basic graphic unit, and the adjacent sides of the first basic graphic unit and the second basic graphic unit share a ground pin, in other words, the ground pins on the adjacent sides of the two basic graphic units are common. In this way, in addition to effectively reducing electromagnetic crosstalk, the pin layout density is more compact and reasonable.

[0057] Based on the fourth implementation of the fourth aspect, the embodiment of the present application also provides a fifth implementation of the fourth aspect: the first basic graphic unit and the second basic graphic unit are translated graphics of each other, and the translation can be a translation in a first direction. The first basic graphic unit and the second basic graphic have a common ground pin, and the common ground pin is located between the fourth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0058] Based on the fourth implementation of the fourth aspect, the embodiment of the present application also provides a sixth implementation of the fourth aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in the second direction, and the first basic graphic unit and the second basic graphic have two spaced-apart common ground pins, and the two common ground pins are located between the sixth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit.

[0059] Based on the fourth implementation of the fourth aspect, the embodiment of the present application also provides a seventh implementation of the fourth aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively, and the first basic graphic unit and the second basic graphic have two spaced-apart common ground pins, and the two common ground pins are located between the fourth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0060] Based on the fourth implementation manner of the fourth aspect, the embodiment of the present application also provides an eighth implementation manner of the fourth aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively, and the first basic graphic unit and the second basic graphic have four common ground pins; the four common ground pins are arranged in sequence at intervals, wherein two common ground pins are located between the sixth pin of the first basic graphic unit and the first pin of the second basic graphic unit, and wherein the other two common ground pins are located between the fourth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit.

[0061] Based on the fourth implementation manner of the fourth aspect, the embodiment of the present application also provides a ninth implementation manner of the fourth aspect: the first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively, and the first basic graphic unit and the second basic graphic have four common ground pins; the four common ground pins are arranged in sequence at intervals, wherein two common ground pins are located between the fourth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit, and wherein the other two common ground pins are located between the sixth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0062] Based on the fourth implementation manner of the fourth aspect, the embodiment of the present application also provides a tenth implementation manner of the fourth aspect: the first basic graphic unit and the second basic graphic unit are mutually translated and rotated graphics, and the first basic graphic unit and the second basic graphic have four common ground pins; the four common ground pins are arranged in sequence at intervals, two of which are adjacent to the fifth pin of the first basic graphic unit, and the other two are adjacent to the fourth pin of the first basic graphic unit.

[0063] A fifth aspect of an embodiment of the present application provides a method for a CPU to read and send data, the CPU comprising a packaging substrate, a pin area of ​​the packaging substrate comprising a data signal pin and a data strobe signal pin, and the data signal pin and the data strobe signal pin are arranged according to a pin arrangement graphic unit, the pin arrangement graphic unit comprises six signal pins, a first pin, a fourth pin, a fifth pin and a sixth pin of the six signal pins are data signal pins, and a second pin and a third pin of the six signal pins are data strobe signal pins; wherein the first pin, the second pin, the third pin and the fourth pin are arranged in a first direction according to The fifth pin and the sixth pin are arranged at intervals in the second direction, the fifth pin and the sixth pin are arranged on a vertical line connecting the second pin and the third pin, and are respectively located on both sides of the second pin and the third pin; the method for the CPU to read and send data includes the following steps: responding to a write instruction or a read instruction of a DDR signal; sending data to the DDR memory through the data signal pin according to the write instruction, and outputting a data selection signal through the data selection signal pin; or, receiving data from the DDR memory through the data signal pin according to the read instruction, and reading the data selection signal through the data selection signal pin.

[0064] A sixth aspect of an embodiment of the present application provides a method for a CPU to read data, the CPU comprising a packaging substrate, a pin area of ​​the packaging substrate comprising a data signal pin and a data strobe signal pin, and the data signal pin and the data strobe signal pin are arranged according to a pin arrangement graphic unit, the pin arrangement graphic unit comprises six signal pins, a first pin, a fourth pin, a fifth pin and a sixth pin of the six signal pins are data signal pins, and a second pin and a third pin of the six signal pins are data strobe signal pins; wherein the first pin, the second pin, the third pin and the fourth pin are arranged in sequence in a first direction, and the fifth pin and the sixth pin are arranged in sequence in a second direction. The fifth pin and the sixth pin are arranged at intervals, and are configured on a vertical line connecting the second pin and the third pin, and are respectively located on both sides of the second pin and the third pin; the method for the CPU to read data includes the following steps: responding to a write instruction of a DDR signal, in a specific implementation, when the CPU or other devices need to read data in the memory, the memory controller sends a read command to the memory module and specifies the address to be read; sending data to the DDR memory through the data signal pin according to the write instruction, and outputting a data selection signal through the data selection signal pin, that is, providing a data clock signal to the DDR memory, so that the DDR memory can correctly receive and parse the data sent by the CPU.

[0065] A seventh aspect of an embodiment of the present application provides a method for a CPU to send data, the CPU comprising a packaging substrate, a pin area of ​​the packaging substrate comprising a data signal pin and a data strobe signal pin, and the data signal pin and the data strobe signal pin are arranged according to a pin arrangement graphic unit, the pin arrangement graphic unit comprises six signal pins, a first pin, a fourth pin, a fifth pin and a sixth pin of the six signal pins are data signal pins, and a second pin and a third pin of the six signal pins are data strobe signal pins; wherein the first pin, the second pin, the third pin and the fourth pin are arranged in sequence in a first direction, and the fifth pin and the sixth pin are arranged in sequence in a second direction. , the fifth pin and the sixth pin are arranged on a vertical line connecting the second pin and the third pin, and are respectively located on both sides of the second pin and the third pin; the method for the CPU to read and send data comprises the following steps: responding to a read instruction of a DDR signal, in a specific implementation, when the CPU or other devices need to write data into the memory, the memory controller sends a write command to the memory module, and provides the data to be written and the target address; receiving data from the DDR memory through the data signal pin according to the read instruction, and reading the data selection signal through the data selection signal pin, that is, providing a data clock signal to the CPU, so that the CPU can correctly sample and parse the data transmitted from the DDR memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1 A schematic diagram of a partial structure of an electronic device provided in an embodiment of the present application;

[0067] Figure 2 A schematic diagram of a pin arrangement of a packaging substrate provided in an embodiment of the present application;

[0068] Figure 3 A schematic diagram of the arrangement structure of the pin area of ​​the packaging substrate provided in an embodiment of the present application;

[0069] Figure 4 A schematic diagram of the construction relationship of the basic graphic units provided in the embodiment of the present application;

[0070] Figure 5 A schematic diagram of a combination method of basic graphic units provided in an embodiment of the present application;

[0071] Figures 6 to 10 Schematic diagrams of combination of five other basic graphic units provided in the embodiments of the present application;

[0072] Fig.11 A schematic diagram of the hardware architecture of the CPU DDR interface provided in an embodiment of the present application;

[0073] Fig.12A schematic diagram of the relationship between the CPU DDR interface and the basic graphics unit described in an embodiment of the present application;

[0074] Fig.13 Schematic diagram of two other combinations of multiple basic graphic units provided in the embodiments of the present application;

[0075] Fig.14 This is a flowchart of a method for a CPU to read and send data according to an embodiment of the present application;

[0076] Fig.15 A schematic diagram of pin configuration in a CPU application scenario provided in an embodiment of the present application;

[0077] Fig.16 A schematic diagram of pin configuration in another CPU application scenario provided in an embodiment of the present application;

[0078] Fig.17 A schematic diagram of pin configuration in another CPU application scenario provided in an embodiment of the present application;

[0079] Fig.18 A schematic diagram of the architecture of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0080] The embodiment of the present application provides a chip packaging substrate pin arrangement solution, which can effectively reduce the crosstalk between pins on the basis of reasonably controlling the package size by increasing the pin arrangement density.

[0081] See also Figure 1 , which is a partial structural diagram of an electronic device provided in an embodiment of the present application. The electronic device 100 includes a circuit board 10 and a chip 20 disposed on the circuit board 10. In a specific implementation, the electronic device can be a communication terminal device, a server, a supercomputer, or a router, a switch, or other devices.

[0082] Among them, the chip 20 may include a packaging substrate 1 and a core particle 2, wherein the packaging substrate 1 is a carrier for packaging the core particle 2, and the packaging is realized through a shell 3. Here, the core particle (Chip) refers to a bare die (Die) formed by processing and cutting a wafer. The packaging substrate (Package substrate) is a carrier for semiconductor chip packaging, and the external pins of the semiconductor package are formed on the packaging substrate. The current development direction of the packaging substrate is to achieve multi-pin, reduce the volume of the packaged product, realize the high-density design of the package pins, and improve the electrical performance of the physical interface.

[0083] When semiconductor core particles are packaged, the core particles 2 can be placed on the packaging substrate 1, and the upper surface of the packaging substrate 1 is the core particle placement area. Specifically, during the manufacturing process of the chip 20, the core particles can be packaged through a packaging process and assembled to form a semiconductor package (Package), that is, a chip product, to provide protection, thermal management, mechanical support, electrical connection and other functions.

[0084] Specifically, when making a semiconductor package, the core particle is usually placed on the package substrate, and the pins of the core particle are electrically connected to the solder balls or pads of the package substrate by gold wire bonding, flip chip or automatic tape welding. Then the core particle and the package substrate are packaged to form a semiconductor package, that is, different chip products. The external pins of the chip can be electrically connected to the PCB, so that the core particle is connected to the external circuit, and the core particle can also be electrically connected to other devices through PCB routing.

[0085] like Figure 1 As shown, the pins on the chip 2 are connected to the solder balls or pads of the package substrate 1 through the flip chip technology. In other specific implementations, the pins on the chip 2 can also be connected to the solder balls or pads of the package substrate 1 through gold wire bonding technology, which is not limited in the embodiment of the present application.

[0086] A packaging filler 4 may also be provided between the packaging substrate 1 and the shell 3. The packaging filler 4 may be used to wrap the core particle 2 on the one hand to reduce the adverse effects of external dust, impurities, etc. on the performance of the core particle 2. On the other hand, the packaging substrate 1, the shell 3, the core particle 2 and other components may be coupled together to improve the structural strength of the chip 20.

[0087] Among them, the external pins of the chip 20 are located on the package substrate 1, and the lower surface of the package substrate 1 is the pin area. Accordingly, a pin interface for connecting with the chip 20 can be provided on the circuit board 10. The signal pin 11 on the package substrate 1 can be a solder ball structure as shown in the figure, which is electrically connected to the corresponding pad on the circuit board 10 through welding, and the core particle 2 is connected to other devices based on the wires on the circuit board 10, so as to realize the connection between the core particle 2 and the external circuit.

[0088] It can be understood that the signal pins are used to establish the pins for signal transmission and data exchange between chips. The signal pins include data signal pins and control signal pins, which can be applied to different parallel bus transmission modes to transmit a large amount of data and control signals. Among them, the data signal pins are used to transmit DQ (Data Input / Output) signals to transmit data bits or bytes of information. Among them, the control signal pins can transmit corresponding control signals according to different application scenarios, for example but not limited to, based on the DDR bus protocol, the control signal pins can be used to transmit DQS (Data Strobe) signals to indicate the sampling time of the data; the control signal pins can also be used to transmit DM (Input Data Mask) signals to indicate the validity of each data signal bit (DQ) to achieve shielding and selective writing of each data bit; or, based on the ONFI (open nand flash interface) bus protocol of flash (flash memory), the control signal pins are used to transmit signals for controlling data transmission to perform data transmission and communication between the flash controller and the flash chip.

[0089] In a specific implementation, the signal pins on the chip 20 can also be metal contact points located on the package substrate 1, and metal springs are correspondingly arranged on the circuit board 10. The metal contact points on the chip 20 side correspond to the metal springs on the circuit board 10 side (not shown in the figure); after the chip 20 is fixed in the mounting position on the circuit board 10, the metal contact points press against the metal springs, and the deformed metal springs maintain reliable contact with the matching metal contact points to achieve electrical connection of the corresponding pins. It is understandable that the specific connection structure between the external pins of the chip 20 and the circuit board 10 can be configured according to the actual application scenario, and the embodiments of the present application are not limited thereto.

[0090] Generally, an important indicator for measuring the performance of chip packaging technology is the ratio of chip area (bare die area) to packaging area. When the area of ​​the core 2 is constant, the smaller the ratio, the larger the packaging area, that is, the larger the size of the chip 20, which will lead to a decrease in the manufacturing yield of the chip 20 and increase the production cost; the closer the ratio is to 1, the smaller the packaging area, so that the manufacturing yield of the chip 20 increases and the production cost can be reduced accordingly. For the packaging substrate 1, the pin arrangement density of the packaging substrate 1 is an important factor affecting the packaging area. However, the increase in the pin arrangement density of the packaging substrate 1 will lead to electromagnetic crosstalk between the pins, affecting the performance of the chip product.

[0091] In addition, in order to reduce electromagnetic crosstalk between pins, ground pins are arranged around the pins of the chip package substrate, and ground connections are provided through the ground pins. Specifically, in the pinmap of the chip, based on the arrangement of the ground pins, a low-impedance ground path can be provided to form a uniform ground potential, which can guide the energy of the electromagnetic field to the ground plane, thereby reducing electromagnetic crosstalk (also known as mutual interference) between signal pins, helping to maintain signal integrity and reduce noise. However, the setting of the ground pin will increase the chip size, so it is necessary to further increase the pin arrangement density to reduce the package area.

[0092] Based on this, the present application embodiment provides a Pinmap pin arrangement solution, see Figure 2 , which is a schematic diagram of a pin arrangement on a package substrate provided in an embodiment of the present application. For ease of description, two arrangement directions of the pin area of ​​the package substrate 1 are defined herein: the first direction X is the left-right arrangement direction of the pins shown in the figure, and the second direction Y is the up-down arrangement direction of the pins shown in the figure. It should be understood that the use of the above-mentioned directional words does not constitute a substantial limitation on the technical solution described in the present application.

[0093] A plurality of pin map pattern units are arranged in the pin area on the package substrate 1. Figure 2 As shown, the pin arrangement graphic unit is a basic graphic unit P including six signal pins 11; wherein the first pin 111, the second pin 112, the third pin 113 and the fourth pin 114 of the six signal pins 11 are sequentially arranged in a first direction X, and the fifth pin 115 and the sixth pin 116 of the six signal pins are arranged in a second direction Y, and the fifth pin 115 and the sixth pin 116 are arranged on the perpendicular midline L2 of the line L1 connecting the second pin 112 and the third pin 113, and are respectively located on both sides of the line L1 connecting the second pin 112 and the third pin 113. wherein the first pin 111, the fourth pin 114, the fifth pin 115 and the sixth pin 116 are data signal pins a (pins shown as solid fill in the figure), and the second pin 111 and the third pin 113 are control signal pins b (pins shown as diagonal fill in the figure).

[0094] On the whole, the pins of the Pinmap Pattern are arranged in a cross-shaped graphic unit, and the four data signal pins a are arranged at the four protruding ends of the cross-shaped graphic unit, and the control signal pin b is arranged in the middle of the cross-shaped graphic unit. As a result, the data signal pins a are kept away from each other, and each data signal pin a has no adjacent data signal pins a that form a crosstalk source, which can effectively avoid the influence of electromagnetic crosstalk between adjacent data signal pins a. Based on this Pinmap solution, on the one hand, the electromagnetic crosstalk between pins is effectively reduced, and a higher parallel bus operation rate can be supported, such as but not limited to the DDR bus or the flash ONFI bus, to transmit data and control signals at high speed; on the other hand, the density of the pin arrangement can be increased, saving packaging area, and providing technical guarantees for further improving product yield and reducing processing costs.

[0095] Here, in Figure 2 In the following figures, the dotted lines connecting the signal pins 11 are only used to illustrate the positional relationship between the pins, and the dotted lines surrounding the periphery of the signal pins 11 are only used to illustrate the arrangement area of ​​the basic graphic unit P. The corresponding dotted lines do not exist in the structure of the packaging substrate and do not constitute a limitation on the specific structure of the packaging substrate.

[0096] In other specific implementations, the multiple pin arrangement graphic units in the pin area of ​​the package substrate 1 can be configured as different pin arrangement modes according to actual functional requirements; for example, for a CPU chip, the multiple pin arrangement graphic units in its pin area can have a part of the basic graphic units P configured as the cross-shaped arrangement graphic units shown in the figure, so as to build a parallel bus channel; the other part of the pin arrangement graphic units can be configured as graphic units including other arrangements (not shown in the figure) to achieve electrical connection with the corresponding external circuit; that is, the pin arrangement of the pin area of ​​the package substrate 1 can be obtained by combining and arranging several types of graphic units, rather than being limited to Figure 2 The diagram shows a situation where the graphic units are arranged in a cross shape.

[0097] In this embodiment, the fifth pin 115 and the sixth pin 116 are arranged on the perpendicular bisector of the line connecting the second pin 112 and the third pin 113, that is, the distances from the second pin 112 and the third pin 113 to the line connecting the fifth pin 115 and the sixth pin 116 are equal, and the cross-shaped graphic unit is a centrally symmetrical structure.

[0098] In a specific implementation, the distances from the second pin 112 and the third pin 113 to the connection line between the fifth pin 115 and the sixth pin 116 may be different (not shown in the figure). In other words, the fifth pin 115 and the sixth pin 116 are located on both sides of the connection line between the second pin 112 and the third pin 113, which can also achieve an implementation scheme in which each data signal pin has no adjacent crosstalk source. In addition, in other specific implementations, the connection line between the fifth pin 115 and the sixth pin 116 may also intersect with the connection line between the second pin 112 and the third pin 113 at other angles (not shown in the figure).

[0099] In comparison, the implementation method of configuring the fifth pin 115 and the sixth pin 116 on the midpoint of the line connecting the second pin 112 and the third pin 113 can maximize the arrangement density of the pin area on the basis of effectively reducing the impact of electromagnetic crosstalk. Figure 3 , which is a schematic diagram of the arrangement structure of the package substrate pin area provided in the embodiment of the present application. Figure 3 As shown, the pins in the pin area of ​​the package substrate 1 are arranged in an array, and the pins between rows and columns are staggered. The staggered arrangement of the pins between rows and columns means that the pins in each row (X1-X15) and the pins in each column (Y1-Y9) are staggered with each other, and as many pins as possible can be arranged in a limited layout space. In other words, the pins in the pin area are arranged in a triangular grid, and the connection line between each pin and the two adjacent pins forms an equilateral triangle. In this way, the closely alternating arrangement of the cross-shaped arrangement graphic units can be achieved, and the pin arrangement density can be improved.

[0100] It should be noted that, for each pin in the pin area of ​​the packaging substrate 1, the pin and the other two adjacent pins are arranged in an equilateral triangle, including an equilateral triangle arrangement relationship with good shape and position tolerance control, and also includes a triangle arrangement relationship with dimensional tolerance affected by the processing accuracy. In other words, it also includes a situation where there is a certain deviation within the range of process accuracy limitations and the pin is arranged in a roughly equilateral triangle that is not completely equilateral.

[0101] Furthermore, a ground (GND) pin may be provided around the six signal pins 11 of the cross-shaped graphic unit. Figure 4 , which is a schematic diagram of the construction relationship of the basic graphic units provided in an embodiment of the present application.

[0102] As shown in the figure, corresponding to the six signal pins 11 of the cross-shaped graphic unit, the basic graphic unit P is provided with fourteen grounding pins 12 (pins c shown as single-line circles in the figure), with two control signal pins b as the center, and four data signal pins a are arranged respectively at the upper, lower, left and right positions closest to the two control signal pins b, and finally grounding pins c are arranged on the periphery to form a return ground around each signal pin 11, thereby reducing electromagnetic interference with other pins.

[0103] Figure 4 The fourteen ground pins 12 described are surrounded by the six signal pins 11, and the fourteen ground pins 12 are arranged in sequence to form a tetragon; in the first direction X, the first ground pin 1201 is located beside the first pin 111, the eighth ground pin 1208 is located beside the fourth pin 114, and the second ground pin 1202, the third ground pin 1203, the fourth ground pin 1204, the fifth ground pin 1205, the sixth ground pin 1206 and the seventh ground pin 1207 are arranged in sequence between the first ground pin 1201 and the eighth ground pin 1208; the ninth ground pin 1209, the tenth ground pin 1210, the eleventh ground pin 1211, the twelfth ground pin 1212, the thirteenth ground pin 1213 and the fourteenth ground pin 1214 are arranged in sequence between the eighth ground pin 1208 and the first ground pin 1201.

[0104] Among them, the data signal pin a adjacent to two adjacent ground pins 12 and the connection line of the two adjacent ground pins 12 form an equilateral triangle S, and each data signal pin a is located on the perpendicular midline of the connection line of the two adjacent ground pins 12; in order to simplify the diagram, the figure only takes the first pin 111 as an example to illustrate the relative position relationship between it and the two adjacent ground pins 12. In this way, the pin area space where the pins between rows and columns are staggered is fully utilized, and the Pinmap unit is constructed according to the rule of alternating arrangement, and the distance between any two adjacent pins is consistent. While providing the return ground function, it can increase the pin arrangement density and have a higher signal-to-ground ratio. The "signal-to-ground ratio" here refers to the ratio of the number of signal pins 11 to the number of ground pins 12 per unit area. It can be understood that in other specific implementations, the number of ground pins 12 can be determined as needed, and the embodiment of the present application is not limited.

[0105] In a specific implementation, a basic graphic unit P may correspond to a Nibbel (half byte) signal pin, and each Nibbel's data may be transmitted using four DQ data signals and a pair of DQS differential clock signals. Among them, the four data signal pins a among the six signal pins 11 are single-ended signal pins for transmitting DQ data signals; and the two control signal pins b among the six signal pins 11 are differential signal pins for transmitting DQS signals.

[0106] When the two control signal pins (the second pin 112 and the third pin 113) transmit the DQS differential clock signal, the polarity of the differential signal pair is opposite during transmission, that is, the amplitudes of the signals transmitted on the two pins of the differential signal pair are opposite, thereby, the interference to the second direction Y and its two upper and lower adjacent single-ended signal pins (the fifth pin 115 and the sixth pin 116) can be completely offset, and the crosstalk to the first direction X and its left and right two single-ended signal pins (the first pin 111 and the fourth pin 114) can be partially offset, thereby reducing the total crosstalk amount of the single-ended signal.

[0107] In the scenario of DDR system, based on the definition of DDR signal, the data signal is usually divided by Byte, and each byte unit is transmitted using four DQ data signals and a pair of DQS differential clock signals. Based on the aforementioned basic graphic unit P, a combination unit formed by two basic graphic units P can be used to realize the transmission of one byte unit of data. That is, when designing DDR Pinmap, one Byte is usually used as the basic unit for arrangement.

[0108] See also Figure 5 , which is a schematic diagram of a combination method of a basic graphic unit P provided in an embodiment of the present application. The figure shows a combination unit formed by splicing two basic graphic units P, which can transmit data in a byte unit. Figure 4 The described basic graphic unit P is a combination unit composed of two basic graphic units P spliced ​​together to form a pin arrangement combination unit corresponding to a byte unit, and the adjacent sides of the first basic graphic unit P1 and the second basic graphic unit P2 share a ground pin.

[0109] like Figure 5As shown, the first basic graphic unit P1 and the second basic graphic unit P2 are mutually translated graphics, that is, one of the two basic graphic units P is a graphic unit formed by translation relative to the other. Among them, the fifth pin 115 of the first basic graphic unit P1 is arranged in the same direction as the first pin 111, the second pin 112, the third pin 113 and the fourth pin 114 of the second basic graphic unit P2; the first pin 111, the second pin 112, the third pin 113 and the fourth pin 114 of the first basic graphic unit P1 are arranged in the same direction as the sixth pin 116 of the second basic graphic unit P2.

[0110] In this implementation, the first basic graphic unit P1 and the second basic graphic unit P2 share two ground pins 12, and the two shared ground pins 12 are located between the fourth pin 114 of the first basic graphic unit P1 and the first pin 111 of the second basic graphic unit P2. Specifically, the seventh ground pin 1207 of the first basic graphic unit P1 and the first ground pin 1201 of the second basic graphic unit P2 are a shared ground pin, and the eighth ground pin 1208 of the first basic graphic unit P1 and the fourteenth ground pin 1214 of the second basic graphic unit P2 are shared ground pins. In this way, in addition to effectively reducing electromagnetic crosstalk, the pin layout density is more compact and reasonable.

[0111] In a specific implementation, the eight data signal pins a of the two basic graphic units P can correspond to the eight data pins on the data bus: DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6 and DQ7, which respectively send or receive data from data bit 0 to data bit 7; the four control signal pins of the two basic graphic units P correspond to the four data clock signal pins on the data bus: DQS0, DQS1, DQS2 and DQS3, where DQS0 and DQS1 are a pair of differential pair pins, and DQS2 and DQS3 are a pair of differential pair pins, which are respectively used for timing and synchronization of data during data transmission.

[0112] Based on the staggered arrangement of the pins between the rows and columns of the pin area of ​​the package substrate 1, different pin arrangement combination units can be formed by translation or rotation translation and splicing. Figures 6 to 10 , five different basic graphic unit combinations are shown, among which, Figure 6 , Figure 7 , Figure 8 and Fig.10 In the assembly unit shown, one of the two basic graphic units P is a graphic unit formed by translation relative to the other, wherein Fig. 9 In the assembled unit shown, one of the two basic graphic units P is a graphic unit formed by rotating and translating relative to the other.

[0113] like Figure 6 As shown, the first basic graphic unit P1 and the second basic graphic unit P2 are mutually translated graphics, wherein the fifth pin 115 and the sixth pin 116 of the first basic graphic unit P1 are arranged in the same direction as the fifth pin 115 and the sixth pin 116 of the second basic graphic unit P1.

[0114] In this implementation, two basic graphic units share two ground pins 12 arranged at intervals, and the two shared ground pins 12 are located between the sixth pin 116 of the first basic graphic unit P1 and the fifth pin 115 of the second basic graphic unit P2. Specifically, the twelfth ground pin 1212 of the first basic graphic unit P1 and the fourth ground pin 1204 of the second basic graphic unit P2 are shared ground pins, and the eleventh ground pin 1211 of the first basic graphic unit P1 and the fifth ground pin 1205 of the second basic graphic unit P2 are shared ground pins.

[0115] like Figure 7 As shown, the first basic graphic unit P1 and the second basic graphic unit P2 are mutually translated graphics, wherein the first pin 111, the second pin 112, the third pin 113 and the fourth pin 114 of the first basic graphic unit P1 are arranged in the same direction as the first pin 111, the second pin 112, the third pin 113 and the fourth pin 114 of the second basic graphic unit P2.

[0116] In this implementation, two basic graphic units share a ground pin 12, which is located between the fourth pin 114 of the first basic graphic unit P1 and the first pin 111 of the second basic graphic unit P2. Specifically, the eighth ground pin 1208 of the first basic graphic unit P1 and the first ground pin 1201 of the second basic graphic unit P2 are common ground pins.

[0117] like Figure 8 As shown, the first basic graphic unit P1 and the second basic graphic unit P2 are mutually translated graphics, wherein the fifth pin 115 and the sixth pin 116 of the first basic graphic unit P1 are arranged in the same direction as the first pin 111 of the second basic graphic unit P2; the fourth pin 114 of the first basic graphic unit P1 is arranged in the same direction as the fifth pin 115 and the sixth pin 116 of the second basic graphic unit P2.

[0118] In this implementation, two basic graphic units share four ground pins 12 that are arranged in sequence, two of which are located between the sixth pin 116 of the first basic graphic unit P1 and the first pin 111 of the second basic graphic unit P2, and the other two are located between the fourth pin 114 of the first basic graphic unit P1 and the fifth pin 115 of the second basic graphic unit P2. Specifically, the twelfth ground pin 1212 of the first basic graphic unit P1 and the second ground pin 1202 of the second basic graphic unit P2 are shared ground pins, the eleventh ground pin 1211 of the first basic graphic unit P1 and the third ground pin 1203 of the second basic graphic unit P2 are shared ground pins, the tenth ground pin 1210 of the first basic graphic unit P1 and the fourth ground pin 1204 of the second basic graphic unit P2 are shared ground pins, and the ninth ground pin 1209 of the first basic graphic unit P1 and the fifth ground pin 1205 of the second basic graphic unit P2 are shared ground pins.

[0119] like Fig. 9 As shown, the first basic graphic unit P1 and the second basic graphic unit P2 are mutually translated and rotated graphics, wherein the first pin 111 and the fifth pin 115 of the first basic graphic unit P1 are arranged in the same direction as the fifth pin 115 and the sixth pin 116 of the second basic graphic unit P2; the sixth pin 116 and the fourth pin 114 of the first basic graphic unit P1 are arranged in the same direction as the first pin 111 of the second basic graphic unit P2.

[0120] In this implementation, two basic graphic units share four ground pins 12 that are spaced apart in sequence, wherein two of the shared ground pins 12 are located between the fifth pin 115 of the first basic graphic unit P1 and the fifth pin 115 of the second basic graphic unit P2, and the other two shared ground pins 12 are located between the fourth pin 114 of the first basic graphic unit P1 and the first pin 111 of the second basic graphic unit P2. Specifically, the fifth ground pin 1205 of the first basic graphic unit P1 and the fifth ground pin 1205 of the second basic graphic unit P2 are common ground pins, the sixth ground pin 1206 of the first basic graphic unit P1 and the fourth ground pin 1204 of the second basic graphic unit P2 are common ground pins, the seventh ground pin 1207 of the first basic graphic unit P1 and the third ground pin 1203 of the second basic graphic unit P2 are common ground pins, and the eighth ground pin 1208 of the first basic graphic unit P1 and the second ground pin 1202 of the second basic graphic unit P2 are common ground pins.

[0121] like Fig.10As shown, the first basic graphic unit P1 and the second basic graphic unit P2 are mutually translated graphics, wherein the fourth pin 114 of the first basic graphic unit P1 and the first pin 111 of the second basic graphic unit P2 are arranged in the same direction; the sixth pin 116 of the first basic graphic unit P1 and the fifth pin 115 of the second basic graphic unit P2 are arranged in the same direction.

[0122] The two share four ground pins 12 that are arranged in sequence and at intervals, two of which are located between the sixth pin 116 of the first basic graphic unit P1 and the first pin 111 of the second basic graphic unit P2, and the other two are located between the fourth pin 114 of the first basic graphic unit P1 and the fifth pin 115 of the second basic graphic unit P2. Specifically, the eleventh ground pin 1211 of the first basic graphic unit P1 and the first ground pin 1201 of the second basic graphic unit P are shared ground pins, the tenth ground pin 1210 of the first basic graphic unit P and the second ground pin 1202 of the second basic graphic unit P2 are shared ground pins, the ninth ground pin 1209 of the first basic graphic unit P and the third ground pin 1203 of the second basic graphic unit P are shared ground pins, and the eighth ground pin 1208 of the first basic graphic unit P and the fourth ground pin 1204 of the second basic graphic unit P2 are shared ground pins.

[0123] It is understandable that the configuration has the aforementioned Figure 2 , Figure 3 and Figure 4 The packaging substrate of the basic graphic unit P described above and the configuration Figures 5 to 10 The package substrate of the described pin arrangement combination unit can be used to match chips such as CPU (central processing unit), GPU (graphics processing unit) or NPU (neural-network processing units), that is, the package substrate described in the above embodiment, the Pinmap formed on the pin area based on the basic graphics unit P can be used for the DDR interface on the CPU chip, NPU chip or GPU chip. For the CPU chip, the DDR signal can be connected to the memory chip (DIMM) on the memory bar DIMM through the signal pin 11 and the PCB routing.

[0124] The following is a brief description of the matching method between the pin arrangement on the aforementioned packaging substrate and the CPU chip.

[0125] See also Fig.11 , which is a schematic diagram of the hardware architecture of the CPU DDR interface provided in an embodiment of the present application.

[0126] like Fig.11 As shown, the CPU chip 21 includes multiple memory channels (DDR channels) 22, and each memory channel 22 can drive and connect to a corresponding memory bar 30. Without loss of generality, Fig.11 The CPU chip 21 including eight memory channels 22 is used as an example for illustration. It should be understood that in other specific implementations, the number of channels of the CPU and the number of memory sticks connected to each channel can be set according to actual needs, which can be implemented based on existing technologies, so it will not be described in detail herein.

[0127] Each memory channel 22 may include multiple DDR Byte units 23, and each Byte includes two Nibbles 24. The memory bandwidth of a memory channel 22 is generally 32 bits or 64 bits. It can be understood that a memory channel 22 with a 32-bit bandwidth may be composed of four byte units 23, and a memory channel 22 with a 64-bit bandwidth may be composed of eight byte units 23. This is not limited in the embodiments of the present application.

[0128] Please also see Fig.12 , this figure is a schematic diagram of the relationship between the interface of the CPU DDR and the basic graphics unit P described in an embodiment of the present application.

[0129] like Fig.12 As shown, each Nibble 24 includes six data signals: four DQ data signals and a pair of DQS differential clock signals. Here, the six data signals of each Nibble 24 and its peripheral GND pins can be arranged in a cross-shaped pin arrangement combination unit P as described in the above embodiment. In other words, each Byte 23 includes twelve data signals: eight DQ data signals and two pairs of DQS differential clock signals. Accordingly, the twelve data signals of each Byte 23 and its peripheral GND pins can be arranged in a cross-shaped pin arrangement combination unit P as described in the above embodiment. Figures 5 to 10 Pinmap Pattern combination unit described.

[0130] In a specific implementation, the pins corresponding to all memory channels 22 of the CPU chip 21 can be arranged based on a Nibble to realize the combination of signal pins and their peripheral ground pins, forming a complete DDR Channel Pinmap (DDR channel pin arrangement pattern), so that the memory channel 22 area of ​​the CPU chip 21 obtains a higher pin arrangement density, and the electromagnetic crosstalk between the signal pins is small, thereby ensuring stable signal transmission between the CPU 21 and the memory stick 30. In a specific implementation, the memory stick 30 can be a dual-inline-memory-modules (DIMM), which is not limited in the embodiment of the present application.

[0131] See also Fig.13 , which is a schematic diagram of a combination method of two or more basic graphic units provided in an embodiment of the present application. Fig.13 In the combination shown in Figure (a), each basic graphic unit P is spliced ​​accordingly after translation. For two adjacent columns of basic graphic units P, the fourth pins of each basic graphic unit P belonging to the left column and the first pins of each basic graphic unit P belonging to the right column are arranged in sequence along the second direction. Fig.13 In the combination shown in Figure (b), a part of the basic graphic units P are correspondingly spliced ​​after translation, and another part of the basic graphic units P are correspondingly spliced ​​after rotation and translation.

[0132] like Fig.13 As shown, based on the staggered arrangement of the pins between the rows and columns of the pin area of ​​the package substrate 1, the DDR Channel Pinmap formed by the combination of the basic graphic units provided by the embodiment of the present application is applied, and each group of adjacent basic graphic units P can share the peripheral ground pin, and the overall pin layout density is more compact and reasonable. By utilizing the structural characteristics of the cross-shaped pin arrangement graphic unit, the data signal pins a of the DDR Channel Pinmap can be kept away from each other, and each data signal pin a has no adjacent crosstalk source, which can effectively avoid the influence of electromagnetic crosstalk between adjacent data signal pins a.

[0133] The CDU chip described in the above embodiment can be used in DDR systems of different generations to implement data storage and reading. For example, but not limited to, DDR4 SDRAM (4th generation double data rate synchronous dynamic random access memory) and DDR5SDRAM (5th generation double data rate synchronous dynamic random access memory), based on different DDR chip data bus widths, DDR4 SDRAM includes two types, X8 and X16, and DDR5 SDRAM includes three types, X4, X8 and X16, where the chip bit width of the X4 device is 4 bits, the chip bit width of the X8 device is 8 bits, and the chip bit width of the X16 device is 16 bits.

[0134] For the control signal pin b of the basic graphics unit P, it is usually defined as the DQS signal pin on the CDU chip side. In other specific implementations, such as in the X8 scenario, if DM signals need to be transmitted, the DQS0~DQS3 pins can be configured as channels for multiplexing DM signals. The DM signal is used to indicate the validity of each DQ data signal to provide shielding and selective writing of each data bit. In the write operation (WR OP), the CPU sends the DM signal to the DRAM at the same time as the DQ signal and the DQS signal. At this time, the DM signal is sampled together with the DQ signal at the rising / falling edge of the DQS clock signal. When the control signal pin is used to transmit the DM signal, the electromagnetic crosstalk actually generated by the DM being sampled as a low level is low and will not affect the data transmission of the DQ data signal pin.

[0135] It should be noted that the aforementioned cross-shaped basic graphic unit P can be applied to the chip packaging structure design for information connection with DDR memory. In addition to CPU chips, GPU chips or NPU chips, it can also be applied to other chips or connectors based on DDR interface. It ensures correct signal transmission and data reading and writing through good anti-crosstalk performance, thereby providing technical guarantee for high-performance and reliable DDR systems.

[0136] Of course, for other parallel bus scenarios, the Pinmap formed by the aforementioned cross-shaped basic graphic units P is used for corresponding physical line interfaces, such as but not limited to parallel cameras, parallel external storage devices or parallel printers, etc., which are input and output devices that transmit data and control signals through parallel buses.

[0137] based on Fig.11 The hardware architecture of the CPU DDR interface shown in FIG. 1 is a CPU DDR interface. The embodiment of the present application also provides a method for the CPU to read and send data. Fig.14 , this figure is a flow chart of a method for CPU to read and send data according to an embodiment of the present application.

[0138] like Fig.14 As shown, the method comprises the following steps:

[0139] Step 101: responding to a write instruction or a read instruction of a DDR signal;

[0140] In a specific implementation, when the CPU or other device needs to read data in the memory, the memory controller sends a read command to the memory module and specifies the address to be read. When the CPU or other device needs to write data to the memory, the memory controller sends a write command to the memory module and provides the data to be written and the target address. Here, the memory controller is a part of the CPU or a separate chip located on the motherboard, which is used to control the read and write operations of the memory module and process memory access requests from the CPU or other devices.

[0141] Step 102: Send data to the DDR memory through the DQ pin according to the write instruction, and output the data strobe signal through the DQS pin, that is, provide a data clock signal to the DDR memory, so that the DDR memory can correctly receive and analyze the data sent by the CPU; or, receive data from the DDR memory through the DQ pin according to the read instruction, and read the data strobe signal through the DQS pin, that is, provide a data clock signal to the CPU, so that the CPU can correctly sample and analyze the data transmitted from the DDR memory;

[0142] Specifically, during data transmission, there is a corresponding timing relationship between the DQS pin and the corresponding DQ pin, and data sampling and transmission occur at the edge (rising or falling edge) of the data clock signal. When sending data, the memory module writes the data to the storage unit at the specified address after receiving the command. When reading data, the memory module transmits the requested data to the CPU through the data bus after receiving the command.

[0143] Among them, the DQ pin (data signal pin) and DQS pin (data select signal pin) of the CPU chip are arranged in a basic graphic unit, and the basic graphic unit includes six signal pins: a first pin 111, a second pin 112, a third pin 113, a fourth pin 114, a fifth pin 115 and a sixth pin 116, wherein the first pin 111, the fourth pin 114, the fifth pin 115 and the sixth pin 116 are DQ pins (pins shown by solid circles in the figure), and the second pin 111 and the third pin 113 are DQS pins (pins shown by diagonal lines in the figure). The six signal pins are arranged in a cross pattern, wherein the first pin 111, the second pin 112, the third pin 113 and the fourth pin 114 are arranged in sequence in the first direction X, and the fifth pin 115 and the sixth pin 116 of the six pins are arranged in the second direction Y. The fifth pin 115 and the sixth pin 116 are configured on a vertical line connecting the second pin 112 and the third pin 113, and are respectively located on both sides of the second pin 112 and the third pin 113.

[0144] Taking the pin arrangement combination unit corresponding to a byte unit as an example, its eight data signal pins: DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6 and DQ7 are used to send or receive data from data bit 0 to data bit 7 respectively; its four data clock signal pins: DQS0, DQS1, DQS2 and DQS3, DQS0 and DQS1 are a pair of differential pair pins, DQS2 and DQS3 are a pair of differential pair pins, which are respectively used for timing and synchronization of data during data transmission.

[0145] See also Fig.15 , which is a schematic diagram of pin configuration in a CPU application scenario provided in an embodiment of the present application.

[0146] For the X4 particle scene, the pin configuration is as follows: Fig.15 As shown in the figure, during the write operation and read operation (WR OP / RD OP), the specific behavior of each signal pin is as follows:

[0147] Write operation: The CPU sends the DQ signal and the DQS signal to the DRAM. The DQS signal is aligned with the center of the DQ signal. On the DRAM side, the DQ signal is sampled at the rising and falling edges of the DQS clock signal, and the sampled signal is stored in the DRAM.

[0148] Read operation: DRAM sends DQ signal and DQS signal to the CPU. The DQS signal is edge-aligned with the DQ signal. The CPU side will first adjust the phase relationship between the DQS signal and the DQ signal so that the DQS signal is center-aligned with the DQ signal, and then perform sampling, and transmit the sampled signal to the back-end for processing.

[0149] See also Fig.16 , this figure is a schematic diagram of pin configuration in another CPU application scenario provided in an embodiment of the present application.

[0150] For the X8 particle scene, the pin configuration is as follows: Fig.16 As shown in the figure, during the write operation and read operation (WR OP / RD OP), the RFU pin in the figure is a protection standby pin (Reserved For Future Use), and the specific behaviors of other signal pins are as follows:

[0151] Write operation: CPU sends DQ signal, DM signal and DQS signal to DRAM, DQS signal is aligned with the center of DQ signal and DM signal, on the DRAM side, DQ signal and DM signal are sampled at the rising edge and falling edge of DQS, and the sampled signals are stored in DRAM. It should be understood that when the DM signal is sampled as a low level, the DQ signal sampled with it will be shielded and not written to DRAM.

[0152] Read operation: DRAM sends DQ signal and DQS signal to CPU, and the DQS signal is edge-aligned with the DQ signal. The CPU side will first adjust the phase relationship between DQS and DQ to align the center of the DQS and DQ signals, and then perform sampling, and transmit the sampled signal to the back-end for processing.

[0153] In practical applications, the cross-shaped basic graphic unit can increase the density of pin arrangement, save packaging area, and effectively reduce electromagnetic crosstalk between pins, and can support higher DDR operating rates.

[0154] It should be noted that, in a specific implementation, the above signal pins may adopt different pin configurations and signal distribution methods, which may be determined according to the type and specification of the CPU chip and the DDR chip, and the control mechanism of the corresponding memory controller. This application embodiment is not limited thereto.

[0155] See also Fig.17 , which is a schematic diagram of pin configuration in another CPU application scenario provided by an embodiment of the present application. Fig.17 As shown, the pin arrangement combination unit formed by two basic graphic units P can support the mixing of DQ signals of different Nibbles / Bytes. Among them, the four data signal pins corresponding to Nibble0 are DQ0, DQ1, DQ2, and DQ3, and the four data signal pins corresponding to Nibble1 are DQ4, DQ5, DQ6, and DQ7, among which DQ0, DQ1, and DQ2 of Nibble0 and DQ4 of Nibble1 are configured in one basic graphic unit P, and DQ3 of Nibble0 and DQ5, DQ6, and DQ7 of Nibble1 are configured in another basic graphic unit P.

[0156] In addition, based on the chip 20 using the cross-shaped arrangement of basic graphic units described in the above embodiment, the embodiment of the present application also provides a signal transmission method applied to the chip, wherein the pin area of ​​the package substrate 4 of the chip 20 is provided with a plurality of pin arrangement graphic units; at least two of the plurality of pin arrangement graphic units are basic graphic units P, and the basic graphic unit P includes six signal pins 11; wherein the first pin 111, the second pin 112, the third pin 113 and the fourth pin 114 of the six signal pins 11 are connected to the first signal pin 111, the second pin 112, the third pin 113 and the fourth pin 114. 14 are arranged in sequence in the first direction X, and the fifth pin 115 and the sixth pin 116 of the six signal pins 11 are arranged in sequence in the second direction Y; the fifth pin 115 and the sixth pin 116 are respectively located on both sides of the connection line between the second pin 112 and the third pin 113; wherein the first pin 111, the fourth pin 114, the fifth pin 115 and the sixth pin 116 are data signal pins, and the second pin 112 and the third pin 113 are control signal pins; the first direction X is different from the second direction Y. In a specific implementation, the chip can be a CPU chip as described above, or can be other chips or connectors based on a DDR interface, which is not limited in the embodiment of the present application.

[0157] The signal transmission method comprises the following steps: transmitting a data signal through the first pin 111, the fourth pin 1114, the fifth pin 115 and the sixth pin 116, and transmitting a control signal through the second pin 112 and the third pin 113. Based on the cross-shaped arrangement of the basic graphic unit P, the correct signal transmission of the chip is ensured by good anti-crosstalk performance, thereby providing technical guarantee for high-performance and reliable system applications.

[0158] The present application also provides an electronic device. Fig.18 , which is a schematic diagram of the architecture of an electronic device provided in an embodiment of the present application. The electronic device 100a includes a housing 40a, a circuit board 10a and a CPU 20a disposed in the housing 40a, the CPU 20a is disposed on the circuit board 10a, and the pin area on the package substrate of the CPU 20a may include the aforementioned Figure 2 , Figure 3 and Figure 4 The basic graphic unit P described may include Figures 5 to 10 The pin arrangement combination unit described. Based on the cross-shaped basic graphic unit provided in this embodiment, the arrangement of its pins can increase the density of the pin arrangement, save the packaging area, and reduce the DDR memory signal crosstalk, thereby improving the computing performance of the computing device.

[0159] It should be understood that other functional components of the computing device are not the core invention of this application, so they will not be elaborated in this article.

[0160] The cross-shaped pin arrangement graphic unit provided in this embodiment has broad application prospects as an important technical means of chip packaging technology. It will play an increasingly important role in different electronic devices, such as but not limited to servers, supercomputers, Ethernet switches and other computing devices, and can also be used in terminal devices such as automobiles, mobile phones, and laptops.

[0161] The ordinal numbers "first" and "second" used herein are only used to describe the composition or structure of the same function in the technical solution. It is understandable that the use of the ordinal numbers "first" and "second" does not constitute an understanding limitation on the technical solution claimed for protection in this application.

[0162] The above are only preferred embodiments of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A chip, characterized in that: It comprises a core particle and a packaging substrate, wherein the core particle is arranged on the packaging substrate, and a plurality of pin arrangement graphic units are arranged in a pin area of ​​the packaging substrate; Among the plurality of pin arrangement graphic units, at least two pin arrangement graphic units are basic graphic units including six signal pins; Among them, the first pin, the second pin, the third pin and the fourth pin of the six signal pins are arranged in sequence in the first direction, and the fifth pin and the sixth pin of the six signal pins are arranged in the second direction, and the fifth pin and the sixth pin are respectively located on both sides of the connection line between the second pin and the third pin; The first pin, the fourth pin, the fifth pin and the sixth pin are data signal pins, the second pin and the third pin are control signal pins; and the first direction is different from the second direction.

2. The chip according to claim 1, characterized in that: The fifth pin and the sixth pin are arranged on a perpendicular line of a line connecting the second pin and the third pin, and the first direction is perpendicular to the second direction.

3. The chip according to claim 2, characterized in that: The fifth pin and the sixth pin are arranged on the perpendicular midline of the line connecting the second pin and the third pin.

4. The chip according to any one of claims 1 to 3, characterized in that: The basic graphic unit is a centrally symmetrical structure or an axially symmetrical structure.

5. The chip according to any one of claims 1 to 4, characterized in that: The pins in the pin area are arranged in an array, and the pins between rows and columns are staggered.

6. The chip according to any one of claims 1 to 5, characterized in that: The pins in the pin area are arranged in a triangular grid, wherein a line connecting the pin and two adjacent pins forms an equilateral triangle.

7. The chip according to any one of claims 1 to 6, characterized in that: The basic graphic unit further includes a ground pin, and the ground pin is arranged around the six signal pins.

8. The chip according to claim 7, characterized in that: The basic graphic unit has fourteen ground pins, and the fourteen ground pins are sequentially arranged at intervals around the six signal pins; in a first direction, the first ground pin is located beside the first pin, the eighth ground pin is located beside the fourth pin, and the second ground pin, the third ground pin, the fourth ground pin, the fifth ground pin, the sixth ground pin and the seventh ground pin are sequentially arranged between the first ground pin and the eighth ground pin; A ninth ground pin, a tenth ground pin, an eleventh ground pin, a twelfth ground pin, a thirteenth ground pin and a fourteenth ground pin are sequentially arranged between the eighth ground pin and the first ground pin.

9. The chip according to claim 8, characterized in that: The two basic graphic units are arranged adjacent to each other, one is a first basic graphic unit, and the other is a second basic graphic unit, and adjacent sides of the first basic graphic unit and the second basic graphic unit share a ground pin.

10. The chip according to claim 9, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the eighth ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are common ground pins.

11. The chip according to claim 9, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the twelfth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are common ground pins, and the eleventh ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are common ground pins.

12. The chip according to claim 9, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the seventh ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are common ground pins, and the eighth ground pin of the first basic graphic unit and the fourteenth ground pin of the second basic graphic unit are common ground pins.

13. The chip according to claim 9, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the twelfth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are common ground pins, the eleventh ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are common ground pins, the tenth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are common ground pins, and the ninth ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are common ground pins.

14. The chip according to claim 9, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the eleventh ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are common ground pins, the tenth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are common ground pins, the ninth ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are common ground pins, and the eighth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are common ground pins.

15. The chip according to claim 9, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated and rotated graphics, the fifth ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are a common ground pin, the sixth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are a common ground pin, the seventh ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are a common ground pin, and the eighth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are a common ground pin.

16. The chip according to any one of claims 8 to 15, characterized in that: In the basic graphic unit, the data signal pin adjacent to two adjacent ground pins and a line connecting the two adjacent ground pins form an equilateral triangle.

17. The chip according to any one of claims 1 to 16, characterized in that: The first pin, the fourth pin, the fifth pin and the sixth pin are single-ended signal pins, and the second pin and the third pin are a pair of differential signal pins.

18. The chip according to any one of claims 1 to 17, characterized in that: The chip is a central processing unit, which is configured with multiple memory channels. The memory channels include multiple byte units, each of which corresponds to two basic graphic units. The data signal pins in the basic graphic units are used to transmit data signals corresponding to the byte units.

19. An electronic device, characterized in that: It comprises a shell and a circuit board arranged in the shell, wherein a chip is arranged on the circuit board, and the chip is the chip according to claim 1 or 18, and a signal pin of the chip is electrically connected to the circuit board.

20. A chip manufacturing method, characterized in that: The chip manufacturing method comprises: placing a core particle on a packaging substrate, and assembling the core particle and the packaging substrate to form the chip; wherein a pin area of ​​the packaging substrate is provided with a plurality of pin arrangement graphic units; Among the plurality of pin arrangement graphic units, at least two pin arrangement graphic units are basic graphic units including six signal pins; Among them, the first pin, the second pin, the third pin and the fourth pin of the six signal pins are arranged in sequence in the first direction, and the fifth pin and the sixth pin of the six signal pins are arranged in the second direction, and the fifth pin and the sixth pin are respectively located on both sides of the connection line between the second pin and the third pin; The first pin, the fourth pin, the fifth pin and the sixth pin are data signal pins, the second pin and the third pin are control signal pins; and the first direction is different from the second direction.

21. The chip manufacturing method according to claim 20, characterized in that: The fifth pin and the sixth pin are arranged on a perpendicular line of a line connecting the second pin and the third pin, and the first direction is perpendicular to the second direction.

22. The chip manufacturing method according to claim 21, characterized in that: The fifth pin and the sixth pin are arranged on the perpendicular midline of the line connecting the second pin and the third pin, and the basic graphic unit is a central symmetrical structure or an axisymmetric structure.

23. The chip manufacturing method according to any one of claims 20 to 22, characterized in that: The pins in the pin area are arranged in an array, and the pins between rows and columns are staggered; the pins in the pin area are arranged in a triangular grid, wherein the line connecting the pin and two adjacent pins forms an equilateral triangle.

24. The chip manufacturing method according to any one of claims 20 to 23, characterized in that: The basic graphic unit further includes a ground pin, the ground pins are fourteen in number, and the fourteen ground pins are sequentially arranged at intervals around the six signal pins; In the first direction, the first ground pin is located beside the first ground pin, the eighth ground pin is located beside the fourth ground pin, and the second ground pin, the third ground pin, the fourth ground pin, the fifth ground pin, the sixth ground pin and the seventh ground pin are sequentially arranged between the first ground pin and the eighth ground pin; A ninth ground pin, a tenth ground pin, an eleventh ground pin, a twelfth ground pin, a thirteenth ground pin and a fourteenth ground pin are sequentially arranged between the eighth ground pin and the first ground pin.

25. The chip manufacturing method according to claim 24, characterized in that: The two basic graphic units are arranged adjacent to each other, one is a first basic graphic unit, and the other is a second basic graphic unit, and adjacent sides of the first basic graphic unit and the second basic graphic unit share a ground pin.

26. The chip manufacturing method according to claim 25, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the eighth ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are common ground pins.

27. The chip manufacturing method according to claim 25, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the twelfth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are common ground pins, and the eleventh ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are common ground pins.

28. The chip manufacturing method according to claim 25, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the seventh ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are common ground pins, and the eighth ground pin of the first basic graphic unit and the fourteenth ground pin of the second basic graphic unit are common ground pins.

29. The chip manufacturing method according to claim 25, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the twelfth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are common ground pins, the eleventh ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are common ground pins, the tenth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are common ground pins, and the ninth ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are common ground pins.

30. The chip manufacturing method according to claim 25, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the eleventh ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are common ground pins, the tenth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are common ground pins, the ninth ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are common ground pins, and the eighth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are common ground pins.

31. The chip manufacturing method according to claim 25, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated and rotated graphics, the fifth ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are a common ground pin, the sixth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are a common ground pin, the seventh ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are a common ground pin, and the eighth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are a common ground pin.

32. A signal transmission method, characterized in that: The signal transmission method is applied to a chip, the chip includes a packaging substrate, a pin area of ​​the packaging substrate is provided with a plurality of pin arrangement graphic units; among the plurality of pin arrangement graphic units, at least two pin arrangement graphic units are basic graphic units including six signal pins; wherein the first pin, the second pin, the third pin and the fourth pin of the six signal pins are sequentially arranged at intervals in a first direction, and the fifth pin and the sixth pin of the six signal pins are arranged at intervals in a second direction; the fifth pin and the sixth pin are respectively located on both sides of a line connecting the second pin and the third pin; wherein the first pin, the fourth pin, the fifth pin and the sixth pin are data signal pins, and the second pin and the third pin are control signal pins; the first direction is different from the second direction; the method comprises the following steps: A data signal is transmitted through the first pin, the fourth pin, the fifth pin and the sixth pin, and a control signal is transmitted through the second pin and the third pin.

33. The signal transmission method according to claim 32, characterized in that: The fifth pin and the sixth pin are arranged on a perpendicular line of a line connecting the second pin and the third pin, and the first direction is perpendicular to the second direction.

34. The signal transmission method according to claim 33, characterized in that: The fifth pin and the sixth pin are arranged on the perpendicular midline of the line connecting the second pin and the third pin, and the basic graphic unit is a central symmetrical structure or an axisymmetric structure.

35. The signal transmission method according to any one of claims 32 to 34, characterized in that: The pins in the pin area are arranged in an array, and the pins between rows and columns are staggered; the pins in the pin area are arranged in a triangular grid, wherein the line connecting the pin and two adjacent pins forms an equilateral triangle.

36. The signal transmission method according to any one of claims 32 to 35, characterized in that: The basic graphic unit further includes a ground pin, the ground pins are fourteen in number, and the fourteen ground pins are sequentially arranged at intervals around the six signal pins; In the first direction, the first ground pin is located beside the first ground pin, the eighth ground pin is located beside the fourth ground pin, and the second ground pin, the third ground pin, the fourth ground pin, the fifth ground pin, the sixth ground pin and the seventh ground pin are sequentially arranged between the first ground pin and the eighth ground pin; A ninth ground pin, a tenth ground pin, an eleventh ground pin, a twelfth ground pin, a thirteenth ground pin and a fourteenth ground pin are sequentially arranged between the eighth ground pin and the first ground pin.

37. The signal transmission method according to claim 36, characterized in that: The two basic graphic units are arranged adjacent to each other, one is a first basic graphic unit, and the other is a second basic graphic unit, and adjacent sides of the first basic graphic unit and the second basic graphic unit share a ground pin.

38. The signal transmission method according to claim 37, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, and the eighth ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are common ground pins.

39. The signal transmission method according to claim 37, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the twelfth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are common ground pins, and the eleventh ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are common ground pins.

40. The signal transmission method according to claim 37, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the seventh ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are common ground pins, and the eighth ground pin of the first basic graphic unit and the fourteenth ground pin of the second basic graphic unit are common ground pins.

41. The signal transmission method according to claim 37, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the twelfth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are common ground pins, the eleventh ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are common ground pins, the tenth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are common ground pins, and the ninth ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are common ground pins.

42. The signal transmission method according to claim 37, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated graphics, the eleventh ground pin of the first basic graphic unit and the first ground pin of the second basic graphic unit are common ground pins, the tenth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are common ground pins, the ninth ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are common ground pins, and the eighth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are common ground pins.

43. The signal transmission method according to claim 37, characterized in that: The first basic graphic unit and the second basic graphic unit are mutually translated and rotated graphics, the fifth ground pin of the first basic graphic unit and the fifth ground pin of the second basic graphic unit are a common ground pin, the sixth ground pin of the first basic graphic unit and the fourth ground pin of the second basic graphic unit are a common ground pin, the seventh ground pin of the first basic graphic unit and the third ground pin of the second basic graphic unit are a common ground pin, and the eighth ground pin of the first basic graphic unit and the second ground pin of the second basic graphic unit are a common ground pin.

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